./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/bist_cell.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8fc3dc66 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/bist_cell.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 --- Real Ultimate output --- This is Ultimate 0.3.0-?-8fc3dc6-m [2025-03-17 20:37:16,880 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-17 20:37:16,933 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-17 20:37:16,936 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-17 20:37:16,938 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-17 20:37:16,938 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-17 20:37:16,955 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-17 20:37:16,956 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-17 20:37:16,956 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-17 20:37:16,956 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-17 20:37:16,956 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-17 20:37:16,956 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-17 20:37:16,956 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-17 20:37:16,956 INFO L153 SettingsManager]: * Use SBE=true [2025-03-17 20:37:16,957 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-17 20:37:16,957 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-17 20:37:16,957 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-17 20:37:16,957 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-17 20:37:16,957 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-17 20:37:16,957 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-17 20:37:16,957 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-17 20:37:16,957 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-17 20:37:16,957 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-17 20:37:16,957 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-17 20:37:16,957 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-17 20:37:16,958 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-17 20:37:16,958 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-17 20:37:16,958 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-17 20:37:16,958 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-17 20:37:16,958 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-17 20:37:16,958 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-17 20:37:16,958 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-17 20:37:16,958 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-17 20:37:16,958 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-17 20:37:16,958 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-17 20:37:16,958 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-17 20:37:16,958 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-17 20:37:16,959 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-17 20:37:16,959 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-17 20:37:16,959 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-17 20:37:16,959 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 [2025-03-17 20:37:17,165 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-17 20:37:17,171 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-17 20:37:17,172 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-17 20:37:17,173 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-17 20:37:17,173 INFO L274 PluginConnector]: CDTParser initialized [2025-03-17 20:37:17,174 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/bist_cell.cil.c [2025-03-17 20:37:18,305 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c655aa1ab/a7b59218b6b7400cadf5c64f1e30843e/FLAG539352f82 [2025-03-17 20:37:18,527 INFO L384 CDTParser]: Found 1 translation units. [2025-03-17 20:37:18,528 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c [2025-03-17 20:37:18,535 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c655aa1ab/a7b59218b6b7400cadf5c64f1e30843e/FLAG539352f82 [2025-03-17 20:37:18,548 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c655aa1ab/a7b59218b6b7400cadf5c64f1e30843e [2025-03-17 20:37:18,550 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-17 20:37:18,551 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-17 20:37:18,553 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-17 20:37:18,553 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-17 20:37:18,556 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-17 20:37:18,557 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,557 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@42509dce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18, skipping insertion in model container [2025-03-17 20:37:18,557 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,574 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-17 20:37:18,699 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 20:37:18,711 INFO L200 MainTranslator]: Completed pre-run [2025-03-17 20:37:18,734 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 20:37:18,745 INFO L204 MainTranslator]: Completed translation [2025-03-17 20:37:18,746 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18 WrapperNode [2025-03-17 20:37:18,746 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-17 20:37:18,746 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-17 20:37:18,746 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-17 20:37:18,746 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-17 20:37:18,750 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,756 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,780 INFO L138 Inliner]: procedures = 30, calls = 31, calls flagged for inlining = 26, calls inlined = 32, statements flattened = 339 [2025-03-17 20:37:18,781 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-17 20:37:18,781 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-17 20:37:18,781 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-17 20:37:18,781 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-17 20:37:18,794 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,794 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,796 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,808 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-17 20:37:18,808 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,808 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,812 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,813 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,813 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,814 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,815 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-17 20:37:18,816 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-17 20:37:18,816 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-17 20:37:18,816 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-17 20:37:18,817 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (1/1) ... [2025-03-17 20:37:18,820 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:37:18,843 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 20:37:18,854 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 20:37:18,858 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-17 20:37:18,877 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-17 20:37:18,877 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-17 20:37:18,877 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-17 20:37:18,878 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-17 20:37:18,942 INFO L256 CfgBuilder]: Building ICFG [2025-03-17 20:37:18,943 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-17 20:37:19,242 INFO L? ?]: Removed 30 outVars from TransFormulas that were not future-live. [2025-03-17 20:37:19,243 INFO L307 CfgBuilder]: Performing block encoding [2025-03-17 20:37:19,251 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-17 20:37:19,251 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-17 20:37:19,251 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:37:19 BoogieIcfgContainer [2025-03-17 20:37:19,252 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-17 20:37:19,252 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-17 20:37:19,252 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-17 20:37:19,257 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-17 20:37:19,257 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 20:37:19,257 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.03 08:37:18" (1/3) ... [2025-03-17 20:37:19,258 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@72980680 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 08:37:19, skipping insertion in model container [2025-03-17 20:37:19,258 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 20:37:19,258 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:18" (2/3) ... [2025-03-17 20:37:19,259 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@72980680 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 08:37:19, skipping insertion in model container [2025-03-17 20:37:19,259 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 20:37:19,259 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:37:19" (3/3) ... [2025-03-17 20:37:19,260 INFO L363 chiAutomizerObserver]: Analyzing ICFG bist_cell.cil.c [2025-03-17 20:37:19,298 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-17 20:37:19,298 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-17 20:37:19,298 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-17 20:37:19,298 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-17 20:37:19,298 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-17 20:37:19,298 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-17 20:37:19,299 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-17 20:37:19,299 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-17 20:37:19,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 102 states, 101 states have (on average 1.702970297029703) internal successors, (172), 101 states have internal predecessors, (172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:19,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:19,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:19,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:19,323 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:19,324 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:19,324 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-17 20:37:19,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 102 states, 101 states have (on average 1.702970297029703) internal successors, (172), 101 states have internal predecessors, (172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:19,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:19,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:19,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:19,330 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:19,330 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:19,335 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:19,336 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-17 20:37:19,342 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:19,343 INFO L85 PathProgramCache]: Analyzing trace with hash 1584250269, now seen corresponding path program 1 times [2025-03-17 20:37:19,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:19,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869179414] [2025-03-17 20:37:19,348 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:19,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:19,402 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 25 statements into 1 equivalence classes. [2025-03-17 20:37:19,415 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 25 of 25 statements. [2025-03-17 20:37:19,415 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:19,416 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:19,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:19,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:19,486 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1869179414] [2025-03-17 20:37:19,487 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1869179414] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:19,487 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:19,487 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:19,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1143879684] [2025-03-17 20:37:19,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:19,492 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:19,494 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:19,494 INFO L85 PathProgramCache]: Analyzing trace with hash -1512438379, now seen corresponding path program 1 times [2025-03-17 20:37:19,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:19,494 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406927417] [2025-03-17 20:37:19,494 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:19,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:19,505 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-17 20:37:19,509 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-17 20:37:19,510 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:19,510 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:19,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:19,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:19,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406927417] [2025-03-17 20:37:19,531 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1406927417] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:19,531 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:19,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:19,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1177450310] [2025-03-17 20:37:19,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:19,533 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:19,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:19,561 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:19,562 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:19,565 INFO L87 Difference]: Start difference. First operand has 102 states, 101 states have (on average 1.702970297029703) internal successors, (172), 101 states have internal predecessors, (172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.333333333333334) internal successors, (25), 2 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:19,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:19,592 INFO L93 Difference]: Finished difference Result 102 states and 168 transitions. [2025-03-17 20:37:19,593 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102 states and 168 transitions. [2025-03-17 20:37:19,595 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:19,603 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102 states to 97 states and 163 transitions. [2025-03-17 20:37:19,605 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2025-03-17 20:37:19,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2025-03-17 20:37:19,607 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 163 transitions. [2025-03-17 20:37:19,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:19,607 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 163 transitions. [2025-03-17 20:37:19,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 163 transitions. [2025-03-17 20:37:19,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2025-03-17 20:37:19,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.6804123711340206) internal successors, (163), 96 states have internal predecessors, (163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:19,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 163 transitions. [2025-03-17 20:37:19,634 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97 states and 163 transitions. [2025-03-17 20:37:19,635 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:19,637 INFO L432 stractBuchiCegarLoop]: Abstraction has 97 states and 163 transitions. [2025-03-17 20:37:19,637 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-17 20:37:19,637 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 163 transitions. [2025-03-17 20:37:19,639 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:19,639 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:19,639 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:19,639 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:19,640 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:19,640 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume !(~b0_val~0 != ~b0_val_t~0);" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:19,640 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-17 20:37:19,641 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:19,641 INFO L85 PathProgramCache]: Analyzing trace with hash 1745941760, now seen corresponding path program 1 times [2025-03-17 20:37:19,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:19,641 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861784932] [2025-03-17 20:37:19,641 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:19,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:19,648 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-17 20:37:19,656 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-17 20:37:19,658 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:19,658 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:19,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:19,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:19,717 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1861784932] [2025-03-17 20:37:19,717 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1861784932] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:19,717 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:19,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:19,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [806501420] [2025-03-17 20:37:19,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:19,717 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:19,718 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:19,718 INFO L85 PathProgramCache]: Analyzing trace with hash -604139734, now seen corresponding path program 1 times [2025-03-17 20:37:19,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:19,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1584750059] [2025-03-17 20:37:19,718 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:19,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:19,726 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:19,732 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:19,732 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:19,732 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:19,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:19,813 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:19,814 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1584750059] [2025-03-17 20:37:19,814 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1584750059] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:19,814 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:19,814 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:19,814 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [446323253] [2025-03-17 20:37:19,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:19,814 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:19,814 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:19,815 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:19,815 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:19,815 INFO L87 Difference]: Start difference. First operand 97 states and 163 transitions. cyclomatic complexity: 67 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:19,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:19,834 INFO L93 Difference]: Finished difference Result 97 states and 162 transitions. [2025-03-17 20:37:19,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 162 transitions. [2025-03-17 20:37:19,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:19,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 162 transitions. [2025-03-17 20:37:19,836 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2025-03-17 20:37:19,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2025-03-17 20:37:19,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 162 transitions. [2025-03-17 20:37:19,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:19,837 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 162 transitions. [2025-03-17 20:37:19,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 162 transitions. [2025-03-17 20:37:19,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2025-03-17 20:37:19,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.6701030927835052) internal successors, (162), 96 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:19,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 162 transitions. [2025-03-17 20:37:19,841 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97 states and 162 transitions. [2025-03-17 20:37:19,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:19,844 INFO L432 stractBuchiCegarLoop]: Abstraction has 97 states and 162 transitions. [2025-03-17 20:37:19,844 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-17 20:37:19,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 162 transitions. [2025-03-17 20:37:19,845 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:19,845 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:19,845 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:19,846 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:19,846 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:19,846 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:19,846 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-17 20:37:19,849 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:19,850 INFO L85 PathProgramCache]: Analyzing trace with hash -471816193, now seen corresponding path program 1 times [2025-03-17 20:37:19,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:19,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9080524] [2025-03-17 20:37:19,850 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:19,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:19,859 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-17 20:37:19,862 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-17 20:37:19,862 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:19,862 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:19,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:19,898 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:19,899 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [9080524] [2025-03-17 20:37:19,899 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [9080524] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:19,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:19,899 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:19,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1539170271] [2025-03-17 20:37:19,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:19,899 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:19,899 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:19,899 INFO L85 PathProgramCache]: Analyzing trace with hash -604139734, now seen corresponding path program 2 times [2025-03-17 20:37:19,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:19,899 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146743255] [2025-03-17 20:37:19,900 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:37:19,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:19,909 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:19,919 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:19,919 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:37:19,919 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:19,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:19,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:19,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146743255] [2025-03-17 20:37:19,966 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [146743255] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:19,966 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:19,966 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:19,966 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680368462] [2025-03-17 20:37:19,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:19,967 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:19,967 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:19,967 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:19,967 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:19,967 INFO L87 Difference]: Start difference. First operand 97 states and 162 transitions. cyclomatic complexity: 66 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:19,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:19,978 INFO L93 Difference]: Finished difference Result 97 states and 161 transitions. [2025-03-17 20:37:19,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 161 transitions. [2025-03-17 20:37:19,979 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:19,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 161 transitions. [2025-03-17 20:37:19,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2025-03-17 20:37:19,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2025-03-17 20:37:19,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 161 transitions. [2025-03-17 20:37:19,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:19,980 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 161 transitions. [2025-03-17 20:37:19,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 161 transitions. [2025-03-17 20:37:19,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2025-03-17 20:37:19,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.6597938144329898) internal successors, (161), 96 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:19,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 161 transitions. [2025-03-17 20:37:19,987 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97 states and 161 transitions. [2025-03-17 20:37:19,987 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:19,988 INFO L432 stractBuchiCegarLoop]: Abstraction has 97 states and 161 transitions. [2025-03-17 20:37:19,988 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-17 20:37:19,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 161 transitions. [2025-03-17 20:37:19,988 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:19,988 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:19,988 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:19,989 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:19,989 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:19,989 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume !(~b1_val~0 != ~b1_val_t~0);" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:19,989 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-17 20:37:19,990 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:19,990 INFO L85 PathProgramCache]: Analyzing trace with hash 817880156, now seen corresponding path program 1 times [2025-03-17 20:37:19,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:19,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776917084] [2025-03-17 20:37:19,990 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:19,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:19,994 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-17 20:37:20,000 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-17 20:37:20,000 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:20,001 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,034 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,034 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776917084] [2025-03-17 20:37:20,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776917084] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,034 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,034 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:20,034 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2146748006] [2025-03-17 20:37:20,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,034 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:20,035 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,035 INFO L85 PathProgramCache]: Analyzing trace with hash -604139734, now seen corresponding path program 3 times [2025-03-17 20:37:20,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024815585] [2025-03-17 20:37:20,035 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:37:20,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,041 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:20,049 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:20,049 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:37:20,049 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024815585] [2025-03-17 20:37:20,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2024815585] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:20,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596104389] [2025-03-17 20:37:20,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,091 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:20,091 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:20,091 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:20,091 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:20,091 INFO L87 Difference]: Start difference. First operand 97 states and 161 transitions. cyclomatic complexity: 65 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 2 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:20,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:20,112 INFO L93 Difference]: Finished difference Result 97 states and 160 transitions. [2025-03-17 20:37:20,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 160 transitions. [2025-03-17 20:37:20,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:20,114 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 160 transitions. [2025-03-17 20:37:20,115 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2025-03-17 20:37:20,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2025-03-17 20:37:20,116 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 160 transitions. [2025-03-17 20:37:20,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:20,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 160 transitions. [2025-03-17 20:37:20,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 160 transitions. [2025-03-17 20:37:20,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2025-03-17 20:37:20,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.6494845360824741) internal successors, (160), 96 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:20,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 160 transitions. [2025-03-17 20:37:20,121 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97 states and 160 transitions. [2025-03-17 20:37:20,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:20,122 INFO L432 stractBuchiCegarLoop]: Abstraction has 97 states and 160 transitions. [2025-03-17 20:37:20,122 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-17 20:37:20,122 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 160 transitions. [2025-03-17 20:37:20,123 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:20,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:20,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:20,124 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:20,124 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:20,124 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:20,124 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-17 20:37:20,124 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,125 INFO L85 PathProgramCache]: Analyzing trace with hash 884886909, now seen corresponding path program 1 times [2025-03-17 20:37:20,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663654693] [2025-03-17 20:37:20,125 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:20,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,133 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-17 20:37:20,137 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-17 20:37:20,139 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:20,139 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1663654693] [2025-03-17 20:37:20,165 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1663654693] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,165 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,165 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:20,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672775376] [2025-03-17 20:37:20,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,165 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:20,165 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,166 INFO L85 PathProgramCache]: Analyzing trace with hash -604139734, now seen corresponding path program 4 times [2025-03-17 20:37:20,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,166 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514120994] [2025-03-17 20:37:20,166 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 20:37:20,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,171 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 33 statements into 2 equivalence classes. [2025-03-17 20:37:20,173 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:20,173 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-17 20:37:20,173 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,205 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,205 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514120994] [2025-03-17 20:37:20,205 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514120994] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,205 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,205 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:20,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608197474] [2025-03-17 20:37:20,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,206 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:20,206 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:20,206 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:20,206 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:20,206 INFO L87 Difference]: Start difference. First operand 97 states and 160 transitions. cyclomatic complexity: 64 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 2 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:20,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:20,217 INFO L93 Difference]: Finished difference Result 97 states and 159 transitions. [2025-03-17 20:37:20,217 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 159 transitions. [2025-03-17 20:37:20,218 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:20,218 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 159 transitions. [2025-03-17 20:37:20,218 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2025-03-17 20:37:20,219 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2025-03-17 20:37:20,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 159 transitions. [2025-03-17 20:37:20,219 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:20,219 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 159 transitions. [2025-03-17 20:37:20,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 159 transitions. [2025-03-17 20:37:20,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2025-03-17 20:37:20,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.6391752577319587) internal successors, (159), 96 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:20,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 159 transitions. [2025-03-17 20:37:20,222 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97 states and 159 transitions. [2025-03-17 20:37:20,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:20,223 INFO L432 stractBuchiCegarLoop]: Abstraction has 97 states and 159 transitions. [2025-03-17 20:37:20,223 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-17 20:37:20,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 159 transitions. [2025-03-17 20:37:20,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:20,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:20,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:20,224 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:20,224 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:20,224 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume !(~d0_val~0 != ~d0_val_t~0);" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:20,224 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-17 20:37:20,225 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,225 INFO L85 PathProgramCache]: Analyzing trace with hash 1548252576, now seen corresponding path program 1 times [2025-03-17 20:37:20,225 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,225 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063056078] [2025-03-17 20:37:20,225 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:20,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,229 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-17 20:37:20,235 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-17 20:37:20,235 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:20,235 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,277 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1063056078] [2025-03-17 20:37:20,277 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1063056078] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,277 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,277 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:20,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679768484] [2025-03-17 20:37:20,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,277 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:20,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,278 INFO L85 PathProgramCache]: Analyzing trace with hash -604139734, now seen corresponding path program 5 times [2025-03-17 20:37:20,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050630270] [2025-03-17 20:37:20,278 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 20:37:20,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,286 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:20,287 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:20,287 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:37:20,287 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050630270] [2025-03-17 20:37:20,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050630270] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,335 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:20,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859960100] [2025-03-17 20:37:20,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,335 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:20,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:20,335 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:20,335 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:20,336 INFO L87 Difference]: Start difference. First operand 97 states and 159 transitions. cyclomatic complexity: 63 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 2 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:20,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:20,350 INFO L93 Difference]: Finished difference Result 97 states and 158 transitions. [2025-03-17 20:37:20,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 158 transitions. [2025-03-17 20:37:20,350 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:20,352 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 158 transitions. [2025-03-17 20:37:20,352 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2025-03-17 20:37:20,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2025-03-17 20:37:20,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 158 transitions. [2025-03-17 20:37:20,352 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:20,352 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 158 transitions. [2025-03-17 20:37:20,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 158 transitions. [2025-03-17 20:37:20,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2025-03-17 20:37:20,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.6288659793814433) internal successors, (158), 96 states have internal predecessors, (158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:20,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 158 transitions. [2025-03-17 20:37:20,355 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97 states and 158 transitions. [2025-03-17 20:37:20,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:20,360 INFO L432 stractBuchiCegarLoop]: Abstraction has 97 states and 158 transitions. [2025-03-17 20:37:20,360 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-17 20:37:20,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 158 transitions. [2025-03-17 20:37:20,361 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:20,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:20,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:20,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:20,364 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:20,364 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:20,364 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-17 20:37:20,364 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,364 INFO L85 PathProgramCache]: Analyzing trace with hash 303488095, now seen corresponding path program 1 times [2025-03-17 20:37:20,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,365 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862990720] [2025-03-17 20:37:20,365 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:20,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,373 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-17 20:37:20,377 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-17 20:37:20,377 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:20,378 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862990720] [2025-03-17 20:37:20,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [862990720] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,397 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,397 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:20,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258471078] [2025-03-17 20:37:20,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,398 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:20,398 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,398 INFO L85 PathProgramCache]: Analyzing trace with hash -604139734, now seen corresponding path program 6 times [2025-03-17 20:37:20,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986132594] [2025-03-17 20:37:20,398 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 20:37:20,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,404 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:20,409 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:20,410 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 20:37:20,410 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,438 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,438 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986132594] [2025-03-17 20:37:20,438 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986132594] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,438 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,438 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:20,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199610419] [2025-03-17 20:37:20,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,439 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:20,439 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:20,439 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:20,439 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:20,439 INFO L87 Difference]: Start difference. First operand 97 states and 158 transitions. cyclomatic complexity: 62 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 2 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:20,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:20,447 INFO L93 Difference]: Finished difference Result 97 states and 157 transitions. [2025-03-17 20:37:20,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 157 transitions. [2025-03-17 20:37:20,448 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:20,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 157 transitions. [2025-03-17 20:37:20,448 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2025-03-17 20:37:20,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2025-03-17 20:37:20,449 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 157 transitions. [2025-03-17 20:37:20,449 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:20,449 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 157 transitions. [2025-03-17 20:37:20,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 157 transitions. [2025-03-17 20:37:20,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2025-03-17 20:37:20,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.6185567010309279) internal successors, (157), 96 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:20,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 157 transitions. [2025-03-17 20:37:20,452 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97 states and 157 transitions. [2025-03-17 20:37:20,452 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:20,453 INFO L432 stractBuchiCegarLoop]: Abstraction has 97 states and 157 transitions. [2025-03-17 20:37:20,453 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-17 20:37:20,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 157 transitions. [2025-03-17 20:37:20,453 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2025-03-17 20:37:20,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:20,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:20,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:20,454 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:20,454 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume !(~d1_val~0 != ~d1_val_t~0);" "~d1_req_up~0 := 0;assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:20,454 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-17 20:37:20,455 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,455 INFO L85 PathProgramCache]: Analyzing trace with hash 1392441340, now seen corresponding path program 1 times [2025-03-17 20:37:20,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841181491] [2025-03-17 20:37:20,455 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:20,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,459 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:20,460 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:20,461 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:20,461 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841181491] [2025-03-17 20:37:20,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [841181491] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,499 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:20,499 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1354359588] [2025-03-17 20:37:20,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,500 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:20,500 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,500 INFO L85 PathProgramCache]: Analyzing trace with hash -604139734, now seen corresponding path program 7 times [2025-03-17 20:37:20,500 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,500 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330063055] [2025-03-17 20:37:20,500 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 20:37:20,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,506 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:20,508 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:20,508 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:20,508 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,535 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [330063055] [2025-03-17 20:37:20,535 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [330063055] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,535 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,535 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:20,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039073531] [2025-03-17 20:37:20,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,536 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:20,536 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:20,536 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:37:20,536 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:37:20,536 INFO L87 Difference]: Start difference. First operand 97 states and 157 transitions. cyclomatic complexity: 61 Second operand has 4 states, 4 states have (on average 8.25) internal successors, (33), 4 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:20,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:20,555 INFO L93 Difference]: Finished difference Result 100 states and 160 transitions. [2025-03-17 20:37:20,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100 states and 160 transitions. [2025-03-17 20:37:20,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 62 [2025-03-17 20:37:20,556 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100 states to 100 states and 160 transitions. [2025-03-17 20:37:20,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100 [2025-03-17 20:37:20,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100 [2025-03-17 20:37:20,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 160 transitions. [2025-03-17 20:37:20,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:20,557 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 160 transitions. [2025-03-17 20:37:20,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 160 transitions. [2025-03-17 20:37:20,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2025-03-17 20:37:20,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.606060606060606) internal successors, (159), 98 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:20,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 159 transitions. [2025-03-17 20:37:20,560 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 159 transitions. [2025-03-17 20:37:20,560 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:37:20,561 INFO L432 stractBuchiCegarLoop]: Abstraction has 99 states and 159 transitions. [2025-03-17 20:37:20,561 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-17 20:37:20,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 159 transitions. [2025-03-17 20:37:20,561 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 61 [2025-03-17 20:37:20,561 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:20,561 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:20,562 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:20,562 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:20,562 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume !(~d1_val~0 != ~d1_val_t~0);" "~d1_req_up~0 := 0;assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:20,563 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-17 20:37:20,563 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,563 INFO L85 PathProgramCache]: Analyzing trace with hash 1392441340, now seen corresponding path program 2 times [2025-03-17 20:37:20,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,563 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455623626] [2025-03-17 20:37:20,563 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:37:20,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,575 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:20,578 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:20,578 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:37:20,578 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,616 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,616 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455623626] [2025-03-17 20:37:20,616 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [455623626] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,617 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,617 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:20,617 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285990548] [2025-03-17 20:37:20,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,617 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:20,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,618 INFO L85 PathProgramCache]: Analyzing trace with hash 97460140, now seen corresponding path program 1 times [2025-03-17 20:37:20,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464329712] [2025-03-17 20:37:20,618 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:20,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,626 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:20,630 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:20,630 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:20,630 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464329712] [2025-03-17 20:37:20,651 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1464329712] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,651 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,651 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:37:20,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205095185] [2025-03-17 20:37:20,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,651 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:20,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:20,652 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:20,652 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:20,652 INFO L87 Difference]: Start difference. First operand 99 states and 159 transitions. cyclomatic complexity: 61 Second operand has 3 states, 3 states have (on average 11.0) internal successors, (33), 3 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:20,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:20,678 INFO L93 Difference]: Finished difference Result 135 states and 216 transitions. [2025-03-17 20:37:20,679 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 135 states and 216 transitions. [2025-03-17 20:37:20,680 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 77 [2025-03-17 20:37:20,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 135 states to 135 states and 216 transitions. [2025-03-17 20:37:20,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 135 [2025-03-17 20:37:20,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 135 [2025-03-17 20:37:20,681 INFO L73 IsDeterministic]: Start isDeterministic. Operand 135 states and 216 transitions. [2025-03-17 20:37:20,681 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:20,681 INFO L218 hiAutomatonCegarLoop]: Abstraction has 135 states and 216 transitions. [2025-03-17 20:37:20,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states and 216 transitions. [2025-03-17 20:37:20,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 135. [2025-03-17 20:37:20,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 135 states, 135 states have (on average 1.6) internal successors, (216), 134 states have internal predecessors, (216), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:20,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 216 transitions. [2025-03-17 20:37:20,686 INFO L240 hiAutomatonCegarLoop]: Abstraction has 135 states and 216 transitions. [2025-03-17 20:37:20,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:20,689 INFO L432 stractBuchiCegarLoop]: Abstraction has 135 states and 216 transitions. [2025-03-17 20:37:20,689 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-17 20:37:20,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 135 states and 216 transitions. [2025-03-17 20:37:20,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 77 [2025-03-17 20:37:20,690 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:20,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:20,691 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:20,691 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:20,691 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume !(~d1_val~0 != ~d1_val_t~0);" "~d1_req_up~0 := 0;assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:20,691 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-17 20:37:20,693 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,693 INFO L85 PathProgramCache]: Analyzing trace with hash -1905453603, now seen corresponding path program 1 times [2025-03-17 20:37:20,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,693 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931662376] [2025-03-17 20:37:20,694 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:20,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,700 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:20,702 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:20,702 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:20,702 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:20,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:20,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:20,755 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1931662376] [2025-03-17 20:37:20,755 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1931662376] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:20,755 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:20,755 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:20,755 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1065556885] [2025-03-17 20:37:20,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:20,755 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:20,756 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:20,756 INFO L85 PathProgramCache]: Analyzing trace with hash 390863147, now seen corresponding path program 1 times [2025-03-17 20:37:20,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:20,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817643020] [2025-03-17 20:37:20,756 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:20,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:20,761 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:20,763 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:20,765 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:20,765 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:20,765 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:20,767 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:20,770 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:20,770 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:20,770 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:20,787 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:21,093 INFO L204 LassoAnalysis]: Preferences: [2025-03-17 20:37:21,094 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-17 20:37:21,094 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-17 20:37:21,094 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-17 20:37:21,094 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2025-03-17 20:37:21,094 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:37:21,095 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-17 20:37:21,095 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-17 20:37:21,095 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration10_Loop [2025-03-17 20:37:21,095 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-17 20:37:21,095 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-17 20:37:21,108 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,113 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,115 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,119 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,123 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,127 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,132 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,134 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,135 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,137 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,139 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,143 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,147 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,151 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,153 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,156 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,160 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,162 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,164 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,166 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,168 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,170 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,172 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,174 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,175 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,177 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,178 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,332 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-17 20:37:21,333 INFO L365 LassoAnalysis]: Checking for nontermination... [2025-03-17 20:37:21,334 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:37:21,334 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 20:37:21,337 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 20:37:21,339 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-03-17 20:37:21,339 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-03-17 20:37:21,340 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-17 20:37:21,358 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-03-17 20:37:21,358 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_method1_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_method1_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-03-17 20:37:21,364 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2025-03-17 20:37:21,364 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:37:21,364 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 20:37:21,366 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 20:37:21,366 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-03-17 20:37:21,372 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-03-17 20:37:21,372 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-17 20:37:21,385 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-03-17 20:37:21,385 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-03-17 20:37:21,390 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2025-03-17 20:37:21,390 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:37:21,390 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 20:37:21,392 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 20:37:21,394 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-03-17 20:37:21,395 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-03-17 20:37:21,395 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-17 20:37:21,411 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2025-03-17 20:37:21,411 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:37:21,411 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 20:37:21,412 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 20:37:21,413 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-03-17 20:37:21,414 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2025-03-17 20:37:21,414 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-17 20:37:21,427 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2025-03-17 20:37:21,432 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2025-03-17 20:37:21,433 INFO L204 LassoAnalysis]: Preferences: [2025-03-17 20:37:21,433 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-17 20:37:21,433 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-17 20:37:21,433 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-17 20:37:21,433 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-03-17 20:37:21,433 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:37:21,433 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-17 20:37:21,433 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-17 20:37:21,433 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration10_Loop [2025-03-17 20:37:21,433 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-17 20:37:21,433 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-17 20:37:21,435 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,440 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,443 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,449 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,454 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,457 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,461 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,463 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,464 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,468 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,479 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,485 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,488 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,491 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,493 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,496 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,498 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,500 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,502 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,505 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,506 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,508 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,510 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,512 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,513 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,519 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,522 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 20:37:21,662 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-17 20:37:21,665 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-03-17 20:37:21,666 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:37:21,666 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 20:37:21,668 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 20:37:21,669 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-03-17 20:37:21,671 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-17 20:37:21,681 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-17 20:37:21,681 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-17 20:37:21,682 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-17 20:37:21,682 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-17 20:37:21,682 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-17 20:37:21,684 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-17 20:37:21,684 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-17 20:37:21,687 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-17 20:37:21,692 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2025-03-17 20:37:21,692 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:37:21,693 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 20:37:21,694 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 20:37:21,696 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-03-17 20:37:21,697 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-17 20:37:21,707 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-17 20:37:21,707 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-17 20:37:21,707 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-17 20:37:21,707 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-17 20:37:21,707 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-17 20:37:21,707 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-17 20:37:21,707 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-17 20:37:21,709 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-17 20:37:21,716 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2025-03-17 20:37:21,717 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:37:21,717 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 20:37:21,718 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 20:37:21,719 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-03-17 20:37:21,721 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-17 20:37:21,731 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-17 20:37:21,732 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-17 20:37:21,732 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-17 20:37:21,732 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-17 20:37:21,732 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-17 20:37:21,733 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-17 20:37:21,733 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-17 20:37:21,735 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-03-17 20:37:21,743 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2025-03-17 20:37:21,745 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2025-03-17 20:37:21,746 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:37:21,746 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 20:37:21,748 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 20:37:21,750 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-03-17 20:37:21,751 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-03-17 20:37:21,751 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2025-03-17 20:37:21,751 INFO L474 LassoAnalysis]: Proved termination. [2025-03-17 20:37:21,752 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~d1_ev~0) = -1*~d1_ev~0 + 1 Supporting invariants [] [2025-03-17 20:37:21,757 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2025-03-17 20:37:21,760 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-03-17 20:37:21,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:21,786 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:21,799 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:21,799 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:21,799 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:21,800 INFO L256 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-03-17 20:37:21,801 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 20:37:21,845 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:21,856 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:21,856 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:21,856 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:21,856 INFO L256 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-17 20:37:21,857 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 20:37:21,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:21,948 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2025-03-17 20:37:21,949 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 135 states and 216 transitions. cyclomatic complexity: 82 Second operand has 5 states, 5 states have (on average 13.2) internal successors, (66), 5 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,004 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 135 states and 216 transitions. cyclomatic complexity: 82. Second operand has 5 states, 5 states have (on average 13.2) internal successors, (66), 5 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 299 states and 481 transitions. Complement of second has 5 states. [2025-03-17 20:37:22,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-03-17 20:37:22,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 13.2) internal successors, (66), 5 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 161 transitions. [2025-03-17 20:37:22,010 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 161 transitions. Stem has 33 letters. Loop has 33 letters. [2025-03-17 20:37:22,012 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-17 20:37:22,012 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 161 transitions. Stem has 66 letters. Loop has 33 letters. [2025-03-17 20:37:22,013 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-17 20:37:22,013 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 161 transitions. Stem has 33 letters. Loop has 66 letters. [2025-03-17 20:37:22,014 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-17 20:37:22,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 299 states and 481 transitions. [2025-03-17 20:37:22,016 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 154 [2025-03-17 20:37:22,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 299 states to 299 states and 481 transitions. [2025-03-17 20:37:22,018 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 214 [2025-03-17 20:37:22,018 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 219 [2025-03-17 20:37:22,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 299 states and 481 transitions. [2025-03-17 20:37:22,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 20:37:22,018 INFO L218 hiAutomatonCegarLoop]: Abstraction has 299 states and 481 transitions. [2025-03-17 20:37:22,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 299 states and 481 transitions. [2025-03-17 20:37:22,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 299 to 294. [2025-03-17 20:37:22,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 294 states, 294 states have (on average 1.619047619047619) internal successors, (476), 293 states have internal predecessors, (476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 294 states to 294 states and 476 transitions. [2025-03-17 20:37:22,024 INFO L240 hiAutomatonCegarLoop]: Abstraction has 294 states and 476 transitions. [2025-03-17 20:37:22,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:22,024 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:22,025 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:22,025 INFO L87 Difference]: Start difference. First operand 294 states and 476 transitions. Second operand has 3 states, 3 states have (on average 11.0) internal successors, (33), 2 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:22,037 INFO L93 Difference]: Finished difference Result 294 states and 475 transitions. [2025-03-17 20:37:22,037 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 294 states and 475 transitions. [2025-03-17 20:37:22,039 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 154 [2025-03-17 20:37:22,040 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 294 states to 294 states and 475 transitions. [2025-03-17 20:37:22,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 214 [2025-03-17 20:37:22,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 214 [2025-03-17 20:37:22,042 INFO L73 IsDeterministic]: Start isDeterministic. Operand 294 states and 475 transitions. [2025-03-17 20:37:22,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 20:37:22,042 INFO L218 hiAutomatonCegarLoop]: Abstraction has 294 states and 475 transitions. [2025-03-17 20:37:22,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 294 states and 475 transitions. [2025-03-17 20:37:22,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 294 to 294. [2025-03-17 20:37:22,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 294 states, 294 states have (on average 1.6156462585034013) internal successors, (475), 293 states have internal predecessors, (475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 294 states to 294 states and 475 transitions. [2025-03-17 20:37:22,052 INFO L240 hiAutomatonCegarLoop]: Abstraction has 294 states and 475 transitions. [2025-03-17 20:37:22,052 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:22,053 INFO L432 stractBuchiCegarLoop]: Abstraction has 294 states and 475 transitions. [2025-03-17 20:37:22,053 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-17 20:37:22,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 294 states and 475 transitions. [2025-03-17 20:37:22,055 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 154 [2025-03-17 20:37:22,055 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:22,055 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:22,055 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,056 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,056 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-17 20:37:22,056 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-17 20:37:22,056 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,057 INFO L85 PathProgramCache]: Analyzing trace with hash -184283908, now seen corresponding path program 1 times [2025-03-17 20:37:22,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,057 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255747750] [2025-03-17 20:37:22,057 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:22,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,061 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-17 20:37:22,065 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-17 20:37:22,066 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,066 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:22,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:22,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:22,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1255747750] [2025-03-17 20:37:22,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1255747750] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:22,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:22,115 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:37:22,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707496315] [2025-03-17 20:37:22,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:22,115 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:22,116 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,116 INFO L85 PathProgramCache]: Analyzing trace with hash 139593755, now seen corresponding path program 1 times [2025-03-17 20:37:22,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,116 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508680653] [2025-03-17 20:37:22,116 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:22,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,119 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,120 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,120 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,120 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,120 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:22,121 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,121 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,121 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,121 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,123 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:22,140 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:22,140 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:37:22,140 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:37:22,140 INFO L87 Difference]: Start difference. First operand 294 states and 475 transitions. cyclomatic complexity: 184 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:22,157 INFO L93 Difference]: Finished difference Result 281 states and 451 transitions. [2025-03-17 20:37:22,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 281 states and 451 transitions. [2025-03-17 20:37:22,158 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 154 [2025-03-17 20:37:22,160 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 281 states to 281 states and 451 transitions. [2025-03-17 20:37:22,160 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201 [2025-03-17 20:37:22,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201 [2025-03-17 20:37:22,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 281 states and 451 transitions. [2025-03-17 20:37:22,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 20:37:22,164 INFO L218 hiAutomatonCegarLoop]: Abstraction has 281 states and 451 transitions. [2025-03-17 20:37:22,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states and 451 transitions. [2025-03-17 20:37:22,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 281. [2025-03-17 20:37:22,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281 states, 281 states have (on average 1.604982206405694) internal successors, (451), 280 states have internal predecessors, (451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281 states to 281 states and 451 transitions. [2025-03-17 20:37:22,169 INFO L240 hiAutomatonCegarLoop]: Abstraction has 281 states and 451 transitions. [2025-03-17 20:37:22,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:37:22,169 INFO L432 stractBuchiCegarLoop]: Abstraction has 281 states and 451 transitions. [2025-03-17 20:37:22,169 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-17 20:37:22,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 281 states and 451 transitions. [2025-03-17 20:37:22,171 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 154 [2025-03-17 20:37:22,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:22,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:22,171 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,171 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,171 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-17 20:37:22,172 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-17 20:37:22,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,172 INFO L85 PathProgramCache]: Analyzing trace with hash 778698684, now seen corresponding path program 1 times [2025-03-17 20:37:22,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1675532705] [2025-03-17 20:37:22,172 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:22,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,176 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-17 20:37:22,177 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-17 20:37:22,178 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,178 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:22,204 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2025-03-17 20:37:22,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:22,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:22,207 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1675532705] [2025-03-17 20:37:22,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1675532705] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:22,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:22,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:37:22,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73422914] [2025-03-17 20:37:22,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:22,208 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:22,208 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,208 INFO L85 PathProgramCache]: Analyzing trace with hash 139593755, now seen corresponding path program 2 times [2025-03-17 20:37:22,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [719096180] [2025-03-17 20:37:22,208 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:37:22,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,210 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,211 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,211 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:37:22,211 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,211 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:22,211 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,212 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,212 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,212 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,213 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:22,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:22,231 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:22,231 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:22,231 INFO L87 Difference]: Start difference. First operand 281 states and 451 transitions. cyclomatic complexity: 173 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:22,247 INFO L93 Difference]: Finished difference Result 326 states and 518 transitions. [2025-03-17 20:37:22,247 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 326 states and 518 transitions. [2025-03-17 20:37:22,249 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 184 [2025-03-17 20:37:22,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 326 states to 326 states and 518 transitions. [2025-03-17 20:37:22,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 231 [2025-03-17 20:37:22,251 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 231 [2025-03-17 20:37:22,251 INFO L73 IsDeterministic]: Start isDeterministic. Operand 326 states and 518 transitions. [2025-03-17 20:37:22,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 20:37:22,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 326 states and 518 transitions. [2025-03-17 20:37:22,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326 states and 518 transitions. [2025-03-17 20:37:22,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326 to 326. [2025-03-17 20:37:22,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 326 states, 326 states have (on average 1.5889570552147239) internal successors, (518), 325 states have internal predecessors, (518), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 518 transitions. [2025-03-17 20:37:22,255 INFO L240 hiAutomatonCegarLoop]: Abstraction has 326 states and 518 transitions. [2025-03-17 20:37:22,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:22,256 INFO L432 stractBuchiCegarLoop]: Abstraction has 326 states and 518 transitions. [2025-03-17 20:37:22,256 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-17 20:37:22,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 326 states and 518 transitions. [2025-03-17 20:37:22,257 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 184 [2025-03-17 20:37:22,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:22,258 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:22,258 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,258 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,258 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-17 20:37:22,258 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-17 20:37:22,259 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,259 INFO L85 PathProgramCache]: Analyzing trace with hash -574611013, now seen corresponding path program 1 times [2025-03-17 20:37:22,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422210067] [2025-03-17 20:37:22,259 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:22,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,262 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-17 20:37:22,263 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-17 20:37:22,263 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,264 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:22,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:22,276 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:22,276 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [422210067] [2025-03-17 20:37:22,276 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [422210067] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:22,276 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:22,276 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:37:22,276 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476930936] [2025-03-17 20:37:22,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:22,277 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:22,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,278 INFO L85 PathProgramCache]: Analyzing trace with hash 139593755, now seen corresponding path program 3 times [2025-03-17 20:37:22,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948679515] [2025-03-17 20:37:22,278 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:37:22,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,280 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,281 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,281 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:37:22,281 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,281 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:22,282 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,283 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,283 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,283 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,284 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:22,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:22,303 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:22,303 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:22,303 INFO L87 Difference]: Start difference. First operand 326 states and 518 transitions. cyclomatic complexity: 195 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:22,329 INFO L93 Difference]: Finished difference Result 401 states and 629 transitions. [2025-03-17 20:37:22,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 401 states and 629 transitions. [2025-03-17 20:37:22,331 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 234 [2025-03-17 20:37:22,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 401 states to 401 states and 629 transitions. [2025-03-17 20:37:22,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2025-03-17 20:37:22,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2025-03-17 20:37:22,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 401 states and 629 transitions. [2025-03-17 20:37:22,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 20:37:22,333 INFO L218 hiAutomatonCegarLoop]: Abstraction has 401 states and 629 transitions. [2025-03-17 20:37:22,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 401 states and 629 transitions. [2025-03-17 20:37:22,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 401 to 401. [2025-03-17 20:37:22,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 401 states, 401 states have (on average 1.56857855361596) internal successors, (629), 400 states have internal predecessors, (629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 401 states to 401 states and 629 transitions. [2025-03-17 20:37:22,339 INFO L240 hiAutomatonCegarLoop]: Abstraction has 401 states and 629 transitions. [2025-03-17 20:37:22,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:22,339 INFO L432 stractBuchiCegarLoop]: Abstraction has 401 states and 629 transitions. [2025-03-17 20:37:22,339 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-17 20:37:22,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 401 states and 629 transitions. [2025-03-17 20:37:22,341 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 234 [2025-03-17 20:37:22,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:22,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:22,341 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,341 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,342 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-17 20:37:22,342 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-17 20:37:22,342 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,342 INFO L85 PathProgramCache]: Analyzing trace with hash -64076836, now seen corresponding path program 1 times [2025-03-17 20:37:22,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983701005] [2025-03-17 20:37:22,342 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:22,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,345 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-17 20:37:22,347 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-17 20:37:22,347 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,347 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:22,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:22,358 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:22,358 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983701005] [2025-03-17 20:37:22,358 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983701005] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:22,358 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:22,359 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:37:22,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [87470878] [2025-03-17 20:37:22,359 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:22,359 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:22,359 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,359 INFO L85 PathProgramCache]: Analyzing trace with hash 139593755, now seen corresponding path program 4 times [2025-03-17 20:37:22,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249335572] [2025-03-17 20:37:22,360 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 20:37:22,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,364 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 6 statements into 2 equivalence classes. [2025-03-17 20:37:22,365 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,365 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 20:37:22,365 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,365 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:22,365 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,366 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,366 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,366 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,367 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:22,380 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:22,381 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:22,381 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:22,381 INFO L87 Difference]: Start difference. First operand 401 states and 629 transitions. cyclomatic complexity: 231 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:22,395 INFO L93 Difference]: Finished difference Result 518 states and 798 transitions. [2025-03-17 20:37:22,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 798 transitions. [2025-03-17 20:37:22,398 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 312 [2025-03-17 20:37:22,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 798 transitions. [2025-03-17 20:37:22,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 359 [2025-03-17 20:37:22,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 359 [2025-03-17 20:37:22,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 798 transitions. [2025-03-17 20:37:22,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 20:37:22,401 INFO L218 hiAutomatonCegarLoop]: Abstraction has 518 states and 798 transitions. [2025-03-17 20:37:22,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 798 transitions. [2025-03-17 20:37:22,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2025-03-17 20:37:22,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 518 states, 518 states have (on average 1.5405405405405406) internal successors, (798), 517 states have internal predecessors, (798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 798 transitions. [2025-03-17 20:37:22,408 INFO L240 hiAutomatonCegarLoop]: Abstraction has 518 states and 798 transitions. [2025-03-17 20:37:22,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:22,409 INFO L432 stractBuchiCegarLoop]: Abstraction has 518 states and 798 transitions. [2025-03-17 20:37:22,409 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-17 20:37:22,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 798 transitions. [2025-03-17 20:37:22,411 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 312 [2025-03-17 20:37:22,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:22,411 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:22,412 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,412 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,412 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-17 20:37:22,412 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-17 20:37:22,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,412 INFO L85 PathProgramCache]: Analyzing trace with hash -1571628645, now seen corresponding path program 1 times [2025-03-17 20:37:22,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599345240] [2025-03-17 20:37:22,413 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:22,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,416 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-17 20:37:22,418 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-17 20:37:22,418 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,418 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:22,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:22,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:22,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599345240] [2025-03-17 20:37:22,427 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [599345240] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:22,427 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:22,427 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:37:22,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [929519160] [2025-03-17 20:37:22,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:22,427 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:22,427 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,427 INFO L85 PathProgramCache]: Analyzing trace with hash 139593755, now seen corresponding path program 5 times [2025-03-17 20:37:22,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327432722] [2025-03-17 20:37:22,427 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 20:37:22,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,429 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,430 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,430 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:37:22,430 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,430 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:22,430 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,431 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,431 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,431 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,432 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:22,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:22,449 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:22,449 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:22,449 INFO L87 Difference]: Start difference. First operand 518 states and 798 transitions. cyclomatic complexity: 283 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:22,465 INFO L93 Difference]: Finished difference Result 573 states and 875 transitions. [2025-03-17 20:37:22,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 573 states and 875 transitions. [2025-03-17 20:37:22,468 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 367 [2025-03-17 20:37:22,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 573 states to 573 states and 875 transitions. [2025-03-17 20:37:22,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 414 [2025-03-17 20:37:22,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 414 [2025-03-17 20:37:22,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 573 states and 875 transitions. [2025-03-17 20:37:22,471 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 20:37:22,471 INFO L218 hiAutomatonCegarLoop]: Abstraction has 573 states and 875 transitions. [2025-03-17 20:37:22,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 573 states and 875 transitions. [2025-03-17 20:37:22,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 573 to 573. [2025-03-17 20:37:22,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 573 states, 573 states have (on average 1.5270506108202444) internal successors, (875), 572 states have internal predecessors, (875), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 573 states to 573 states and 875 transitions. [2025-03-17 20:37:22,482 INFO L240 hiAutomatonCegarLoop]: Abstraction has 573 states and 875 transitions. [2025-03-17 20:37:22,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:22,483 INFO L432 stractBuchiCegarLoop]: Abstraction has 573 states and 875 transitions. [2025-03-17 20:37:22,483 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-17 20:37:22,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 573 states and 875 transitions. [2025-03-17 20:37:22,486 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 367 [2025-03-17 20:37:22,486 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:22,486 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:22,486 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,486 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,486 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-17 20:37:22,486 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-17 20:37:22,487 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,487 INFO L85 PathProgramCache]: Analyzing trace with hash -1066070020, now seen corresponding path program 1 times [2025-03-17 20:37:22,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,487 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761759859] [2025-03-17 20:37:22,487 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:22,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,493 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-17 20:37:22,495 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-17 20:37:22,495 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,495 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:22,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:22,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:22,509 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1761759859] [2025-03-17 20:37:22,509 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1761759859] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:22,509 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:22,509 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:37:22,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1800912511] [2025-03-17 20:37:22,509 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:22,509 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:22,509 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,509 INFO L85 PathProgramCache]: Analyzing trace with hash 139593755, now seen corresponding path program 6 times [2025-03-17 20:37:22,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,510 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1118830422] [2025-03-17 20:37:22,510 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 20:37:22,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,512 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,512 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,512 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 20:37:22,512 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,512 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:22,513 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,513 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,513 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,513 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,515 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:22,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:22,538 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:22,538 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:22,538 INFO L87 Difference]: Start difference. First operand 573 states and 875 transitions. cyclomatic complexity: 305 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:22,558 INFO L93 Difference]: Finished difference Result 626 states and 945 transitions. [2025-03-17 20:37:22,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 945 transitions. [2025-03-17 20:37:22,561 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 406 [2025-03-17 20:37:22,564 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 945 transitions. [2025-03-17 20:37:22,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 450 [2025-03-17 20:37:22,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 450 [2025-03-17 20:37:22,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 945 transitions. [2025-03-17 20:37:22,566 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 20:37:22,566 INFO L218 hiAutomatonCegarLoop]: Abstraction has 626 states and 945 transitions. [2025-03-17 20:37:22,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 945 transitions. [2025-03-17 20:37:22,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2025-03-17 20:37:22,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.5095846645367412) internal successors, (945), 625 states have internal predecessors, (945), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 945 transitions. [2025-03-17 20:37:22,575 INFO L240 hiAutomatonCegarLoop]: Abstraction has 626 states and 945 transitions. [2025-03-17 20:37:22,575 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:22,576 INFO L432 stractBuchiCegarLoop]: Abstraction has 626 states and 945 transitions. [2025-03-17 20:37:22,576 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-17 20:37:22,576 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 945 transitions. [2025-03-17 20:37:22,578 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 406 [2025-03-17 20:37:22,578 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:22,578 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:22,579 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,579 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,579 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-17 20:37:22,579 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-17 20:37:22,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,580 INFO L85 PathProgramCache]: Analyzing trace with hash -1953573701, now seen corresponding path program 1 times [2025-03-17 20:37:22,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,580 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796063456] [2025-03-17 20:37:22,580 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:22,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,584 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-17 20:37:22,585 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-17 20:37:22,585 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,585 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:22,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:22,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:22,607 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796063456] [2025-03-17 20:37:22,607 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1796063456] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:22,607 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:22,607 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:37:22,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596415357] [2025-03-17 20:37:22,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:22,608 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:22,608 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,608 INFO L85 PathProgramCache]: Analyzing trace with hash 139593755, now seen corresponding path program 7 times [2025-03-17 20:37:22,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447926992] [2025-03-17 20:37:22,608 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 20:37:22,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,610 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,611 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,611 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,611 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,611 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:22,612 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,612 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,612 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,612 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,613 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:22,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:22,629 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:22,629 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:22,629 INFO L87 Difference]: Start difference. First operand 626 states and 945 transitions. cyclomatic complexity: 322 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:22,645 INFO L93 Difference]: Finished difference Result 715 states and 1071 transitions. [2025-03-17 20:37:22,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 715 states and 1071 transitions. [2025-03-17 20:37:22,649 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 466 [2025-03-17 20:37:22,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 715 states to 715 states and 1071 transitions. [2025-03-17 20:37:22,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 510 [2025-03-17 20:37:22,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 510 [2025-03-17 20:37:22,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 715 states and 1071 transitions. [2025-03-17 20:37:22,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 20:37:22,652 INFO L218 hiAutomatonCegarLoop]: Abstraction has 715 states and 1071 transitions. [2025-03-17 20:37:22,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 715 states and 1071 transitions. [2025-03-17 20:37:22,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 715 to 715. [2025-03-17 20:37:22,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 715 states, 715 states have (on average 1.4979020979020978) internal successors, (1071), 714 states have internal predecessors, (1071), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 715 states to 715 states and 1071 transitions. [2025-03-17 20:37:22,661 INFO L240 hiAutomatonCegarLoop]: Abstraction has 715 states and 1071 transitions. [2025-03-17 20:37:22,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:22,662 INFO L432 stractBuchiCegarLoop]: Abstraction has 715 states and 1071 transitions. [2025-03-17 20:37:22,662 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-17 20:37:22,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 715 states and 1071 transitions. [2025-03-17 20:37:22,665 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 466 [2025-03-17 20:37:22,665 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:22,665 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:22,665 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,665 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,665 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-17 20:37:22,665 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-17 20:37:22,666 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,666 INFO L85 PathProgramCache]: Analyzing trace with hash -1982202852, now seen corresponding path program 1 times [2025-03-17 20:37:22,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,666 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635082699] [2025-03-17 20:37:22,666 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:22,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,669 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-17 20:37:22,671 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-17 20:37:22,671 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,671 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:22,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:22,685 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:22,685 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635082699] [2025-03-17 20:37:22,685 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1635082699] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:22,685 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:22,685 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:37:22,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439705278] [2025-03-17 20:37:22,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:22,685 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:22,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,686 INFO L85 PathProgramCache]: Analyzing trace with hash 139593755, now seen corresponding path program 8 times [2025-03-17 20:37:22,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335669754] [2025-03-17 20:37:22,686 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:37:22,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,688 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,688 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,688 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:37:22,688 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,689 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:22,689 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,689 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,689 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,689 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,690 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:22,710 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:22,710 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:22,711 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:22,711 INFO L87 Difference]: Start difference. First operand 715 states and 1071 transitions. cyclomatic complexity: 359 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:22,727 INFO L93 Difference]: Finished difference Result 870 states and 1295 transitions. [2025-03-17 20:37:22,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 870 states and 1295 transitions. [2025-03-17 20:37:22,731 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 568 [2025-03-17 20:37:22,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 870 states to 870 states and 1295 transitions. [2025-03-17 20:37:22,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 612 [2025-03-17 20:37:22,735 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 612 [2025-03-17 20:37:22,735 INFO L73 IsDeterministic]: Start isDeterministic. Operand 870 states and 1295 transitions. [2025-03-17 20:37:22,735 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 20:37:22,735 INFO L218 hiAutomatonCegarLoop]: Abstraction has 870 states and 1295 transitions. [2025-03-17 20:37:22,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 870 states and 1295 transitions. [2025-03-17 20:37:22,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 870 to 870. [2025-03-17 20:37:22,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 870 states, 870 states have (on average 1.4885057471264367) internal successors, (1295), 869 states have internal predecessors, (1295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:22,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 870 states to 870 states and 1295 transitions. [2025-03-17 20:37:22,747 INFO L240 hiAutomatonCegarLoop]: Abstraction has 870 states and 1295 transitions. [2025-03-17 20:37:22,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:22,748 INFO L432 stractBuchiCegarLoop]: Abstraction has 870 states and 1295 transitions. [2025-03-17 20:37:22,748 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-17 20:37:22,748 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 870 states and 1295 transitions. [2025-03-17 20:37:22,751 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 568 [2025-03-17 20:37:22,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:22,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:22,751 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,751 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-17 20:37:22,752 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-17 20:37:22,752 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-17 20:37:22,752 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,752 INFO L85 PathProgramCache]: Analyzing trace with hash -1983126373, now seen corresponding path program 1 times [2025-03-17 20:37:22,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417038303] [2025-03-17 20:37:22,752 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:22,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,756 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-17 20:37:22,758 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-17 20:37:22,758 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,759 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,759 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:22,760 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-17 20:37:22,762 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-17 20:37:22,762 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,762 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,766 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:22,766 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,767 INFO L85 PathProgramCache]: Analyzing trace with hash 139593755, now seen corresponding path program 9 times [2025-03-17 20:37:22,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459434482] [2025-03-17 20:37:22,767 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:37:22,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,769 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,769 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,769 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:37:22,769 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,770 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:22,770 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-17 20:37:22,771 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-17 20:37:22,771 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,771 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,772 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:22,772 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:22,772 INFO L85 PathProgramCache]: Analyzing trace with hash -1390243531, now seen corresponding path program 1 times [2025-03-17 20:37:22,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:22,772 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358769252] [2025-03-17 20:37:22,772 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:22,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:22,776 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-17 20:37:22,779 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-17 20:37:22,779 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,779 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,779 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:22,780 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-17 20:37:22,782 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-17 20:37:22,782 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:22,782 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:22,786 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:23,341 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-17 20:37:23,345 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-17 20:37:23,345 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:23,345 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:23,345 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:23,355 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-17 20:37:23,358 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-17 20:37:23,358 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:23,358 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:23,430 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.03 08:37:23 BoogieIcfgContainer [2025-03-17 20:37:23,431 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-17 20:37:23,431 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-17 20:37:23,431 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-17 20:37:23,431 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-17 20:37:23,432 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:37:19" (3/4) ... [2025-03-17 20:37:23,433 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-03-17 20:37:23,486 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-17 20:37:23,486 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-17 20:37:23,487 INFO L158 Benchmark]: Toolchain (without parser) took 4935.58ms. Allocated memory was 142.6MB in the beginning and 310.4MB in the end (delta: 167.8MB). Free memory was 111.2MB in the beginning and 111.4MB in the end (delta: -176.2kB). Peak memory consumption was 167.9MB. Max. memory is 16.1GB. [2025-03-17 20:37:23,487 INFO L158 Benchmark]: CDTParser took 0.24ms. Allocated memory is still 201.3MB. Free memory is still 128.6MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 20:37:23,487 INFO L158 Benchmark]: CACSL2BoogieTranslator took 193.65ms. Allocated memory is still 142.6MB. Free memory was 111.2MB in the beginning and 97.9MB in the end (delta: 13.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-17 20:37:23,487 INFO L158 Benchmark]: Boogie Procedure Inliner took 34.35ms. Allocated memory is still 142.6MB. Free memory was 97.9MB in the beginning and 96.1MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 20:37:23,488 INFO L158 Benchmark]: Boogie Preprocessor took 34.19ms. Allocated memory is still 142.6MB. Free memory was 96.1MB in the beginning and 94.3MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 20:37:23,489 INFO L158 Benchmark]: IcfgBuilder took 435.82ms. Allocated memory is still 142.6MB. Free memory was 94.3MB in the beginning and 71.8MB in the end (delta: 22.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2025-03-17 20:37:23,490 INFO L158 Benchmark]: BuchiAutomizer took 4178.38ms. Allocated memory was 142.6MB in the beginning and 310.4MB in the end (delta: 167.8MB). Free memory was 71.8MB in the beginning and 118.3MB in the end (delta: -46.4MB). Peak memory consumption was 117.6MB. Max. memory is 16.1GB. [2025-03-17 20:37:23,490 INFO L158 Benchmark]: Witness Printer took 55.16ms. Allocated memory is still 310.4MB. Free memory was 116.9MB in the beginning and 111.4MB in the end (delta: 5.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-17 20:37:23,491 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24ms. Allocated memory is still 201.3MB. Free memory is still 128.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 193.65ms. Allocated memory is still 142.6MB. Free memory was 111.2MB in the beginning and 97.9MB in the end (delta: 13.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 34.35ms. Allocated memory is still 142.6MB. Free memory was 97.9MB in the beginning and 96.1MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 34.19ms. Allocated memory is still 142.6MB. Free memory was 96.1MB in the beginning and 94.3MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 435.82ms. Allocated memory is still 142.6MB. Free memory was 94.3MB in the beginning and 71.8MB in the end (delta: 22.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 4178.38ms. Allocated memory was 142.6MB in the beginning and 310.4MB in the end (delta: 167.8MB). Free memory was 71.8MB in the beginning and 118.3MB in the end (delta: -46.4MB). Peak memory consumption was 117.6MB. Max. memory is 16.1GB. * Witness Printer took 55.16ms. Allocated memory is still 310.4MB. Free memory was 116.9MB in the beginning and 111.4MB in the end (delta: 5.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 19 terminating modules (18 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * d1_ev) + 1) and consists of 3 locations. 18 modules have a trivial ranking function, the largest among these consists of 4 locations. The remainder module has 870 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.0s and 19 iterations. TraceHistogramMax:1. Analysis of lassos took 3.1s. Construction of modules took 0.1s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 3. Minimization of det autom 9. Minimization of nondet autom 10. Automata minimization 0.1s AutomataMinimizationTime, 19 MinimizatonAttempts, 6 StatesRemovedByMinimization, 2 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 555 SdHoareTripleChecker+Valid, 0.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 554 mSDsluCounter, 5754 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2739 mSDsCounter, 36 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 185 IncrementalHoareTripleChecker+Invalid, 221 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 36 mSolverCounterUnsat, 3015 mSDtfsCounter, 185 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT0 conc0 concLT0 SILN8 SILU0 SILI9 SILT1 lasso0 LassoPreprocessingBenchmarks: Lassos: inital59 mio100 ax100 hnf100 lsp15 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq188 hnf94 smp100 dnf137 smp100 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 21ms VariablesStem: 0 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 2 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 285]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 285]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-03-17 20:37:23,507 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)