./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/kundu.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8fc3dc66 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/kundu.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb --- Real Ultimate output --- This is Ultimate 0.3.0-?-8fc3dc6-m [2025-03-17 20:37:22,059 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-17 20:37:22,114 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-17 20:37:22,118 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-17 20:37:22,119 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-17 20:37:22,119 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-17 20:37:22,141 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-17 20:37:22,142 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-17 20:37:22,142 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-17 20:37:22,142 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-17 20:37:22,143 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-17 20:37:22,143 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-17 20:37:22,144 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-17 20:37:22,144 INFO L153 SettingsManager]: * Use SBE=true [2025-03-17 20:37:22,144 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-17 20:37:22,144 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-17 20:37:22,144 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-17 20:37:22,144 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-17 20:37:22,144 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-17 20:37:22,144 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-17 20:37:22,145 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-17 20:37:22,145 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-17 20:37:22,145 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-17 20:37:22,145 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-17 20:37:22,145 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-17 20:37:22,145 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-17 20:37:22,145 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-17 20:37:22,145 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-17 20:37:22,145 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-17 20:37:22,145 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-17 20:37:22,146 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-17 20:37:22,146 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-17 20:37:22,146 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-17 20:37:22,146 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-17 20:37:22,146 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-17 20:37:22,146 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-17 20:37:22,146 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-17 20:37:22,146 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-17 20:37:22,146 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-17 20:37:22,147 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-17 20:37:22,147 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb [2025-03-17 20:37:22,402 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-17 20:37:22,410 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-17 20:37:22,412 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-17 20:37:22,413 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-17 20:37:22,413 INFO L274 PluginConnector]: CDTParser initialized [2025-03-17 20:37:22,414 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/kundu.cil.c [2025-03-17 20:37:23,588 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ae67f2134/e70a63abd71b44d68373d488e16ffc2a/FLAGd30d179a6 [2025-03-17 20:37:23,815 INFO L384 CDTParser]: Found 1 translation units. [2025-03-17 20:37:23,815 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu.cil.c [2025-03-17 20:37:23,822 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ae67f2134/e70a63abd71b44d68373d488e16ffc2a/FLAGd30d179a6 [2025-03-17 20:37:23,832 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ae67f2134/e70a63abd71b44d68373d488e16ffc2a [2025-03-17 20:37:23,835 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-17 20:37:23,836 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-17 20:37:23,837 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-17 20:37:23,837 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-17 20:37:23,840 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-17 20:37:23,841 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 08:37:23" (1/1) ... [2025-03-17 20:37:23,841 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3d223daa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:23, skipping insertion in model container [2025-03-17 20:37:23,842 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 08:37:23" (1/1) ... [2025-03-17 20:37:23,871 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-17 20:37:24,028 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 20:37:24,042 INFO L200 MainTranslator]: Completed pre-run [2025-03-17 20:37:24,072 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 20:37:24,092 INFO L204 MainTranslator]: Completed translation [2025-03-17 20:37:24,093 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24 WrapperNode [2025-03-17 20:37:24,093 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-17 20:37:24,094 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-17 20:37:24,094 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-17 20:37:24,094 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-17 20:37:24,099 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (1/1) ... [2025-03-17 20:37:24,106 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (1/1) ... [2025-03-17 20:37:24,136 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 49, statements flattened = 525 [2025-03-17 20:37:24,139 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-17 20:37:24,139 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-17 20:37:24,139 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-17 20:37:24,140 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-17 20:37:24,146 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (1/1) ... [2025-03-17 20:37:24,146 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (1/1) ... [2025-03-17 20:37:24,148 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (1/1) ... [2025-03-17 20:37:24,165 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-17 20:37:24,167 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (1/1) ... [2025-03-17 20:37:24,167 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (1/1) ... [2025-03-17 20:37:24,172 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (1/1) ... [2025-03-17 20:37:24,173 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (1/1) ... [2025-03-17 20:37:24,174 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (1/1) ... [2025-03-17 20:37:24,175 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (1/1) ... [2025-03-17 20:37:24,176 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-17 20:37:24,177 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-17 20:37:24,177 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-17 20:37:24,177 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-17 20:37:24,178 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (1/1) ... [2025-03-17 20:37:24,181 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:37:24,191 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 20:37:24,203 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 20:37:24,206 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-17 20:37:24,223 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-17 20:37:24,223 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-17 20:37:24,223 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-17 20:37:24,223 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-17 20:37:24,280 INFO L256 CfgBuilder]: Building ICFG [2025-03-17 20:37:24,282 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-17 20:37:24,668 INFO L? ?]: Removed 78 outVars from TransFormulas that were not future-live. [2025-03-17 20:37:24,668 INFO L307 CfgBuilder]: Performing block encoding [2025-03-17 20:37:24,678 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-17 20:37:24,678 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-17 20:37:24,678 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:37:24 BoogieIcfgContainer [2025-03-17 20:37:24,678 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-17 20:37:24,679 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-17 20:37:24,679 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-17 20:37:24,682 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-17 20:37:24,683 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 20:37:24,683 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.03 08:37:23" (1/3) ... [2025-03-17 20:37:24,684 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3cc4d5dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 08:37:24, skipping insertion in model container [2025-03-17 20:37:24,684 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 20:37:24,684 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:24" (2/3) ... [2025-03-17 20:37:24,684 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3cc4d5dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 08:37:24, skipping insertion in model container [2025-03-17 20:37:24,684 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 20:37:24,684 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:37:24" (3/3) ... [2025-03-17 20:37:24,685 INFO L363 chiAutomizerObserver]: Analyzing ICFG kundu.cil.c [2025-03-17 20:37:24,725 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-17 20:37:24,726 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-17 20:37:24,726 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-17 20:37:24,726 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-17 20:37:24,726 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-17 20:37:24,727 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-17 20:37:24,727 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-17 20:37:24,727 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-17 20:37:24,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 149 states, 148 states have (on average 1.614864864864865) internal successors, (239), 148 states have internal predecessors, (239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:24,748 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 121 [2025-03-17 20:37:24,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:24,748 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:24,753 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:24,754 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:24,754 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-17 20:37:24,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 149 states, 148 states have (on average 1.614864864864865) internal successors, (239), 148 states have internal predecessors, (239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:24,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 121 [2025-03-17 20:37:24,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:24,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:24,760 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:24,761 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:24,766 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~P_1_i~0);~P_1_st~0 := 2;" "assume !(1 == ~P_2_i~0);~P_2_st~0 := 2;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:24,766 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume !true;" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-17 20:37:24,769 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:24,769 INFO L85 PathProgramCache]: Analyzing trace with hash -683479608, now seen corresponding path program 1 times [2025-03-17 20:37:24,774 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:24,774 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744338095] [2025-03-17 20:37:24,774 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:24,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:24,822 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-03-17 20:37:24,837 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-03-17 20:37:24,838 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:24,838 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:24,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:24,919 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:24,919 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744338095] [2025-03-17 20:37:24,920 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744338095] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:24,920 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:24,920 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:24,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732197897] [2025-03-17 20:37:24,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:24,925 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:24,926 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:24,927 INFO L85 PathProgramCache]: Analyzing trace with hash -1668356368, now seen corresponding path program 1 times [2025-03-17 20:37:24,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:24,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [528046326] [2025-03-17 20:37:24,927 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:24,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:24,937 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-17 20:37:24,938 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-17 20:37:24,938 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:24,938 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:24,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:24,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:24,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [528046326] [2025-03-17 20:37:24,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [528046326] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:24,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:24,950 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:24,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1002571141] [2025-03-17 20:37:24,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:24,955 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:24,956 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:24,975 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:24,975 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:24,978 INFO L87 Difference]: Start difference. First operand has 149 states, 148 states have (on average 1.614864864864865) internal successors, (239), 148 states have internal predecessors, (239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 6.666666666666667) internal successors, (20), 2 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:25,003 INFO L93 Difference]: Finished difference Result 149 states and 232 transitions. [2025-03-17 20:37:25,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 149 states and 232 transitions. [2025-03-17 20:37:25,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 121 [2025-03-17 20:37:25,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 149 states to 146 states and 229 transitions. [2025-03-17 20:37:25,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146 [2025-03-17 20:37:25,020 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146 [2025-03-17 20:37:25,020 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146 states and 229 transitions. [2025-03-17 20:37:25,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:25,021 INFO L218 hiAutomatonCegarLoop]: Abstraction has 146 states and 229 transitions. [2025-03-17 20:37:25,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states and 229 transitions. [2025-03-17 20:37:25,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2025-03-17 20:37:25,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146 states, 146 states have (on average 1.5684931506849316) internal successors, (229), 145 states have internal predecessors, (229), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 229 transitions. [2025-03-17 20:37:25,053 INFO L240 hiAutomatonCegarLoop]: Abstraction has 146 states and 229 transitions. [2025-03-17 20:37:25,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:25,057 INFO L432 stractBuchiCegarLoop]: Abstraction has 146 states and 229 transitions. [2025-03-17 20:37:25,058 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-17 20:37:25,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146 states and 229 transitions. [2025-03-17 20:37:25,060 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 121 [2025-03-17 20:37:25,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:25,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:25,063 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,063 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,063 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume !(1 == ~P_2_i~0);~P_2_st~0 := 2;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:25,063 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-17 20:37:25,064 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,064 INFO L85 PathProgramCache]: Analyzing trace with hash 160992263, now seen corresponding path program 1 times [2025-03-17 20:37:25,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [571367291] [2025-03-17 20:37:25,064 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:25,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,073 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-03-17 20:37:25,077 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-03-17 20:37:25,077 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,077 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:25,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:25,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:25,114 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [571367291] [2025-03-17 20:37:25,114 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [571367291] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:25,114 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:25,114 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:25,114 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053227223] [2025-03-17 20:37:25,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:25,114 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:25,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,114 INFO L85 PathProgramCache]: Analyzing trace with hash 1689156743, now seen corresponding path program 1 times [2025-03-17 20:37:25,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1604017465] [2025-03-17 20:37:25,115 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:25,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,123 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-17 20:37:25,134 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-17 20:37:25,134 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,134 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:25,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:25,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:25,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1604017465] [2025-03-17 20:37:25,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1604017465] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:25,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:25,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:25,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845449049] [2025-03-17 20:37:25,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:25,197 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:25,197 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:25,198 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:25,198 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:25,198 INFO L87 Difference]: Start difference. First operand 146 states and 229 transitions. cyclomatic complexity: 84 Second operand has 3 states, 3 states have (on average 6.666666666666667) internal successors, (20), 2 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:25,207 INFO L93 Difference]: Finished difference Result 146 states and 228 transitions. [2025-03-17 20:37:25,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 146 states and 228 transitions. [2025-03-17 20:37:25,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 121 [2025-03-17 20:37:25,209 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 146 states to 146 states and 228 transitions. [2025-03-17 20:37:25,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146 [2025-03-17 20:37:25,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146 [2025-03-17 20:37:25,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146 states and 228 transitions. [2025-03-17 20:37:25,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:25,210 INFO L218 hiAutomatonCegarLoop]: Abstraction has 146 states and 228 transitions. [2025-03-17 20:37:25,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states and 228 transitions. [2025-03-17 20:37:25,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2025-03-17 20:37:25,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146 states, 146 states have (on average 1.5616438356164384) internal successors, (228), 145 states have internal predecessors, (228), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 228 transitions. [2025-03-17 20:37:25,216 INFO L240 hiAutomatonCegarLoop]: Abstraction has 146 states and 228 transitions. [2025-03-17 20:37:25,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:25,217 INFO L432 stractBuchiCegarLoop]: Abstraction has 146 states and 228 transitions. [2025-03-17 20:37:25,218 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-17 20:37:25,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146 states and 228 transitions. [2025-03-17 20:37:25,219 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 121 [2025-03-17 20:37:25,219 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:25,219 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:25,220 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,220 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,220 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:25,220 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-17 20:37:25,221 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,221 INFO L85 PathProgramCache]: Analyzing trace with hash 1158064616, now seen corresponding path program 1 times [2025-03-17 20:37:25,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,221 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675310598] [2025-03-17 20:37:25,221 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:25,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,226 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-03-17 20:37:25,232 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-03-17 20:37:25,232 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,232 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:25,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:25,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:25,274 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [675310598] [2025-03-17 20:37:25,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [675310598] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:25,274 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:25,274 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:25,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636774764] [2025-03-17 20:37:25,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:25,274 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:25,275 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,275 INFO L85 PathProgramCache]: Analyzing trace with hash 1689156743, now seen corresponding path program 2 times [2025-03-17 20:37:25,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130185241] [2025-03-17 20:37:25,275 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:37:25,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,281 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 30 statements into 1 equivalence classes. [2025-03-17 20:37:25,290 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-17 20:37:25,290 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:37:25,290 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:25,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:25,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:25,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130185241] [2025-03-17 20:37:25,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130185241] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:25,328 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:25,328 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:25,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940158113] [2025-03-17 20:37:25,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:25,328 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:25,328 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:25,329 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:25,329 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:25,329 INFO L87 Difference]: Start difference. First operand 146 states and 228 transitions. cyclomatic complexity: 83 Second operand has 3 states, 3 states have (on average 6.666666666666667) internal successors, (20), 2 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:25,337 INFO L93 Difference]: Finished difference Result 146 states and 227 transitions. [2025-03-17 20:37:25,337 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 146 states and 227 transitions. [2025-03-17 20:37:25,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 121 [2025-03-17 20:37:25,339 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 146 states to 146 states and 227 transitions. [2025-03-17 20:37:25,339 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146 [2025-03-17 20:37:25,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146 [2025-03-17 20:37:25,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146 states and 227 transitions. [2025-03-17 20:37:25,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:25,340 INFO L218 hiAutomatonCegarLoop]: Abstraction has 146 states and 227 transitions. [2025-03-17 20:37:25,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states and 227 transitions. [2025-03-17 20:37:25,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2025-03-17 20:37:25,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146 states, 146 states have (on average 1.5547945205479452) internal successors, (227), 145 states have internal predecessors, (227), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 227 transitions. [2025-03-17 20:37:25,347 INFO L240 hiAutomatonCegarLoop]: Abstraction has 146 states and 227 transitions. [2025-03-17 20:37:25,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:25,349 INFO L432 stractBuchiCegarLoop]: Abstraction has 146 states and 227 transitions. [2025-03-17 20:37:25,349 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-17 20:37:25,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146 states and 227 transitions. [2025-03-17 20:37:25,350 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 121 [2025-03-17 20:37:25,350 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:25,350 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:25,351 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,351 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,351 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:25,351 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-17 20:37:25,351 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,351 INFO L85 PathProgramCache]: Analyzing trace with hash -195245081, now seen corresponding path program 1 times [2025-03-17 20:37:25,352 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,352 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406131612] [2025-03-17 20:37:25,352 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:25,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,360 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-03-17 20:37:25,362 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-03-17 20:37:25,362 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,362 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:25,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:25,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:25,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406131612] [2025-03-17 20:37:25,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [406131612] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:25,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:25,385 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:25,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917537442] [2025-03-17 20:37:25,385 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:25,385 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:25,385 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,385 INFO L85 PathProgramCache]: Analyzing trace with hash -867378972, now seen corresponding path program 1 times [2025-03-17 20:37:25,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,386 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151917447] [2025-03-17 20:37:25,386 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:25,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,394 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-17 20:37:25,397 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-17 20:37:25,398 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,398 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:25,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:25,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:25,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151917447] [2025-03-17 20:37:25,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1151917447] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:25,426 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:25,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:25,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935162537] [2025-03-17 20:37:25,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:25,427 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:25,427 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:25,427 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:25,427 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:25,427 INFO L87 Difference]: Start difference. First operand 146 states and 227 transitions. cyclomatic complexity: 82 Second operand has 3 states, 3 states have (on average 6.666666666666667) internal successors, (20), 2 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:25,469 INFO L93 Difference]: Finished difference Result 263 states and 405 transitions. [2025-03-17 20:37:25,469 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 263 states and 405 transitions. [2025-03-17 20:37:25,470 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 239 [2025-03-17 20:37:25,472 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 263 states to 263 states and 405 transitions. [2025-03-17 20:37:25,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 263 [2025-03-17 20:37:25,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 263 [2025-03-17 20:37:25,472 INFO L73 IsDeterministic]: Start isDeterministic. Operand 263 states and 405 transitions. [2025-03-17 20:37:25,474 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:25,477 INFO L218 hiAutomatonCegarLoop]: Abstraction has 263 states and 405 transitions. [2025-03-17 20:37:25,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 263 states and 405 transitions. [2025-03-17 20:37:25,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 263 to 260. [2025-03-17 20:37:25,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 260 states, 260 states have (on average 1.5423076923076924) internal successors, (401), 259 states have internal predecessors, (401), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 260 states to 260 states and 401 transitions. [2025-03-17 20:37:25,489 INFO L240 hiAutomatonCegarLoop]: Abstraction has 260 states and 401 transitions. [2025-03-17 20:37:25,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:25,490 INFO L432 stractBuchiCegarLoop]: Abstraction has 260 states and 401 transitions. [2025-03-17 20:37:25,490 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-17 20:37:25,490 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 260 states and 401 transitions. [2025-03-17 20:37:25,491 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 236 [2025-03-17 20:37:25,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:25,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:25,491 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,491 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,492 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:25,492 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-17 20:37:25,493 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,493 INFO L85 PathProgramCache]: Analyzing trace with hash -1971543318, now seen corresponding path program 1 times [2025-03-17 20:37:25,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,493 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520908384] [2025-03-17 20:37:25,493 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:25,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,498 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-03-17 20:37:25,500 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-03-17 20:37:25,500 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,500 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:25,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:25,514 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:25,514 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520908384] [2025-03-17 20:37:25,514 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [520908384] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:25,514 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:25,514 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:25,514 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1044237665] [2025-03-17 20:37:25,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:25,515 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:25,515 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,515 INFO L85 PathProgramCache]: Analyzing trace with hash 282293863, now seen corresponding path program 1 times [2025-03-17 20:37:25,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825003449] [2025-03-17 20:37:25,515 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:25,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,520 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-17 20:37:25,521 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-17 20:37:25,521 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,521 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:25,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:25,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:25,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1825003449] [2025-03-17 20:37:25,547 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1825003449] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:25,547 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:25,547 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:25,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859979859] [2025-03-17 20:37:25,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:25,548 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:25,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:25,548 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:25,548 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:25,548 INFO L87 Difference]: Start difference. First operand 260 states and 401 transitions. cyclomatic complexity: 142 Second operand has 3 states, 3 states have (on average 6.666666666666667) internal successors, (20), 2 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:25,581 INFO L93 Difference]: Finished difference Result 489 states and 746 transitions. [2025-03-17 20:37:25,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 489 states and 746 transitions. [2025-03-17 20:37:25,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 466 [2025-03-17 20:37:25,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 489 states to 489 states and 746 transitions. [2025-03-17 20:37:25,590 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 489 [2025-03-17 20:37:25,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 489 [2025-03-17 20:37:25,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 489 states and 746 transitions. [2025-03-17 20:37:25,591 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:25,591 INFO L218 hiAutomatonCegarLoop]: Abstraction has 489 states and 746 transitions. [2025-03-17 20:37:25,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 489 states and 746 transitions. [2025-03-17 20:37:25,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 489 to 463. [2025-03-17 20:37:25,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 463 states, 463 states have (on average 1.529157667386609) internal successors, (708), 462 states have internal predecessors, (708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 708 transitions. [2025-03-17 20:37:25,612 INFO L240 hiAutomatonCegarLoop]: Abstraction has 463 states and 708 transitions. [2025-03-17 20:37:25,612 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:25,612 INFO L432 stractBuchiCegarLoop]: Abstraction has 463 states and 708 transitions. [2025-03-17 20:37:25,612 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-17 20:37:25,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 463 states and 708 transitions. [2025-03-17 20:37:25,614 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 440 [2025-03-17 20:37:25,614 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:25,615 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:25,615 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,615 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,615 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:25,615 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-17 20:37:25,616 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,616 INFO L85 PathProgramCache]: Analyzing trace with hash 1446852103, now seen corresponding path program 1 times [2025-03-17 20:37:25,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2036551892] [2025-03-17 20:37:25,617 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:25,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,622 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-03-17 20:37:25,625 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-03-17 20:37:25,626 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,626 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:25,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:25,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:25,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2036551892] [2025-03-17 20:37:25,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2036551892] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:25,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:25,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:25,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2037021395] [2025-03-17 20:37:25,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:25,646 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:37:25,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,646 INFO L85 PathProgramCache]: Analyzing trace with hash 282293863, now seen corresponding path program 2 times [2025-03-17 20:37:25,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879089670] [2025-03-17 20:37:25,646 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:37:25,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,651 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 30 statements into 1 equivalence classes. [2025-03-17 20:37:25,654 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-17 20:37:25,654 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:37:25,654 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:25,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:25,679 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:25,680 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879089670] [2025-03-17 20:37:25,680 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1879089670] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:25,680 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:25,680 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:25,680 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368170198] [2025-03-17 20:37:25,680 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:25,680 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:25,680 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:25,680 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:25,680 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:25,683 INFO L87 Difference]: Start difference. First operand 463 states and 708 transitions. cyclomatic complexity: 246 Second operand has 3 states, 3 states have (on average 6.666666666666667) internal successors, (20), 2 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:25,728 INFO L93 Difference]: Finished difference Result 873 states and 1300 transitions. [2025-03-17 20:37:25,728 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 873 states and 1300 transitions. [2025-03-17 20:37:25,733 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 852 [2025-03-17 20:37:25,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 873 states to 873 states and 1300 transitions. [2025-03-17 20:37:25,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 873 [2025-03-17 20:37:25,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 873 [2025-03-17 20:37:25,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 873 states and 1300 transitions. [2025-03-17 20:37:25,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:25,739 INFO L218 hiAutomatonCegarLoop]: Abstraction has 873 states and 1300 transitions. [2025-03-17 20:37:25,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 873 states and 1300 transitions. [2025-03-17 20:37:25,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 873 to 845. [2025-03-17 20:37:25,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 845 states, 845 states have (on average 1.4958579881656804) internal successors, (1264), 844 states have internal predecessors, (1264), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 845 states to 845 states and 1264 transitions. [2025-03-17 20:37:25,754 INFO L240 hiAutomatonCegarLoop]: Abstraction has 845 states and 1264 transitions. [2025-03-17 20:37:25,755 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:25,756 INFO L432 stractBuchiCegarLoop]: Abstraction has 845 states and 1264 transitions. [2025-03-17 20:37:25,756 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-17 20:37:25,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 845 states and 1264 transitions. [2025-03-17 20:37:25,759 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 824 [2025-03-17 20:37:25,759 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:25,759 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:25,762 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,762 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,763 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:25,763 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-17 20:37:25,763 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,763 INFO L85 PathProgramCache]: Analyzing trace with hash 1929555402, now seen corresponding path program 1 times [2025-03-17 20:37:25,763 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,763 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504385813] [2025-03-17 20:37:25,763 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:25,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,770 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-17 20:37:25,772 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-17 20:37:25,773 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,773 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:25,773 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:25,774 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-17 20:37:25,779 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-17 20:37:25,779 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,779 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:25,797 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:25,798 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,798 INFO L85 PathProgramCache]: Analyzing trace with hash -1282026752, now seen corresponding path program 1 times [2025-03-17 20:37:25,799 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,799 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588050532] [2025-03-17 20:37:25,799 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:25,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,829 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-17 20:37:25,832 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-17 20:37:25,833 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,833 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:25,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:25,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:25,862 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1588050532] [2025-03-17 20:37:25,862 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1588050532] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:25,862 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:25,862 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:25,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463839112] [2025-03-17 20:37:25,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:25,862 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:25,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:25,863 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:37:25,863 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:37:25,863 INFO L87 Difference]: Start difference. First operand 845 states and 1264 transitions. cyclomatic complexity: 420 Second operand has 4 states, 4 states have (on average 7.75) internal successors, (31), 4 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:25,909 INFO L93 Difference]: Finished difference Result 869 states and 1279 transitions. [2025-03-17 20:37:25,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 869 states and 1279 transitions. [2025-03-17 20:37:25,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 848 [2025-03-17 20:37:25,916 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 869 states to 869 states and 1279 transitions. [2025-03-17 20:37:25,916 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 869 [2025-03-17 20:37:25,917 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 869 [2025-03-17 20:37:25,917 INFO L73 IsDeterministic]: Start isDeterministic. Operand 869 states and 1279 transitions. [2025-03-17 20:37:25,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:25,918 INFO L218 hiAutomatonCegarLoop]: Abstraction has 869 states and 1279 transitions. [2025-03-17 20:37:25,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 869 states and 1279 transitions. [2025-03-17 20:37:25,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 869 to 869. [2025-03-17 20:37:25,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 869 states, 869 states have (on average 1.4718066743383198) internal successors, (1279), 868 states have internal predecessors, (1279), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:25,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 869 states to 869 states and 1279 transitions. [2025-03-17 20:37:25,930 INFO L240 hiAutomatonCegarLoop]: Abstraction has 869 states and 1279 transitions. [2025-03-17 20:37:25,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:37:25,932 INFO L432 stractBuchiCegarLoop]: Abstraction has 869 states and 1279 transitions. [2025-03-17 20:37:25,932 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-17 20:37:25,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 869 states and 1279 transitions. [2025-03-17 20:37:25,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 848 [2025-03-17 20:37:25,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:25,936 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:25,936 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,936 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:25,936 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:25,936 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-17 20:37:25,937 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,937 INFO L85 PathProgramCache]: Analyzing trace with hash 1929555402, now seen corresponding path program 2 times [2025-03-17 20:37:25,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,937 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968347355] [2025-03-17 20:37:25,937 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:37:25,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,941 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 21 statements into 1 equivalence classes. [2025-03-17 20:37:25,945 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-17 20:37:25,946 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:37:25,946 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:25,946 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:25,948 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-17 20:37:25,950 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-17 20:37:25,950 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,950 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:25,954 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:25,954 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:25,954 INFO L85 PathProgramCache]: Analyzing trace with hash 71282945, now seen corresponding path program 1 times [2025-03-17 20:37:25,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:25,955 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043777584] [2025-03-17 20:37:25,955 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:25,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:25,960 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-17 20:37:25,963 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-17 20:37:25,963 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:25,963 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:25,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:25,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:25,985 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043777584] [2025-03-17 20:37:25,985 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043777584] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:25,985 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:25,985 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:25,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949226026] [2025-03-17 20:37:25,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:25,985 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:25,986 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:25,986 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:37:25,986 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:37:25,986 INFO L87 Difference]: Start difference. First operand 869 states and 1279 transitions. cyclomatic complexity: 411 Second operand has 4 states, 4 states have (on average 7.75) internal successors, (31), 4 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:26,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:26,034 INFO L93 Difference]: Finished difference Result 889 states and 1288 transitions. [2025-03-17 20:37:26,034 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 889 states and 1288 transitions. [2025-03-17 20:37:26,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 868 [2025-03-17 20:37:26,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 889 states to 889 states and 1288 transitions. [2025-03-17 20:37:26,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 889 [2025-03-17 20:37:26,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 889 [2025-03-17 20:37:26,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 889 states and 1288 transitions. [2025-03-17 20:37:26,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:26,044 INFO L218 hiAutomatonCegarLoop]: Abstraction has 889 states and 1288 transitions. [2025-03-17 20:37:26,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 889 states and 1288 transitions. [2025-03-17 20:37:26,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 889 to 889. [2025-03-17 20:37:26,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 889 states, 889 states have (on average 1.4488188976377954) internal successors, (1288), 888 states have internal predecessors, (1288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:26,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 889 states to 889 states and 1288 transitions. [2025-03-17 20:37:26,055 INFO L240 hiAutomatonCegarLoop]: Abstraction has 889 states and 1288 transitions. [2025-03-17 20:37:26,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:37:26,057 INFO L432 stractBuchiCegarLoop]: Abstraction has 889 states and 1288 transitions. [2025-03-17 20:37:26,058 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-17 20:37:26,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 889 states and 1288 transitions. [2025-03-17 20:37:26,061 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 868 [2025-03-17 20:37:26,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:26,061 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:26,062 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:26,062 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:26,062 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:26,062 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-17 20:37:26,062 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,063 INFO L85 PathProgramCache]: Analyzing trace with hash 1929555402, now seen corresponding path program 3 times [2025-03-17 20:37:26,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,063 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878755057] [2025-03-17 20:37:26,063 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:37:26,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,069 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 21 statements into 1 equivalence classes. [2025-03-17 20:37:26,071 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-17 20:37:26,072 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:37:26,072 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,072 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:26,074 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-17 20:37:26,075 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-17 20:37:26,076 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,076 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,078 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:26,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,080 INFO L85 PathProgramCache]: Analyzing trace with hash -1725668414, now seen corresponding path program 1 times [2025-03-17 20:37:26,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920975049] [2025-03-17 20:37:26,080 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:26,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,087 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-17 20:37:26,088 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-17 20:37:26,088 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,088 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:26,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:26,123 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:26,123 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [920975049] [2025-03-17 20:37:26,123 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [920975049] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:26,123 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:26,123 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:26,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1468342322] [2025-03-17 20:37:26,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:26,124 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:26,124 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:26,124 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:37:26,124 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:37:26,124 INFO L87 Difference]: Start difference. First operand 889 states and 1288 transitions. cyclomatic complexity: 400 Second operand has 4 states, 4 states have (on average 7.75) internal successors, (31), 4 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:26,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:26,155 INFO L93 Difference]: Finished difference Result 921 states and 1320 transitions. [2025-03-17 20:37:26,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 921 states and 1320 transitions. [2025-03-17 20:37:26,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 900 [2025-03-17 20:37:26,162 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 921 states to 921 states and 1320 transitions. [2025-03-17 20:37:26,162 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 921 [2025-03-17 20:37:26,162 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 921 [2025-03-17 20:37:26,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 921 states and 1320 transitions. [2025-03-17 20:37:26,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:26,163 INFO L218 hiAutomatonCegarLoop]: Abstraction has 921 states and 1320 transitions. [2025-03-17 20:37:26,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 921 states and 1320 transitions. [2025-03-17 20:37:26,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 921 to 905. [2025-03-17 20:37:26,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 905 states, 905 states have (on average 1.4408839779005524) internal successors, (1304), 904 states have internal predecessors, (1304), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:26,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 905 states to 905 states and 1304 transitions. [2025-03-17 20:37:26,174 INFO L240 hiAutomatonCegarLoop]: Abstraction has 905 states and 1304 transitions. [2025-03-17 20:37:26,174 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:37:26,174 INFO L432 stractBuchiCegarLoop]: Abstraction has 905 states and 1304 transitions. [2025-03-17 20:37:26,174 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-17 20:37:26,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 905 states and 1304 transitions. [2025-03-17 20:37:26,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 884 [2025-03-17 20:37:26,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:26,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:26,179 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:26,179 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:26,179 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:26,179 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume !(0 == ~P_1_st~0);" "assume !(0 == ~P_2_st~0);" "assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-17 20:37:26,180 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,180 INFO L85 PathProgramCache]: Analyzing trace with hash 1929555402, now seen corresponding path program 4 times [2025-03-17 20:37:26,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,180 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1620308128] [2025-03-17 20:37:26,180 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 20:37:26,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,186 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 21 statements into 2 equivalence classes. [2025-03-17 20:37:26,188 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 21 of 21 statements. [2025-03-17 20:37:26,188 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 20:37:26,188 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,188 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:26,190 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-17 20:37:26,192 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-17 20:37:26,193 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,194 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,199 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:26,199 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,200 INFO L85 PathProgramCache]: Analyzing trace with hash -232424981, now seen corresponding path program 1 times [2025-03-17 20:37:26,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143040545] [2025-03-17 20:37:26,200 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:26,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,205 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:26,206 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:26,206 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,206 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:26,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:26,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:26,234 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143040545] [2025-03-17 20:37:26,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143040545] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:26,234 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:26,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:37:26,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [900053477] [2025-03-17 20:37:26,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:26,234 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:26,234 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:26,235 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:37:26,235 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:37:26,235 INFO L87 Difference]: Start difference. First operand 905 states and 1304 transitions. cyclomatic complexity: 400 Second operand has 4 states, 4 states have (on average 8.25) internal successors, (33), 4 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:26,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:26,278 INFO L93 Difference]: Finished difference Result 929 states and 1315 transitions. [2025-03-17 20:37:26,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 929 states and 1315 transitions. [2025-03-17 20:37:26,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 908 [2025-03-17 20:37:26,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 929 states to 929 states and 1315 transitions. [2025-03-17 20:37:26,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 929 [2025-03-17 20:37:26,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 929 [2025-03-17 20:37:26,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 929 states and 1315 transitions. [2025-03-17 20:37:26,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:26,286 INFO L218 hiAutomatonCegarLoop]: Abstraction has 929 states and 1315 transitions. [2025-03-17 20:37:26,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 929 states and 1315 transitions. [2025-03-17 20:37:26,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 929 to 929. [2025-03-17 20:37:26,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 929 states, 929 states have (on average 1.4155005382131325) internal successors, (1315), 928 states have internal predecessors, (1315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:26,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 929 states to 929 states and 1315 transitions. [2025-03-17 20:37:26,328 INFO L240 hiAutomatonCegarLoop]: Abstraction has 929 states and 1315 transitions. [2025-03-17 20:37:26,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:37:26,329 INFO L432 stractBuchiCegarLoop]: Abstraction has 929 states and 1315 transitions. [2025-03-17 20:37:26,329 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-17 20:37:26,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 929 states and 1315 transitions. [2025-03-17 20:37:26,332 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 908 [2025-03-17 20:37:26,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:26,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:26,332 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:26,332 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:26,333 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:37:26,333 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume !(0 == ~P_1_st~0);" "assume !(0 == ~P_2_st~0);" "assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-17 20:37:26,333 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,333 INFO L85 PathProgramCache]: Analyzing trace with hash 1929555402, now seen corresponding path program 5 times [2025-03-17 20:37:26,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610679270] [2025-03-17 20:37:26,333 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 20:37:26,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,338 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 21 statements into 1 equivalence classes. [2025-03-17 20:37:26,340 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-17 20:37:26,340 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:37:26,340 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,340 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:26,341 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-17 20:37:26,344 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-17 20:37:26,344 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,344 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,349 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:26,350 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,350 INFO L85 PathProgramCache]: Analyzing trace with hash 2024486026, now seen corresponding path program 1 times [2025-03-17 20:37:26,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,350 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386553983] [2025-03-17 20:37:26,350 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:26,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,355 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-17 20:37:26,357 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-17 20:37:26,357 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,357 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:26,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:26,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:26,376 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [386553983] [2025-03-17 20:37:26,376 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [386553983] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:26,376 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:26,376 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:37:26,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909711807] [2025-03-17 20:37:26,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:26,376 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:37:26,376 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:26,376 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:26,376 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:26,376 INFO L87 Difference]: Start difference. First operand 929 states and 1315 transitions. cyclomatic complexity: 387 Second operand has 3 states, 3 states have (on average 11.0) internal successors, (33), 3 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:26,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:26,413 INFO L93 Difference]: Finished difference Result 1466 states and 2042 transitions. [2025-03-17 20:37:26,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1466 states and 2042 transitions. [2025-03-17 20:37:26,421 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1432 [2025-03-17 20:37:26,427 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1466 states to 1466 states and 2042 transitions. [2025-03-17 20:37:26,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1466 [2025-03-17 20:37:26,429 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1466 [2025-03-17 20:37:26,429 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1466 states and 2042 transitions. [2025-03-17 20:37:26,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:26,431 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1466 states and 2042 transitions. [2025-03-17 20:37:26,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1466 states and 2042 transitions. [2025-03-17 20:37:26,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1466 to 1466. [2025-03-17 20:37:26,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1466 states, 1466 states have (on average 1.3929058663028648) internal successors, (2042), 1465 states have internal predecessors, (2042), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:26,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1466 states to 1466 states and 2042 transitions. [2025-03-17 20:37:26,455 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1466 states and 2042 transitions. [2025-03-17 20:37:26,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:26,456 INFO L432 stractBuchiCegarLoop]: Abstraction has 1466 states and 2042 transitions. [2025-03-17 20:37:26,456 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-17 20:37:26,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1466 states and 2042 transitions. [2025-03-17 20:37:26,462 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1432 [2025-03-17 20:37:26,462 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:26,462 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:26,463 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:26,463 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:26,463 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" [2025-03-17 20:37:26,463 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume !(0 == ~P_2_st~0);" "assume !(0 == ~C_1_st~0);" [2025-03-17 20:37:26,465 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,465 INFO L85 PathProgramCache]: Analyzing trace with hash -313324438, now seen corresponding path program 1 times [2025-03-17 20:37:26,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,465 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [489072158] [2025-03-17 20:37:26,465 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:26,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,469 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-17 20:37:26,472 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-17 20:37:26,472 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,472 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,472 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:26,474 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-17 20:37:26,475 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-17 20:37:26,475 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,475 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,482 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:26,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,483 INFO L85 PathProgramCache]: Analyzing trace with hash -2111963204, now seen corresponding path program 1 times [2025-03-17 20:37:26,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,483 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92843336] [2025-03-17 20:37:26,483 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:26,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,486 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-17 20:37:26,487 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-17 20:37:26,487 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,487 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,487 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:26,489 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-17 20:37:26,490 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-17 20:37:26,490 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,491 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,492 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:26,494 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,494 INFO L85 PathProgramCache]: Analyzing trace with hash 1907790629, now seen corresponding path program 1 times [2025-03-17 20:37:26,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,495 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [964466869] [2025-03-17 20:37:26,495 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:26,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,500 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-17 20:37:26,502 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-17 20:37:26,502 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,502 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:26,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:26,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:26,522 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [964466869] [2025-03-17 20:37:26,522 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [964466869] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:26,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:26,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:37:26,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [162961046] [2025-03-17 20:37:26,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:26,573 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:26,573 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:26,573 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:26,573 INFO L87 Difference]: Start difference. First operand 1466 states and 2042 transitions. cyclomatic complexity: 579 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:26,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:26,624 INFO L93 Difference]: Finished difference Result 2342 states and 3229 transitions. [2025-03-17 20:37:26,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2342 states and 3229 transitions. [2025-03-17 20:37:26,639 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2296 [2025-03-17 20:37:26,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2342 states to 2342 states and 3229 transitions. [2025-03-17 20:37:26,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2342 [2025-03-17 20:37:26,648 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2342 [2025-03-17 20:37:26,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2342 states and 3229 transitions. [2025-03-17 20:37:26,650 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:26,650 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2342 states and 3229 transitions. [2025-03-17 20:37:26,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2342 states and 3229 transitions. [2025-03-17 20:37:26,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2342 to 2262. [2025-03-17 20:37:26,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2262 states, 2262 states have (on average 1.3832891246684351) internal successors, (3129), 2261 states have internal predecessors, (3129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:26,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2262 states to 2262 states and 3129 transitions. [2025-03-17 20:37:26,674 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2262 states and 3129 transitions. [2025-03-17 20:37:26,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:26,676 INFO L432 stractBuchiCegarLoop]: Abstraction has 2262 states and 3129 transitions. [2025-03-17 20:37:26,676 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-17 20:37:26,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2262 states and 3129 transitions. [2025-03-17 20:37:26,682 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2216 [2025-03-17 20:37:26,682 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:26,682 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:26,683 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:26,683 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:26,683 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" [2025-03-17 20:37:26,683 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume !(0 == ~C_1_st~0);" [2025-03-17 20:37:26,683 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,683 INFO L85 PathProgramCache]: Analyzing trace with hash -313324438, now seen corresponding path program 2 times [2025-03-17 20:37:26,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,684 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055048336] [2025-03-17 20:37:26,684 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:37:26,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,689 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 22 statements into 1 equivalence classes. [2025-03-17 20:37:26,691 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-17 20:37:26,691 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:37:26,691 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,691 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:26,694 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-17 20:37:26,695 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-17 20:37:26,695 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,695 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,700 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:26,701 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,701 INFO L85 PathProgramCache]: Analyzing trace with hash -1046348990, now seen corresponding path program 1 times [2025-03-17 20:37:26,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,701 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978546961] [2025-03-17 20:37:26,701 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:26,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,704 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-17 20:37:26,705 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-17 20:37:26,705 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,705 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,705 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:26,705 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-17 20:37:26,706 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-17 20:37:26,706 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,706 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,708 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:26,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,709 INFO L85 PathProgramCache]: Analyzing trace with hash -988031751, now seen corresponding path program 1 times [2025-03-17 20:37:26,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [728451511] [2025-03-17 20:37:26,709 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:26,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,715 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-17 20:37:26,718 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-17 20:37:26,718 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,719 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:37:26,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:37:26,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:37:26,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [728451511] [2025-03-17 20:37:26,734 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [728451511] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:37:26,735 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:37:26,735 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:37:26,735 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [557834154] [2025-03-17 20:37:26,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:37:26,771 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:37:26,771 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:37:26,771 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:37:26,771 INFO L87 Difference]: Start difference. First operand 2262 states and 3129 transitions. cyclomatic complexity: 870 Second operand has 3 states, 2 states have (on average 15.5) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:26,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:37:26,805 INFO L93 Difference]: Finished difference Result 3740 states and 5135 transitions. [2025-03-17 20:37:26,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3740 states and 5135 transitions. [2025-03-17 20:37:26,832 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3670 [2025-03-17 20:37:26,844 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3740 states to 3740 states and 5135 transitions. [2025-03-17 20:37:26,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3740 [2025-03-17 20:37:26,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3740 [2025-03-17 20:37:26,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3740 states and 5135 transitions. [2025-03-17 20:37:26,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:37:26,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3740 states and 5135 transitions. [2025-03-17 20:37:26,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3740 states and 5135 transitions. [2025-03-17 20:37:26,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3740 to 3740. [2025-03-17 20:37:26,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3740 states, 3740 states have (on average 1.3729946524064172) internal successors, (5135), 3739 states have internal predecessors, (5135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:37:26,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3740 states to 3740 states and 5135 transitions. [2025-03-17 20:37:26,895 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3740 states and 5135 transitions. [2025-03-17 20:37:26,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:37:26,896 INFO L432 stractBuchiCegarLoop]: Abstraction has 3740 states and 5135 transitions. [2025-03-17 20:37:26,897 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-17 20:37:26,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3740 states and 5135 transitions. [2025-03-17 20:37:26,906 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3670 [2025-03-17 20:37:26,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:37:26,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:37:26,907 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:26,907 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:37:26,907 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" [2025-03-17 20:37:26,907 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume 0 == ~C_1_st~0;havoc eval_#t~nondet8#1;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp___1~0#1);" [2025-03-17 20:37:26,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,908 INFO L85 PathProgramCache]: Analyzing trace with hash -313324438, now seen corresponding path program 3 times [2025-03-17 20:37:26,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047760843] [2025-03-17 20:37:26,908 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:37:26,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,912 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 22 statements into 1 equivalence classes. [2025-03-17 20:37:26,914 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-17 20:37:26,914 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:37:26,914 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,914 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:26,916 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-17 20:37:26,917 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-17 20:37:26,917 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,918 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,921 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:26,921 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,922 INFO L85 PathProgramCache]: Analyzing trace with hash 1922919795, now seen corresponding path program 1 times [2025-03-17 20:37:26,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,922 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905172119] [2025-03-17 20:37:26,922 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:26,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,924 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-17 20:37:26,925 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-17 20:37:26,925 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,925 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,926 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:26,927 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-17 20:37:26,927 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-17 20:37:26,930 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,930 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,932 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:26,932 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:37:26,932 INFO L85 PathProgramCache]: Analyzing trace with hash -564213092, now seen corresponding path program 1 times [2025-03-17 20:37:26,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:37:26,933 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213652045] [2025-03-17 20:37:26,933 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:37:26,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:37:26,938 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-03-17 20:37:26,941 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-03-17 20:37:26,942 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,942 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,942 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:26,945 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-03-17 20:37:26,946 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-03-17 20:37:26,949 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:26,949 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:26,952 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:37:27,500 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-17 20:37:27,503 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-17 20:37:27,503 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:27,503 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:27,503 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:37:27,510 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-17 20:37:27,513 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-17 20:37:27,513 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:37:27,513 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:37:27,601 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.03 08:37:27 BoogieIcfgContainer [2025-03-17 20:37:27,602 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-17 20:37:27,602 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-17 20:37:27,602 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-17 20:37:27,602 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-17 20:37:27,603 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:37:24" (3/4) ... [2025-03-17 20:37:27,604 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-03-17 20:37:27,655 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-17 20:37:27,655 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-17 20:37:27,656 INFO L158 Benchmark]: Toolchain (without parser) took 3819.53ms. Allocated memory was 167.8MB in the beginning and 369.1MB in the end (delta: 201.3MB). Free memory was 123.3MB in the beginning and 269.3MB in the end (delta: -146.1MB). Peak memory consumption was 55.1MB. Max. memory is 16.1GB. [2025-03-17 20:37:27,657 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 201.3MB. Free memory is still 117.4MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 20:37:27,657 INFO L158 Benchmark]: CACSL2BoogieTranslator took 256.09ms. Allocated memory is still 167.8MB. Free memory was 123.3MB in the beginning and 109.9MB in the end (delta: 13.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-17 20:37:27,657 INFO L158 Benchmark]: Boogie Procedure Inliner took 45.13ms. Allocated memory is still 167.8MB. Free memory was 109.9MB in the beginning and 107.1MB in the end (delta: 2.8MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 20:37:27,657 INFO L158 Benchmark]: Boogie Preprocessor took 37.24ms. Allocated memory is still 167.8MB. Free memory was 107.1MB in the beginning and 105.2MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 20:37:27,658 INFO L158 Benchmark]: IcfgBuilder took 501.22ms. Allocated memory is still 167.8MB. Free memory was 105.2MB in the beginning and 75.4MB in the end (delta: 29.8MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2025-03-17 20:37:27,658 INFO L158 Benchmark]: BuchiAutomizer took 2922.79ms. Allocated memory was 167.8MB in the beginning and 369.1MB in the end (delta: 201.3MB). Free memory was 75.4MB in the beginning and 274.4MB in the end (delta: -199.0MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 20:37:27,658 INFO L158 Benchmark]: Witness Printer took 52.86ms. Allocated memory is still 369.1MB. Free memory was 274.4MB in the beginning and 269.3MB in the end (delta: 5.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-17 20:37:27,659 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 201.3MB. Free memory is still 117.4MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 256.09ms. Allocated memory is still 167.8MB. Free memory was 123.3MB in the beginning and 109.9MB in the end (delta: 13.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 45.13ms. Allocated memory is still 167.8MB. Free memory was 109.9MB in the beginning and 107.1MB in the end (delta: 2.8MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 37.24ms. Allocated memory is still 167.8MB. Free memory was 107.1MB in the beginning and 105.2MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 501.22ms. Allocated memory is still 167.8MB. Free memory was 105.2MB in the beginning and 75.4MB in the end (delta: 29.8MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 2922.79ms. Allocated memory was 167.8MB in the beginning and 369.1MB in the end (delta: 201.3MB). Free memory was 75.4MB in the beginning and 274.4MB in the end (delta: -199.0MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 52.86ms. Allocated memory is still 369.1MB. Free memory was 274.4MB in the beginning and 269.3MB in the end (delta: 5.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (13 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.13 modules have a trivial ranking function, the largest among these consists of 4 locations. The remainder module has 3740 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.8s and 14 iterations. TraceHistogramMax:1. Analysis of lassos took 1.7s. Construction of modules took 0.2s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 0. Minimization of det autom 13. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 13 MinimizatonAttempts, 153 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1668 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1668 mSDsluCounter, 5477 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2609 mSDsCounter, 87 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 250 IncrementalHoareTripleChecker+Invalid, 337 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 87 mSolverCounterUnsat, 2868 mSDtfsCounter, 250 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc2 concLT0 SILN0 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 357]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L118] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L128] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L130] return (__retres1); [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L186] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L196] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L198] return (__retres1); [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L268] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L278] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L288] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L290] return (__retres1); [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 357]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L118] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L128] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L130] return (__retres1); [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L186] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L196] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L198] return (__retres1); [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L268] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L278] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L288] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L290] return (__retres1); [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-03-17 20:37:27,677 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)