./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output --architecture 32bit


--------------------------------------------------------------------------------


Checking for termination
Using default analysis
Version 8fc3dc66
Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) )

 --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba
--- Real Ultimate output ---
This is Ultimate 0.3.0-?-8fc3dc6-m
[2025-03-17 20:37:42,369 INFO  L188        SettingsManager]: Resetting all preferences to default values...
[2025-03-17 20:37:42,421 INFO  L114        SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf
[2025-03-17 20:37:42,426 WARN  L101        SettingsManager]: Preference file contains the following unknown settings:
[2025-03-17 20:37:42,427 WARN  L103        SettingsManager]:   * de.uni_freiburg.informatik.ultimate.core.Log level for class
[2025-03-17 20:37:42,427 WARN  L103        SettingsManager]:   * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG
[2025-03-17 20:37:42,451 INFO  L130        SettingsManager]: Preferences different from defaults after loading the file:
[2025-03-17 20:37:42,452 INFO  L151        SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2025-03-17 20:37:42,452 INFO  L153        SettingsManager]:  * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2025-03-17 20:37:42,453 INFO  L151        SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults:
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * Use memory slicer=true
[2025-03-17 20:37:42,454 INFO  L151        SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * Create parallel compositions if possible=false
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * Use SBE=true
[2025-03-17 20:37:42,454 INFO  L151        SettingsManager]: Preferences of BuchiAutomizer differ from their defaults:
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * NCSB implementation=INTSET_LAZY3
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * Use old map elimination=false
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * Use external solver (rank synthesis)=false
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * Use only trivial implications for array writes=true
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * Rank analysis=LINEAR_WITH_GUESSES
[2025-03-17 20:37:42,454 INFO  L151        SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * Pointer base address is valid at dereference=ASSUME
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * sizeof long=4
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * Overapproximate operations on floating types=true
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * sizeof POINTER=4
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * Check division by zero=IGNORE
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * Pointer to allocated memory at dereference=ASSUME
[2025-03-17 20:37:42,454 INFO  L153        SettingsManager]:  * If two pointers are subtracted or compared they have the same base address=ASSUME
[2025-03-17 20:37:42,455 INFO  L153        SettingsManager]:  * Check array bounds for arrays that are off heap=ASSUME
[2025-03-17 20:37:42,455 INFO  L153        SettingsManager]:  * Check unreachability of reach_error function=false
[2025-03-17 20:37:42,455 INFO  L153        SettingsManager]:  * sizeof long double=12
[2025-03-17 20:37:42,455 INFO  L153        SettingsManager]:  * Check if freed pointer was valid=false
[2025-03-17 20:37:42,455 INFO  L153        SettingsManager]:  * Assume nondeterminstic values are in range=false
[2025-03-17 20:37:42,455 INFO  L153        SettingsManager]:  * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR
[2025-03-17 20:37:42,455 INFO  L153        SettingsManager]:  * Use constant arrays=true
[2025-03-17 20:37:42,455 INFO  L151        SettingsManager]: Preferences of IcfgBuilder differ from their defaults:
[2025-03-17 20:37:42,455 INFO  L153        SettingsManager]:  * Size of a code block=SequenceOfStatements
[2025-03-17 20:37:42,455 INFO  L151        SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2025-03-17 20:37:42,455 INFO  L153        SettingsManager]:  * Trace refinement strategy=CAMEL
[2025-03-17 20:37:42,455 INFO  L151        SettingsManager]: Preferences of IcfgTransformer differ from their defaults:
[2025-03-17 20:37:42,455 INFO  L153        SettingsManager]:  * TransformationType=MODULO_NEIGHBOR
Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) )


Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba
[2025-03-17 20:37:42,674 INFO  L75    nceAwareModelManager]: Repository-Root is: /tmp
[2025-03-17 20:37:42,681 INFO  L261   ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2025-03-17 20:37:42,684 INFO  L217   ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2025-03-17 20:37:42,685 INFO  L270        PluginConnector]: Initializing CDTParser...
[2025-03-17 20:37:42,685 INFO  L274        PluginConnector]: CDTParser initialized
[2025-03-17 20:37:42,686 INFO  L431   ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.04.cil-1.c
[2025-03-17 20:37:43,791 INFO  L533              CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/80c1aaa0e/fce0f8a04c834046a87bdb416199b2c6/FLAG6b0f7f48a
[2025-03-17 20:37:44,066 INFO  L384              CDTParser]: Found 1 translation units.
[2025-03-17 20:37:44,068 INFO  L180              CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-1.c
[2025-03-17 20:37:44,075 INFO  L427              CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/80c1aaa0e/fce0f8a04c834046a87bdb416199b2c6/FLAG6b0f7f48a
[2025-03-17 20:37:44,371 INFO  L435              CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/80c1aaa0e/fce0f8a04c834046a87bdb416199b2c6
[2025-03-17 20:37:44,372 INFO  L299   ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2025-03-17 20:37:44,373 INFO  L133        ToolchainWalker]: Walking toolchain with 6 elements.
[2025-03-17 20:37:44,374 INFO  L112        PluginConnector]: ------------------------CACSL2BoogieTranslator----------------------------
[2025-03-17 20:37:44,374 INFO  L270        PluginConnector]: Initializing CACSL2BoogieTranslator...
[2025-03-17 20:37:44,377 INFO  L274        PluginConnector]: CACSL2BoogieTranslator initialized
[2025-03-17 20:37:44,377 INFO  L184        PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,378 INFO  L204        PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@35aaa9e4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44, skipping insertion in model container
[2025-03-17 20:37:44,378 INFO  L184        PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,399 INFO  L175         MainTranslator]: Built tables and reachable declarations
[2025-03-17 20:37:44,531 INFO  L210          PostProcessor]: Analyzing one entry point: main
[2025-03-17 20:37:44,539 INFO  L200         MainTranslator]: Completed pre-run
[2025-03-17 20:37:44,563 INFO  L210          PostProcessor]: Analyzing one entry point: main
[2025-03-17 20:37:44,574 INFO  L204         MainTranslator]: Completed translation
[2025-03-17 20:37:44,574 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44 WrapperNode
[2025-03-17 20:37:44,574 INFO  L131        PluginConnector]: ------------------------ END CACSL2BoogieTranslator----------------------------
[2025-03-17 20:37:44,575 INFO  L112        PluginConnector]: ------------------------Boogie Procedure Inliner----------------------------
[2025-03-17 20:37:44,575 INFO  L270        PluginConnector]: Initializing Boogie Procedure Inliner...
[2025-03-17 20:37:44,575 INFO  L274        PluginConnector]: Boogie Procedure Inliner initialized
[2025-03-17 20:37:44,579 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,585 INFO  L184        PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,614 INFO  L138                Inliner]: procedures = 36, calls = 44, calls flagged for inlining = 39, calls inlined = 78, statements flattened = 1052
[2025-03-17 20:37:44,615 INFO  L131        PluginConnector]: ------------------------ END Boogie Procedure Inliner----------------------------
[2025-03-17 20:37:44,616 INFO  L112        PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2025-03-17 20:37:44,616 INFO  L270        PluginConnector]: Initializing Boogie Preprocessor...
[2025-03-17 20:37:44,616 INFO  L274        PluginConnector]: Boogie Preprocessor initialized
[2025-03-17 20:37:44,622 INFO  L184        PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,622 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,630 INFO  L184        PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,640 INFO  L175           MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0].
[2025-03-17 20:37:44,641 INFO  L184        PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,641 INFO  L184        PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,648 INFO  L184        PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,650 INFO  L184        PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,655 INFO  L184        PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,656 INFO  L184        PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,660 INFO  L131        PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2025-03-17 20:37:44,664 INFO  L112        PluginConnector]: ------------------------IcfgBuilder----------------------------
[2025-03-17 20:37:44,667 INFO  L270        PluginConnector]: Initializing IcfgBuilder...
[2025-03-17 20:37:44,667 INFO  L274        PluginConnector]: IcfgBuilder initialized
[2025-03-17 20:37:44,667 INFO  L184        PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (1/1) ...
[2025-03-17 20:37:44,671 INFO  L173          SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000
[2025-03-17 20:37:44,679 INFO  L189       MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3
[2025-03-17 20:37:44,693 INFO  L229       MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null)
[2025-03-17 20:37:44,695 INFO  L327       MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process
[2025-03-17 20:37:44,714 INFO  L130     BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit
[2025-03-17 20:37:44,714 INFO  L130     BoogieDeclarations]: Found specification of procedure write~init~int#0
[2025-03-17 20:37:44,714 INFO  L130     BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2025-03-17 20:37:44,714 INFO  L138     BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2025-03-17 20:37:44,787 INFO  L256             CfgBuilder]: Building ICFG
[2025-03-17 20:37:44,788 INFO  L286             CfgBuilder]: Building CFG for each procedure with an implementation
[2025-03-17 20:37:45,477 INFO  L?                        ?]: Removed 148 outVars from TransFormulas that were not future-live.
[2025-03-17 20:37:45,477 INFO  L307             CfgBuilder]: Performing block encoding
[2025-03-17 20:37:45,496 INFO  L331             CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2025-03-17 20:37:45,496 INFO  L336             CfgBuilder]: Removed 0 assume(true) statements.
[2025-03-17 20:37:45,496 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:37:45 BoogieIcfgContainer
[2025-03-17 20:37:45,497 INFO  L131        PluginConnector]: ------------------------ END IcfgBuilder----------------------------
[2025-03-17 20:37:45,497 INFO  L112        PluginConnector]: ------------------------BuchiAutomizer----------------------------
[2025-03-17 20:37:45,497 INFO  L270        PluginConnector]: Initializing BuchiAutomizer...
[2025-03-17 20:37:45,502 INFO  L274        PluginConnector]: BuchiAutomizer initialized
[2025-03-17 20:37:45,503 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-03-17 20:37:45,503 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.03 08:37:44" (1/3) ...
[2025-03-17 20:37:45,504 INFO  L204        PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5d13ac4e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 08:37:45, skipping insertion in model container
[2025-03-17 20:37:45,504 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-03-17 20:37:45,504 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:37:44" (2/3) ...
[2025-03-17 20:37:45,504 INFO  L204        PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5d13ac4e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 08:37:45, skipping insertion in model container
[2025-03-17 20:37:45,504 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-03-17 20:37:45,504 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:37:45" (3/3) ...
[2025-03-17 20:37:45,505 INFO  L363   chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c
[2025-03-17 20:37:45,539 INFO  L306   stractBuchiCegarLoop]: Interprodecural is true
[2025-03-17 20:37:45,539 INFO  L307   stractBuchiCegarLoop]: Hoare is None
[2025-03-17 20:37:45,539 INFO  L308   stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates
[2025-03-17 20:37:45,540 INFO  L309   stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE
[2025-03-17 20:37:45,540 INFO  L310   stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION
[2025-03-17 20:37:45,540 INFO  L311   stractBuchiCegarLoop]: Difference is false
[2025-03-17 20:37:45,540 INFO  L312   stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA
[2025-03-17 20:37:45,540 INFO  L316   stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ========
[2025-03-17 20:37:45,544 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand  has 372 states, 371 states have (on average 1.5983827493261455) internal successors, (593), 371 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:45,562 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 310
[2025-03-17 20:37:45,562 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:45,562 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:45,571 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:45,571 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:45,571 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 1 ============
[2025-03-17 20:37:45,572 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand  has 372 states, 371 states have (on average 1.5983827493261455) internal successors, (593), 371 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:45,586 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 310
[2025-03-17 20:37:45,586 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:45,586 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:45,587 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:45,587 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:45,596 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:45,597 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:45,603 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:45,603 INFO  L85        PathProgramCache]: Analyzing trace with hash 825966189, now seen corresponding path program 1 times
[2025-03-17 20:37:45,608 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:45,608 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230211524]
[2025-03-17 20:37:45,608 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:45,609 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:45,659 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:45,672 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:45,672 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:45,672 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:45,779 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:45,779 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:45,779 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230211524]
[2025-03-17 20:37:45,780 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1230211524] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:45,780 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:45,780 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:37:45,781 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700882787]
[2025-03-17 20:37:45,781 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:45,784 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:45,784 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:45,784 INFO  L85        PathProgramCache]: Analyzing trace with hash 1194771490, now seen corresponding path program 1 times
[2025-03-17 20:37:45,785 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:45,785 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463148480]
[2025-03-17 20:37:45,785 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:45,785 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:45,794 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 59 statements into 1 equivalence classes.
[2025-03-17 20:37:45,795 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 59 of 59 statements.
[2025-03-17 20:37:45,795 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:45,795 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:45,815 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:45,815 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:45,815 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [463148480]
[2025-03-17 20:37:45,815 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [463148480] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:45,815 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:45,815 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:37:45,816 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [870647481]
[2025-03-17 20:37:45,816 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:45,816 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:45,821 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:45,839 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:45,840 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:45,842 INFO  L87              Difference]: Start difference. First operand  has 372 states, 371 states have (on average 1.5983827493261455) internal successors, (593), 371 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand  has 3 states, 3 states have (on average 18.0) internal successors, (54), 2 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:45,873 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:45,874 INFO  L93              Difference]: Finished difference Result 372 states and 584 transitions.
[2025-03-17 20:37:45,875 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 372 states and 584 transitions.
[2025-03-17 20:37:45,882 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 310
[2025-03-17 20:37:45,890 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 372 states to 369 states and 581 transitions.
[2025-03-17 20:37:45,892 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 369
[2025-03-17 20:37:45,893 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 369
[2025-03-17 20:37:45,897 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 369 states and 581 transitions.
[2025-03-17 20:37:45,898 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:45,898 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 369 states and 581 transitions.
[2025-03-17 20:37:45,910 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 369 states and 581 transitions.
[2025-03-17 20:37:45,926 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 369.
[2025-03-17 20:37:45,927 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 369 states, 369 states have (on average 1.5745257452574526) internal successors, (581), 368 states have internal predecessors, (581), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:45,928 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 369 states to 369 states and 581 transitions.
[2025-03-17 20:37:45,929 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 369 states and 581 transitions.
[2025-03-17 20:37:45,930 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:45,932 INFO  L432   stractBuchiCegarLoop]: Abstraction has 369 states and 581 transitions.
[2025-03-17 20:37:45,932 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 2 ============
[2025-03-17 20:37:45,932 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 369 states and 581 transitions.
[2025-03-17 20:37:45,934 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 310
[2025-03-17 20:37:45,934 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:45,934 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:45,935 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:45,935 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:45,936 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:45,936 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:45,936 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:45,936 INFO  L85        PathProgramCache]: Analyzing trace with hash -1543467796, now seen corresponding path program 1 times
[2025-03-17 20:37:45,937 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:45,937 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179286785]
[2025-03-17 20:37:45,937 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:45,937 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:45,944 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:45,948 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:45,948 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:45,948 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:45,989 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:45,989 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:45,990 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1179286785]
[2025-03-17 20:37:45,990 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1179286785] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:45,990 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:45,990 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:37:45,990 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456867722]
[2025-03-17 20:37:45,990 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:45,990 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:45,991 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:45,991 INFO  L85        PathProgramCache]: Analyzing trace with hash 1898976729, now seen corresponding path program 1 times
[2025-03-17 20:37:45,992 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:45,992 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462652093]
[2025-03-17 20:37:45,992 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:45,992 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:45,999 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:46,006 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:46,006 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:46,006 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,104 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,104 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,104 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1462652093]
[2025-03-17 20:37:46,104 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1462652093] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,104 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,104 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:46,104 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396196647]
[2025-03-17 20:37:46,104 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,104 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:46,104 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:46,105 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:46,105 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:46,105 INFO  L87              Difference]: Start difference. First operand 369 states and 581 transitions. cyclomatic complexity: 213 Second operand  has 3 states, 3 states have (on average 18.0) internal successors, (54), 2 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:46,117 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:46,117 INFO  L93              Difference]: Finished difference Result 369 states and 580 transitions.
[2025-03-17 20:37:46,117 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 369 states and 580 transitions.
[2025-03-17 20:37:46,119 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 310
[2025-03-17 20:37:46,121 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 369 states to 369 states and 580 transitions.
[2025-03-17 20:37:46,121 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 369
[2025-03-17 20:37:46,122 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 369
[2025-03-17 20:37:46,122 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 369 states and 580 transitions.
[2025-03-17 20:37:46,123 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:46,123 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 369 states and 580 transitions.
[2025-03-17 20:37:46,123 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 369 states and 580 transitions.
[2025-03-17 20:37:46,146 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 369.
[2025-03-17 20:37:46,147 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 369 states, 369 states have (on average 1.5718157181571815) internal successors, (580), 368 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:46,148 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 369 states to 369 states and 580 transitions.
[2025-03-17 20:37:46,148 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 369 states and 580 transitions.
[2025-03-17 20:37:46,152 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:46,152 INFO  L432   stractBuchiCegarLoop]: Abstraction has 369 states and 580 transitions.
[2025-03-17 20:37:46,152 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 3 ============
[2025-03-17 20:37:46,152 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 369 states and 580 transitions.
[2025-03-17 20:37:46,154 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 310
[2025-03-17 20:37:46,154 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:46,154 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:46,155 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:46,158 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:46,158 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:46,158 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:46,159 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:46,159 INFO  L85        PathProgramCache]: Analyzing trace with hash 1982329485, now seen corresponding path program 1 times
[2025-03-17 20:37:46,159 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:46,159 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293806793]
[2025-03-17 20:37:46,159 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:46,159 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:46,167 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:46,170 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:46,174 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:46,174 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,203 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,203 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,204 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1293806793]
[2025-03-17 20:37:46,204 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1293806793] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,204 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,204 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:37:46,204 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618590752]
[2025-03-17 20:37:46,204 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,204 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:46,204 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:46,204 INFO  L85        PathProgramCache]: Analyzing trace with hash -1407970436, now seen corresponding path program 1 times
[2025-03-17 20:37:46,204 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:46,204 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286377255]
[2025-03-17 20:37:46,204 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:46,205 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:46,212 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:46,225 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:46,225 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:46,225 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,256 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,256 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,256 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286377255]
[2025-03-17 20:37:46,256 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [286377255] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,256 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,256 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:37:46,256 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244213876]
[2025-03-17 20:37:46,257 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,257 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:46,257 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:46,257 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:46,257 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:46,257 INFO  L87              Difference]: Start difference. First operand 369 states and 580 transitions. cyclomatic complexity: 212 Second operand  has 3 states, 3 states have (on average 18.0) internal successors, (54), 2 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:46,265 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:46,265 INFO  L93              Difference]: Finished difference Result 369 states and 579 transitions.
[2025-03-17 20:37:46,265 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 369 states and 579 transitions.
[2025-03-17 20:37:46,267 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 310
[2025-03-17 20:37:46,272 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 369 states to 369 states and 579 transitions.
[2025-03-17 20:37:46,272 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 369
[2025-03-17 20:37:46,272 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 369
[2025-03-17 20:37:46,273 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 369 states and 579 transitions.
[2025-03-17 20:37:46,274 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:46,274 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 369 states and 579 transitions.
[2025-03-17 20:37:46,275 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 369 states and 579 transitions.
[2025-03-17 20:37:46,283 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 369.
[2025-03-17 20:37:46,284 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 369 states, 369 states have (on average 1.5691056910569106) internal successors, (579), 368 states have internal predecessors, (579), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:46,285 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 369 states to 369 states and 579 transitions.
[2025-03-17 20:37:46,285 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 369 states and 579 transitions.
[2025-03-17 20:37:46,288 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:46,288 INFO  L432   stractBuchiCegarLoop]: Abstraction has 369 states and 579 transitions.
[2025-03-17 20:37:46,289 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 4 ============
[2025-03-17 20:37:46,289 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 369 states and 579 transitions.
[2025-03-17 20:37:46,291 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 310
[2025-03-17 20:37:46,291 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:46,291 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:46,292 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:46,292 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:46,292 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:46,292 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:46,294 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:46,294 INFO  L85        PathProgramCache]: Analyzing trace with hash 849138892, now seen corresponding path program 1 times
[2025-03-17 20:37:46,294 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:46,294 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661796920]
[2025-03-17 20:37:46,294 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:46,294 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:46,304 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:46,309 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:46,309 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:46,309 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,325 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,325 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,325 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661796920]
[2025-03-17 20:37:46,326 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661796920] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,326 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,326 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:37:46,326 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [474910027]
[2025-03-17 20:37:46,326 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,326 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:46,326 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:46,326 INFO  L85        PathProgramCache]: Analyzing trace with hash 1898976729, now seen corresponding path program 2 times
[2025-03-17 20:37:46,327 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:46,327 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209915091]
[2025-03-17 20:37:46,327 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-17 20:37:46,327 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:46,333 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:46,337 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:46,337 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:37:46,337 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,374 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,374 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,374 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209915091]
[2025-03-17 20:37:46,374 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1209915091] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,375 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,375 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:46,375 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393068019]
[2025-03-17 20:37:46,375 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,375 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:46,375 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:46,375 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:46,375 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:46,376 INFO  L87              Difference]: Start difference. First operand 369 states and 579 transitions. cyclomatic complexity: 211 Second operand  has 3 states, 3 states have (on average 18.0) internal successors, (54), 2 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:46,381 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:46,381 INFO  L93              Difference]: Finished difference Result 369 states and 578 transitions.
[2025-03-17 20:37:46,382 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 369 states and 578 transitions.
[2025-03-17 20:37:46,384 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 310
[2025-03-17 20:37:46,385 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 369 states to 369 states and 578 transitions.
[2025-03-17 20:37:46,385 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 369
[2025-03-17 20:37:46,385 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 369
[2025-03-17 20:37:46,386 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 369 states and 578 transitions.
[2025-03-17 20:37:46,386 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:46,386 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 369 states and 578 transitions.
[2025-03-17 20:37:46,387 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 369 states and 578 transitions.
[2025-03-17 20:37:46,392 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 369.
[2025-03-17 20:37:46,393 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 369 states, 369 states have (on average 1.5663956639566397) internal successors, (578), 368 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:46,394 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 369 states to 369 states and 578 transitions.
[2025-03-17 20:37:46,394 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 369 states and 578 transitions.
[2025-03-17 20:37:46,395 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:46,395 INFO  L432   stractBuchiCegarLoop]: Abstraction has 369 states and 578 transitions.
[2025-03-17 20:37:46,395 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 5 ============
[2025-03-17 20:37:46,395 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 369 states and 578 transitions.
[2025-03-17 20:37:46,397 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 310
[2025-03-17 20:37:46,397 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:46,397 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:46,398 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:46,398 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:46,398 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:46,398 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:46,399 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:46,399 INFO  L85        PathProgramCache]: Analyzing trace with hash 1089679021, now seen corresponding path program 1 times
[2025-03-17 20:37:46,399 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:46,399 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018777532]
[2025-03-17 20:37:46,399 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:46,399 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:46,404 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:46,409 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:46,409 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:46,409 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,440 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,440 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,440 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018777532]
[2025-03-17 20:37:46,440 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1018777532] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,440 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,440 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:37:46,440 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1726476112]
[2025-03-17 20:37:46,440 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,440 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:46,441 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:46,441 INFO  L85        PathProgramCache]: Analyzing trace with hash 1512109593, now seen corresponding path program 1 times
[2025-03-17 20:37:46,441 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:46,441 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175014071]
[2025-03-17 20:37:46,441 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:46,441 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:46,470 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:46,473 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:46,473 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:46,473 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,503 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,503 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,503 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175014071]
[2025-03-17 20:37:46,504 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1175014071] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,504 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,504 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:37:46,504 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [911689505]
[2025-03-17 20:37:46,504 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,504 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:46,504 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:46,504 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:46,504 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:46,506 INFO  L87              Difference]: Start difference. First operand 369 states and 578 transitions. cyclomatic complexity: 210 Second operand  has 3 states, 3 states have (on average 18.0) internal successors, (54), 2 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:46,517 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:46,517 INFO  L93              Difference]: Finished difference Result 369 states and 577 transitions.
[2025-03-17 20:37:46,517 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 369 states and 577 transitions.
[2025-03-17 20:37:46,520 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 310
[2025-03-17 20:37:46,522 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 369 states to 369 states and 577 transitions.
[2025-03-17 20:37:46,522 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 369
[2025-03-17 20:37:46,523 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 369
[2025-03-17 20:37:46,523 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 369 states and 577 transitions.
[2025-03-17 20:37:46,523 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:46,523 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 369 states and 577 transitions.
[2025-03-17 20:37:46,524 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 369 states and 577 transitions.
[2025-03-17 20:37:46,526 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 369.
[2025-03-17 20:37:46,527 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 369 states, 369 states have (on average 1.5636856368563685) internal successors, (577), 368 states have internal predecessors, (577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:46,528 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 369 states to 369 states and 577 transitions.
[2025-03-17 20:37:46,528 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 369 states and 577 transitions.
[2025-03-17 20:37:46,528 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:46,530 INFO  L432   stractBuchiCegarLoop]: Abstraction has 369 states and 577 transitions.
[2025-03-17 20:37:46,530 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 6 ============
[2025-03-17 20:37:46,530 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 369 states and 577 transitions.
[2025-03-17 20:37:46,532 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 310
[2025-03-17 20:37:46,532 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:46,532 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:46,532 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:46,533 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:46,533 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:46,533 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:46,534 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:46,534 INFO  L85        PathProgramCache]: Analyzing trace with hash 1097438380, now seen corresponding path program 1 times
[2025-03-17 20:37:46,534 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:46,534 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476643731]
[2025-03-17 20:37:46,534 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:46,534 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:46,540 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:46,542 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:46,542 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:46,542 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,579 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,580 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,580 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476643731]
[2025-03-17 20:37:46,580 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476643731] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,580 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,580 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:37:46,580 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2112465847]
[2025-03-17 20:37:46,580 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,580 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:46,580 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:46,580 INFO  L85        PathProgramCache]: Analyzing trace with hash -1407970436, now seen corresponding path program 2 times
[2025-03-17 20:37:46,581 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:46,581 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893771128]
[2025-03-17 20:37:46,581 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-17 20:37:46,581 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:46,590 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:46,591 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:46,591 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:37:46,591 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,624 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,624 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,624 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893771128]
[2025-03-17 20:37:46,624 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1893771128] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,624 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,624 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:46,624 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [112300529]
[2025-03-17 20:37:46,624 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,625 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:46,625 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:46,625 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:37:46,625 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:37:46,625 INFO  L87              Difference]: Start difference. First operand 369 states and 577 transitions. cyclomatic complexity: 209 Second operand  has 4 states, 4 states have (on average 13.5) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:46,706 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:46,706 INFO  L93              Difference]: Finished difference Result 648 states and 1008 transitions.
[2025-03-17 20:37:46,706 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 648 states and 1008 transitions.
[2025-03-17 20:37:46,709 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 579
[2025-03-17 20:37:46,712 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 648 states to 648 states and 1008 transitions.
[2025-03-17 20:37:46,712 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 648
[2025-03-17 20:37:46,713 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 648
[2025-03-17 20:37:46,713 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 648 states and 1008 transitions.
[2025-03-17 20:37:46,714 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:46,714 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 648 states and 1008 transitions.
[2025-03-17 20:37:46,715 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 648 states and 1008 transitions.
[2025-03-17 20:37:46,725 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 648 to 648.
[2025-03-17 20:37:46,726 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 648 states, 648 states have (on average 1.5555555555555556) internal successors, (1008), 647 states have internal predecessors, (1008), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:46,728 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 648 states to 648 states and 1008 transitions.
[2025-03-17 20:37:46,728 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 648 states and 1008 transitions.
[2025-03-17 20:37:46,729 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:37:46,731 INFO  L432   stractBuchiCegarLoop]: Abstraction has 648 states and 1008 transitions.
[2025-03-17 20:37:46,731 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 7 ============
[2025-03-17 20:37:46,731 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 648 states and 1008 transitions.
[2025-03-17 20:37:46,733 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 579
[2025-03-17 20:37:46,734 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:46,734 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:46,735 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:46,736 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:46,736 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:46,736 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:46,737 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:46,737 INFO  L85        PathProgramCache]: Analyzing trace with hash 1193649260, now seen corresponding path program 1 times
[2025-03-17 20:37:46,737 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:46,737 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803160458]
[2025-03-17 20:37:46,737 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:46,737 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:46,742 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:46,746 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:46,746 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:46,746 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,766 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,766 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,767 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803160458]
[2025-03-17 20:37:46,767 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803160458] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,767 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,767 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:37:46,767 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [624022229]
[2025-03-17 20:37:46,767 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,767 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:46,767 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:46,768 INFO  L85        PathProgramCache]: Analyzing trace with hash -969960933, now seen corresponding path program 1 times
[2025-03-17 20:37:46,768 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:46,768 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [938837368]
[2025-03-17 20:37:46,768 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:46,768 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:46,775 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:46,779 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:46,779 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:46,779 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,799 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,799 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,799 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [938837368]
[2025-03-17 20:37:46,800 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [938837368] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,800 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,800 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:37:46,800 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [772716794]
[2025-03-17 20:37:46,800 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,800 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:46,800 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:46,801 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:46,801 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:46,801 INFO  L87              Difference]: Start difference. First operand 648 states and 1008 transitions. cyclomatic complexity: 362 Second operand  has 3 states, 3 states have (on average 18.0) internal successors, (54), 2 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:46,864 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:46,865 INFO  L93              Difference]: Finished difference Result 1209 states and 1857 transitions.
[2025-03-17 20:37:46,865 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 1209 states and 1857 transitions.
[2025-03-17 20:37:46,870 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 1137
[2025-03-17 20:37:46,875 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 1209 states to 1209 states and 1857 transitions.
[2025-03-17 20:37:46,875 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 1209
[2025-03-17 20:37:46,876 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 1209
[2025-03-17 20:37:46,876 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 1209 states and 1857 transitions.
[2025-03-17 20:37:46,877 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:46,878 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 1209 states and 1857 transitions.
[2025-03-17 20:37:46,878 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 1209 states and 1857 transitions.
[2025-03-17 20:37:46,894 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 1209 to 1153.
[2025-03-17 20:37:46,896 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 1153 states, 1153 states have (on average 1.5394622723330442) internal successors, (1775), 1152 states have internal predecessors, (1775), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:46,898 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 1153 states to 1153 states and 1775 transitions.
[2025-03-17 20:37:46,899 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 1153 states and 1775 transitions.
[2025-03-17 20:37:46,899 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:46,901 INFO  L432   stractBuchiCegarLoop]: Abstraction has 1153 states and 1775 transitions.
[2025-03-17 20:37:46,901 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 8 ============
[2025-03-17 20:37:46,901 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 1153 states and 1775 transitions.
[2025-03-17 20:37:46,906 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 1081
[2025-03-17 20:37:46,906 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:46,906 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:46,907 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:46,907 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:46,907 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:46,907 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:46,908 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:46,910 INFO  L85        PathProgramCache]: Analyzing trace with hash -307012279, now seen corresponding path program 1 times
[2025-03-17 20:37:46,911 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:46,911 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996327912]
[2025-03-17 20:37:46,911 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:46,911 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:46,916 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:46,918 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:46,918 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:46,919 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,940 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,940 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,940 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1996327912]
[2025-03-17 20:37:46,940 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1996327912] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,940 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,940 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:37:46,941 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528327945]
[2025-03-17 20:37:46,941 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,941 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:46,941 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:46,941 INFO  L85        PathProgramCache]: Analyzing trace with hash -621313570, now seen corresponding path program 1 times
[2025-03-17 20:37:46,941 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:46,942 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56589056]
[2025-03-17 20:37:46,943 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:46,943 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:46,948 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:46,949 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:46,949 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:46,949 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:46,978 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:46,979 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:46,979 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56589056]
[2025-03-17 20:37:46,979 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56589056] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:46,979 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:46,979 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:46,979 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [273177155]
[2025-03-17 20:37:46,979 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:46,981 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:46,981 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:46,981 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:46,981 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:46,981 INFO  L87              Difference]: Start difference. First operand 1153 states and 1775 transitions. cyclomatic complexity: 626 Second operand  has 3 states, 3 states have (on average 18.0) internal successors, (54), 2 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:47,028 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:47,028 INFO  L93              Difference]: Finished difference Result 2091 states and 3193 transitions.
[2025-03-17 20:37:47,028 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 2091 states and 3193 transitions.
[2025-03-17 20:37:47,039 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 2008
[2025-03-17 20:37:47,047 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 2091 states to 2091 states and 3193 transitions.
[2025-03-17 20:37:47,048 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 2091
[2025-03-17 20:37:47,049 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 2091
[2025-03-17 20:37:47,049 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 2091 states and 3193 transitions.
[2025-03-17 20:37:47,051 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:47,051 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 2091 states and 3193 transitions.
[2025-03-17 20:37:47,053 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 2091 states and 3193 transitions.
[2025-03-17 20:37:47,075 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 2091 to 2087.
[2025-03-17 20:37:47,078 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 2087 states, 2087 states have (on average 1.5280306660277911) internal successors, (3189), 2086 states have internal predecessors, (3189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:47,083 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 2087 states to 2087 states and 3189 transitions.
[2025-03-17 20:37:47,083 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 2087 states and 3189 transitions.
[2025-03-17 20:37:47,084 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:47,085 INFO  L432   stractBuchiCegarLoop]: Abstraction has 2087 states and 3189 transitions.
[2025-03-17 20:37:47,086 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 9 ============
[2025-03-17 20:37:47,086 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 2087 states and 3189 transitions.
[2025-03-17 20:37:47,093 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 2004
[2025-03-17 20:37:47,093 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:47,093 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:47,096 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:47,096 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:47,096 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:47,097 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:47,098 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:47,098 INFO  L85        PathProgramCache]: Analyzing trace with hash 21155404, now seen corresponding path program 1 times
[2025-03-17 20:37:47,098 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:47,098 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128522910]
[2025-03-17 20:37:47,098 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:47,098 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:47,103 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:47,107 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:47,107 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:47,107 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:47,151 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:47,151 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:47,151 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128522910]
[2025-03-17 20:37:47,152 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2128522910] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:47,152 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:47,152 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:37:47,152 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [933491576]
[2025-03-17 20:37:47,152 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:47,152 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:47,153 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:47,154 INFO  L85        PathProgramCache]: Analyzing trace with hash -632449509, now seen corresponding path program 1 times
[2025-03-17 20:37:47,154 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:47,154 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744530089]
[2025-03-17 20:37:47,154 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:47,154 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:47,160 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:47,160 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:47,160 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:47,160 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:47,186 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:47,187 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:47,187 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744530089]
[2025-03-17 20:37:47,187 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744530089] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:47,187 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:47,187 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:47,187 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [767948098]
[2025-03-17 20:37:47,188 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:47,188 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:47,188 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:47,188 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:47,188 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:47,189 INFO  L87              Difference]: Start difference. First operand 2087 states and 3189 transitions. cyclomatic complexity: 1110 Second operand  has 3 states, 3 states have (on average 18.0) internal successors, (54), 2 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:47,242 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:47,242 INFO  L93              Difference]: Finished difference Result 3814 states and 5786 transitions.
[2025-03-17 20:37:47,242 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 3814 states and 5786 transitions.
[2025-03-17 20:37:47,262 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 3708
[2025-03-17 20:37:47,278 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 3814 states to 3814 states and 5786 transitions.
[2025-03-17 20:37:47,279 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 3814
[2025-03-17 20:37:47,282 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 3814
[2025-03-17 20:37:47,282 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 3814 states and 5786 transitions.
[2025-03-17 20:37:47,287 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:47,287 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 3814 states and 5786 transitions.
[2025-03-17 20:37:47,290 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 3814 states and 5786 transitions.
[2025-03-17 20:37:47,334 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 3814 to 3806.
[2025-03-17 20:37:47,339 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 3806 states, 3806 states have (on average 1.5181292695743562) internal successors, (5778), 3805 states have internal predecessors, (5778), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:47,350 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 3806 states to 3806 states and 5778 transitions.
[2025-03-17 20:37:47,351 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 3806 states and 5778 transitions.
[2025-03-17 20:37:47,351 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:47,352 INFO  L432   stractBuchiCegarLoop]: Abstraction has 3806 states and 5778 transitions.
[2025-03-17 20:37:47,352 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 10 ============
[2025-03-17 20:37:47,352 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 3806 states and 5778 transitions.
[2025-03-17 20:37:47,368 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 3700
[2025-03-17 20:37:47,368 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:47,368 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:47,370 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:47,370 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:47,370 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:47,370 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:47,371 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:47,371 INFO  L85        PathProgramCache]: Analyzing trace with hash -88373399, now seen corresponding path program 1 times
[2025-03-17 20:37:47,371 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:47,371 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [778945278]
[2025-03-17 20:37:47,371 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:47,371 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:47,400 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:47,403 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:47,403 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:47,403 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:47,443 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:47,443 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:47,443 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [778945278]
[2025-03-17 20:37:47,443 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [778945278] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:47,443 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:47,443 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:37:47,444 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1061118996]
[2025-03-17 20:37:47,444 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:47,444 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:47,444 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:47,444 INFO  L85        PathProgramCache]: Analyzing trace with hash -957952610, now seen corresponding path program 1 times
[2025-03-17 20:37:47,444 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:47,444 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690864448]
[2025-03-17 20:37:47,444 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:47,444 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:47,450 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:47,451 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:47,451 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:47,452 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:47,474 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:47,474 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:47,474 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690864448]
[2025-03-17 20:37:47,474 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [690864448] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:47,474 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:47,474 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:47,475 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [628047060]
[2025-03-17 20:37:47,475 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:47,475 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:47,475 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:47,475 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:37:47,475 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:37:47,475 INFO  L87              Difference]: Start difference. First operand 3806 states and 5778 transitions. cyclomatic complexity: 1988 Second operand  has 4 states, 4 states have (on average 13.5) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:47,609 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:47,610 INFO  L93              Difference]: Finished difference Result 8613 states and 12967 transitions.
[2025-03-17 20:37:47,610 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 8613 states and 12967 transitions.
[2025-03-17 20:37:47,654 INFO  L131   ngComponentsAnalysis]: Automaton has 24 accepting balls. 8412
[2025-03-17 20:37:47,694 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 8613 states to 8613 states and 12967 transitions.
[2025-03-17 20:37:47,694 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 8613
[2025-03-17 20:37:47,701 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 8613
[2025-03-17 20:37:47,702 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 8613 states and 12967 transitions.
[2025-03-17 20:37:47,712 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:47,713 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 8613 states and 12967 transitions.
[2025-03-17 20:37:47,718 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 8613 states and 12967 transitions.
[2025-03-17 20:37:47,814 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 8613 to 6977.
[2025-03-17 20:37:47,823 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 6977 states, 6977 states have (on average 1.5116812383545937) internal successors, (10547), 6976 states have internal predecessors, (10547), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:47,839 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 6977 states to 6977 states and 10547 transitions.
[2025-03-17 20:37:47,840 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 6977 states and 10547 transitions.
[2025-03-17 20:37:47,840 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:37:47,840 INFO  L432   stractBuchiCegarLoop]: Abstraction has 6977 states and 10547 transitions.
[2025-03-17 20:37:47,840 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 11 ============
[2025-03-17 20:37:47,841 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 6977 states and 10547 transitions.
[2025-03-17 20:37:47,863 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 6832
[2025-03-17 20:37:47,863 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:47,863 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:47,864 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:47,864 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:47,864 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:47,864 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:47,865 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:47,865 INFO  L85        PathProgramCache]: Analyzing trace with hash 940625964, now seen corresponding path program 1 times
[2025-03-17 20:37:47,865 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:47,865 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405186196]
[2025-03-17 20:37:47,865 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:47,865 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:47,870 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:47,873 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:47,873 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:47,873 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:47,893 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:47,893 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:47,893 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405186196]
[2025-03-17 20:37:47,893 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405186196] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:47,893 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:47,893 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:37:47,893 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1678771554]
[2025-03-17 20:37:47,893 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:47,894 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:47,894 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:47,894 INFO  L85        PathProgramCache]: Analyzing trace with hash 985243227, now seen corresponding path program 1 times
[2025-03-17 20:37:47,894 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:47,894 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190002128]
[2025-03-17 20:37:47,894 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:47,894 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:47,899 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:47,900 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:47,900 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:47,900 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:47,926 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:47,926 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:47,927 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190002128]
[2025-03-17 20:37:47,927 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190002128] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:47,927 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:47,927 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:47,927 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2021905954]
[2025-03-17 20:37:47,927 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:47,927 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:47,927 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:47,927 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:47,928 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:47,928 INFO  L87              Difference]: Start difference. First operand 6977 states and 10547 transitions. cyclomatic complexity: 3586 Second operand  has 3 states, 3 states have (on average 18.0) internal successors, (54), 2 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:48,008 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:48,009 INFO  L93              Difference]: Finished difference Result 12816 states and 19312 transitions.
[2025-03-17 20:37:48,009 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 12816 states and 19312 transitions.
[2025-03-17 20:37:48,096 INFO  L131   ngComponentsAnalysis]: Automaton has 32 accepting balls. 12528
[2025-03-17 20:37:48,142 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 12816 states to 12816 states and 19312 transitions.
[2025-03-17 20:37:48,142 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 12816
[2025-03-17 20:37:48,152 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 12816
[2025-03-17 20:37:48,152 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 12816 states and 19312 transitions.
[2025-03-17 20:37:48,168 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:48,168 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 12816 states and 19312 transitions.
[2025-03-17 20:37:48,179 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 12816 states and 19312 transitions.
[2025-03-17 20:37:48,320 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 12816 to 12784.
[2025-03-17 20:37:48,344 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 12784 states, 12784 states have (on average 1.5081351689612015) internal successors, (19280), 12783 states have internal predecessors, (19280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:48,382 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 12784 states to 12784 states and 19280 transitions.
[2025-03-17 20:37:48,382 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 12784 states and 19280 transitions.
[2025-03-17 20:37:48,382 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:48,383 INFO  L432   stractBuchiCegarLoop]: Abstraction has 12784 states and 19280 transitions.
[2025-03-17 20:37:48,383 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 12 ============
[2025-03-17 20:37:48,383 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 12784 states and 19280 transitions.
[2025-03-17 20:37:48,449 INFO  L131   ngComponentsAnalysis]: Automaton has 32 accepting balls. 12496
[2025-03-17 20:37:48,449 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:48,449 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:48,454 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:48,454 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:48,455 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:48,455 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:48,456 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:48,456 INFO  L85        PathProgramCache]: Analyzing trace with hash 1709955465, now seen corresponding path program 1 times
[2025-03-17 20:37:48,456 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:48,456 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986592274]
[2025-03-17 20:37:48,456 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:48,456 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:48,464 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:48,466 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:48,466 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:48,466 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:48,509 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:48,510 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:48,510 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986592274]
[2025-03-17 20:37:48,510 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986592274] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:48,510 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:48,510 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:48,510 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366861757]
[2025-03-17 20:37:48,510 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:48,510 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:48,510 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:48,510 INFO  L85        PathProgramCache]: Analyzing trace with hash -957952610, now seen corresponding path program 2 times
[2025-03-17 20:37:48,511 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:48,511 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142018742]
[2025-03-17 20:37:48,511 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-17 20:37:48,511 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:48,530 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:48,531 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:48,531 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:37:48,531 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:48,612 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:48,612 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:48,612 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142018742]
[2025-03-17 20:37:48,612 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142018742] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:48,612 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:48,612 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:48,612 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386229371]
[2025-03-17 20:37:48,612 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:48,613 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:48,613 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:48,614 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:37:48,614 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:37:48,614 INFO  L87              Difference]: Start difference. First operand 12784 states and 19280 transitions. cyclomatic complexity: 6528 Second operand  has 4 states, 4 states have (on average 13.5) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:48,765 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:48,765 INFO  L93              Difference]: Finished difference Result 13072 states and 19455 transitions.
[2025-03-17 20:37:48,765 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 13072 states and 19455 transitions.
[2025-03-17 20:37:48,818 INFO  L131   ngComponentsAnalysis]: Automaton has 32 accepting balls. 12784
[2025-03-17 20:37:48,862 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 13072 states to 13072 states and 19455 transitions.
[2025-03-17 20:37:48,862 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 13072
[2025-03-17 20:37:48,874 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 13072
[2025-03-17 20:37:48,875 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 13072 states and 19455 transitions.
[2025-03-17 20:37:48,891 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:48,892 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 13072 states and 19455 transitions.
[2025-03-17 20:37:48,903 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 13072 states and 19455 transitions.
[2025-03-17 20:37:49,045 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 13072 to 13072.
[2025-03-17 20:37:49,063 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 13072 states, 13072 states have (on average 1.4882955936352509) internal successors, (19455), 13071 states have internal predecessors, (19455), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:49,089 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 13072 states to 13072 states and 19455 transitions.
[2025-03-17 20:37:49,089 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 13072 states and 19455 transitions.
[2025-03-17 20:37:49,090 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:37:49,090 INFO  L432   stractBuchiCegarLoop]: Abstraction has 13072 states and 19455 transitions.
[2025-03-17 20:37:49,090 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 13 ============
[2025-03-17 20:37:49,090 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 13072 states and 19455 transitions.
[2025-03-17 20:37:49,120 INFO  L131   ngComponentsAnalysis]: Automaton has 32 accepting balls. 12784
[2025-03-17 20:37:49,121 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:49,121 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:49,121 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:49,121 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:49,122 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:49,122 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:49,122 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:49,122 INFO  L85        PathProgramCache]: Analyzing trace with hash 1416552458, now seen corresponding path program 1 times
[2025-03-17 20:37:49,122 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:49,122 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1577047282]
[2025-03-17 20:37:49,123 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:49,123 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:49,130 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:49,132 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:49,132 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:49,132 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:49,152 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:49,152 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:49,152 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1577047282]
[2025-03-17 20:37:49,152 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1577047282] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:49,152 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:49,152 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:37:49,152 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2117006628]
[2025-03-17 20:37:49,152 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:49,153 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:49,153 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:49,153 INFO  L85        PathProgramCache]: Analyzing trace with hash 1298958397, now seen corresponding path program 1 times
[2025-03-17 20:37:49,153 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:49,153 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640172250]
[2025-03-17 20:37:49,153 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:49,153 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:49,159 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:49,161 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:49,161 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:49,161 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:49,184 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:49,184 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:49,184 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640172250]
[2025-03-17 20:37:49,184 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [640172250] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:49,184 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:49,184 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:49,184 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [927535789]
[2025-03-17 20:37:49,185 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:49,185 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:49,185 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:49,185 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:49,185 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:49,185 INFO  L87              Difference]: Start difference. First operand 13072 states and 19455 transitions. cyclomatic complexity: 6415 Second operand  has 3 states, 3 states have (on average 18.0) internal successors, (54), 2 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:49,242 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:49,242 INFO  L93              Difference]: Finished difference Result 19262 states and 28714 transitions.
[2025-03-17 20:37:49,242 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 19262 states and 28714 transitions.
[2025-03-17 20:37:49,414 INFO  L131   ngComponentsAnalysis]: Automaton has 32 accepting balls. 18864
[2025-03-17 20:37:49,472 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 19262 states to 19262 states and 28714 transitions.
[2025-03-17 20:37:49,473 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 19262
[2025-03-17 20:37:49,494 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 19262
[2025-03-17 20:37:49,497 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 19262 states and 28714 transitions.
[2025-03-17 20:37:49,513 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:49,514 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 19262 states and 28714 transitions.
[2025-03-17 20:37:49,531 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 19262 states and 28714 transitions.
[2025-03-17 20:37:49,647 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 19262 to 13382.
[2025-03-17 20:37:49,665 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 13382 states, 13382 states have (on average 1.4953669107756689) internal successors, (20011), 13381 states have internal predecessors, (20011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:49,753 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 13382 states to 13382 states and 20011 transitions.
[2025-03-17 20:37:49,754 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 13382 states and 20011 transitions.
[2025-03-17 20:37:49,754 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:49,754 INFO  L432   stractBuchiCegarLoop]: Abstraction has 13382 states and 20011 transitions.
[2025-03-17 20:37:49,755 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 14 ============
[2025-03-17 20:37:49,755 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 13382 states and 20011 transitions.
[2025-03-17 20:37:49,783 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 13104
[2025-03-17 20:37:49,784 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:49,784 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:49,784 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:49,785 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:49,785 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:49,785 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:49,786 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:49,786 INFO  L85        PathProgramCache]: Analyzing trace with hash -380398901, now seen corresponding path program 1 times
[2025-03-17 20:37:49,786 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:49,786 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512915159]
[2025-03-17 20:37:49,786 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:49,786 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:49,790 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:49,793 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:49,793 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:49,793 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:49,793 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:49,795 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:49,797 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:49,798 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:49,798 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:49,818 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:49,818 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:49,818 INFO  L85        PathProgramCache]: Analyzing trace with hash 910471547, now seen corresponding path program 1 times
[2025-03-17 20:37:49,819 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:49,819 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1185566141]
[2025-03-17 20:37:49,819 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:49,819 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:49,824 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 62 statements into 1 equivalence classes.
[2025-03-17 20:37:49,825 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 62 of 62 statements.
[2025-03-17 20:37:49,825 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:49,825 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:49,849 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:49,849 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:49,849 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1185566141]
[2025-03-17 20:37:49,849 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1185566141] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:49,849 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:49,849 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:49,849 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1479828526]
[2025-03-17 20:37:49,850 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:49,850 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:49,850 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:49,850 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:37:49,850 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:37:49,850 INFO  L87              Difference]: Start difference. First operand 13382 states and 20011 transitions. cyclomatic complexity: 6645 Second operand  has 4 states, 4 states have (on average 15.5) internal successors, (62), 4 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:49,906 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:49,907 INFO  L93              Difference]: Finished difference Result 13638 states and 20267 transitions.
[2025-03-17 20:37:49,907 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 13638 states and 20267 transitions.
[2025-03-17 20:37:50,001 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 13360
[2025-03-17 20:37:50,057 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 13638 states to 13638 states and 20267 transitions.
[2025-03-17 20:37:50,057 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 13638
[2025-03-17 20:37:50,065 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 13638
[2025-03-17 20:37:50,065 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 13638 states and 20267 transitions.
[2025-03-17 20:37:50,074 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:50,074 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 13638 states and 20267 transitions.
[2025-03-17 20:37:50,084 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 13638 states and 20267 transitions.
[2025-03-17 20:37:50,275 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 13638 to 13510.
[2025-03-17 20:37:50,316 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 13510 states, 13510 states have (on average 1.4906735751295337) internal successors, (20139), 13509 states have internal predecessors, (20139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:50,348 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 13510 states to 13510 states and 20139 transitions.
[2025-03-17 20:37:50,348 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 13510 states and 20139 transitions.
[2025-03-17 20:37:50,349 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:37:50,349 INFO  L432   stractBuchiCegarLoop]: Abstraction has 13510 states and 20139 transitions.
[2025-03-17 20:37:50,349 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 15 ============
[2025-03-17 20:37:50,349 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 13510 states and 20139 transitions.
[2025-03-17 20:37:50,389 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 13232
[2025-03-17 20:37:50,389 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:50,389 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:50,390 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:50,390 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:50,391 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:50,391 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:50,391 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:50,392 INFO  L85        PathProgramCache]: Analyzing trace with hash -380398901, now seen corresponding path program 2 times
[2025-03-17 20:37:50,392 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:50,393 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969824075]
[2025-03-17 20:37:50,393 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-17 20:37:50,393 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:50,400 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:50,404 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:50,404 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:37:50,404 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:50,404 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:50,406 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:50,410 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:50,412 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:50,413 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:50,423 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:50,424 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:50,424 INFO  L85        PathProgramCache]: Analyzing trace with hash -1137755925, now seen corresponding path program 1 times
[2025-03-17 20:37:50,424 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:50,424 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774154805]
[2025-03-17 20:37:50,424 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:50,424 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:50,431 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 66 statements into 1 equivalence classes.
[2025-03-17 20:37:50,434 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 66 of 66 statements.
[2025-03-17 20:37:50,434 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:50,434 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:50,470 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:50,470 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:50,470 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774154805]
[2025-03-17 20:37:50,470 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [774154805] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:50,470 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:50,470 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:50,471 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964788934]
[2025-03-17 20:37:50,471 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:50,471 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:50,471 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:50,471 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:37:50,471 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:37:50,471 INFO  L87              Difference]: Start difference. First operand 13510 states and 20139 transitions. cyclomatic complexity: 6645 Second operand  has 4 states, 4 states have (on average 16.5) internal successors, (66), 4 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:50,586 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:50,586 INFO  L93              Difference]: Finished difference Result 13798 states and 20314 transitions.
[2025-03-17 20:37:50,586 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 13798 states and 20314 transitions.
[2025-03-17 20:37:50,646 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 13520
[2025-03-17 20:37:50,696 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 13798 states to 13798 states and 20314 transitions.
[2025-03-17 20:37:50,696 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 13798
[2025-03-17 20:37:50,707 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 13798
[2025-03-17 20:37:50,707 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 13798 states and 20314 transitions.
[2025-03-17 20:37:50,720 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:50,721 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 13798 states and 20314 transitions.
[2025-03-17 20:37:50,729 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 13798 states and 20314 transitions.
[2025-03-17 20:37:50,861 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 13798 to 13798.
[2025-03-17 20:37:50,878 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 13798 states, 13798 states have (on average 1.4722423539643426) internal successors, (20314), 13797 states have internal predecessors, (20314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:50,908 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 13798 states to 13798 states and 20314 transitions.
[2025-03-17 20:37:50,909 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 13798 states and 20314 transitions.
[2025-03-17 20:37:50,909 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:37:50,909 INFO  L432   stractBuchiCegarLoop]: Abstraction has 13798 states and 20314 transitions.
[2025-03-17 20:37:50,910 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 16 ============
[2025-03-17 20:37:50,910 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 13798 states and 20314 transitions.
[2025-03-17 20:37:50,949 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 13520
[2025-03-17 20:37:50,949 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:50,950 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:50,950 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:50,950 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:50,951 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:50,951 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:50,951 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:50,952 INFO  L85        PathProgramCache]: Analyzing trace with hash -380398901, now seen corresponding path program 3 times
[2025-03-17 20:37:50,952 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:50,952 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267974746]
[2025-03-17 20:37:50,952 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2
[2025-03-17 20:37:50,952 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:50,959 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:50,961 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:50,962 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s)
[2025-03-17 20:37:50,962 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:50,962 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:50,964 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:50,966 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:50,966 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:50,966 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:50,974 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:50,974 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:50,974 INFO  L85        PathProgramCache]: Analyzing trace with hash -1013682678, now seen corresponding path program 1 times
[2025-03-17 20:37:50,974 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:50,975 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052948875]
[2025-03-17 20:37:50,975 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:50,975 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:50,986 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 66 statements into 1 equivalence classes.
[2025-03-17 20:37:50,989 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 66 of 66 statements.
[2025-03-17 20:37:50,989 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:50,989 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:51,020 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:51,020 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:51,020 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1052948875]
[2025-03-17 20:37:51,020 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1052948875] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:51,021 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:51,021 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:51,021 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771584485]
[2025-03-17 20:37:51,021 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:51,021 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:51,021 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:51,021 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:37:51,021 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:37:51,021 INFO  L87              Difference]: Start difference. First operand 13798 states and 20314 transitions. cyclomatic complexity: 6532 Second operand  has 4 states, 4 states have (on average 16.5) internal successors, (66), 4 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:51,142 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:51,142 INFO  L93              Difference]: Finished difference Result 14086 states and 20489 transitions.
[2025-03-17 20:37:51,143 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 14086 states and 20489 transitions.
[2025-03-17 20:37:51,200 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 13808
[2025-03-17 20:37:51,242 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 14086 states to 14086 states and 20489 transitions.
[2025-03-17 20:37:51,242 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 14086
[2025-03-17 20:37:51,253 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 14086
[2025-03-17 20:37:51,253 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 14086 states and 20489 transitions.
[2025-03-17 20:37:51,265 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:51,265 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 14086 states and 20489 transitions.
[2025-03-17 20:37:51,273 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 14086 states and 20489 transitions.
[2025-03-17 20:37:51,444 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 14086 to 14086.
[2025-03-17 20:37:51,458 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 14086 states, 14086 states have (on average 1.4545648161294902) internal successors, (20489), 14085 states have internal predecessors, (20489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:51,481 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 14086 states to 14086 states and 20489 transitions.
[2025-03-17 20:37:51,481 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 14086 states and 20489 transitions.
[2025-03-17 20:37:51,482 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:37:51,483 INFO  L432   stractBuchiCegarLoop]: Abstraction has 14086 states and 20489 transitions.
[2025-03-17 20:37:51,483 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 17 ============
[2025-03-17 20:37:51,483 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 14086 states and 20489 transitions.
[2025-03-17 20:37:51,517 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 13808
[2025-03-17 20:37:51,517 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:51,517 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:51,518 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:51,518 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:51,518 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:51,518 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:51,519 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:51,519 INFO  L85        PathProgramCache]: Analyzing trace with hash -380398901, now seen corresponding path program 4 times
[2025-03-17 20:37:51,519 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:51,519 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113246973]
[2025-03-17 20:37:51,519 INFO  L95    rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST
[2025-03-17 20:37:51,519 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:51,525 INFO  L108    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 54 statements into 2 equivalence classes.
[2025-03-17 20:37:51,530 INFO  L111    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:51,530 INFO  L114    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s)
[2025-03-17 20:37:51,530 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:51,530 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:51,533 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:51,535 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:51,535 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:51,535 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:51,544 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:51,545 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:51,545 INFO  L85        PathProgramCache]: Analyzing trace with hash 1271180777, now seen corresponding path program 1 times
[2025-03-17 20:37:51,545 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:51,545 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285587914]
[2025-03-17 20:37:51,545 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:51,545 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:51,550 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 66 statements into 1 equivalence classes.
[2025-03-17 20:37:51,552 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 66 of 66 statements.
[2025-03-17 20:37:51,552 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:51,552 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:51,579 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:51,579 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:51,579 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285587914]
[2025-03-17 20:37:51,579 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285587914] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:51,579 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:51,579 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:51,579 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503446511]
[2025-03-17 20:37:51,579 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:51,579 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:51,579 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:51,580 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:37:51,580 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:37:51,580 INFO  L87              Difference]: Start difference. First operand 14086 states and 20489 transitions. cyclomatic complexity: 6419 Second operand  has 4 states, 4 states have (on average 16.5) internal successors, (66), 4 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:51,684 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:51,684 INFO  L93              Difference]: Finished difference Result 14374 states and 20664 transitions.
[2025-03-17 20:37:51,684 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 14374 states and 20664 transitions.
[2025-03-17 20:37:51,732 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 14096
[2025-03-17 20:37:51,771 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 14374 states to 14374 states and 20664 transitions.
[2025-03-17 20:37:51,771 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 14374
[2025-03-17 20:37:51,782 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 14374
[2025-03-17 20:37:51,782 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 14374 states and 20664 transitions.
[2025-03-17 20:37:51,793 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:51,794 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 14374 states and 20664 transitions.
[2025-03-17 20:37:51,802 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 14374 states and 20664 transitions.
[2025-03-17 20:37:51,892 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 14374 to 14374.
[2025-03-17 20:37:51,907 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 14374 states, 14374 states have (on average 1.4375956588284402) internal successors, (20664), 14373 states have internal predecessors, (20664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:51,926 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 14374 states to 14374 states and 20664 transitions.
[2025-03-17 20:37:51,927 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 14374 states and 20664 transitions.
[2025-03-17 20:37:51,927 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:37:51,928 INFO  L432   stractBuchiCegarLoop]: Abstraction has 14374 states and 20664 transitions.
[2025-03-17 20:37:51,928 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 18 ============
[2025-03-17 20:37:51,928 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 14374 states and 20664 transitions.
[2025-03-17 20:37:51,963 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 14096
[2025-03-17 20:37:51,963 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:51,963 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:51,964 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:51,964 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:51,964 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:51,964 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:51,965 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:51,965 INFO  L85        PathProgramCache]: Analyzing trace with hash -380398901, now seen corresponding path program 5 times
[2025-03-17 20:37:51,965 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:51,965 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038369750]
[2025-03-17 20:37:51,965 INFO  L95    rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1
[2025-03-17 20:37:51,965 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:51,973 INFO  L108    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:51,975 INFO  L111    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:51,975 INFO  L114    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:37:51,976 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:51,976 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:51,977 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:51,981 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:51,981 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:51,981 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:51,988 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:51,988 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:51,988 INFO  L85        PathProgramCache]: Analyzing trace with hash 1600946538, now seen corresponding path program 1 times
[2025-03-17 20:37:51,988 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:51,989 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2034969491]
[2025-03-17 20:37:51,989 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:51,989 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:51,995 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 66 statements into 1 equivalence classes.
[2025-03-17 20:37:51,997 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 66 of 66 statements.
[2025-03-17 20:37:51,997 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:51,997 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:52,015 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:52,015 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:52,016 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2034969491]
[2025-03-17 20:37:52,016 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2034969491] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:52,016 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:52,016 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:37:52,016 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288974928]
[2025-03-17 20:37:52,016 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:52,017 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:52,017 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:52,017 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:52,017 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:52,017 INFO  L87              Difference]: Start difference. First operand 14374 states and 20664 transitions. cyclomatic complexity: 6306 Second operand  has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:52,100 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:52,101 INFO  L93              Difference]: Finished difference Result 21770 states and 30861 transitions.
[2025-03-17 20:37:52,101 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 21770 states and 30861 transitions.
[2025-03-17 20:37:52,297 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 21376
[2025-03-17 20:37:52,357 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 21770 states to 21770 states and 30861 transitions.
[2025-03-17 20:37:52,357 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 21770
[2025-03-17 20:37:52,370 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 21770
[2025-03-17 20:37:52,370 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 21770 states and 30861 transitions.
[2025-03-17 20:37:52,384 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:52,384 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 21770 states and 30861 transitions.
[2025-03-17 20:37:52,394 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 21770 states and 30861 transitions.
[2025-03-17 20:37:52,532 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 21770 to 21658.
[2025-03-17 20:37:52,555 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 21658 states, 21658 states have (on average 1.4175362452673377) internal successors, (30701), 21657 states have internal predecessors, (30701), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:52,587 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 21658 states to 21658 states and 30701 transitions.
[2025-03-17 20:37:52,588 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 21658 states and 30701 transitions.
[2025-03-17 20:37:52,588 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:52,589 INFO  L432   stractBuchiCegarLoop]: Abstraction has 21658 states and 30701 transitions.
[2025-03-17 20:37:52,589 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 19 ============
[2025-03-17 20:37:52,589 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 21658 states and 30701 transitions.
[2025-03-17 20:37:52,647 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 21296
[2025-03-17 20:37:52,647 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:52,647 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:52,648 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:52,648 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:52,649 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:52,649 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:52,650 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:52,650 INFO  L85        PathProgramCache]: Analyzing trace with hash 1554337865, now seen corresponding path program 1 times
[2025-03-17 20:37:52,650 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:52,650 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1489773022]
[2025-03-17 20:37:52,650 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:52,650 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:52,655 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:52,656 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:52,656 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:52,656 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:52,681 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:52,681 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:52,681 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1489773022]
[2025-03-17 20:37:52,681 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1489773022] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:52,681 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:52,681 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:37:52,682 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1459390035]
[2025-03-17 20:37:52,682 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:52,682 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:37:52,682 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:52,682 INFO  L85        PathProgramCache]: Analyzing trace with hash 1360406409, now seen corresponding path program 1 times
[2025-03-17 20:37:52,682 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:52,682 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504577236]
[2025-03-17 20:37:52,682 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:52,682 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:52,688 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 66 statements into 1 equivalence classes.
[2025-03-17 20:37:52,690 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 66 of 66 statements.
[2025-03-17 20:37:52,690 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:52,691 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:52,713 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:52,713 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:52,713 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1504577236]
[2025-03-17 20:37:52,713 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1504577236] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:52,713 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:52,713 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:52,713 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [243018029]
[2025-03-17 20:37:52,714 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:52,714 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:52,714 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:52,714 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:37:52,715 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:37:52,715 INFO  L87              Difference]: Start difference. First operand 21658 states and 30701 transitions. cyclomatic complexity: 9059 Second operand  has 4 states, 4 states have (on average 13.5) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:52,823 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:52,824 INFO  L93              Difference]: Finished difference Result 24426 states and 34538 transitions.
[2025-03-17 20:37:52,824 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 24426 states and 34538 transitions.
[2025-03-17 20:37:52,903 INFO  L131   ngComponentsAnalysis]: Automaton has 28 accepting balls. 23592
[2025-03-17 20:37:53,102 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 24426 states to 24426 states and 34538 transitions.
[2025-03-17 20:37:53,103 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 24426
[2025-03-17 20:37:53,134 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 24426
[2025-03-17 20:37:53,154 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 24426 states and 34538 transitions.
[2025-03-17 20:37:53,181 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:53,181 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 24426 states and 34538 transitions.
[2025-03-17 20:37:53,215 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 24426 states and 34538 transitions.
[2025-03-17 20:37:53,348 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 24426 to 20310.
[2025-03-17 20:37:53,369 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 20310 states, 20310 states have (on average 1.4179714426390941) internal successors, (28799), 20309 states have internal predecessors, (28799), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:53,397 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 20310 states to 20310 states and 28799 transitions.
[2025-03-17 20:37:53,397 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 20310 states and 28799 transitions.
[2025-03-17 20:37:53,398 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:37:53,398 INFO  L432   stractBuchiCegarLoop]: Abstraction has 20310 states and 28799 transitions.
[2025-03-17 20:37:53,398 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 20 ============
[2025-03-17 20:37:53,398 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 20310 states and 28799 transitions.
[2025-03-17 20:37:53,450 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 19984
[2025-03-17 20:37:53,450 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:53,450 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:53,451 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:53,451 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:53,451 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:53,451 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:53,452 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:53,452 INFO  L85        PathProgramCache]: Analyzing trace with hash -380398901, now seen corresponding path program 6 times
[2025-03-17 20:37:53,452 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:53,452 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627530214]
[2025-03-17 20:37:53,452 INFO  L95    rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE
[2025-03-17 20:37:53,452 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:53,461 INFO  L108    AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:53,465 INFO  L111    AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:53,466 INFO  L114    AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s)
[2025-03-17 20:37:53,466 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:53,466 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:53,467 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:53,470 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:53,471 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:53,471 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:53,477 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:53,477 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:53,477 INFO  L85        PathProgramCache]: Analyzing trace with hash 1360406409, now seen corresponding path program 2 times
[2025-03-17 20:37:53,477 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:53,477 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939351203]
[2025-03-17 20:37:53,477 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-17 20:37:53,477 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:53,484 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 66 statements into 1 equivalence classes.
[2025-03-17 20:37:53,486 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 66 of 66 statements.
[2025-03-17 20:37:53,486 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:37:53,486 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:53,510 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:53,510 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:53,510 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939351203]
[2025-03-17 20:37:53,510 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1939351203] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:53,511 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:53,511 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:37:53,511 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021592252]
[2025-03-17 20:37:53,511 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:53,511 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:53,511 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:53,511 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:37:53,511 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:37:53,511 INFO  L87              Difference]: Start difference. First operand 20310 states and 28799 transitions. cyclomatic complexity: 8505 Second operand  has 4 states, 4 states have (on average 16.5) internal successors, (66), 4 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:53,618 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:53,618 INFO  L93              Difference]: Finished difference Result 20742 states and 29062 transitions.
[2025-03-17 20:37:53,618 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 20742 states and 29062 transitions.
[2025-03-17 20:37:53,802 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 20416
[2025-03-17 20:37:53,851 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 20742 states to 20742 states and 29062 transitions.
[2025-03-17 20:37:53,851 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 20742
[2025-03-17 20:37:53,867 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 20742
[2025-03-17 20:37:53,868 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 20742 states and 29062 transitions.
[2025-03-17 20:37:53,883 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:53,883 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 20742 states and 29062 transitions.
[2025-03-17 20:37:53,896 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 20742 states and 29062 transitions.
[2025-03-17 20:37:54,018 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 20742 to 20742.
[2025-03-17 20:37:54,035 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 20742 states, 20742 states have (on average 1.4011185035194291) internal successors, (29062), 20741 states have internal predecessors, (29062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:54,062 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 20742 states to 20742 states and 29062 transitions.
[2025-03-17 20:37:54,062 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 20742 states and 29062 transitions.
[2025-03-17 20:37:54,063 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:37:54,063 INFO  L432   stractBuchiCegarLoop]: Abstraction has 20742 states and 29062 transitions.
[2025-03-17 20:37:54,063 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 21 ============
[2025-03-17 20:37:54,063 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 20742 states and 29062 transitions.
[2025-03-17 20:37:54,112 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 20416
[2025-03-17 20:37:54,112 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:54,112 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:54,113 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:54,113 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:54,113 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:37:54,113 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:37:54,114 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:54,114 INFO  L85        PathProgramCache]: Analyzing trace with hash -380398901, now seen corresponding path program 7 times
[2025-03-17 20:37:54,114 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:54,114 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037505239]
[2025-03-17 20:37:54,114 INFO  L95    rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY
[2025-03-17 20:37:54,114 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:54,119 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:54,121 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:54,121 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:54,121 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:54,121 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:54,124 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes.
[2025-03-17 20:37:54,126 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements.
[2025-03-17 20:37:54,127 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:54,127 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:54,132 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:54,132 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:54,132 INFO  L85        PathProgramCache]: Analyzing trace with hash -1972946870, now seen corresponding path program 1 times
[2025-03-17 20:37:54,133 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:54,133 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296411199]
[2025-03-17 20:37:54,133 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:54,133 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:54,139 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 66 statements into 1 equivalence classes.
[2025-03-17 20:37:54,141 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 66 of 66 statements.
[2025-03-17 20:37:54,142 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:54,142 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:54,163 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:54,163 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:54,163 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296411199]
[2025-03-17 20:37:54,163 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [296411199] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:54,163 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:54,163 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:37:54,163 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1138919125]
[2025-03-17 20:37:54,163 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:54,163 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:37:54,163 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:54,163 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:54,164 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:54,164 INFO  L87              Difference]: Start difference. First operand 20742 states and 29062 transitions. cyclomatic complexity: 8336 Second operand  has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:54,249 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:54,249 INFO  L93              Difference]: Finished difference Result 32327 states and 44379 transitions.
[2025-03-17 20:37:54,249 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 32327 states and 44379 transitions.
[2025-03-17 20:37:54,484 INFO  L131   ngComponentsAnalysis]: Automaton has 29 accepting balls. 31874
[2025-03-17 20:37:54,571 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 32327 states to 32327 states and 44379 transitions.
[2025-03-17 20:37:54,571 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 32327
[2025-03-17 20:37:54,595 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 32327
[2025-03-17 20:37:54,596 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 32327 states and 44379 transitions.
[2025-03-17 20:37:54,622 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:54,622 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 32327 states and 44379 transitions.
[2025-03-17 20:37:54,644 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 32327 states and 44379 transitions.
[2025-03-17 20:37:54,823 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 32327 to 31463.
[2025-03-17 20:37:54,850 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 31463 states, 31463 states have (on average 1.3774592378349173) internal successors, (43339), 31462 states have internal predecessors, (43339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:54,895 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 31463 states to 31463 states and 43339 transitions.
[2025-03-17 20:37:54,895 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 31463 states and 43339 transitions.
[2025-03-17 20:37:54,895 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:54,895 INFO  L432   stractBuchiCegarLoop]: Abstraction has 31463 states and 43339 transitions.
[2025-03-17 20:37:54,895 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 22 ============
[2025-03-17 20:37:54,895 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 31463 states and 43339 transitions.
[2025-03-17 20:37:55,069 INFO  L131   ngComponentsAnalysis]: Automaton has 29 accepting balls. 31010
[2025-03-17 20:37:55,072 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:55,072 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:55,075 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:55,075 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:55,076 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-17 20:37:55,076 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" 
[2025-03-17 20:37:55,076 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:55,077 INFO  L85        PathProgramCache]: Analyzing trace with hash 1092536524, now seen corresponding path program 1 times
[2025-03-17 20:37:55,077 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:55,077 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286202589]
[2025-03-17 20:37:55,077 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:55,079 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:55,104 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes.
[2025-03-17 20:37:55,107 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements.
[2025-03-17 20:37:55,112 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:55,112 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:55,112 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:55,114 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes.
[2025-03-17 20:37:55,116 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements.
[2025-03-17 20:37:55,119 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:55,119 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:55,130 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:55,132 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:55,132 INFO  L85        PathProgramCache]: Analyzing trace with hash 613580106, now seen corresponding path program 1 times
[2025-03-17 20:37:55,132 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:55,132 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989307504]
[2025-03-17 20:37:55,132 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:55,132 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:55,136 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes.
[2025-03-17 20:37:55,139 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements.
[2025-03-17 20:37:55,140 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:55,140 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:55,140 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:55,141 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes.
[2025-03-17 20:37:55,146 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements.
[2025-03-17 20:37:55,147 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:55,147 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:55,148 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:55,149 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:55,149 INFO  L85        PathProgramCache]: Analyzing trace with hash -2017142881, now seen corresponding path program 1 times
[2025-03-17 20:37:55,149 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:55,149 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79980868]
[2025-03-17 20:37:55,149 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:55,149 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:55,162 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 66 statements into 1 equivalence classes.
[2025-03-17 20:37:55,169 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 66 of 66 statements.
[2025-03-17 20:37:55,171 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:55,171 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:55,206 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:55,206 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:55,206 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [79980868]
[2025-03-17 20:37:55,206 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [79980868] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:55,206 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:55,206 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:37:55,206 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2042119224]
[2025-03-17 20:37:55,206 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:55,326 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:55,326 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:55,330 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:55,331 INFO  L87              Difference]: Start difference. First operand 31463 states and 43339 transitions. cyclomatic complexity: 11905 Second operand  has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:55,472 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:55,472 INFO  L93              Difference]: Finished difference Result 39733 states and 53891 transitions.
[2025-03-17 20:37:55,472 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 39733 states and 53891 transitions.
[2025-03-17 20:37:55,640 INFO  L131   ngComponentsAnalysis]: Automaton has 30 accepting balls. 39166
[2025-03-17 20:37:55,741 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 39733 states to 39733 states and 53891 transitions.
[2025-03-17 20:37:55,742 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 39733
[2025-03-17 20:37:55,774 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 39733
[2025-03-17 20:37:55,774 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 39733 states and 53891 transitions.
[2025-03-17 20:37:55,816 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:55,816 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 39733 states and 53891 transitions.
[2025-03-17 20:37:55,848 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 39733 states and 53891 transitions.
[2025-03-17 20:37:56,140 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 39733 to 38529.
[2025-03-17 20:37:56,171 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 38529 states, 38529 states have (on average 1.3609229411612032) internal successors, (52435), 38528 states have internal predecessors, (52435), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:56,220 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 38529 states to 38529 states and 52435 transitions.
[2025-03-17 20:37:56,220 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 38529 states and 52435 transitions.
[2025-03-17 20:37:56,220 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:56,220 INFO  L432   stractBuchiCegarLoop]: Abstraction has 38529 states and 52435 transitions.
[2025-03-17 20:37:56,220 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 23 ============
[2025-03-17 20:37:56,221 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 38529 states and 52435 transitions.
[2025-03-17 20:37:56,308 INFO  L131   ngComponentsAnalysis]: Automaton has 30 accepting balls. 37962
[2025-03-17 20:37:56,308 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:56,308 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:56,309 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:56,309 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:56,309 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-17 20:37:56,309 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" 
[2025-03-17 20:37:56,309 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:56,310 INFO  L85        PathProgramCache]: Analyzing trace with hash 1092536524, now seen corresponding path program 2 times
[2025-03-17 20:37:56,310 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:56,310 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336476785]
[2025-03-17 20:37:56,310 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-17 20:37:56,310 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:56,315 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 55 statements into 1 equivalence classes.
[2025-03-17 20:37:56,317 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 55 of 55 statements.
[2025-03-17 20:37:56,317 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:37:56,317 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:56,317 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:56,318 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes.
[2025-03-17 20:37:56,320 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements.
[2025-03-17 20:37:56,320 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:56,320 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:56,323 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:56,324 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:56,324 INFO  L85        PathProgramCache]: Analyzing trace with hash 1272572298, now seen corresponding path program 1 times
[2025-03-17 20:37:56,324 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:56,324 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476601952]
[2025-03-17 20:37:56,324 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:56,324 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:56,326 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes.
[2025-03-17 20:37:56,327 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements.
[2025-03-17 20:37:56,327 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:56,327 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:56,327 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:56,327 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes.
[2025-03-17 20:37:56,328 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements.
[2025-03-17 20:37:56,328 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:56,328 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:56,329 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:56,329 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:56,329 INFO  L85        PathProgramCache]: Analyzing trace with hash -1411448161, now seen corresponding path program 1 times
[2025-03-17 20:37:56,329 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:56,330 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472897933]
[2025-03-17 20:37:56,330 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:56,330 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:56,334 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 68 statements into 1 equivalence classes.
[2025-03-17 20:37:56,336 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 68 of 68 statements.
[2025-03-17 20:37:56,336 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:56,336 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:56,353 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:56,353 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:56,353 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472897933]
[2025-03-17 20:37:56,353 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472897933] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:56,353 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:56,353 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:37:56,353 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [450832451]
[2025-03-17 20:37:56,354 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:56,525 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:56,526 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:56,526 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:56,526 INFO  L87              Difference]: Start difference. First operand 38529 states and 52435 transitions. cyclomatic complexity: 13936 Second operand  has 3 states, 3 states have (on average 22.666666666666668) internal successors, (68), 3 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:56,633 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:56,633 INFO  L93              Difference]: Finished difference Result 45929 states and 61988 transitions.
[2025-03-17 20:37:56,634 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 45929 states and 61988 transitions.
[2025-03-17 20:37:56,790 INFO  L131   ngComponentsAnalysis]: Automaton has 32 accepting balls. 45274
[2025-03-17 20:37:56,894 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 45929 states to 45929 states and 61988 transitions.
[2025-03-17 20:37:56,895 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 45929
[2025-03-17 20:37:56,925 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 45929
[2025-03-17 20:37:56,926 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 45929 states and 61988 transitions.
[2025-03-17 20:37:56,950 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:56,951 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 45929 states and 61988 transitions.
[2025-03-17 20:37:56,978 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 45929 states and 61988 transitions.
[2025-03-17 20:37:57,240 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 45929 to 44009.
[2025-03-17 20:37:57,276 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 44009 states, 44009 states have (on average 1.3561771455838578) internal successors, (59684), 44008 states have internal predecessors, (59684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:57,337 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 44009 states to 44009 states and 59684 transitions.
[2025-03-17 20:37:57,337 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 44009 states and 59684 transitions.
[2025-03-17 20:37:57,338 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:57,338 INFO  L432   stractBuchiCegarLoop]: Abstraction has 44009 states and 59684 transitions.
[2025-03-17 20:37:57,338 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 24 ============
[2025-03-17 20:37:57,338 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 44009 states and 59684 transitions.
[2025-03-17 20:37:57,565 INFO  L131   ngComponentsAnalysis]: Automaton has 32 accepting balls. 43354
[2025-03-17 20:37:57,565 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:57,565 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:57,565 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:57,565 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:57,566 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-17 20:37:57,566 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" 
[2025-03-17 20:37:57,566 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:57,566 INFO  L85        PathProgramCache]: Analyzing trace with hash 1092536524, now seen corresponding path program 3 times
[2025-03-17 20:37:57,566 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:57,566 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083731324]
[2025-03-17 20:37:57,566 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2
[2025-03-17 20:37:57,566 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:57,571 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 55 statements into 1 equivalence classes.
[2025-03-17 20:37:57,573 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 55 of 55 statements.
[2025-03-17 20:37:57,574 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s)
[2025-03-17 20:37:57,574 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:57,574 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:57,575 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes.
[2025-03-17 20:37:57,577 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements.
[2025-03-17 20:37:57,577 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:57,577 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:57,585 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:57,585 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:57,586 INFO  L85        PathProgramCache]: Analyzing trace with hash -1122642550, now seen corresponding path program 1 times
[2025-03-17 20:37:57,586 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:57,586 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647742269]
[2025-03-17 20:37:57,586 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:57,586 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:57,588 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes.
[2025-03-17 20:37:57,589 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements.
[2025-03-17 20:37:57,589 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:57,589 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:57,589 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:57,590 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes.
[2025-03-17 20:37:57,590 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements.
[2025-03-17 20:37:57,590 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:57,590 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:57,592 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:57,593 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:57,593 INFO  L85        PathProgramCache]: Analyzing trace with hash 809041247, now seen corresponding path program 1 times
[2025-03-17 20:37:57,593 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:57,593 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45634240]
[2025-03-17 20:37:57,593 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:57,593 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:57,598 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 70 statements into 1 equivalence classes.
[2025-03-17 20:37:57,599 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 70 of 70 statements.
[2025-03-17 20:37:57,599 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:57,599 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:57,617 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:57,617 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:57,617 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [45634240]
[2025-03-17 20:37:57,618 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [45634240] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:57,618 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:57,618 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:37:57,618 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1568693479]
[2025-03-17 20:37:57,618 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:57,662 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:57,662 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:57,662 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:57,663 INFO  L87              Difference]: Start difference. First operand 44009 states and 59684 transitions. cyclomatic complexity: 15707 Second operand  has 3 states, 3 states have (on average 23.333333333333332) internal successors, (70), 3 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:57,827 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:37:57,828 INFO  L93              Difference]: Finished difference Result 77263 states and 104040 transitions.
[2025-03-17 20:37:57,828 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 77263 states and 104040 transitions.
[2025-03-17 20:37:58,117 INFO  L131   ngComponentsAnalysis]: Automaton has 32 accepting balls. 76041
[2025-03-17 20:37:58,310 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 77263 states to 77263 states and 104040 transitions.
[2025-03-17 20:37:58,311 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 77263
[2025-03-17 20:37:58,368 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 77263
[2025-03-17 20:37:58,368 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 77263 states and 104040 transitions.
[2025-03-17 20:37:58,416 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:37:58,416 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 77263 states and 104040 transitions.
[2025-03-17 20:37:58,463 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 77263 states and 104040 transitions.
[2025-03-17 20:37:59,210 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 77263 to 75835.
[2025-03-17 20:37:59,272 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 75835 states, 75835 states have (on average 1.3497725324718137) internal successors, (102360), 75834 states have internal predecessors, (102360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:37:59,373 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 75835 states to 75835 states and 102360 transitions.
[2025-03-17 20:37:59,374 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 75835 states and 102360 transitions.
[2025-03-17 20:37:59,374 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:37:59,375 INFO  L432   stractBuchiCegarLoop]: Abstraction has 75835 states and 102360 transitions.
[2025-03-17 20:37:59,375 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 25 ============
[2025-03-17 20:37:59,375 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 75835 states and 102360 transitions.
[2025-03-17 20:37:59,705 INFO  L131   ngComponentsAnalysis]: Automaton has 32 accepting balls. 74613
[2025-03-17 20:37:59,706 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:37:59,706 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:37:59,706 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:59,706 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:37:59,707 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-17 20:37:59,707 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume !(0 == ~t4_st~0);" 
[2025-03-17 20:37:59,707 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:59,707 INFO  L85        PathProgramCache]: Analyzing trace with hash 1092536524, now seen corresponding path program 4 times
[2025-03-17 20:37:59,707 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:59,707 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1626563561]
[2025-03-17 20:37:59,708 INFO  L95    rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST
[2025-03-17 20:37:59,708 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:59,713 INFO  L108    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 55 statements into 2 equivalence classes.
[2025-03-17 20:37:59,716 INFO  L111    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 55 of 55 statements.
[2025-03-17 20:37:59,716 INFO  L114    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s)
[2025-03-17 20:37:59,716 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:59,716 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:59,717 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes.
[2025-03-17 20:37:59,719 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements.
[2025-03-17 20:37:59,719 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:59,719 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:59,722 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:59,723 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:59,723 INFO  L85        PathProgramCache]: Analyzing trace with hash -822658614, now seen corresponding path program 1 times
[2025-03-17 20:37:59,723 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:59,723 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408621174]
[2025-03-17 20:37:59,723 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:59,723 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:59,725 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes.
[2025-03-17 20:37:59,726 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements.
[2025-03-17 20:37:59,726 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:59,726 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:59,726 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:37:59,726 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes.
[2025-03-17 20:37:59,727 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements.
[2025-03-17 20:37:59,727 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:59,727 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:37:59,729 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:37:59,729 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:37:59,731 INFO  L85        PathProgramCache]: Analyzing trace with hash 99598431, now seen corresponding path program 1 times
[2025-03-17 20:37:59,731 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:37:59,731 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2010781136]
[2025-03-17 20:37:59,731 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:37:59,731 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:37:59,737 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 72 statements into 1 equivalence classes.
[2025-03-17 20:37:59,738 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-17 20:37:59,740 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:37:59,740 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:37:59,755 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:37:59,755 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:37:59,755 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2010781136]
[2025-03-17 20:37:59,755 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2010781136] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:37:59,755 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:37:59,755 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:37:59,756 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1974141964]
[2025-03-17 20:37:59,756 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:37:59,825 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:37:59,825 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:37:59,825 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:37:59,826 INFO  L87              Difference]: Start difference. First operand 75835 states and 102360 transitions. cyclomatic complexity: 26557 Second operand  has 3 states, 2 states have (on average 36.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:38:00,024 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:38:00,025 INFO  L93              Difference]: Finished difference Result 90547 states and 121492 transitions.
[2025-03-17 20:38:00,025 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 90547 states and 121492 transitions.
[2025-03-17 20:38:00,499 INFO  L131   ngComponentsAnalysis]: Automaton has 33 accepting balls. 89269
[2025-03-17 20:38:00,707 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 90547 states to 90547 states and 121492 transitions.
[2025-03-17 20:38:00,709 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 90547
[2025-03-17 20:38:00,776 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 90547
[2025-03-17 20:38:00,776 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 90547 states and 121492 transitions.
[2025-03-17 20:38:00,830 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:38:00,830 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 90547 states and 121492 transitions.
[2025-03-17 20:38:00,887 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 90547 states and 121492 transitions.
[2025-03-17 20:38:01,680 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 90547 to 89875.
[2025-03-17 20:38:01,745 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 89875 states, 89875 states have (on average 1.3443115438108484) internal successors, (120820), 89874 states have internal predecessors, (120820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:38:01,872 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 89875 states to 89875 states and 120820 transitions.
[2025-03-17 20:38:01,873 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 89875 states and 120820 transitions.
[2025-03-17 20:38:01,873 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:38:01,873 INFO  L432   stractBuchiCegarLoop]: Abstraction has 89875 states and 120820 transitions.
[2025-03-17 20:38:01,873 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 26 ============
[2025-03-17 20:38:01,873 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 89875 states and 120820 transitions.
[2025-03-17 20:38:02,268 INFO  L131   ngComponentsAnalysis]: Automaton has 33 accepting balls. 88597
[2025-03-17 20:38:02,268 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:38:02,268 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:38:02,269 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:38:02,269 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:38:02,269 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-17 20:38:02,269 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp_ndt_5~0#1);" "havoc eval_~tmp_ndt_5~0#1;" 
[2025-03-17 20:38:02,270 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:38:02,270 INFO  L85        PathProgramCache]: Analyzing trace with hash 1092536524, now seen corresponding path program 5 times
[2025-03-17 20:38:02,270 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:38:02,270 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463453344]
[2025-03-17 20:38:02,270 INFO  L95    rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1
[2025-03-17 20:38:02,270 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:38:02,275 INFO  L108    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 55 statements into 1 equivalence classes.
[2025-03-17 20:38:02,277 INFO  L111    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 55 of 55 statements.
[2025-03-17 20:38:02,278 INFO  L114    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:38:02,278 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:38:02,278 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:38:02,280 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes.
[2025-03-17 20:38:02,282 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements.
[2025-03-17 20:38:02,282 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:38:02,282 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:38:02,287 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:38:02,288 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:38:02,288 INFO  L85        PathProgramCache]: Analyzing trace with hash -300937782, now seen corresponding path program 1 times
[2025-03-17 20:38:02,288 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:38:02,288 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944000736]
[2025-03-17 20:38:02,288 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:38:02,288 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:38:02,290 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes.
[2025-03-17 20:38:02,291 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements.
[2025-03-17 20:38:02,291 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:38:02,291 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:38:02,291 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:38:02,292 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes.
[2025-03-17 20:38:02,292 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements.
[2025-03-17 20:38:02,292 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:38:02,292 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:38:02,294 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:38:02,296 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:38:02,296 INFO  L85        PathProgramCache]: Analyzing trace with hash 1224819487, now seen corresponding path program 1 times
[2025-03-17 20:38:02,296 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:38:02,296 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954545184]
[2025-03-17 20:38:02,296 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:38:02,296 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:38:02,301 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes.
[2025-03-17 20:38:02,303 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements.
[2025-03-17 20:38:02,303 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:38:02,303 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:38:02,303 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:38:02,305 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes.
[2025-03-17 20:38:02,307 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements.
[2025-03-17 20:38:02,307 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:38:02,307 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:38:02,311 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:38:03,081 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes.
[2025-03-17 20:38:03,086 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements.
[2025-03-17 20:38:03,087 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:38:03,087 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:38:03,087 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:38:03,095 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes.
[2025-03-17 20:38:03,100 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements.
[2025-03-17 20:38:03,101 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:38:03,101 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:38:03,218 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.03 08:38:03 BoogieIcfgContainer
[2025-03-17 20:38:03,219 INFO  L131        PluginConnector]: ------------------------ END BuchiAutomizer----------------------------
[2025-03-17 20:38:03,219 INFO  L112        PluginConnector]: ------------------------Witness Printer----------------------------
[2025-03-17 20:38:03,219 INFO  L270        PluginConnector]: Initializing Witness Printer...
[2025-03-17 20:38:03,220 INFO  L274        PluginConnector]: Witness Printer initialized
[2025-03-17 20:38:03,220 INFO  L184        PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:37:45" (3/4) ...
[2025-03-17 20:38:03,222 INFO  L143         WitnessPrinter]: Generating witness for non-termination counterexample
[2025-03-17 20:38:03,297 INFO  L149         WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml
[2025-03-17 20:38:03,298 INFO  L131        PluginConnector]: ------------------------ END Witness Printer----------------------------
[2025-03-17 20:38:03,300 INFO  L158              Benchmark]: Toolchain (without parser) took 18924.81ms. Allocated memory was 142.6MB in the beginning and 2.6GB in the end (delta: 2.5GB). Free memory was 112.3MB in the beginning and 1.6GB in the end (delta: -1.5GB). Peak memory consumption was 996.1MB. Max. memory is 16.1GB.
[2025-03-17 20:38:03,300 INFO  L158              Benchmark]: CDTParser took 0.22ms. Allocated memory is still 201.3MB. Free memory is still 123.5MB. There was no memory consumed. Max. memory is 16.1GB.
[2025-03-17 20:38:03,300 INFO  L158              Benchmark]: CACSL2BoogieTranslator took 200.41ms. Allocated memory is still 142.6MB. Free memory was 111.8MB in the beginning and 96.9MB in the end (delta: 14.9MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
[2025-03-17 20:38:03,300 INFO  L158              Benchmark]: Boogie Procedure Inliner took 40.18ms. Allocated memory is still 142.6MB. Free memory was 96.9MB in the beginning and 93.0MB in the end (delta: 3.9MB). There was no memory consumed. Max. memory is 16.1GB.
[2025-03-17 20:38:03,301 INFO  L158              Benchmark]: Boogie Preprocessor took 44.95ms. Allocated memory is still 142.6MB. Free memory was 93.0MB in the beginning and 89.5MB in the end (delta: 3.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
[2025-03-17 20:38:03,301 INFO  L158              Benchmark]: IcfgBuilder took 832.73ms. Allocated memory is still 142.6MB. Free memory was 89.5MB in the beginning and 102.4MB in the end (delta: -12.9MB). Peak memory consumption was 57.0MB. Max. memory is 16.1GB.
[2025-03-17 20:38:03,302 INFO  L158              Benchmark]: BuchiAutomizer took 17721.56ms. Allocated memory was 142.6MB in the beginning and 2.6GB in the end (delta: 2.5GB). Free memory was 101.6MB in the beginning and 1.6GB in the end (delta: -1.5GB). Peak memory consumption was 980.9MB. Max. memory is 16.1GB.
[2025-03-17 20:38:03,302 INFO  L158              Benchmark]: Witness Printer took 78.24ms. Allocated memory is still 2.6GB. Free memory was 1.6GB in the beginning and 1.6GB in the end (delta: 12.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
[2025-03-17 20:38:03,303 INFO  L338   ainManager$Toolchain]: #######################  End [Toolchain 1] #######################
 --- Results ---
 * Results from de.uni_freiburg.informatik.ultimate.core:
  - StatisticsResult: Toolchain Benchmarks
    Benchmark results are:
 * CDTParser took 0.22ms. Allocated memory is still 201.3MB. Free memory is still 123.5MB. There was no memory consumed. Max. memory is 16.1GB.
 * CACSL2BoogieTranslator took 200.41ms. Allocated memory is still 142.6MB. Free memory was 111.8MB in the beginning and 96.9MB in the end (delta: 14.9MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
 * Boogie Procedure Inliner took 40.18ms. Allocated memory is still 142.6MB. Free memory was 96.9MB in the beginning and 93.0MB in the end (delta: 3.9MB). There was no memory consumed. Max. memory is 16.1GB.
 * Boogie Preprocessor took 44.95ms. Allocated memory is still 142.6MB. Free memory was 93.0MB in the beginning and 89.5MB in the end (delta: 3.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
 * IcfgBuilder took 832.73ms. Allocated memory is still 142.6MB. Free memory was 89.5MB in the beginning and 102.4MB in the end (delta: -12.9MB). Peak memory consumption was 57.0MB. Max. memory is 16.1GB.
 * BuchiAutomizer took 17721.56ms. Allocated memory was 142.6MB in the beginning and 2.6GB in the end (delta: 2.5GB). Free memory was 101.6MB in the beginning and 1.6GB in the end (delta: -1.5GB). Peak memory consumption was 980.9MB. Max. memory is 16.1GB.
 * Witness Printer took 78.24ms. Allocated memory is still 2.6GB. Free memory was 1.6GB in the beginning and 1.6GB in the end (delta: 12.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction:
  - StatisticsResult: Constructed decomposition of program
    Your program was decomposed into 25 terminating modules (25 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.25 modules have a trivial ranking function, the largest among these consists of 4 locations. The remainder module has 89875 locations.
  - StatisticsResult: Timing statistics
    BüchiAutomizer plugin needed 17.5s and 26 iterations.  TraceHistogramMax:1. Analysis of lassos took 3.4s. Construction of modules took 0.7s. Büchi inclusion checks took 11.5s. Highest rank in rank-based complementation 0. Minimization of det autom 25. Minimization of nondet autom 0. Automata minimization 5.5s AutomataMinimizationTime, 25 MinimizatonAttempts, 18060 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 3.8s Buchi closure took 0.3s. Biggest automaton had -1 states and ocurred in iteration -1.	Nontrivial modules had stage [0, 0, 0, 0, 0].	InterpolantCoveringCapabilityFinite: 0/0	InterpolantCoveringCapabilityBuchi: 0/0	HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 10877 SdHoareTripleChecker+Valid, 0.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 10877 mSDsluCounter, 28305 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 13228 mSDsCounter, 283 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 838 IncrementalHoareTripleChecker+Invalid, 1121 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 283 mSolverCounterUnsat, 15077 mSDtfsCounter, 838 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown	LassoAnalysisResults: nont1 unkn0 SFLI7 SFLT0 conc4 concLT0 SILN0 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0	LassoNonterminationAnalysisSatUnbounded: 0	LassoNonterminationAnalysisUnsat: 0	LassoNonterminationAnalysisUnknown: 0	LassoNonterminationAnalysisTime: 0.0s	InitialAbstractionConstructionTime: 0.0s
  - TerminationAnalysisResult: Nontermination possible
    Buchi Automizer proved that your program is nonterminating for some inputs
  - LassoShapedNonTerminationArgument [Line: 423]: Nontermination argument in form of an infinite program execution.
    Nontermination argument in form of an infinite program execution.
Stem:
[L24]               int m_pc  =    0;
[L25]               int t1_pc  =    0;
[L26]               int t2_pc  =    0;
[L27]               int t3_pc  =    0;
[L28]               int t4_pc  =    0;
[L29]               int m_st  ;
[L30]               int t1_st  ;
[L31]               int t2_st  ;
[L32]               int t3_st  ;
[L33]               int t4_st  ;
[L34]               int m_i  ;
[L35]               int t1_i  ;
[L36]               int t2_i  ;
[L37]               int t3_i  ;
[L38]               int t4_i  ;
[L39]               int M_E  =    2;
[L40]               int T1_E  =    2;
[L41]               int T2_E  =    2;
[L42]               int T3_E  =    2;
[L43]               int T4_E  =    2;
[L44]               int E_M  =    2;
[L45]               int E_1  =    2;
[L46]               int E_2  =    2;
[L47]               int E_3  =    2;
[L48]               int E_4  =    2;
[L55]               int token  ;
[L57]               int local  ;
[L848]              int __retres1 ;
[L852]  CALL        init_model()
[L760]              m_i = 1
[L761]              t1_i = 1
[L762]              t2_i = 1
[L763]              t3_i = 1
[L764]              t4_i = 1
[L852]  RET         init_model()
[L853]  CALL        start_simulation()
[L789]              int kernel_st ;
[L790]              int tmp ;
[L791]              int tmp___0 ;
[L795]              kernel_st = 0
[L796]  FCALL       update_channels()
[L797]  CALL        init_threads()
[L353]  COND TRUE   m_i == 1
[L354]              m_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L358]  COND TRUE   t1_i == 1
[L359]              t1_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L363]  COND TRUE   t2_i == 1
[L364]              t2_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L368]  COND TRUE   t3_i == 1
[L369]              t3_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L373]  COND TRUE   t4_i == 1
[L374]              t4_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L797]  RET         init_threads()
[L798]  CALL        fire_delta_events()
[L514]  COND FALSE  !(M_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L519]  COND FALSE  !(T1_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L524]  COND FALSE  !(T2_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L529]  COND FALSE  !(T3_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L534]  COND FALSE  !(T4_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L539]  COND FALSE  !(E_M == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L544]  COND FALSE  !(E_1 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L549]  COND FALSE  !(E_2 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L554]  COND FALSE  !(E_3 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L559]  COND FALSE  !(E_4 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L798]  RET         fire_delta_events()
[L799]  CALL        activate_threads()
[L627]              int tmp ;
[L628]              int tmp___0 ;
[L629]              int tmp___1 ;
[L630]              int tmp___2 ;
[L631]              int tmp___3 ;
[L635]  CALL, EXPR  is_master_triggered()
[L247]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L250]  COND FALSE  !(m_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L260]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L262]              return (__retres1);
[L635]  RET, EXPR   is_master_triggered()
[L635]              tmp = is_master_triggered()
[L637]  COND FALSE  !(\read(tmp))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L643]  CALL, EXPR  is_transmit1_triggered()
[L266]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L269]  COND FALSE  !(t1_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L279]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L281]              return (__retres1);
[L643]  RET, EXPR   is_transmit1_triggered()
[L643]              tmp___0 = is_transmit1_triggered()
[L645]  COND FALSE  !(\read(tmp___0))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L651]  CALL, EXPR  is_transmit2_triggered()
[L285]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L288]  COND FALSE  !(t2_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L298]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L300]              return (__retres1);
[L651]  RET, EXPR   is_transmit2_triggered()
[L651]              tmp___1 = is_transmit2_triggered()
[L653]  COND FALSE  !(\read(tmp___1))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L659]  CALL, EXPR  is_transmit3_triggered()
[L304]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L307]  COND FALSE  !(t3_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L317]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L319]              return (__retres1);
[L659]  RET, EXPR   is_transmit3_triggered()
[L659]              tmp___2 = is_transmit3_triggered()
[L661]  COND FALSE  !(\read(tmp___2))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L667]  CALL, EXPR  is_transmit4_triggered()
[L323]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L326]  COND FALSE  !(t4_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L336]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L338]              return (__retres1);
[L667]  RET, EXPR   is_transmit4_triggered()
[L667]              tmp___3 = is_transmit4_triggered()
[L669]  COND FALSE  !(\read(tmp___3))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L799]  RET         activate_threads()
[L800]  CALL        reset_delta_events()
[L572]  COND FALSE  !(M_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L577]  COND FALSE  !(T1_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L582]  COND FALSE  !(T2_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L587]  COND FALSE  !(T3_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L592]  COND FALSE  !(T4_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L597]  COND FALSE  !(E_M == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L602]  COND FALSE  !(E_1 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L607]  COND FALSE  !(E_2 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L612]  COND FALSE  !(E_3 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L617]  COND FALSE  !(E_4 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L800]  RET         reset_delta_events()
[L803]  COND TRUE   1
[L806]              kernel_st = 1
[L807]  CALL        eval()
[L419]              int tmp ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
Loop:
[L423]  COND TRUE   1
[L426]  CALL, EXPR  exists_runnable_thread()
[L383]              int __retres1 ;
[L386]  COND TRUE   m_st == 0
[L387]              __retres1 = 1
[L414]              return (__retres1);
[L426]  RET, EXPR   exists_runnable_thread()
[L426]              tmp = exists_runnable_thread()
[L428]  COND TRUE   \read(tmp)
[L433]  COND TRUE   m_st == 0
[L434]              int tmp_ndt_1;
[L435]              tmp_ndt_1 = __VERIFIER_nondet_int()
[L436]  COND FALSE  !(\read(tmp_ndt_1))
[L447]  COND TRUE   t1_st == 0
[L448]              int tmp_ndt_2;
[L449]              tmp_ndt_2 = __VERIFIER_nondet_int()
[L450]  COND FALSE  !(\read(tmp_ndt_2))
[L461]  COND TRUE   t2_st == 0
[L462]              int tmp_ndt_3;
[L463]              tmp_ndt_3 = __VERIFIER_nondet_int()
[L464]  COND FALSE  !(\read(tmp_ndt_3))
[L475]  COND TRUE   t3_st == 0
[L476]              int tmp_ndt_4;
[L477]              tmp_ndt_4 = __VERIFIER_nondet_int()
[L478]  COND FALSE  !(\read(tmp_ndt_4))
[L489]  COND TRUE   t4_st == 0
[L490]              int tmp_ndt_5;
[L491]              tmp_ndt_5 = __VERIFIER_nondet_int()
[L492]  COND FALSE  !(\read(tmp_ndt_5))
End of lasso representation.
  - StatisticsResult: NonterminationArgumentStatistics
    Fixpoint
  - NonterminatingLassoResult [Line: 423]: Nonterminating execution
    Found a nonterminating execution for the following lasso shaped sequence of statements.
Stem:
[L24]               int m_pc  =    0;
[L25]               int t1_pc  =    0;
[L26]               int t2_pc  =    0;
[L27]               int t3_pc  =    0;
[L28]               int t4_pc  =    0;
[L29]               int m_st  ;
[L30]               int t1_st  ;
[L31]               int t2_st  ;
[L32]               int t3_st  ;
[L33]               int t4_st  ;
[L34]               int m_i  ;
[L35]               int t1_i  ;
[L36]               int t2_i  ;
[L37]               int t3_i  ;
[L38]               int t4_i  ;
[L39]               int M_E  =    2;
[L40]               int T1_E  =    2;
[L41]               int T2_E  =    2;
[L42]               int T3_E  =    2;
[L43]               int T4_E  =    2;
[L44]               int E_M  =    2;
[L45]               int E_1  =    2;
[L46]               int E_2  =    2;
[L47]               int E_3  =    2;
[L48]               int E_4  =    2;
[L55]               int token  ;
[L57]               int local  ;
[L848]              int __retres1 ;
[L852]  CALL        init_model()
[L760]              m_i = 1
[L761]              t1_i = 1
[L762]              t2_i = 1
[L763]              t3_i = 1
[L764]              t4_i = 1
[L852]  RET         init_model()
[L853]  CALL        start_simulation()
[L789]              int kernel_st ;
[L790]              int tmp ;
[L791]              int tmp___0 ;
[L795]              kernel_st = 0
[L796]  FCALL       update_channels()
[L797]  CALL        init_threads()
[L353]  COND TRUE   m_i == 1
[L354]              m_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L358]  COND TRUE   t1_i == 1
[L359]              t1_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L363]  COND TRUE   t2_i == 1
[L364]              t2_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L368]  COND TRUE   t3_i == 1
[L369]              t3_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L373]  COND TRUE   t4_i == 1
[L374]              t4_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L797]  RET         init_threads()
[L798]  CALL        fire_delta_events()
[L514]  COND FALSE  !(M_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L519]  COND FALSE  !(T1_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L524]  COND FALSE  !(T2_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L529]  COND FALSE  !(T3_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L534]  COND FALSE  !(T4_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L539]  COND FALSE  !(E_M == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L544]  COND FALSE  !(E_1 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L549]  COND FALSE  !(E_2 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L554]  COND FALSE  !(E_3 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L559]  COND FALSE  !(E_4 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L798]  RET         fire_delta_events()
[L799]  CALL        activate_threads()
[L627]              int tmp ;
[L628]              int tmp___0 ;
[L629]              int tmp___1 ;
[L630]              int tmp___2 ;
[L631]              int tmp___3 ;
[L635]  CALL, EXPR  is_master_triggered()
[L247]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L250]  COND FALSE  !(m_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L260]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L262]              return (__retres1);
[L635]  RET, EXPR   is_master_triggered()
[L635]              tmp = is_master_triggered()
[L637]  COND FALSE  !(\read(tmp))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L643]  CALL, EXPR  is_transmit1_triggered()
[L266]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L269]  COND FALSE  !(t1_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L279]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L281]              return (__retres1);
[L643]  RET, EXPR   is_transmit1_triggered()
[L643]              tmp___0 = is_transmit1_triggered()
[L645]  COND FALSE  !(\read(tmp___0))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L651]  CALL, EXPR  is_transmit2_triggered()
[L285]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L288]  COND FALSE  !(t2_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L298]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L300]              return (__retres1);
[L651]  RET, EXPR   is_transmit2_triggered()
[L651]              tmp___1 = is_transmit2_triggered()
[L653]  COND FALSE  !(\read(tmp___1))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L659]  CALL, EXPR  is_transmit3_triggered()
[L304]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L307]  COND FALSE  !(t3_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L317]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L319]              return (__retres1);
[L659]  RET, EXPR   is_transmit3_triggered()
[L659]              tmp___2 = is_transmit3_triggered()
[L661]  COND FALSE  !(\read(tmp___2))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L667]  CALL, EXPR  is_transmit4_triggered()
[L323]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L326]  COND FALSE  !(t4_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L336]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L338]              return (__retres1);
[L667]  RET, EXPR   is_transmit4_triggered()
[L667]              tmp___3 = is_transmit4_triggered()
[L669]  COND FALSE  !(\read(tmp___3))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L799]  RET         activate_threads()
[L800]  CALL        reset_delta_events()
[L572]  COND FALSE  !(M_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L577]  COND FALSE  !(T1_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L582]  COND FALSE  !(T2_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L587]  COND FALSE  !(T3_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L592]  COND FALSE  !(T4_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L597]  COND FALSE  !(E_M == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L602]  COND FALSE  !(E_1 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L607]  COND FALSE  !(E_2 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L612]  COND FALSE  !(E_3 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L617]  COND FALSE  !(E_4 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
[L800]  RET         reset_delta_events()
[L803]  COND TRUE   1
[L806]              kernel_st = 1
[L807]  CALL        eval()
[L419]              int tmp ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0]
Loop:
[L423]  COND TRUE   1
[L426]  CALL, EXPR  exists_runnable_thread()
[L383]              int __retres1 ;
[L386]  COND TRUE   m_st == 0
[L387]              __retres1 = 1
[L414]              return (__retres1);
[L426]  RET, EXPR   exists_runnable_thread()
[L426]              tmp = exists_runnable_thread()
[L428]  COND TRUE   \read(tmp)
[L433]  COND TRUE   m_st == 0
[L434]              int tmp_ndt_1;
[L435]              tmp_ndt_1 = __VERIFIER_nondet_int()
[L436]  COND FALSE  !(\read(tmp_ndt_1))
[L447]  COND TRUE   t1_st == 0
[L448]              int tmp_ndt_2;
[L449]              tmp_ndt_2 = __VERIFIER_nondet_int()
[L450]  COND FALSE  !(\read(tmp_ndt_2))
[L461]  COND TRUE   t2_st == 0
[L462]              int tmp_ndt_3;
[L463]              tmp_ndt_3 = __VERIFIER_nondet_int()
[L464]  COND FALSE  !(\read(tmp_ndt_3))
[L475]  COND TRUE   t3_st == 0
[L476]              int tmp_ndt_4;
[L477]              tmp_ndt_4 = __VERIFIER_nondet_int()
[L478]  COND FALSE  !(\read(tmp_ndt_4))
[L489]  COND TRUE   t4_st == 0
[L490]              int tmp_ndt_5;
[L491]              tmp_ndt_5 = __VERIFIER_nondet_int()
[L492]  COND FALSE  !(\read(tmp_ndt_5))
End of lasso representation.
RESULT: Ultimate proved your program to be incorrect!
[2025-03-17 20:38:03,384 INFO  L552       MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0
Received shutdown request...
--- End real Ultimate output ---

Execution finished normally
Writing output log to file Ultimate.log
Writing human readable error path to file UltimateCounterExample.errorpath
Result:
FALSE(TERM)