./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output --architecture 32bit


--------------------------------------------------------------------------------


Checking for termination
Using default analysis
Version 8fc3dc66
Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) )

 --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe
--- Real Ultimate output ---
This is Ultimate 0.3.0-?-8fc3dc6-m
[2025-03-17 20:39:13,385 INFO  L188        SettingsManager]: Resetting all preferences to default values...
[2025-03-17 20:39:13,426 INFO  L114        SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf
[2025-03-17 20:39:13,430 WARN  L101        SettingsManager]: Preference file contains the following unknown settings:
[2025-03-17 20:39:13,430 WARN  L103        SettingsManager]:   * de.uni_freiburg.informatik.ultimate.core.Log level for class
[2025-03-17 20:39:13,430 WARN  L103        SettingsManager]:   * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG
[2025-03-17 20:39:13,450 INFO  L130        SettingsManager]: Preferences different from defaults after loading the file:
[2025-03-17 20:39:13,451 INFO  L151        SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2025-03-17 20:39:13,451 INFO  L153        SettingsManager]:  * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2025-03-17 20:39:13,452 INFO  L151        SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults:
[2025-03-17 20:39:13,453 INFO  L153        SettingsManager]:  * Use memory slicer=true
[2025-03-17 20:39:13,453 INFO  L151        SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2025-03-17 20:39:13,453 INFO  L153        SettingsManager]:  * Create parallel compositions if possible=false
[2025-03-17 20:39:13,453 INFO  L153        SettingsManager]:  * Use SBE=true
[2025-03-17 20:39:13,454 INFO  L151        SettingsManager]: Preferences of BuchiAutomizer differ from their defaults:
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * NCSB implementation=INTSET_LAZY3
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * Use old map elimination=false
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * Use external solver (rank synthesis)=false
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * Use only trivial implications for array writes=true
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * Rank analysis=LINEAR_WITH_GUESSES
[2025-03-17 20:39:13,454 INFO  L151        SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * Pointer base address is valid at dereference=ASSUME
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * sizeof long=4
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * Overapproximate operations on floating types=true
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * sizeof POINTER=4
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * Check division by zero=IGNORE
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * Pointer to allocated memory at dereference=ASSUME
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * If two pointers are subtracted or compared they have the same base address=ASSUME
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * Check array bounds for arrays that are off heap=ASSUME
[2025-03-17 20:39:13,454 INFO  L153        SettingsManager]:  * Check unreachability of reach_error function=false
[2025-03-17 20:39:13,455 INFO  L153        SettingsManager]:  * sizeof long double=12
[2025-03-17 20:39:13,455 INFO  L153        SettingsManager]:  * Check if freed pointer was valid=false
[2025-03-17 20:39:13,455 INFO  L153        SettingsManager]:  * Assume nondeterminstic values are in range=false
[2025-03-17 20:39:13,455 INFO  L153        SettingsManager]:  * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR
[2025-03-17 20:39:13,455 INFO  L153        SettingsManager]:  * Use constant arrays=true
[2025-03-17 20:39:13,455 INFO  L151        SettingsManager]: Preferences of IcfgBuilder differ from their defaults:
[2025-03-17 20:39:13,455 INFO  L153        SettingsManager]:  * Size of a code block=SequenceOfStatements
[2025-03-17 20:39:13,455 INFO  L151        SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2025-03-17 20:39:13,455 INFO  L153        SettingsManager]:  * Trace refinement strategy=CAMEL
[2025-03-17 20:39:13,455 INFO  L151        SettingsManager]: Preferences of IcfgTransformer differ from their defaults:
[2025-03-17 20:39:13,456 INFO  L153        SettingsManager]:  * TransformationType=MODULO_NEIGHBOR
Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) )


Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe
[2025-03-17 20:39:13,816 INFO  L75    nceAwareModelManager]: Repository-Root is: /tmp
[2025-03-17 20:39:13,826 INFO  L261   ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2025-03-17 20:39:13,831 INFO  L217   ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2025-03-17 20:39:13,832 INFO  L270        PluginConnector]: Initializing CDTParser...
[2025-03-17 20:39:13,832 INFO  L274        PluginConnector]: CDTParser initialized
[2025-03-17 20:39:13,833 INFO  L431   ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.01.cil.c
[2025-03-17 20:39:15,000 INFO  L533              CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/545db411b/a521c18148714b7395af69ea7fdd3ca8/FLAG25c92e74b
[2025-03-17 20:39:15,206 INFO  L384              CDTParser]: Found 1 translation units.
[2025-03-17 20:39:15,207 INFO  L180              CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.01.cil.c
[2025-03-17 20:39:15,246 INFO  L427              CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/545db411b/a521c18148714b7395af69ea7fdd3ca8/FLAG25c92e74b
[2025-03-17 20:39:15,271 INFO  L435              CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/545db411b/a521c18148714b7395af69ea7fdd3ca8
[2025-03-17 20:39:15,273 INFO  L299   ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2025-03-17 20:39:15,276 INFO  L133        ToolchainWalker]: Walking toolchain with 6 elements.
[2025-03-17 20:39:15,277 INFO  L112        PluginConnector]: ------------------------CACSL2BoogieTranslator----------------------------
[2025-03-17 20:39:15,277 INFO  L270        PluginConnector]: Initializing CACSL2BoogieTranslator...
[2025-03-17 20:39:15,280 INFO  L274        PluginConnector]: CACSL2BoogieTranslator initialized
[2025-03-17 20:39:15,281 INFO  L184        PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,282 INFO  L204        PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@53972418 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15, skipping insertion in model container
[2025-03-17 20:39:15,283 INFO  L184        PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,303 INFO  L175         MainTranslator]: Built tables and reachable declarations
[2025-03-17 20:39:15,423 INFO  L210          PostProcessor]: Analyzing one entry point: main
[2025-03-17 20:39:15,432 INFO  L200         MainTranslator]: Completed pre-run
[2025-03-17 20:39:15,451 INFO  L210          PostProcessor]: Analyzing one entry point: main
[2025-03-17 20:39:15,463 INFO  L204         MainTranslator]: Completed translation
[2025-03-17 20:39:15,464 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15 WrapperNode
[2025-03-17 20:39:15,464 INFO  L131        PluginConnector]: ------------------------ END CACSL2BoogieTranslator----------------------------
[2025-03-17 20:39:15,465 INFO  L112        PluginConnector]: ------------------------Boogie Procedure Inliner----------------------------
[2025-03-17 20:39:15,465 INFO  L270        PluginConnector]: Initializing Boogie Procedure Inliner...
[2025-03-17 20:39:15,465 INFO  L274        PluginConnector]: Boogie Procedure Inliner initialized
[2025-03-17 20:39:15,469 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,474 INFO  L184        PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,493 INFO  L138                Inliner]: procedures = 30, calls = 34, calls flagged for inlining = 29, calls inlined = 35, statements flattened = 346
[2025-03-17 20:39:15,493 INFO  L131        PluginConnector]: ------------------------ END Boogie Procedure Inliner----------------------------
[2025-03-17 20:39:15,494 INFO  L112        PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2025-03-17 20:39:15,494 INFO  L270        PluginConnector]: Initializing Boogie Preprocessor...
[2025-03-17 20:39:15,494 INFO  L274        PluginConnector]: Boogie Preprocessor initialized
[2025-03-17 20:39:15,499 INFO  L184        PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,499 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,500 INFO  L184        PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,509 INFO  L175           MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0].
[2025-03-17 20:39:15,509 INFO  L184        PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,509 INFO  L184        PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,516 INFO  L184        PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,518 INFO  L184        PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,518 INFO  L184        PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,519 INFO  L184        PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,520 INFO  L131        PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2025-03-17 20:39:15,522 INFO  L112        PluginConnector]: ------------------------IcfgBuilder----------------------------
[2025-03-17 20:39:15,522 INFO  L270        PluginConnector]: Initializing IcfgBuilder...
[2025-03-17 20:39:15,522 INFO  L274        PluginConnector]: IcfgBuilder initialized
[2025-03-17 20:39:15,523 INFO  L184        PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (1/1) ...
[2025-03-17 20:39:15,527 INFO  L173          SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000
[2025-03-17 20:39:15,536 INFO  L189       MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3
[2025-03-17 20:39:15,549 INFO  L229       MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null)
[2025-03-17 20:39:15,554 INFO  L327       MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process
[2025-03-17 20:39:15,572 INFO  L130     BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit
[2025-03-17 20:39:15,572 INFO  L130     BoogieDeclarations]: Found specification of procedure write~init~int#0
[2025-03-17 20:39:15,572 INFO  L130     BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2025-03-17 20:39:15,572 INFO  L138     BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2025-03-17 20:39:15,625 INFO  L256             CfgBuilder]: Building ICFG
[2025-03-17 20:39:15,626 INFO  L286             CfgBuilder]: Building CFG for each procedure with an implementation
[2025-03-17 20:39:15,931 INFO  L?                        ?]: Removed 46 outVars from TransFormulas that were not future-live.
[2025-03-17 20:39:15,931 INFO  L307             CfgBuilder]: Performing block encoding
[2025-03-17 20:39:15,940 INFO  L331             CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2025-03-17 20:39:15,940 INFO  L336             CfgBuilder]: Removed 0 assume(true) statements.
[2025-03-17 20:39:15,940 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:39:15 BoogieIcfgContainer
[2025-03-17 20:39:15,940 INFO  L131        PluginConnector]: ------------------------ END IcfgBuilder----------------------------
[2025-03-17 20:39:15,941 INFO  L112        PluginConnector]: ------------------------BuchiAutomizer----------------------------
[2025-03-17 20:39:15,941 INFO  L270        PluginConnector]: Initializing BuchiAutomizer...
[2025-03-17 20:39:15,945 INFO  L274        PluginConnector]: BuchiAutomizer initialized
[2025-03-17 20:39:15,946 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-03-17 20:39:15,946 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.03 08:39:15" (1/3) ...
[2025-03-17 20:39:15,947 INFO  L204        PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@83e0e93 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 08:39:15, skipping insertion in model container
[2025-03-17 20:39:15,947 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-03-17 20:39:15,947 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:15" (2/3) ...
[2025-03-17 20:39:15,947 INFO  L204        PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@83e0e93 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 08:39:15, skipping insertion in model container
[2025-03-17 20:39:15,947 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-03-17 20:39:15,948 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:39:15" (3/3) ...
[2025-03-17 20:39:15,949 INFO  L363   chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c
[2025-03-17 20:39:15,983 INFO  L306   stractBuchiCegarLoop]: Interprodecural is true
[2025-03-17 20:39:15,983 INFO  L307   stractBuchiCegarLoop]: Hoare is None
[2025-03-17 20:39:15,983 INFO  L308   stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates
[2025-03-17 20:39:15,983 INFO  L309   stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE
[2025-03-17 20:39:15,983 INFO  L310   stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION
[2025-03-17 20:39:15,984 INFO  L311   stractBuchiCegarLoop]: Difference is false
[2025-03-17 20:39:15,984 INFO  L312   stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA
[2025-03-17 20:39:15,984 INFO  L316   stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ========
[2025-03-17 20:39:15,989 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand  has 109 states, 108 states have (on average 1.5925925925925926) internal successors, (172), 108 states have internal predecessors, (172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:16,004 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 82
[2025-03-17 20:39:16,005 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:16,005 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:16,012 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:16,012 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:16,012 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 1 ============
[2025-03-17 20:39:16,013 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand  has 109 states, 108 states have (on average 1.5925925925925926) internal successors, (172), 108 states have internal predecessors, (172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:16,017 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 82
[2025-03-17 20:39:16,017 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:16,017 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:16,018 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:16,018 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:16,024 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:39:16,024 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:39:16,028 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:16,029 INFO  L85        PathProgramCache]: Analyzing trace with hash -1313700596, now seen corresponding path program 1 times
[2025-03-17 20:39:16,034 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:16,034 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [486756975]
[2025-03-17 20:39:16,034 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:16,035 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:16,088 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:16,099 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:16,099 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:16,100 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:16,168 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:16,171 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:16,171 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [486756975]
[2025-03-17 20:39:16,172 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [486756975] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:16,172 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:16,172 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:39:16,174 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [171372180]
[2025-03-17 20:39:16,174 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:16,176 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:39:16,177 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:16,177 INFO  L85        PathProgramCache]: Analyzing trace with hash 1945573150, now seen corresponding path program 1 times
[2025-03-17 20:39:16,177 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:16,177 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927998976]
[2025-03-17 20:39:16,177 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:16,177 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:16,187 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes.
[2025-03-17 20:39:16,192 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements.
[2025-03-17 20:39:16,192 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:16,192 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:16,213 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:16,213 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:16,213 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927998976]
[2025-03-17 20:39:16,213 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927998976] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:16,213 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:16,213 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:39:16,214 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [573713664]
[2025-03-17 20:39:16,214 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:16,214 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:39:16,219 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:39:16,248 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:39:16,249 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:39:16,252 INFO  L87              Difference]: Start difference. First operand  has 109 states, 108 states have (on average 1.5925925925925926) internal successors, (172), 108 states have internal predecessors, (172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand  has 3 states, 3 states have (on average 7.333333333333333) internal successors, (22), 2 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:16,271 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:39:16,273 INFO  L93              Difference]: Finished difference Result 109 states and 165 transitions.
[2025-03-17 20:39:16,274 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 109 states and 165 transitions.
[2025-03-17 20:39:16,279 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 81
[2025-03-17 20:39:16,286 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 109 states to 105 states and 161 transitions.
[2025-03-17 20:39:16,287 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 105
[2025-03-17 20:39:16,289 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 105
[2025-03-17 20:39:16,290 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 105 states and 161 transitions.
[2025-03-17 20:39:16,290 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:39:16,290 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 105 states and 161 transitions.
[2025-03-17 20:39:16,305 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 105 states and 161 transitions.
[2025-03-17 20:39:16,320 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105.
[2025-03-17 20:39:16,322 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 105 states, 105 states have (on average 1.5333333333333334) internal successors, (161), 104 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:16,323 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 161 transitions.
[2025-03-17 20:39:16,326 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 105 states and 161 transitions.
[2025-03-17 20:39:16,327 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:39:16,329 INFO  L432   stractBuchiCegarLoop]: Abstraction has 105 states and 161 transitions.
[2025-03-17 20:39:16,330 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 2 ============
[2025-03-17 20:39:16,330 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 105 states and 161 transitions.
[2025-03-17 20:39:16,331 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 81
[2025-03-17 20:39:16,334 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:16,335 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:16,335 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:16,335 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:16,336 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:39:16,336 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:39:16,336 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:16,337 INFO  L85        PathProgramCache]: Analyzing trace with hash -1525051509, now seen corresponding path program 1 times
[2025-03-17 20:39:16,337 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:16,337 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899023266]
[2025-03-17 20:39:16,337 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:16,337 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:16,345 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:16,352 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:16,356 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:16,357 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:16,395 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:16,395 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:16,397 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899023266]
[2025-03-17 20:39:16,398 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899023266] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:16,398 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:16,398 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:39:16,398 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383761374]
[2025-03-17 20:39:16,398 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:16,398 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:39:16,398 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:16,399 INFO  L85        PathProgramCache]: Analyzing trace with hash -1342074765, now seen corresponding path program 1 times
[2025-03-17 20:39:16,399 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:16,399 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005578355]
[2025-03-17 20:39:16,399 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:16,399 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:16,409 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes.
[2025-03-17 20:39:16,417 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements.
[2025-03-17 20:39:16,420 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:16,420 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:16,517 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:16,517 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:16,517 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1005578355]
[2025-03-17 20:39:16,517 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1005578355] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:16,517 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:16,517 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:39:16,517 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467323668]
[2025-03-17 20:39:16,517 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:16,518 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:39:16,518 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:39:16,518 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:39:16,518 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:39:16,518 INFO  L87              Difference]: Start difference. First operand 105 states and 161 transitions. cyclomatic complexity: 57 Second operand  has 3 states, 3 states have (on average 7.333333333333333) internal successors, (22), 2 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:16,531 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:39:16,535 INFO  L93              Difference]: Finished difference Result 105 states and 160 transitions.
[2025-03-17 20:39:16,535 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 160 transitions.
[2025-03-17 20:39:16,540 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 81
[2025-03-17 20:39:16,541 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 105 states and 160 transitions.
[2025-03-17 20:39:16,541 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 105
[2025-03-17 20:39:16,541 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 105
[2025-03-17 20:39:16,541 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 105 states and 160 transitions.
[2025-03-17 20:39:16,542 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:39:16,542 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 105 states and 160 transitions.
[2025-03-17 20:39:16,542 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 105 states and 160 transitions.
[2025-03-17 20:39:16,560 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105.
[2025-03-17 20:39:16,560 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 105 states, 105 states have (on average 1.5238095238095237) internal successors, (160), 104 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:16,561 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 160 transitions.
[2025-03-17 20:39:16,561 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 105 states and 160 transitions.
[2025-03-17 20:39:16,564 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:39:16,564 INFO  L432   stractBuchiCegarLoop]: Abstraction has 105 states and 160 transitions.
[2025-03-17 20:39:16,564 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 3 ============
[2025-03-17 20:39:16,564 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 105 states and 160 transitions.
[2025-03-17 20:39:16,565 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 81
[2025-03-17 20:39:16,565 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:16,565 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:16,566 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:16,566 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:16,566 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:39:16,566 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:39:16,567 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:16,567 INFO  L85        PathProgramCache]: Analyzing trace with hash -1116227284, now seen corresponding path program 1 times
[2025-03-17 20:39:16,567 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:16,567 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934208839]
[2025-03-17 20:39:16,567 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:16,567 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:16,578 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:16,581 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:16,583 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:16,583 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:16,620 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:16,621 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:16,621 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934208839]
[2025-03-17 20:39:16,621 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934208839] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:16,621 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:16,621 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:39:16,621 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [863956198]
[2025-03-17 20:39:16,621 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:16,622 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:39:16,622 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:16,623 INFO  L85        PathProgramCache]: Analyzing trace with hash -907440551, now seen corresponding path program 1 times
[2025-03-17 20:39:16,623 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:16,623 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100151272]
[2025-03-17 20:39:16,623 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:16,623 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:16,632 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes.
[2025-03-17 20:39:16,637 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements.
[2025-03-17 20:39:16,637 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:16,637 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:16,697 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:16,697 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:16,697 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100151272]
[2025-03-17 20:39:16,697 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100151272] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:16,697 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:16,698 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:39:16,698 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [971974588]
[2025-03-17 20:39:16,698 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:16,698 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:39:16,698 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:39:16,698 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:39:16,698 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:39:16,698 INFO  L87              Difference]: Start difference. First operand 105 states and 160 transitions. cyclomatic complexity: 56 Second operand  has 3 states, 3 states have (on average 7.333333333333333) internal successors, (22), 2 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:16,732 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:39:16,733 INFO  L93              Difference]: Finished difference Result 180 states and 268 transitions.
[2025-03-17 20:39:16,733 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 180 states and 268 transitions.
[2025-03-17 20:39:16,734 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 156
[2025-03-17 20:39:16,735 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 180 states to 180 states and 268 transitions.
[2025-03-17 20:39:16,736 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 180
[2025-03-17 20:39:16,736 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 180
[2025-03-17 20:39:16,736 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 180 states and 268 transitions.
[2025-03-17 20:39:16,738 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:39:16,738 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 180 states and 268 transitions.
[2025-03-17 20:39:16,738 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 180 states and 268 transitions.
[2025-03-17 20:39:16,743 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 169.
[2025-03-17 20:39:16,746 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 169 states, 169 states have (on average 1.4970414201183433) internal successors, (253), 168 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:16,746 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 253 transitions.
[2025-03-17 20:39:16,748 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 169 states and 253 transitions.
[2025-03-17 20:39:16,748 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:39:16,749 INFO  L432   stractBuchiCegarLoop]: Abstraction has 169 states and 253 transitions.
[2025-03-17 20:39:16,749 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 4 ============
[2025-03-17 20:39:16,749 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 169 states and 253 transitions.
[2025-03-17 20:39:16,750 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 145
[2025-03-17 20:39:16,750 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:16,751 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:16,751 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:16,751 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:16,751 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:39:16,751 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:39:16,752 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:16,752 INFO  L85        PathProgramCache]: Analyzing trace with hash -1034979895, now seen corresponding path program 1 times
[2025-03-17 20:39:16,752 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:16,752 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722807217]
[2025-03-17 20:39:16,752 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:16,752 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:16,761 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:16,764 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:16,764 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:16,764 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:16,810 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:16,810 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:16,810 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1722807217]
[2025-03-17 20:39:16,810 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1722807217] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:16,811 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:16,811 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:39:16,811 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164009693]
[2025-03-17 20:39:16,811 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:16,811 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:39:16,811 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:16,811 INFO  L85        PathProgramCache]: Analyzing trace with hash -907440551, now seen corresponding path program 2 times
[2025-03-17 20:39:16,812 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:16,812 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1527418441]
[2025-03-17 20:39:16,812 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-17 20:39:16,812 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:16,818 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 33 statements into 1 equivalence classes.
[2025-03-17 20:39:16,822 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 33 of 33 statements.
[2025-03-17 20:39:16,822 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:39:16,822 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:16,862 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:16,862 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:16,862 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1527418441]
[2025-03-17 20:39:16,862 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1527418441] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:16,863 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:16,863 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:39:16,863 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969383495]
[2025-03-17 20:39:16,863 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:16,863 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:39:16,863 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:39:16,863 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:39:16,863 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:39:16,864 INFO  L87              Difference]: Start difference. First operand 169 states and 253 transitions. cyclomatic complexity: 86 Second operand  has 4 states, 4 states have (on average 5.5) internal successors, (22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:16,957 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:39:16,957 INFO  L93              Difference]: Finished difference Result 377 states and 552 transitions.
[2025-03-17 20:39:16,957 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 377 states and 552 transitions.
[2025-03-17 20:39:16,962 INFO  L131   ngComponentsAnalysis]: Automaton has 3 accepting balls. 337
[2025-03-17 20:39:16,964 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 377 states to 377 states and 552 transitions.
[2025-03-17 20:39:16,964 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 377
[2025-03-17 20:39:16,967 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 377
[2025-03-17 20:39:16,967 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 377 states and 552 transitions.
[2025-03-17 20:39:16,969 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:39:16,969 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 377 states and 552 transitions.
[2025-03-17 20:39:16,969 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 377 states and 552 transitions.
[2025-03-17 20:39:16,977 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 377 to 301.
[2025-03-17 20:39:16,978 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 301 states, 301 states have (on average 1.478405315614618) internal successors, (445), 300 states have internal predecessors, (445), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:16,981 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 301 states to 301 states and 445 transitions.
[2025-03-17 20:39:16,981 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 301 states and 445 transitions.
[2025-03-17 20:39:16,981 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:39:16,983 INFO  L432   stractBuchiCegarLoop]: Abstraction has 301 states and 445 transitions.
[2025-03-17 20:39:16,983 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 5 ============
[2025-03-17 20:39:16,983 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 301 states and 445 transitions.
[2025-03-17 20:39:16,984 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 277
[2025-03-17 20:39:16,984 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:16,984 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:16,985 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:16,985 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:16,985 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:39:16,985 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:39:16,986 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:16,986 INFO  L85        PathProgramCache]: Analyzing trace with hash -2033087732, now seen corresponding path program 1 times
[2025-03-17 20:39:16,986 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:16,986 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088039673]
[2025-03-17 20:39:16,986 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:16,986 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:16,990 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:16,996 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:16,999 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:16,999 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,000 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:39:17,001 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:17,004 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:17,004 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,004 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,023 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:39:17,024 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,025 INFO  L85        PathProgramCache]: Analyzing trace with hash -316165002, now seen corresponding path program 1 times
[2025-03-17 20:39:17,025 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,025 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293195816]
[2025-03-17 20:39:17,025 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:17,025 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,032 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes.
[2025-03-17 20:39:17,038 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements.
[2025-03-17 20:39:17,038 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,038 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:17,062 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:17,062 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:17,062 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1293195816]
[2025-03-17 20:39:17,062 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1293195816] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:17,062 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:17,062 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:39:17,062 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1529494117]
[2025-03-17 20:39:17,062 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:17,062 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:39:17,062 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:39:17,063 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:39:17,063 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:39:17,063 INFO  L87              Difference]: Start difference. First operand 301 states and 445 transitions. cyclomatic complexity: 146 Second operand  has 4 states, 4 states have (on average 8.25) internal successors, (33), 4 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,111 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:39:17,112 INFO  L93              Difference]: Finished difference Result 311 states and 449 transitions.
[2025-03-17 20:39:17,112 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 311 states and 449 transitions.
[2025-03-17 20:39:17,115 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 287
[2025-03-17 20:39:17,117 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 311 states to 311 states and 449 transitions.
[2025-03-17 20:39:17,117 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 311
[2025-03-17 20:39:17,118 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 311
[2025-03-17 20:39:17,118 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 311 states and 449 transitions.
[2025-03-17 20:39:17,118 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:39:17,118 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 311 states and 449 transitions.
[2025-03-17 20:39:17,118 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 311 states and 449 transitions.
[2025-03-17 20:39:17,125 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 311 to 311.
[2025-03-17 20:39:17,126 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 311 states, 311 states have (on average 1.4437299035369775) internal successors, (449), 310 states have internal predecessors, (449), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,127 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 311 states and 449 transitions.
[2025-03-17 20:39:17,127 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 311 states and 449 transitions.
[2025-03-17 20:39:17,130 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:39:17,131 INFO  L432   stractBuchiCegarLoop]: Abstraction has 311 states and 449 transitions.
[2025-03-17 20:39:17,131 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 6 ============
[2025-03-17 20:39:17,131 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 311 states and 449 transitions.
[2025-03-17 20:39:17,133 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 287
[2025-03-17 20:39:17,133 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:17,133 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:17,133 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,133 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,136 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:39:17,136 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:39:17,136 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,137 INFO  L85        PathProgramCache]: Analyzing trace with hash -2033087732, now seen corresponding path program 2 times
[2025-03-17 20:39:17,137 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,137 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1732151135]
[2025-03-17 20:39:17,137 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-17 20:39:17,137 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,141 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:17,143 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:17,143 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:39:17,143 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,143 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:39:17,144 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:17,146 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:17,146 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,146 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,152 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:39:17,155 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,155 INFO  L85        PathProgramCache]: Analyzing trace with hash 1191386807, now seen corresponding path program 1 times
[2025-03-17 20:39:17,155 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,155 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83676116]
[2025-03-17 20:39:17,155 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:17,155 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,160 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes.
[2025-03-17 20:39:17,162 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements.
[2025-03-17 20:39:17,162 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,162 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:17,195 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:17,196 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:17,196 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [83676116]
[2025-03-17 20:39:17,197 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [83676116] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:17,197 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:17,197 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:39:17,197 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285187266]
[2025-03-17 20:39:17,197 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:17,197 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:39:17,197 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:39:17,197 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:39:17,197 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:39:17,198 INFO  L87              Difference]: Start difference. First operand 311 states and 449 transitions. cyclomatic complexity: 140 Second operand  has 4 states, 4 states have (on average 8.25) internal successors, (33), 4 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,246 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:39:17,247 INFO  L93              Difference]: Finished difference Result 327 states and 465 transitions.
[2025-03-17 20:39:17,247 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 465 transitions.
[2025-03-17 20:39:17,248 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 303
[2025-03-17 20:39:17,251 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 327 states and 465 transitions.
[2025-03-17 20:39:17,252 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 327
[2025-03-17 20:39:17,252 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 327
[2025-03-17 20:39:17,252 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 327 states and 465 transitions.
[2025-03-17 20:39:17,252 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:39:17,252 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 327 states and 465 transitions.
[2025-03-17 20:39:17,253 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 327 states and 465 transitions.
[2025-03-17 20:39:17,258 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 319.
[2025-03-17 20:39:17,261 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 319 states, 319 states have (on average 1.432601880877743) internal successors, (457), 318 states have internal predecessors, (457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,262 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 319 states to 319 states and 457 transitions.
[2025-03-17 20:39:17,263 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 319 states and 457 transitions.
[2025-03-17 20:39:17,263 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:39:17,263 INFO  L432   stractBuchiCegarLoop]: Abstraction has 319 states and 457 transitions.
[2025-03-17 20:39:17,265 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 7 ============
[2025-03-17 20:39:17,266 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 319 states and 457 transitions.
[2025-03-17 20:39:17,267 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 295
[2025-03-17 20:39:17,267 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:17,267 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:17,268 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,268 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,268 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:39:17,268 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:39:17,271 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,271 INFO  L85        PathProgramCache]: Analyzing trace with hash -2033087732, now seen corresponding path program 3 times
[2025-03-17 20:39:17,271 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,271 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [778243739]
[2025-03-17 20:39:17,272 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2
[2025-03-17 20:39:17,272 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,278 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:17,282 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:17,282 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s)
[2025-03-17 20:39:17,282 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,282 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:39:17,286 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:17,287 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:17,287 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,287 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,294 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:39:17,294 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,294 INFO  L85        PathProgramCache]: Analyzing trace with hash 17997630, now seen corresponding path program 1 times
[2025-03-17 20:39:17,295 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,295 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902006830]
[2025-03-17 20:39:17,295 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:17,295 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,302 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes.
[2025-03-17 20:39:17,304 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements.
[2025-03-17 20:39:17,306 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,306 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:17,323 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:17,323 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:17,323 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902006830]
[2025-03-17 20:39:17,323 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902006830] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:17,323 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:17,324 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:39:17,324 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811725746]
[2025-03-17 20:39:17,324 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:17,324 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:39:17,324 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:39:17,324 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:39:17,324 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:39:17,325 INFO  L87              Difference]: Start difference. First operand 319 states and 457 transitions. cyclomatic complexity: 140 Second operand  has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,352 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:39:17,352 INFO  L93              Difference]: Finished difference Result 470 states and 651 transitions.
[2025-03-17 20:39:17,352 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 470 states and 651 transitions.
[2025-03-17 20:39:17,355 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 432
[2025-03-17 20:39:17,356 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 470 states to 470 states and 651 transitions.
[2025-03-17 20:39:17,357 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 470
[2025-03-17 20:39:17,357 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 470
[2025-03-17 20:39:17,357 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 470 states and 651 transitions.
[2025-03-17 20:39:17,358 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:39:17,358 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 470 states and 651 transitions.
[2025-03-17 20:39:17,358 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 470 states and 651 transitions.
[2025-03-17 20:39:17,363 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 470 to 470.
[2025-03-17 20:39:17,364 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 470 states, 470 states have (on average 1.3851063829787233) internal successors, (651), 469 states have internal predecessors, (651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,365 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 651 transitions.
[2025-03-17 20:39:17,365 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 470 states and 651 transitions.
[2025-03-17 20:39:17,369 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:39:17,370 INFO  L432   stractBuchiCegarLoop]: Abstraction has 470 states and 651 transitions.
[2025-03-17 20:39:17,370 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 8 ============
[2025-03-17 20:39:17,370 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 470 states and 651 transitions.
[2025-03-17 20:39:17,372 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 432
[2025-03-17 20:39:17,372 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:17,372 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:17,372 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,372 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,372 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:39:17,373 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:39:17,373 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,373 INFO  L85        PathProgramCache]: Analyzing trace with hash -1036045170, now seen corresponding path program 1 times
[2025-03-17 20:39:17,373 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,373 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952852779]
[2025-03-17 20:39:17,373 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:17,373 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,378 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:17,381 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:17,381 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,381 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:17,403 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:17,403 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:17,403 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952852779]
[2025-03-17 20:39:17,403 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952852779] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:17,403 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:17,403 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:39:17,404 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1655711576]
[2025-03-17 20:39:17,404 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:17,404 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-17 20:39:17,404 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,404 INFO  L85        PathProgramCache]: Analyzing trace with hash 979611647, now seen corresponding path program 1 times
[2025-03-17 20:39:17,404 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,404 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154976028]
[2025-03-17 20:39:17,405 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:17,405 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,409 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes.
[2025-03-17 20:39:17,410 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements.
[2025-03-17 20:39:17,410 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,410 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:17,437 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:17,437 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:17,437 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [154976028]
[2025-03-17 20:39:17,437 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [154976028] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:17,437 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:17,437 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:39:17,437 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523818673]
[2025-03-17 20:39:17,437 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:17,437 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:39:17,437 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:39:17,437 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:39:17,437 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:39:17,438 INFO  L87              Difference]: Start difference. First operand 470 states and 651 transitions. cyclomatic complexity: 183 Second operand  has 3 states, 3 states have (on average 7.333333333333333) internal successors, (22), 2 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,456 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:39:17,456 INFO  L93              Difference]: Finished difference Result 319 states and 437 transitions.
[2025-03-17 20:39:17,456 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 319 states and 437 transitions.
[2025-03-17 20:39:17,458 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 295
[2025-03-17 20:39:17,459 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 319 states to 319 states and 437 transitions.
[2025-03-17 20:39:17,459 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 319
[2025-03-17 20:39:17,459 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 319
[2025-03-17 20:39:17,459 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 319 states and 437 transitions.
[2025-03-17 20:39:17,460 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:39:17,460 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 319 states and 437 transitions.
[2025-03-17 20:39:17,460 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 319 states and 437 transitions.
[2025-03-17 20:39:17,463 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 319.
[2025-03-17 20:39:17,463 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 319 states, 319 states have (on average 1.3699059561128526) internal successors, (437), 318 states have internal predecessors, (437), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,464 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 319 states to 319 states and 437 transitions.
[2025-03-17 20:39:17,464 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 319 states and 437 transitions.
[2025-03-17 20:39:17,465 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:39:17,465 INFO  L432   stractBuchiCegarLoop]: Abstraction has 319 states and 437 transitions.
[2025-03-17 20:39:17,465 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 9 ============
[2025-03-17 20:39:17,465 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 319 states and 437 transitions.
[2025-03-17 20:39:17,466 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 295
[2025-03-17 20:39:17,466 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:17,466 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:17,467 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,467 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,467 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:39:17,467 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:39:17,469 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,469 INFO  L85        PathProgramCache]: Analyzing trace with hash -2033087732, now seen corresponding path program 4 times
[2025-03-17 20:39:17,469 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,469 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [750689573]
[2025-03-17 20:39:17,469 INFO  L95    rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST
[2025-03-17 20:39:17,469 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,473 INFO  L108    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 22 statements into 2 equivalence classes.
[2025-03-17 20:39:17,478 INFO  L111    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:17,478 INFO  L114    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s)
[2025-03-17 20:39:17,478 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,478 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:39:17,479 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:17,481 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:17,481 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,481 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,485 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:39:17,485 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,485 INFO  L85        PathProgramCache]: Analyzing trace with hash 979611647, now seen corresponding path program 2 times
[2025-03-17 20:39:17,485 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,485 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2021538572]
[2025-03-17 20:39:17,485 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-17 20:39:17,485 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,490 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 34 statements into 1 equivalence classes.
[2025-03-17 20:39:17,491 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 34 of 34 statements.
[2025-03-17 20:39:17,491 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:39:17,491 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:17,525 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:17,525 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:17,525 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2021538572]
[2025-03-17 20:39:17,525 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2021538572] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:17,526 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:17,526 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-03-17 20:39:17,526 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265099305]
[2025-03-17 20:39:17,526 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:17,527 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:39:17,527 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:39:17,527 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-17 20:39:17,527 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-17 20:39:17,527 INFO  L87              Difference]: Start difference. First operand 319 states and 437 transitions. cyclomatic complexity: 120 Second operand  has 4 states, 4 states have (on average 8.5) internal successors, (34), 4 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,557 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:39:17,557 INFO  L93              Difference]: Finished difference Result 323 states and 432 transitions.
[2025-03-17 20:39:17,558 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 432 transitions.
[2025-03-17 20:39:17,559 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 299
[2025-03-17 20:39:17,560 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 323 states and 432 transitions.
[2025-03-17 20:39:17,561 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 323
[2025-03-17 20:39:17,561 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 323
[2025-03-17 20:39:17,561 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 323 states and 432 transitions.
[2025-03-17 20:39:17,561 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:39:17,561 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 323 states and 432 transitions.
[2025-03-17 20:39:17,562 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 323 states and 432 transitions.
[2025-03-17 20:39:17,564 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323.
[2025-03-17 20:39:17,565 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 323 states, 323 states have (on average 1.3374613003095974) internal successors, (432), 322 states have internal predecessors, (432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,565 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 432 transitions.
[2025-03-17 20:39:17,566 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 323 states and 432 transitions.
[2025-03-17 20:39:17,566 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-17 20:39:17,567 INFO  L432   stractBuchiCegarLoop]: Abstraction has 323 states and 432 transitions.
[2025-03-17 20:39:17,567 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 10 ============
[2025-03-17 20:39:17,567 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 432 transitions.
[2025-03-17 20:39:17,568 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 299
[2025-03-17 20:39:17,569 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:17,569 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:17,569 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,569 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,569 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-17 20:39:17,569 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-17 20:39:17,570 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,570 INFO  L85        PathProgramCache]: Analyzing trace with hash -2033087732, now seen corresponding path program 5 times
[2025-03-17 20:39:17,570 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,570 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025815857]
[2025-03-17 20:39:17,570 INFO  L95    rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1
[2025-03-17 20:39:17,570 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,574 INFO  L108    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:17,575 INFO  L111    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:17,575 INFO  L114    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:39:17,575 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,575 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:39:17,576 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-03-17 20:39:17,578 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-03-17 20:39:17,578 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,578 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,580 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:39:17,582 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,582 INFO  L85        PathProgramCache]: Analyzing trace with hash 570787422, now seen corresponding path program 1 times
[2025-03-17 20:39:17,582 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,582 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [709083350]
[2025-03-17 20:39:17,582 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:17,582 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,586 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes.
[2025-03-17 20:39:17,590 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements.
[2025-03-17 20:39:17,590 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,590 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:17,610 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:17,610 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:17,610 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [709083350]
[2025-03-17 20:39:17,610 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [709083350] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:17,610 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:17,610 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-17 20:39:17,610 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827452336]
[2025-03-17 20:39:17,610 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:17,611 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-17 20:39:17,611 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:39:17,611 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:39:17,611 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:39:17,611 INFO  L87              Difference]: Start difference. First operand 323 states and 432 transitions. cyclomatic complexity: 111 Second operand  has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,628 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:39:17,628 INFO  L93              Difference]: Finished difference Result 403 states and 525 transitions.
[2025-03-17 20:39:17,628 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 403 states and 525 transitions.
[2025-03-17 20:39:17,630 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 378
[2025-03-17 20:39:17,632 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 403 states to 403 states and 525 transitions.
[2025-03-17 20:39:17,632 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 403
[2025-03-17 20:39:17,632 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 403
[2025-03-17 20:39:17,632 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 403 states and 525 transitions.
[2025-03-17 20:39:17,633 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:39:17,633 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 403 states and 525 transitions.
[2025-03-17 20:39:17,633 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 403 states and 525 transitions.
[2025-03-17 20:39:17,636 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 403 to 403.
[2025-03-17 20:39:17,636 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 403 states, 403 states have (on average 1.3027295285359801) internal successors, (525), 402 states have internal predecessors, (525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,637 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 403 states and 525 transitions.
[2025-03-17 20:39:17,637 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 403 states and 525 transitions.
[2025-03-17 20:39:17,638 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:39:17,638 INFO  L432   stractBuchiCegarLoop]: Abstraction has 403 states and 525 transitions.
[2025-03-17 20:39:17,638 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 11 ============
[2025-03-17 20:39:17,638 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 403 states and 525 transitions.
[2025-03-17 20:39:17,640 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 378
[2025-03-17 20:39:17,640 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:17,640 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:17,640 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,640 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,640 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-17 20:39:17,641 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" 
[2025-03-17 20:39:17,641 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,641 INFO  L85        PathProgramCache]: Analyzing trace with hash 1398789908, now seen corresponding path program 1 times
[2025-03-17 20:39:17,641 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,641 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690705496]
[2025-03-17 20:39:17,641 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:17,641 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,646 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes.
[2025-03-17 20:39:17,647 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements.
[2025-03-17 20:39:17,647 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,647 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,647 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:39:17,648 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes.
[2025-03-17 20:39:17,651 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements.
[2025-03-17 20:39:17,651 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,651 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,655 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:39:17,656 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,656 INFO  L85        PathProgramCache]: Analyzing trace with hash 546209463, now seen corresponding path program 1 times
[2025-03-17 20:39:17,656 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,656 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505704812]
[2025-03-17 20:39:17,656 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:17,656 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,658 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes.
[2025-03-17 20:39:17,659 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements.
[2025-03-17 20:39:17,659 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,659 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,659 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:39:17,659 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes.
[2025-03-17 20:39:17,659 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements.
[2025-03-17 20:39:17,659 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,659 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,660 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:39:17,661 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,661 INFO  L85        PathProgramCache]: Analyzing trace with hash 523997898, now seen corresponding path program 1 times
[2025-03-17 20:39:17,661 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,661 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68658246]
[2025-03-17 20:39:17,661 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:17,661 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,665 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes.
[2025-03-17 20:39:17,667 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements.
[2025-03-17 20:39:17,667 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,667 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-17 20:39:17,706 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-17 20:39:17,706 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-17 20:39:17,706 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [68658246]
[2025-03-17 20:39:17,706 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [68658246] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-17 20:39:17,706 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-17 20:39:17,706 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-17 20:39:17,706 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [829981810]
[2025-03-17 20:39:17,706 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-17 20:39:17,746 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-17 20:39:17,746 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-17 20:39:17,746 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-17 20:39:17,746 INFO  L87              Difference]: Start difference. First operand 403 states and 525 transitions. cyclomatic complexity: 126 Second operand  has 3 states, 2 states have (on average 15.5) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,770 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-17 20:39:17,770 INFO  L93              Difference]: Finished difference Result 652 states and 832 transitions.
[2025-03-17 20:39:17,770 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 652 states and 832 transitions.
[2025-03-17 20:39:17,773 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 626
[2025-03-17 20:39:17,775 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 652 states to 652 states and 832 transitions.
[2025-03-17 20:39:17,775 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 652
[2025-03-17 20:39:17,776 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 652
[2025-03-17 20:39:17,776 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 652 states and 832 transitions.
[2025-03-17 20:39:17,776 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-17 20:39:17,776 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 652 states and 832 transitions.
[2025-03-17 20:39:17,778 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 652 states and 832 transitions.
[2025-03-17 20:39:17,784 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 652 to 595.
[2025-03-17 20:39:17,784 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 595 states, 595 states have (on average 1.289075630252101) internal successors, (767), 594 states have internal predecessors, (767), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-17 20:39:17,786 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 595 states to 595 states and 767 transitions.
[2025-03-17 20:39:17,786 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 595 states and 767 transitions.
[2025-03-17 20:39:17,786 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-17 20:39:17,787 INFO  L432   stractBuchiCegarLoop]: Abstraction has 595 states and 767 transitions.
[2025-03-17 20:39:17,787 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 12 ============
[2025-03-17 20:39:17,787 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 595 states and 767 transitions.
[2025-03-17 20:39:17,788 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 569
[2025-03-17 20:39:17,788 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-17 20:39:17,789 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-17 20:39:17,789 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,789 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-17 20:39:17,789 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-17 20:39:17,789 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" 
[2025-03-17 20:39:17,789 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,789 INFO  L85        PathProgramCache]: Analyzing trace with hash 1398789908, now seen corresponding path program 2 times
[2025-03-17 20:39:17,789 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,789 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628294046]
[2025-03-17 20:39:17,789 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-17 20:39:17,790 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,793 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 23 statements into 1 equivalence classes.
[2025-03-17 20:39:17,794 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 23 of 23 statements.
[2025-03-17 20:39:17,794 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-17 20:39:17,794 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,794 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:39:17,795 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes.
[2025-03-17 20:39:17,796 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements.
[2025-03-17 20:39:17,796 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,796 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,798 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:39:17,798 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,798 INFO  L85        PathProgramCache]: Analyzing trace with hash 921286249, now seen corresponding path program 1 times
[2025-03-17 20:39:17,799 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,799 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861747515]
[2025-03-17 20:39:17,799 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:17,799 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,800 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes.
[2025-03-17 20:39:17,801 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements.
[2025-03-17 20:39:17,801 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,801 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,801 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:39:17,801 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes.
[2025-03-17 20:39:17,801 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements.
[2025-03-17 20:39:17,802 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,802 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,802 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:39:17,803 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-17 20:39:17,803 INFO  L85        PathProgramCache]: Analyzing trace with hash 1050808764, now seen corresponding path program 1 times
[2025-03-17 20:39:17,803 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-17 20:39:17,803 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [772838629]
[2025-03-17 20:39:17,803 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-17 20:39:17,803 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-17 20:39:17,806 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes.
[2025-03-17 20:39:17,812 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements.
[2025-03-17 20:39:17,812 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,812 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,812 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:39:17,814 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes.
[2025-03-17 20:39:17,816 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements.
[2025-03-17 20:39:17,816 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:17,816 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:17,819 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-17 20:39:18,140 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes.
[2025-03-17 20:39:18,144 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements.
[2025-03-17 20:39:18,144 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:18,144 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:18,144 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-17 20:39:18,149 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes.
[2025-03-17 20:39:18,152 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements.
[2025-03-17 20:39:18,152 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-17 20:39:18,152 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-17 20:39:18,224 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.03 08:39:18 BoogieIcfgContainer
[2025-03-17 20:39:18,225 INFO  L131        PluginConnector]: ------------------------ END BuchiAutomizer----------------------------
[2025-03-17 20:39:18,225 INFO  L112        PluginConnector]: ------------------------Witness Printer----------------------------
[2025-03-17 20:39:18,225 INFO  L270        PluginConnector]: Initializing Witness Printer...
[2025-03-17 20:39:18,225 INFO  L274        PluginConnector]: Witness Printer initialized
[2025-03-17 20:39:18,226 INFO  L184        PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:39:15" (3/4) ...
[2025-03-17 20:39:18,227 INFO  L143         WitnessPrinter]: Generating witness for non-termination counterexample
[2025-03-17 20:39:18,292 INFO  L149         WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml
[2025-03-17 20:39:18,292 INFO  L131        PluginConnector]: ------------------------ END Witness Printer----------------------------
[2025-03-17 20:39:18,294 INFO  L158              Benchmark]: Toolchain (without parser) took 3018.72ms. Allocated memory is still 142.6MB. Free memory was 112.3MB in the beginning and 107.0MB in the end (delta: 5.3MB). Peak memory consumption was 78.8MB. Max. memory is 16.1GB.
[2025-03-17 20:39:18,295 INFO  L158              Benchmark]: CDTParser took 0.16ms. Allocated memory is still 201.3MB. Free memory is still 126.7MB. There was no memory consumed. Max. memory is 16.1GB.
[2025-03-17 20:39:18,295 INFO  L158              Benchmark]: CACSL2BoogieTranslator took 187.12ms. Allocated memory is still 142.6MB. Free memory was 112.3MB in the beginning and 100.4MB in the end (delta: 11.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
[2025-03-17 20:39:18,295 INFO  L158              Benchmark]: Boogie Procedure Inliner took 28.77ms. Allocated memory is still 142.6MB. Free memory was 100.4MB in the beginning and 98.3MB in the end (delta: 2.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
[2025-03-17 20:39:18,295 INFO  L158              Benchmark]: Boogie Preprocessor took 26.66ms. Allocated memory is still 142.6MB. Free memory was 98.3MB in the beginning and 96.2MB in the end (delta: 2.1MB). There was no memory consumed. Max. memory is 16.1GB.
[2025-03-17 20:39:18,296 INFO  L158              Benchmark]: IcfgBuilder took 418.34ms. Allocated memory is still 142.6MB. Free memory was 96.2MB in the beginning and 75.0MB in the end (delta: 21.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
[2025-03-17 20:39:18,296 INFO  L158              Benchmark]: BuchiAutomizer took 2283.56ms. Allocated memory is still 142.6MB. Free memory was 75.0MB in the beginning and 45.7MB in the end (delta: 29.3MB). Peak memory consumption was 31.8MB. Max. memory is 16.1GB.
[2025-03-17 20:39:18,296 INFO  L158              Benchmark]: Witness Printer took 67.44ms. Allocated memory is still 142.6MB. Free memory was 45.7MB in the beginning and 107.0MB in the end (delta: -61.3MB). Peak memory consumption was 13.4MB. Max. memory is 16.1GB.
[2025-03-17 20:39:18,298 INFO  L338   ainManager$Toolchain]: #######################  End [Toolchain 1] #######################
 --- Results ---
 * Results from de.uni_freiburg.informatik.ultimate.core:
  - StatisticsResult: Toolchain Benchmarks
    Benchmark results are:
 * CDTParser took 0.16ms. Allocated memory is still 201.3MB. Free memory is still 126.7MB. There was no memory consumed. Max. memory is 16.1GB.
 * CACSL2BoogieTranslator took 187.12ms. Allocated memory is still 142.6MB. Free memory was 112.3MB in the beginning and 100.4MB in the end (delta: 11.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
 * Boogie Procedure Inliner took 28.77ms. Allocated memory is still 142.6MB. Free memory was 100.4MB in the beginning and 98.3MB in the end (delta: 2.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
 * Boogie Preprocessor took 26.66ms. Allocated memory is still 142.6MB. Free memory was 98.3MB in the beginning and 96.2MB in the end (delta: 2.1MB). There was no memory consumed. Max. memory is 16.1GB.
 * IcfgBuilder took 418.34ms. Allocated memory is still 142.6MB. Free memory was 96.2MB in the beginning and 75.0MB in the end (delta: 21.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
 * BuchiAutomizer took 2283.56ms. Allocated memory is still 142.6MB. Free memory was 75.0MB in the beginning and 45.7MB in the end (delta: 29.3MB). Peak memory consumption was 31.8MB. Max. memory is 16.1GB.
 * Witness Printer took 67.44ms. Allocated memory is still 142.6MB. Free memory was 45.7MB in the beginning and 107.0MB in the end (delta: -61.3MB). Peak memory consumption was 13.4MB. Max. memory is 16.1GB.
 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction:
  - StatisticsResult: Constructed decomposition of program
    Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 4 locations. The remainder module has 595 locations.
  - StatisticsResult: Timing statistics
    BüchiAutomizer plugin needed 2.1s and 12 iterations.  TraceHistogramMax:1. Analysis of lassos took 1.4s. Construction of modules took 0.2s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 11 MinimizatonAttempts, 152 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1.	Nontrivial modules had stage [0, 0, 0, 0, 0].	InterpolantCoveringCapabilityFinite: 0/0	InterpolantCoveringCapabilityBuchi: 0/0	HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1183 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1183 mSDsluCounter, 3177 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1515 mSDsCounter, 75 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 207 IncrementalHoareTripleChecker+Invalid, 282 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 75 mSolverCounterUnsat, 1662 mSDtfsCounter, 207 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown	LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0	LassoNonterminationAnalysisSatUnbounded: 0	LassoNonterminationAnalysisUnsat: 0	LassoNonterminationAnalysisUnknown: 0	LassoNonterminationAnalysisTime: 0.0s	InitialAbstractionConstructionTime: 0.0s
  - TerminationAnalysisResult: Nontermination possible
    Buchi Automizer proved that your program is nonterminating for some inputs
  - LassoShapedNonTerminationArgument [Line: 201]: Nontermination argument in form of an infinite program execution.
    Nontermination argument in form of an infinite program execution.
Stem:
[L25]               int m_pc  =    0;
[L26]               int t1_pc  =    0;
[L27]               int m_st  ;
[L28]               int t1_st  ;
[L29]               int m_i  ;
[L30]               int t1_i  ;
[L31]               int M_E  =    2;
[L32]               int T1_E  =    2;
[L33]               int E_1  =    2;
[L449]              int __retres1 ;
[L453]  CALL        init_model()
[L364]              m_i = 1
[L365]              t1_i = 1
[L453]  RET         init_model()
[L454]  CALL        start_simulation()
[L390]              int kernel_st ;
[L391]              int tmp ;
[L392]              int tmp___0 ;
[L396]              kernel_st = 0
[L397]  FCALL       update_channels()
[L398]  CALL        init_threads()
[L161]  COND TRUE   m_i == 1
[L162]              m_st = 0
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L166]  COND TRUE   t1_i == 1
[L167]              t1_st = 0
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L398]  RET         init_threads()
[L399]  CALL        fire_delta_events()
[L250]  COND FALSE  !(M_E == 0)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L255]  COND FALSE  !(T1_E == 0)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L260]  COND FALSE  !(E_1 == 0)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L399]  RET         fire_delta_events()
[L400]  CALL        activate_threads()
[L293]              int tmp ;
[L294]              int tmp___0 ;
[L298]  CALL, EXPR  is_master_triggered()
[L112]              int __retres1 ;
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L115]  COND FALSE  !(m_pc == 1)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L125]              __retres1 = 0
        VAL         [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L127]              return (__retres1);
[L298]  RET, EXPR   is_master_triggered()
[L298]              tmp = is_master_triggered()
[L300]  COND FALSE  !(\read(tmp))
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L306]  CALL, EXPR  is_transmit1_triggered()
[L131]              int __retres1 ;
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L134]  COND FALSE  !(t1_pc == 1)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L144]              __retres1 = 0
        VAL         [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L146]              return (__retres1);
[L306]  RET, EXPR   is_transmit1_triggered()
[L306]              tmp___0 = is_transmit1_triggered()
[L308]  COND FALSE  !(\read(tmp___0))
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L400]  RET         activate_threads()
[L401]  CALL        reset_delta_events()
[L273]  COND FALSE  !(M_E == 1)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L278]  COND FALSE  !(T1_E == 1)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L283]  COND FALSE  !(E_1 == 1)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L401]  RET         reset_delta_events()
[L404]  COND TRUE   1
[L407]              kernel_st = 1
[L408]  CALL        eval()
[L197]              int tmp ;
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
Loop:
[L201]  COND TRUE   1
[L204]  CALL, EXPR  exists_runnable_thread()
[L176]              int __retres1 ;
[L179]  COND TRUE   m_st == 0
[L180]              __retres1 = 1
[L192]              return (__retres1);
[L204]  RET, EXPR   exists_runnable_thread()
[L204]              tmp = exists_runnable_thread()
[L206]  COND TRUE   \read(tmp)
[L211]  COND TRUE   m_st == 0
[L212]              int tmp_ndt_1;
[L213]              tmp_ndt_1 = __VERIFIER_nondet_int()
[L214]  COND FALSE  !(\read(tmp_ndt_1))
[L225]  COND TRUE   t1_st == 0
[L226]              int tmp_ndt_2;
[L227]              tmp_ndt_2 = __VERIFIER_nondet_int()
[L228]  COND FALSE  !(\read(tmp_ndt_2))
End of lasso representation.
  - StatisticsResult: NonterminationArgumentStatistics
    Fixpoint
  - NonterminatingLassoResult [Line: 201]: Nonterminating execution
    Found a nonterminating execution for the following lasso shaped sequence of statements.
Stem:
[L25]               int m_pc  =    0;
[L26]               int t1_pc  =    0;
[L27]               int m_st  ;
[L28]               int t1_st  ;
[L29]               int m_i  ;
[L30]               int t1_i  ;
[L31]               int M_E  =    2;
[L32]               int T1_E  =    2;
[L33]               int E_1  =    2;
[L449]              int __retres1 ;
[L453]  CALL        init_model()
[L364]              m_i = 1
[L365]              t1_i = 1
[L453]  RET         init_model()
[L454]  CALL        start_simulation()
[L390]              int kernel_st ;
[L391]              int tmp ;
[L392]              int tmp___0 ;
[L396]              kernel_st = 0
[L397]  FCALL       update_channels()
[L398]  CALL        init_threads()
[L161]  COND TRUE   m_i == 1
[L162]              m_st = 0
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L166]  COND TRUE   t1_i == 1
[L167]              t1_st = 0
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L398]  RET         init_threads()
[L399]  CALL        fire_delta_events()
[L250]  COND FALSE  !(M_E == 0)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L255]  COND FALSE  !(T1_E == 0)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L260]  COND FALSE  !(E_1 == 0)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L399]  RET         fire_delta_events()
[L400]  CALL        activate_threads()
[L293]              int tmp ;
[L294]              int tmp___0 ;
[L298]  CALL, EXPR  is_master_triggered()
[L112]              int __retres1 ;
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L115]  COND FALSE  !(m_pc == 1)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L125]              __retres1 = 0
        VAL         [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L127]              return (__retres1);
[L298]  RET, EXPR   is_master_triggered()
[L298]              tmp = is_master_triggered()
[L300]  COND FALSE  !(\read(tmp))
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L306]  CALL, EXPR  is_transmit1_triggered()
[L131]              int __retres1 ;
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L134]  COND FALSE  !(t1_pc == 1)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L144]              __retres1 = 0
        VAL         [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L146]              return (__retres1);
[L306]  RET, EXPR   is_transmit1_triggered()
[L306]              tmp___0 = is_transmit1_triggered()
[L308]  COND FALSE  !(\read(tmp___0))
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L400]  RET         activate_threads()
[L401]  CALL        reset_delta_events()
[L273]  COND FALSE  !(M_E == 1)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L278]  COND FALSE  !(T1_E == 1)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L283]  COND FALSE  !(E_1 == 1)
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
[L401]  RET         reset_delta_events()
[L404]  COND TRUE   1
[L407]              kernel_st = 1
[L408]  CALL        eval()
[L197]              int tmp ;
        VAL         [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0]
Loop:
[L201]  COND TRUE   1
[L204]  CALL, EXPR  exists_runnable_thread()
[L176]              int __retres1 ;
[L179]  COND TRUE   m_st == 0
[L180]              __retres1 = 1
[L192]              return (__retres1);
[L204]  RET, EXPR   exists_runnable_thread()
[L204]              tmp = exists_runnable_thread()
[L206]  COND TRUE   \read(tmp)
[L211]  COND TRUE   m_st == 0
[L212]              int tmp_ndt_1;
[L213]              tmp_ndt_1 = __VERIFIER_nondet_int()
[L214]  COND FALSE  !(\read(tmp_ndt_1))
[L225]  COND TRUE   t1_st == 0
[L226]              int tmp_ndt_2;
[L227]              tmp_ndt_2 = __VERIFIER_nondet_int()
[L228]  COND FALSE  !(\read(tmp_ndt_2))
End of lasso representation.
RESULT: Ultimate proved your program to be incorrect!
[2025-03-17 20:39:18,316 INFO  L552       MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0
Received shutdown request...
--- End real Ultimate output ---

Execution finished normally
Writing output log to file Ultimate.log
Writing human readable error path to file UltimateCounterExample.errorpath
Result:
FALSE(TERM)