./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8fc3dc66 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 --- Real Ultimate output --- This is Ultimate 0.3.0-?-8fc3dc6-m [2025-03-17 20:39:18,403 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-17 20:39:18,440 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-17 20:39:18,445 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-17 20:39:18,447 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-17 20:39:18,448 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-17 20:39:18,470 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-17 20:39:18,470 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-17 20:39:18,470 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-17 20:39:18,471 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-17 20:39:18,472 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-17 20:39:18,473 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-17 20:39:18,473 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-17 20:39:18,473 INFO L153 SettingsManager]: * Use SBE=true [2025-03-17 20:39:18,473 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-17 20:39:18,473 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-17 20:39:18,473 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-17 20:39:18,473 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-17 20:39:18,474 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-17 20:39:18,474 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-17 20:39:18,474 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-17 20:39:18,474 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-17 20:39:18,474 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-17 20:39:18,474 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-17 20:39:18,474 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-17 20:39:18,474 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-17 20:39:18,474 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-17 20:39:18,474 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-17 20:39:18,474 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-17 20:39:18,474 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-17 20:39:18,475 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-17 20:39:18,475 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-17 20:39:18,475 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-17 20:39:18,475 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-17 20:39:18,475 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-17 20:39:18,475 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-17 20:39:18,475 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-17 20:39:18,475 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-17 20:39:18,475 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-17 20:39:18,476 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-17 20:39:18,476 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 [2025-03-17 20:39:18,672 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-17 20:39:18,677 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-17 20:39:18,679 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-17 20:39:18,679 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-17 20:39:18,680 INFO L274 PluginConnector]: CDTParser initialized [2025-03-17 20:39:18,680 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.03.cil.c [2025-03-17 20:39:19,805 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/52e133155/c3407260a6154525989ca5ccdb5b0cd6/FLAGeb9ce7d9d [2025-03-17 20:39:20,058 INFO L384 CDTParser]: Found 1 translation units. [2025-03-17 20:39:20,062 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.03.cil.c [2025-03-17 20:39:20,091 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/52e133155/c3407260a6154525989ca5ccdb5b0cd6/FLAGeb9ce7d9d [2025-03-17 20:39:20,377 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/52e133155/c3407260a6154525989ca5ccdb5b0cd6 [2025-03-17 20:39:20,379 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-17 20:39:20,380 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-17 20:39:20,381 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-17 20:39:20,381 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-17 20:39:20,384 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-17 20:39:20,385 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,385 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1bb92a75 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20, skipping insertion in model container [2025-03-17 20:39:20,385 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,406 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-17 20:39:20,562 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 20:39:20,575 INFO L200 MainTranslator]: Completed pre-run [2025-03-17 20:39:20,609 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 20:39:20,633 INFO L204 MainTranslator]: Completed translation [2025-03-17 20:39:20,633 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20 WrapperNode [2025-03-17 20:39:20,634 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-17 20:39:20,634 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-17 20:39:20,635 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-17 20:39:20,635 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-17 20:39:20,639 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,649 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,689 INFO L138 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 57, statements flattened = 720 [2025-03-17 20:39:20,690 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-17 20:39:20,690 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-17 20:39:20,690 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-17 20:39:20,692 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-17 20:39:20,699 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,699 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,702 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,715 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-17 20:39:20,716 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,716 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,722 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,723 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,724 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,725 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,727 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-17 20:39:20,729 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-17 20:39:20,729 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-17 20:39:20,729 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-17 20:39:20,730 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (1/1) ... [2025-03-17 20:39:20,734 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:39:20,749 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 20:39:20,761 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 20:39:20,763 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-17 20:39:20,779 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-17 20:39:20,779 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-17 20:39:20,779 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-17 20:39:20,779 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-17 20:39:20,842 INFO L256 CfgBuilder]: Building ICFG [2025-03-17 20:39:20,843 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-17 20:39:21,299 INFO L? ?]: Removed 98 outVars from TransFormulas that were not future-live. [2025-03-17 20:39:21,299 INFO L307 CfgBuilder]: Performing block encoding [2025-03-17 20:39:21,310 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-17 20:39:21,310 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-17 20:39:21,310 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:39:21 BoogieIcfgContainer [2025-03-17 20:39:21,310 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-17 20:39:21,311 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-17 20:39:21,311 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-17 20:39:21,317 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-17 20:39:21,318 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 20:39:21,318 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.03 08:39:20" (1/3) ... [2025-03-17 20:39:21,319 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1ba76f44 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 08:39:21, skipping insertion in model container [2025-03-17 20:39:21,319 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 20:39:21,320 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:39:20" (2/3) ... [2025-03-17 20:39:21,320 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1ba76f44 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 08:39:21, skipping insertion in model container [2025-03-17 20:39:21,320 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 20:39:21,320 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:39:21" (3/3) ... [2025-03-17 20:39:21,321 INFO L363 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2025-03-17 20:39:21,358 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-17 20:39:21,358 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-17 20:39:21,358 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-17 20:39:21,358 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-17 20:39:21,358 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-17 20:39:21,359 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-17 20:39:21,359 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-17 20:39:21,359 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-17 20:39:21,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 249 states, 248 states have (on average 1.6048387096774193) internal successors, (398), 248 states have internal predecessors, (398), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:21,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 200 [2025-03-17 20:39:21,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:21,380 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:21,386 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:21,386 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:21,387 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-17 20:39:21,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 249 states, 248 states have (on average 1.6048387096774193) internal successors, (398), 248 states have internal predecessors, (398), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:21,395 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 200 [2025-03-17 20:39:21,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:21,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:21,399 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:21,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:21,406 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:21,408 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:21,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:21,412 INFO L85 PathProgramCache]: Analyzing trace with hash 1123979163, now seen corresponding path program 1 times [2025-03-17 20:39:21,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:21,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074474107] [2025-03-17 20:39:21,419 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:21,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:21,468 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:21,481 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:21,481 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:21,481 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:21,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:21,572 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:21,572 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074474107] [2025-03-17 20:39:21,572 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1074474107] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:21,572 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:21,573 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:39:21,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151460879] [2025-03-17 20:39:21,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:21,576 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:39:21,577 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:21,577 INFO L85 PathProgramCache]: Analyzing trace with hash -1029234080, now seen corresponding path program 1 times [2025-03-17 20:39:21,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:21,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1640072838] [2025-03-17 20:39:21,577 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:21,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:21,589 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 48 statements into 1 equivalence classes. [2025-03-17 20:39:21,590 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 48 of 48 statements. [2025-03-17 20:39:21,591 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:21,591 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:21,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:21,611 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:21,611 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1640072838] [2025-03-17 20:39:21,611 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1640072838] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:21,611 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:21,611 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:39:21,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3288627] [2025-03-17 20:39:21,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:21,612 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:21,613 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:21,634 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:21,634 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:21,637 INFO L87 Difference]: Start difference. First operand has 249 states, 248 states have (on average 1.6048387096774193) internal successors, (398), 248 states have internal predecessors, (398), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 2 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:21,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:21,670 INFO L93 Difference]: Finished difference Result 249 states and 389 transitions. [2025-03-17 20:39:21,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 249 states and 389 transitions. [2025-03-17 20:39:21,674 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 199 [2025-03-17 20:39:21,685 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 249 states to 245 states and 385 transitions. [2025-03-17 20:39:21,685 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245 [2025-03-17 20:39:21,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245 [2025-03-17 20:39:21,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 245 states and 385 transitions. [2025-03-17 20:39:21,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:21,691 INFO L218 hiAutomatonCegarLoop]: Abstraction has 245 states and 385 transitions. [2025-03-17 20:39:21,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states and 385 transitions. [2025-03-17 20:39:21,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 245. [2025-03-17 20:39:21,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 245 states, 245 states have (on average 1.5714285714285714) internal successors, (385), 244 states have internal predecessors, (385), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:21,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 385 transitions. [2025-03-17 20:39:21,723 INFO L240 hiAutomatonCegarLoop]: Abstraction has 245 states and 385 transitions. [2025-03-17 20:39:21,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:21,725 INFO L432 stractBuchiCegarLoop]: Abstraction has 245 states and 385 transitions. [2025-03-17 20:39:21,725 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-17 20:39:21,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 245 states and 385 transitions. [2025-03-17 20:39:21,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 199 [2025-03-17 20:39:21,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:21,728 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:21,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:21,729 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:21,729 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:21,729 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:21,733 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:21,733 INFO L85 PathProgramCache]: Analyzing trace with hash -1235327846, now seen corresponding path program 1 times [2025-03-17 20:39:21,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:21,733 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266523833] [2025-03-17 20:39:21,733 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:21,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:21,756 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:21,763 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:21,763 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:21,763 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:21,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:21,797 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:21,797 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [266523833] [2025-03-17 20:39:21,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [266523833] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:21,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:21,798 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:39:21,798 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1521774921] [2025-03-17 20:39:21,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:21,799 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:39:21,799 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:21,799 INFO L85 PathProgramCache]: Analyzing trace with hash -433384280, now seen corresponding path program 1 times [2025-03-17 20:39:21,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:21,800 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135324517] [2025-03-17 20:39:21,800 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:21,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:21,808 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-03-17 20:39:21,813 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-17 20:39:21,813 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:21,814 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:21,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:21,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:21,912 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1135324517] [2025-03-17 20:39:21,912 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1135324517] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:21,912 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:21,912 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:21,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1666796419] [2025-03-17 20:39:21,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:21,913 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:21,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:21,913 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:21,913 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:21,914 INFO L87 Difference]: Start difference. First operand 245 states and 385 transitions. cyclomatic complexity: 141 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 2 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:21,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:21,927 INFO L93 Difference]: Finished difference Result 245 states and 384 transitions. [2025-03-17 20:39:21,927 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 384 transitions. [2025-03-17 20:39:21,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 199 [2025-03-17 20:39:21,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 245 states and 384 transitions. [2025-03-17 20:39:21,932 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245 [2025-03-17 20:39:21,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245 [2025-03-17 20:39:21,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 245 states and 384 transitions. [2025-03-17 20:39:21,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:21,933 INFO L218 hiAutomatonCegarLoop]: Abstraction has 245 states and 384 transitions. [2025-03-17 20:39:21,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states and 384 transitions. [2025-03-17 20:39:21,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 245. [2025-03-17 20:39:21,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 245 states, 245 states have (on average 1.5673469387755101) internal successors, (384), 244 states have internal predecessors, (384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:21,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 384 transitions. [2025-03-17 20:39:21,944 INFO L240 hiAutomatonCegarLoop]: Abstraction has 245 states and 384 transitions. [2025-03-17 20:39:21,945 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:21,945 INFO L432 stractBuchiCegarLoop]: Abstraction has 245 states and 384 transitions. [2025-03-17 20:39:21,945 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-17 20:39:21,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 245 states and 384 transitions. [2025-03-17 20:39:21,946 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 199 [2025-03-17 20:39:21,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:21,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:21,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:21,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:21,948 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:21,948 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:21,951 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:21,951 INFO L85 PathProgramCache]: Analyzing trace with hash 1598059451, now seen corresponding path program 1 times [2025-03-17 20:39:21,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:21,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1890785270] [2025-03-17 20:39:21,951 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:21,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:21,960 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:21,966 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:21,966 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:21,966 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:21,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:21,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:21,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1890785270] [2025-03-17 20:39:21,984 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1890785270] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:21,984 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:21,984 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:39:21,984 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916651726] [2025-03-17 20:39:21,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:21,984 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:39:21,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:21,985 INFO L85 PathProgramCache]: Analyzing trace with hash -433384280, now seen corresponding path program 2 times [2025-03-17 20:39:21,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:21,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167239274] [2025-03-17 20:39:21,985 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:39:21,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:21,997 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 51 statements into 1 equivalence classes. [2025-03-17 20:39:21,999 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-17 20:39:22,000 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:39:22,000 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:22,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:22,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:22,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [167239274] [2025-03-17 20:39:22,079 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [167239274] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:22,079 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:22,079 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:22,079 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1976069738] [2025-03-17 20:39:22,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:22,080 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:22,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:22,080 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:22,080 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:22,080 INFO L87 Difference]: Start difference. First operand 245 states and 384 transitions. cyclomatic complexity: 140 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 2 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:22,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:22,095 INFO L93 Difference]: Finished difference Result 245 states and 383 transitions. [2025-03-17 20:39:22,095 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 383 transitions. [2025-03-17 20:39:22,096 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 199 [2025-03-17 20:39:22,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 245 states and 383 transitions. [2025-03-17 20:39:22,097 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245 [2025-03-17 20:39:22,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245 [2025-03-17 20:39:22,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 245 states and 383 transitions. [2025-03-17 20:39:22,098 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:22,098 INFO L218 hiAutomatonCegarLoop]: Abstraction has 245 states and 383 transitions. [2025-03-17 20:39:22,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states and 383 transitions. [2025-03-17 20:39:22,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 245. [2025-03-17 20:39:22,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 245 states, 245 states have (on average 1.563265306122449) internal successors, (383), 244 states have internal predecessors, (383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:22,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 383 transitions. [2025-03-17 20:39:22,106 INFO L240 hiAutomatonCegarLoop]: Abstraction has 245 states and 383 transitions. [2025-03-17 20:39:22,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:22,111 INFO L432 stractBuchiCegarLoop]: Abstraction has 245 states and 383 transitions. [2025-03-17 20:39:22,111 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-17 20:39:22,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 245 states and 383 transitions. [2025-03-17 20:39:22,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 199 [2025-03-17 20:39:22,113 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:22,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:22,115 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:22,115 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:22,115 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:22,115 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:22,116 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:22,118 INFO L85 PathProgramCache]: Analyzing trace with hash -1774224262, now seen corresponding path program 1 times [2025-03-17 20:39:22,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:22,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244962656] [2025-03-17 20:39:22,118 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:22,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:22,129 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:22,135 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:22,137 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:22,138 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:22,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:22,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:22,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1244962656] [2025-03-17 20:39:22,173 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1244962656] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:22,173 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:22,173 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:39:22,173 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [65577051] [2025-03-17 20:39:22,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:22,173 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:39:22,174 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:22,174 INFO L85 PathProgramCache]: Analyzing trace with hash 1149879301, now seen corresponding path program 1 times [2025-03-17 20:39:22,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:22,174 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83327381] [2025-03-17 20:39:22,174 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:22,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:22,182 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-03-17 20:39:22,185 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-17 20:39:22,187 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:22,188 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:22,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:22,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:22,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [83327381] [2025-03-17 20:39:22,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [83327381] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:22,252 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:22,252 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:22,252 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630750072] [2025-03-17 20:39:22,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:22,252 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:22,253 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:22,254 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:22,254 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:22,254 INFO L87 Difference]: Start difference. First operand 245 states and 383 transitions. cyclomatic complexity: 139 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 2 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:22,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:22,302 INFO L93 Difference]: Finished difference Result 437 states and 673 transitions. [2025-03-17 20:39:22,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 437 states and 673 transitions. [2025-03-17 20:39:22,304 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 390 [2025-03-17 20:39:22,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 437 states to 437 states and 673 transitions. [2025-03-17 20:39:22,307 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 437 [2025-03-17 20:39:22,307 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 437 [2025-03-17 20:39:22,307 INFO L73 IsDeterministic]: Start isDeterministic. Operand 437 states and 673 transitions. [2025-03-17 20:39:22,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:22,309 INFO L218 hiAutomatonCegarLoop]: Abstraction has 437 states and 673 transitions. [2025-03-17 20:39:22,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 437 states and 673 transitions. [2025-03-17 20:39:22,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 437 to 414. [2025-03-17 20:39:22,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 414 states, 414 states have (on average 1.5458937198067633) internal successors, (640), 413 states have internal predecessors, (640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:22,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 414 states to 414 states and 640 transitions. [2025-03-17 20:39:22,325 INFO L240 hiAutomatonCegarLoop]: Abstraction has 414 states and 640 transitions. [2025-03-17 20:39:22,326 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:22,326 INFO L432 stractBuchiCegarLoop]: Abstraction has 414 states and 640 transitions. [2025-03-17 20:39:22,326 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-17 20:39:22,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 414 states and 640 transitions. [2025-03-17 20:39:22,328 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 367 [2025-03-17 20:39:22,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:22,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:22,329 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:22,329 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:22,329 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:22,329 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:22,329 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:22,329 INFO L85 PathProgramCache]: Analyzing trace with hash 342778455, now seen corresponding path program 1 times [2025-03-17 20:39:22,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:22,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [472292089] [2025-03-17 20:39:22,332 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:22,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:22,336 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:22,339 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:22,339 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:22,339 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:22,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:22,361 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:22,361 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [472292089] [2025-03-17 20:39:22,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [472292089] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:22,361 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:22,361 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:39:22,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [139130057] [2025-03-17 20:39:22,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:22,361 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:39:22,362 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:22,362 INFO L85 PathProgramCache]: Analyzing trace with hash 312828136, now seen corresponding path program 1 times [2025-03-17 20:39:22,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:22,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592301311] [2025-03-17 20:39:22,362 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:22,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:22,383 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-03-17 20:39:22,389 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-17 20:39:22,390 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:22,390 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:22,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:22,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:22,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1592301311] [2025-03-17 20:39:22,430 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1592301311] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:22,430 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:22,430 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:22,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318780896] [2025-03-17 20:39:22,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:22,430 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:22,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:22,430 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:22,431 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:22,431 INFO L87 Difference]: Start difference. First operand 414 states and 640 transitions. cyclomatic complexity: 228 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 2 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:22,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:22,471 INFO L93 Difference]: Finished difference Result 724 states and 1111 transitions. [2025-03-17 20:39:22,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 724 states and 1111 transitions. [2025-03-17 20:39:22,475 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 672 [2025-03-17 20:39:22,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 724 states to 724 states and 1111 transitions. [2025-03-17 20:39:22,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 724 [2025-03-17 20:39:22,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 724 [2025-03-17 20:39:22,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 724 states and 1111 transitions. [2025-03-17 20:39:22,481 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:22,481 INFO L218 hiAutomatonCegarLoop]: Abstraction has 724 states and 1111 transitions. [2025-03-17 20:39:22,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 724 states and 1111 transitions. [2025-03-17 20:39:22,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 724 to 722. [2025-03-17 20:39:22,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 722 states, 722 states have (on average 1.53601108033241) internal successors, (1109), 721 states have internal predecessors, (1109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:22,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 722 states and 1109 transitions. [2025-03-17 20:39:22,504 INFO L240 hiAutomatonCegarLoop]: Abstraction has 722 states and 1109 transitions. [2025-03-17 20:39:22,504 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:22,505 INFO L432 stractBuchiCegarLoop]: Abstraction has 722 states and 1109 transitions. [2025-03-17 20:39:22,505 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-17 20:39:22,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 722 states and 1109 transitions. [2025-03-17 20:39:22,508 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 670 [2025-03-17 20:39:22,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:22,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:22,510 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:22,510 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:22,510 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:22,511 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:22,511 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:22,512 INFO L85 PathProgramCache]: Analyzing trace with hash 1368688218, now seen corresponding path program 1 times [2025-03-17 20:39:22,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:22,512 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786231327] [2025-03-17 20:39:22,512 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:22,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:22,517 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:22,519 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:22,520 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:22,520 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:22,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:22,548 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:22,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786231327] [2025-03-17 20:39:22,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786231327] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:22,548 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:22,548 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:39:22,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2115672307] [2025-03-17 20:39:22,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:22,549 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:39:22,549 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:22,549 INFO L85 PathProgramCache]: Analyzing trace with hash -586746267, now seen corresponding path program 1 times [2025-03-17 20:39:22,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:22,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264985505] [2025-03-17 20:39:22,549 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:22,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:22,558 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-03-17 20:39:22,562 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-17 20:39:22,562 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:22,562 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:22,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:22,583 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:22,583 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1264985505] [2025-03-17 20:39:22,583 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1264985505] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:22,583 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:22,583 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:22,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370930001] [2025-03-17 20:39:22,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:22,584 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:22,584 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:22,584 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:22,584 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:22,584 INFO L87 Difference]: Start difference. First operand 722 states and 1109 transitions. cyclomatic complexity: 391 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 2 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:22,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:22,622 INFO L93 Difference]: Finished difference Result 1287 states and 1968 transitions. [2025-03-17 20:39:22,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1287 states and 1968 transitions. [2025-03-17 20:39:22,629 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1220 [2025-03-17 20:39:22,634 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1287 states to 1287 states and 1968 transitions. [2025-03-17 20:39:22,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1287 [2025-03-17 20:39:22,636 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1287 [2025-03-17 20:39:22,636 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1287 states and 1968 transitions. [2025-03-17 20:39:22,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:22,640 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1287 states and 1968 transitions. [2025-03-17 20:39:22,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1287 states and 1968 transitions. [2025-03-17 20:39:22,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1287 to 1283. [2025-03-17 20:39:22,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1283 states, 1283 states have (on average 1.5307872174590802) internal successors, (1964), 1282 states have internal predecessors, (1964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:22,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1283 states to 1283 states and 1964 transitions. [2025-03-17 20:39:22,661 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1283 states and 1964 transitions. [2025-03-17 20:39:22,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:22,662 INFO L432 stractBuchiCegarLoop]: Abstraction has 1283 states and 1964 transitions. [2025-03-17 20:39:22,662 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-17 20:39:22,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1283 states and 1964 transitions. [2025-03-17 20:39:22,666 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1216 [2025-03-17 20:39:22,666 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:22,666 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:22,667 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:22,667 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:22,667 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:22,667 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:22,668 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:22,668 INFO L85 PathProgramCache]: Analyzing trace with hash 1959963767, now seen corresponding path program 1 times [2025-03-17 20:39:22,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:22,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [174974952] [2025-03-17 20:39:22,668 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:22,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:22,672 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:22,674 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:22,674 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:22,675 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:22,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:22,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:22,705 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [174974952] [2025-03-17 20:39:22,705 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [174974952] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:22,705 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:22,705 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:39:22,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [907139781] [2025-03-17 20:39:22,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:22,705 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:39:22,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:22,706 INFO L85 PathProgramCache]: Analyzing trace with hash 312828136, now seen corresponding path program 2 times [2025-03-17 20:39:22,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:22,706 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899994026] [2025-03-17 20:39:22,706 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:39:22,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:22,711 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 51 statements into 1 equivalence classes. [2025-03-17 20:39:22,711 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-17 20:39:22,712 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:39:22,712 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:22,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:22,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:22,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899994026] [2025-03-17 20:39:22,734 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1899994026] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:22,735 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:22,735 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:22,735 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1549318819] [2025-03-17 20:39:22,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:22,735 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:22,735 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:22,735 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:39:22,735 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:39:22,736 INFO L87 Difference]: Start difference. First operand 1283 states and 1964 transitions. cyclomatic complexity: 689 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:22,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:22,805 INFO L93 Difference]: Finished difference Result 2831 states and 4280 transitions. [2025-03-17 20:39:22,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2831 states and 4280 transitions. [2025-03-17 20:39:22,840 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 2676 [2025-03-17 20:39:22,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2831 states to 2831 states and 4280 transitions. [2025-03-17 20:39:22,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2831 [2025-03-17 20:39:22,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2831 [2025-03-17 20:39:22,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2831 states and 4280 transitions. [2025-03-17 20:39:22,858 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:22,858 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2831 states and 4280 transitions. [2025-03-17 20:39:22,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2831 states and 4280 transitions. [2025-03-17 20:39:22,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2831 to 2831. [2025-03-17 20:39:22,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2831 states, 2831 states have (on average 1.511833274461321) internal successors, (4280), 2830 states have internal predecessors, (4280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:22,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2831 states to 2831 states and 4280 transitions. [2025-03-17 20:39:22,898 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2831 states and 4280 transitions. [2025-03-17 20:39:22,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:39:22,899 INFO L432 stractBuchiCegarLoop]: Abstraction has 2831 states and 4280 transitions. [2025-03-17 20:39:22,899 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-17 20:39:22,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2831 states and 4280 transitions. [2025-03-17 20:39:22,909 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 2676 [2025-03-17 20:39:22,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:22,910 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:22,910 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:22,910 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:22,911 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:22,911 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:22,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:22,911 INFO L85 PathProgramCache]: Analyzing trace with hash -1876807499, now seen corresponding path program 1 times [2025-03-17 20:39:22,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:22,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1558752031] [2025-03-17 20:39:22,911 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:22,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:22,915 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:22,917 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:22,917 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:22,917 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:22,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:22,938 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:22,938 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1558752031] [2025-03-17 20:39:22,938 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1558752031] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:22,938 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:22,939 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:39:22,939 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1971461019] [2025-03-17 20:39:22,939 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:22,939 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:39:22,939 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:22,939 INFO L85 PathProgramCache]: Analyzing trace with hash 312828136, now seen corresponding path program 3 times [2025-03-17 20:39:22,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:22,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241631113] [2025-03-17 20:39:22,939 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:39:22,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:22,946 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 51 statements into 1 equivalence classes. [2025-03-17 20:39:22,946 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-17 20:39:22,946 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:39:22,948 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:22,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:22,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:22,979 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241631113] [2025-03-17 20:39:22,979 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241631113] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:22,979 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:22,979 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:22,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1303222912] [2025-03-17 20:39:22,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:22,979 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:22,979 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:22,980 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:22,980 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:22,980 INFO L87 Difference]: Start difference. First operand 2831 states and 4280 transitions. cyclomatic complexity: 1465 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 2 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:23,003 INFO L93 Difference]: Finished difference Result 2800 states and 4193 transitions. [2025-03-17 20:39:23,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2800 states and 4193 transitions. [2025-03-17 20:39:23,015 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 2676 [2025-03-17 20:39:23,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2800 states to 2800 states and 4193 transitions. [2025-03-17 20:39:23,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2800 [2025-03-17 20:39:23,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2800 [2025-03-17 20:39:23,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2800 states and 4193 transitions. [2025-03-17 20:39:23,030 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:23,030 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2800 states and 4193 transitions. [2025-03-17 20:39:23,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2800 states and 4193 transitions. [2025-03-17 20:39:23,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2800 to 1556. [2025-03-17 20:39:23,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1556 states, 1556 states have (on average 1.4948586118251928) internal successors, (2326), 1555 states have internal predecessors, (2326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1556 states to 1556 states and 2326 transitions. [2025-03-17 20:39:23,054 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1556 states and 2326 transitions. [2025-03-17 20:39:23,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:23,056 INFO L432 stractBuchiCegarLoop]: Abstraction has 1556 states and 2326 transitions. [2025-03-17 20:39:23,057 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-17 20:39:23,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1556 states and 2326 transitions. [2025-03-17 20:39:23,062 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1460 [2025-03-17 20:39:23,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:23,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:23,064 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,064 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,064 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:23,064 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:23,064 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,064 INFO L85 PathProgramCache]: Analyzing trace with hash -151326602, now seen corresponding path program 1 times [2025-03-17 20:39:23,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117633284] [2025-03-17 20:39:23,064 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:23,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,071 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:23,072 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,072 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,072 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:23,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:23,098 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:23,098 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117633284] [2025-03-17 20:39:23,098 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1117633284] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:23,098 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:23,098 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:39:23,099 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [927121157] [2025-03-17 20:39:23,099 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:23,099 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:39:23,099 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,099 INFO L85 PathProgramCache]: Analyzing trace with hash -1222399962, now seen corresponding path program 1 times [2025-03-17 20:39:23,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557025848] [2025-03-17 20:39:23,099 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:23,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,105 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-03-17 20:39:23,105 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-17 20:39:23,105 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,105 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:23,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:23,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:23,148 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557025848] [2025-03-17 20:39:23,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557025848] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:23,148 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:23,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:23,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1640365995] [2025-03-17 20:39:23,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:23,148 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:23,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:23,149 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:39:23,149 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:39:23,149 INFO L87 Difference]: Start difference. First operand 1556 states and 2326 transitions. cyclomatic complexity: 778 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:23,171 INFO L93 Difference]: Finished difference Result 1283 states and 1912 transitions. [2025-03-17 20:39:23,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1283 states and 1912 transitions. [2025-03-17 20:39:23,176 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1216 [2025-03-17 20:39:23,180 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1283 states to 1283 states and 1912 transitions. [2025-03-17 20:39:23,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1283 [2025-03-17 20:39:23,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1283 [2025-03-17 20:39:23,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1283 states and 1912 transitions. [2025-03-17 20:39:23,182 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:23,182 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1283 states and 1912 transitions. [2025-03-17 20:39:23,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1283 states and 1912 transitions. [2025-03-17 20:39:23,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1283 to 1283. [2025-03-17 20:39:23,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1283 states, 1283 states have (on average 1.490257209664848) internal successors, (1912), 1282 states have internal predecessors, (1912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1283 states to 1283 states and 1912 transitions. [2025-03-17 20:39:23,196 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1283 states and 1912 transitions. [2025-03-17 20:39:23,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:23,198 INFO L432 stractBuchiCegarLoop]: Abstraction has 1283 states and 1912 transitions. [2025-03-17 20:39:23,198 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-17 20:39:23,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1283 states and 1912 transitions. [2025-03-17 20:39:23,202 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1216 [2025-03-17 20:39:23,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:23,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:23,203 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,203 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,203 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:23,203 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:23,203 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,203 INFO L85 PathProgramCache]: Analyzing trace with hash 1960887288, now seen corresponding path program 1 times [2025-03-17 20:39:23,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,203 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664262789] [2025-03-17 20:39:23,203 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:23,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,208 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:23,212 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,212 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,212 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:23,212 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:23,214 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:23,215 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,216 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,217 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:23,237 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:23,238 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,238 INFO L85 PathProgramCache]: Analyzing trace with hash -1603885340, now seen corresponding path program 1 times [2025-03-17 20:39:23,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161290009] [2025-03-17 20:39:23,238 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:23,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,243 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-03-17 20:39:23,245 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-17 20:39:23,245 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,245 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:23,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:23,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:23,263 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161290009] [2025-03-17 20:39:23,263 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161290009] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:23,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:23,264 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:23,264 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [331163078] [2025-03-17 20:39:23,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:23,264 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:23,264 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:23,264 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:39:23,264 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:39:23,265 INFO L87 Difference]: Start difference. First operand 1283 states and 1912 transitions. cyclomatic complexity: 637 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 4 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:23,326 INFO L93 Difference]: Finished difference Result 1315 states and 1931 transitions. [2025-03-17 20:39:23,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1315 states and 1931 transitions. [2025-03-17 20:39:23,330 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1248 [2025-03-17 20:39:23,334 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1315 states to 1315 states and 1931 transitions. [2025-03-17 20:39:23,334 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1315 [2025-03-17 20:39:23,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1315 [2025-03-17 20:39:23,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1315 states and 1931 transitions. [2025-03-17 20:39:23,336 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:23,336 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1315 states and 1931 transitions. [2025-03-17 20:39:23,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1315 states and 1931 transitions. [2025-03-17 20:39:23,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1315 to 1315. [2025-03-17 20:39:23,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1315 states, 1315 states have (on average 1.4684410646387833) internal successors, (1931), 1314 states have internal predecessors, (1931), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1315 states to 1315 states and 1931 transitions. [2025-03-17 20:39:23,350 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1315 states and 1931 transitions. [2025-03-17 20:39:23,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:39:23,351 INFO L432 stractBuchiCegarLoop]: Abstraction has 1315 states and 1931 transitions. [2025-03-17 20:39:23,351 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-17 20:39:23,351 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1315 states and 1931 transitions. [2025-03-17 20:39:23,354 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1248 [2025-03-17 20:39:23,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:23,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:23,354 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,354 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,355 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:23,355 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:23,355 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,355 INFO L85 PathProgramCache]: Analyzing trace with hash 1960887288, now seen corresponding path program 2 times [2025-03-17 20:39:23,355 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,355 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1644042261] [2025-03-17 20:39:23,355 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:39:23,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,359 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:23,361 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,361 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:39:23,362 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:23,362 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:23,363 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:23,364 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,364 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,365 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:23,369 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:23,369 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,369 INFO L85 PathProgramCache]: Analyzing trace with hash 789866022, now seen corresponding path program 1 times [2025-03-17 20:39:23,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,369 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243487637] [2025-03-17 20:39:23,369 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:23,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,374 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-03-17 20:39:23,375 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-17 20:39:23,375 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,375 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:23,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:23,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:23,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243487637] [2025-03-17 20:39:23,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [243487637] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:23,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:23,396 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:23,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1182736009] [2025-03-17 20:39:23,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:23,396 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:23,396 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:23,397 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:39:23,397 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:39:23,397 INFO L87 Difference]: Start difference. First operand 1315 states and 1931 transitions. cyclomatic complexity: 624 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 4 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:23,426 INFO L93 Difference]: Finished difference Result 1347 states and 1963 transitions. [2025-03-17 20:39:23,427 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1347 states and 1963 transitions. [2025-03-17 20:39:23,430 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1280 [2025-03-17 20:39:23,434 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1347 states to 1347 states and 1963 transitions. [2025-03-17 20:39:23,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1347 [2025-03-17 20:39:23,435 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1347 [2025-03-17 20:39:23,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1347 states and 1963 transitions. [2025-03-17 20:39:23,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:23,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1347 states and 1963 transitions. [2025-03-17 20:39:23,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1347 states and 1963 transitions. [2025-03-17 20:39:23,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1347 to 1331. [2025-03-17 20:39:23,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1331 states, 1331 states have (on average 1.462809917355372) internal successors, (1947), 1330 states have internal predecessors, (1947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1331 states to 1331 states and 1947 transitions. [2025-03-17 20:39:23,452 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1331 states and 1947 transitions. [2025-03-17 20:39:23,452 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:39:23,454 INFO L432 stractBuchiCegarLoop]: Abstraction has 1331 states and 1947 transitions. [2025-03-17 20:39:23,454 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-17 20:39:23,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1331 states and 1947 transitions. [2025-03-17 20:39:23,457 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1264 [2025-03-17 20:39:23,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:23,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:23,457 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,457 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,458 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:23,458 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:23,458 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,458 INFO L85 PathProgramCache]: Analyzing trace with hash 1960887288, now seen corresponding path program 3 times [2025-03-17 20:39:23,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615518638] [2025-03-17 20:39:23,458 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:39:23,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,463 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:23,464 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,464 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:39:23,464 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:23,464 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:23,466 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:23,478 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,478 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,478 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:23,483 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:23,484 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,485 INFO L85 PathProgramCache]: Analyzing trace with hash 452160123, now seen corresponding path program 1 times [2025-03-17 20:39:23,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1570191789] [2025-03-17 20:39:23,485 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:23,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,490 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes. [2025-03-17 20:39:23,491 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements. [2025-03-17 20:39:23,491 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,491 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:23,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:23,514 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:23,514 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1570191789] [2025-03-17 20:39:23,514 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1570191789] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:23,514 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:23,514 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:23,514 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [300713414] [2025-03-17 20:39:23,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:23,515 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:23,515 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:23,515 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:39:23,515 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:39:23,515 INFO L87 Difference]: Start difference. First operand 1331 states and 1947 transitions. cyclomatic complexity: 624 Second operand has 4 states, 4 states have (on average 13.5) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:23,574 INFO L93 Difference]: Finished difference Result 1363 states and 1966 transitions. [2025-03-17 20:39:23,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1363 states and 1966 transitions. [2025-03-17 20:39:23,579 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1296 [2025-03-17 20:39:23,584 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1363 states to 1363 states and 1966 transitions. [2025-03-17 20:39:23,584 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1363 [2025-03-17 20:39:23,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1363 [2025-03-17 20:39:23,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1363 states and 1966 transitions. [2025-03-17 20:39:23,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:23,587 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1363 states and 1966 transitions. [2025-03-17 20:39:23,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1363 states and 1966 transitions. [2025-03-17 20:39:23,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1363 to 1363. [2025-03-17 20:39:23,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1363 states, 1363 states have (on average 1.4424064563462948) internal successors, (1966), 1362 states have internal predecessors, (1966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1363 states to 1363 states and 1966 transitions. [2025-03-17 20:39:23,606 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1363 states and 1966 transitions. [2025-03-17 20:39:23,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:39:23,608 INFO L432 stractBuchiCegarLoop]: Abstraction has 1363 states and 1966 transitions. [2025-03-17 20:39:23,608 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-17 20:39:23,608 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1363 states and 1966 transitions. [2025-03-17 20:39:23,612 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1296 [2025-03-17 20:39:23,612 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:23,612 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:23,612 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,612 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:23,613 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:23,613 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,613 INFO L85 PathProgramCache]: Analyzing trace with hash 1960887288, now seen corresponding path program 4 times [2025-03-17 20:39:23,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,613 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209337553] [2025-03-17 20:39:23,613 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 20:39:23,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,620 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 42 statements into 2 equivalence classes. [2025-03-17 20:39:23,623 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,624 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 20:39:23,624 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:23,624 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:23,626 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:23,629 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,629 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,629 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:23,638 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:23,638 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,638 INFO L85 PathProgramCache]: Analyzing trace with hash 1477652122, now seen corresponding path program 1 times [2025-03-17 20:39:23,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,639 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574890472] [2025-03-17 20:39:23,639 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:23,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,645 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes. [2025-03-17 20:39:23,648 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements. [2025-03-17 20:39:23,648 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,648 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:23,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:23,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:23,672 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1574890472] [2025-03-17 20:39:23,672 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1574890472] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:23,672 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:23,673 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:23,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1939501467] [2025-03-17 20:39:23,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:23,673 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:23,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:23,675 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:39:23,675 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:39:23,675 INFO L87 Difference]: Start difference. First operand 1363 states and 1966 transitions. cyclomatic complexity: 611 Second operand has 4 states, 4 states have (on average 13.5) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:23,742 INFO L93 Difference]: Finished difference Result 1395 states and 1985 transitions. [2025-03-17 20:39:23,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1395 states and 1985 transitions. [2025-03-17 20:39:23,747 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1328 [2025-03-17 20:39:23,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1395 states to 1395 states and 1985 transitions. [2025-03-17 20:39:23,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1395 [2025-03-17 20:39:23,753 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1395 [2025-03-17 20:39:23,753 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1395 states and 1985 transitions. [2025-03-17 20:39:23,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:23,755 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1395 states and 1985 transitions. [2025-03-17 20:39:23,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1395 states and 1985 transitions. [2025-03-17 20:39:23,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1395 to 1395. [2025-03-17 20:39:23,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1395 states, 1395 states have (on average 1.4229390681003584) internal successors, (1985), 1394 states have internal predecessors, (1985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1395 states to 1395 states and 1985 transitions. [2025-03-17 20:39:23,775 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1395 states and 1985 transitions. [2025-03-17 20:39:23,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:39:23,775 INFO L432 stractBuchiCegarLoop]: Abstraction has 1395 states and 1985 transitions. [2025-03-17 20:39:23,775 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-17 20:39:23,776 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1395 states and 1985 transitions. [2025-03-17 20:39:23,779 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1328 [2025-03-17 20:39:23,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:23,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:23,780 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,780 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,780 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:23,781 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:23,781 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,781 INFO L85 PathProgramCache]: Analyzing trace with hash 1960887288, now seen corresponding path program 5 times [2025-03-17 20:39:23,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141713258] [2025-03-17 20:39:23,781 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 20:39:23,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,788 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:23,790 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,790 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:39:23,790 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:23,790 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:23,794 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:23,796 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,797 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,797 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:23,806 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:23,806 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,806 INFO L85 PathProgramCache]: Analyzing trace with hash -2124213477, now seen corresponding path program 1 times [2025-03-17 20:39:23,806 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,806 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999207409] [2025-03-17 20:39:23,806 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:23,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,812 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes. [2025-03-17 20:39:23,814 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements. [2025-03-17 20:39:23,815 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,815 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:23,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:23,840 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:23,840 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [999207409] [2025-03-17 20:39:23,840 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [999207409] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:23,840 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:23,841 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:39:23,841 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969639114] [2025-03-17 20:39:23,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:23,841 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:23,841 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:23,841 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:39:23,841 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:39:23,842 INFO L87 Difference]: Start difference. First operand 1395 states and 1985 transitions. cyclomatic complexity: 598 Second operand has 4 states, 4 states have (on average 13.5) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:23,909 INFO L93 Difference]: Finished difference Result 1453 states and 2043 transitions. [2025-03-17 20:39:23,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1453 states and 2043 transitions. [2025-03-17 20:39:23,913 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1384 [2025-03-17 20:39:23,918 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1453 states to 1453 states and 2043 transitions. [2025-03-17 20:39:23,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1453 [2025-03-17 20:39:23,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1453 [2025-03-17 20:39:23,919 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1453 states and 2043 transitions. [2025-03-17 20:39:23,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:23,921 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1453 states and 2043 transitions. [2025-03-17 20:39:23,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1453 states and 2043 transitions. [2025-03-17 20:39:23,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1453 to 1453. [2025-03-17 20:39:23,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1453 states, 1453 states have (on average 1.4060564349621474) internal successors, (2043), 1452 states have internal predecessors, (2043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:23,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1453 states to 1453 states and 2043 transitions. [2025-03-17 20:39:23,940 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1453 states and 2043 transitions. [2025-03-17 20:39:23,941 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:39:23,941 INFO L432 stractBuchiCegarLoop]: Abstraction has 1453 states and 2043 transitions. [2025-03-17 20:39:23,941 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-17 20:39:23,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1453 states and 2043 transitions. [2025-03-17 20:39:23,944 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1384 [2025-03-17 20:39:23,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:23,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:23,945 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,945 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:23,945 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:23,945 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:23,946 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,946 INFO L85 PathProgramCache]: Analyzing trace with hash 1960887288, now seen corresponding path program 6 times [2025-03-17 20:39:23,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,946 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318288370] [2025-03-17 20:39:23,946 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 20:39:23,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,952 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:23,954 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,954 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 20:39:23,954 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:23,954 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:23,956 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:23,958 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:23,958 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,958 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:23,962 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:23,962 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:23,963 INFO L85 PathProgramCache]: Analyzing trace with hash 336544638, now seen corresponding path program 1 times [2025-03-17 20:39:23,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:23,963 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738902875] [2025-03-17 20:39:23,963 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:23,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:23,968 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes. [2025-03-17 20:39:23,970 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements. [2025-03-17 20:39:23,971 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:23,971 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:23,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:23,987 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:23,987 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738902875] [2025-03-17 20:39:23,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [738902875] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:23,987 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:23,987 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:39:23,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [147641364] [2025-03-17 20:39:23,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:23,987 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:23,988 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:23,988 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:23,988 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:23,988 INFO L87 Difference]: Start difference. First operand 1453 states and 2043 transitions. cyclomatic complexity: 598 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:24,028 INFO L93 Difference]: Finished difference Result 2146 states and 2953 transitions. [2025-03-17 20:39:24,029 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2146 states and 2953 transitions. [2025-03-17 20:39:24,035 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2038 [2025-03-17 20:39:24,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2146 states to 2146 states and 2953 transitions. [2025-03-17 20:39:24,042 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2146 [2025-03-17 20:39:24,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2146 [2025-03-17 20:39:24,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2146 states and 2953 transitions. [2025-03-17 20:39:24,046 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:24,046 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2146 states and 2953 transitions. [2025-03-17 20:39:24,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2146 states and 2953 transitions. [2025-03-17 20:39:24,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2146 to 2146. [2025-03-17 20:39:24,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2146 states, 2146 states have (on average 1.3760484622553588) internal successors, (2953), 2145 states have internal predecessors, (2953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2146 states to 2146 states and 2953 transitions. [2025-03-17 20:39:24,076 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2146 states and 2953 transitions. [2025-03-17 20:39:24,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:24,076 INFO L432 stractBuchiCegarLoop]: Abstraction has 2146 states and 2953 transitions. [2025-03-17 20:39:24,076 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-17 20:39:24,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2146 states and 2953 transitions. [2025-03-17 20:39:24,081 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2038 [2025-03-17 20:39:24,082 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:24,082 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:24,082 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:24,082 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:24,083 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:24,083 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:24,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,083 INFO L85 PathProgramCache]: Analyzing trace with hash -1732223302, now seen corresponding path program 1 times [2025-03-17 20:39:24,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427332577] [2025-03-17 20:39:24,084 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:24,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,089 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:24,090 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:24,090 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,090 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:24,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:24,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:24,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427332577] [2025-03-17 20:39:24,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [427332577] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:24,104 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:24,105 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:39:24,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951240409] [2025-03-17 20:39:24,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:24,105 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:39:24,105 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,105 INFO L85 PathProgramCache]: Analyzing trace with hash -1016765059, now seen corresponding path program 1 times [2025-03-17 20:39:24,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,105 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134081385] [2025-03-17 20:39:24,106 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:24,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,111 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes. [2025-03-17 20:39:24,114 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements. [2025-03-17 20:39:24,114 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,114 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:24,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:24,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:24,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134081385] [2025-03-17 20:39:24,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1134081385] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:24,129 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:24,129 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:39:24,129 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007081742] [2025-03-17 20:39:24,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:24,130 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:24,130 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:24,130 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:24,130 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:24,130 INFO L87 Difference]: Start difference. First operand 2146 states and 2953 transitions. cyclomatic complexity: 815 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 2 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:24,152 INFO L93 Difference]: Finished difference Result 1429 states and 1965 transitions. [2025-03-17 20:39:24,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1429 states and 1965 transitions. [2025-03-17 20:39:24,156 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1360 [2025-03-17 20:39:24,160 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1429 states to 1429 states and 1965 transitions. [2025-03-17 20:39:24,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1429 [2025-03-17 20:39:24,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1429 [2025-03-17 20:39:24,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1429 states and 1965 transitions. [2025-03-17 20:39:24,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:24,163 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1429 states and 1965 transitions. [2025-03-17 20:39:24,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1429 states and 1965 transitions. [2025-03-17 20:39:24,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1429 to 1429. [2025-03-17 20:39:24,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1429 states, 1429 states have (on average 1.3750874737578727) internal successors, (1965), 1428 states have internal predecessors, (1965), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1429 states to 1429 states and 1965 transitions. [2025-03-17 20:39:24,181 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1429 states and 1965 transitions. [2025-03-17 20:39:24,182 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:24,182 INFO L432 stractBuchiCegarLoop]: Abstraction has 1429 states and 1965 transitions. [2025-03-17 20:39:24,182 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-17 20:39:24,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1429 states and 1965 transitions. [2025-03-17 20:39:24,185 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1360 [2025-03-17 20:39:24,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:24,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:24,186 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:24,186 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:24,186 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-17 20:39:24,187 INFO L754 eck$LassoCheckResult]: Loop: "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume !(1 == ~T3_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-17 20:39:24,187 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,187 INFO L85 PathProgramCache]: Analyzing trace with hash 1960887288, now seen corresponding path program 7 times [2025-03-17 20:39:24,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [691313729] [2025-03-17 20:39:24,187 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 20:39:24,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,192 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:24,195 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:24,196 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,196 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,196 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:24,197 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-17 20:39:24,199 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-17 20:39:24,199 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,199 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,207 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:24,207 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,207 INFO L85 PathProgramCache]: Analyzing trace with hash -1364195841, now seen corresponding path program 1 times [2025-03-17 20:39:24,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18975316] [2025-03-17 20:39:24,207 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:24,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,213 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes. [2025-03-17 20:39:24,216 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements. [2025-03-17 20:39:24,216 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,216 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:24,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:24,233 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:24,233 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [18975316] [2025-03-17 20:39:24,233 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [18975316] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:24,233 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:24,233 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:39:24,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556626330] [2025-03-17 20:39:24,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:24,233 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:39:24,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:24,233 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:24,233 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:24,234 INFO L87 Difference]: Start difference. First operand 1429 states and 1965 transitions. cyclomatic complexity: 544 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:24,255 INFO L93 Difference]: Finished difference Result 2006 states and 2718 transitions. [2025-03-17 20:39:24,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2006 states and 2718 transitions. [2025-03-17 20:39:24,260 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 1920 [2025-03-17 20:39:24,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2006 states to 2006 states and 2718 transitions. [2025-03-17 20:39:24,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2006 [2025-03-17 20:39:24,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2006 [2025-03-17 20:39:24,270 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2006 states and 2718 transitions. [2025-03-17 20:39:24,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:24,272 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2006 states and 2718 transitions. [2025-03-17 20:39:24,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2006 states and 2718 transitions. [2025-03-17 20:39:24,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2006 to 2006. [2025-03-17 20:39:24,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2006 states, 2006 states have (on average 1.3549351944167498) internal successors, (2718), 2005 states have internal predecessors, (2718), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2006 states to 2006 states and 2718 transitions. [2025-03-17 20:39:24,299 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2006 states and 2718 transitions. [2025-03-17 20:39:24,299 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:24,300 INFO L432 stractBuchiCegarLoop]: Abstraction has 2006 states and 2718 transitions. [2025-03-17 20:39:24,300 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-17 20:39:24,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2006 states and 2718 transitions. [2025-03-17 20:39:24,318 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 1920 [2025-03-17 20:39:24,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:24,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:24,318 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:24,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:24,319 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-03-17 20:39:24,319 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2025-03-17 20:39:24,320 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,321 INFO L85 PathProgramCache]: Analyzing trace with hash 657964158, now seen corresponding path program 1 times [2025-03-17 20:39:24,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804660131] [2025-03-17 20:39:24,321 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:24,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,326 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-17 20:39:24,329 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-17 20:39:24,329 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,329 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,329 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:24,330 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-17 20:39:24,332 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-17 20:39:24,333 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,333 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,336 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:24,336 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,337 INFO L85 PathProgramCache]: Analyzing trace with hash -1264027911, now seen corresponding path program 1 times [2025-03-17 20:39:24,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355369288] [2025-03-17 20:39:24,337 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:24,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,339 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-17 20:39:24,340 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-17 20:39:24,340 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,340 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,340 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:24,341 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-17 20:39:24,342 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-17 20:39:24,342 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,342 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,343 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:24,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,344 INFO L85 PathProgramCache]: Analyzing trace with hash 705723190, now seen corresponding path program 1 times [2025-03-17 20:39:24,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396012816] [2025-03-17 20:39:24,344 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:24,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,348 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 53 statements into 1 equivalence classes. [2025-03-17 20:39:24,350 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 53 of 53 statements. [2025-03-17 20:39:24,350 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,350 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:24,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:24,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:24,364 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396012816] [2025-03-17 20:39:24,364 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1396012816] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:24,364 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:24,364 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:39:24,364 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [544977398] [2025-03-17 20:39:24,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:24,411 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:24,412 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:24,412 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:24,412 INFO L87 Difference]: Start difference. First operand 2006 states and 2718 transitions. cyclomatic complexity: 724 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:24,440 INFO L93 Difference]: Finished difference Result 2333 states and 3122 transitions. [2025-03-17 20:39:24,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2333 states and 3122 transitions. [2025-03-17 20:39:24,445 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2184 [2025-03-17 20:39:24,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2333 states to 2333 states and 3122 transitions. [2025-03-17 20:39:24,450 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2333 [2025-03-17 20:39:24,451 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2333 [2025-03-17 20:39:24,451 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2333 states and 3122 transitions. [2025-03-17 20:39:24,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:24,453 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2333 states and 3122 transitions. [2025-03-17 20:39:24,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2333 states and 3122 transitions. [2025-03-17 20:39:24,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2333 to 2201. [2025-03-17 20:39:24,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2201 states, 2201 states have (on average 1.3421172194457065) internal successors, (2954), 2200 states have internal predecessors, (2954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2201 states to 2201 states and 2954 transitions. [2025-03-17 20:39:24,476 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2201 states and 2954 transitions. [2025-03-17 20:39:24,477 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:24,477 INFO L432 stractBuchiCegarLoop]: Abstraction has 2201 states and 2954 transitions. [2025-03-17 20:39:24,477 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-17 20:39:24,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2201 states and 2954 transitions. [2025-03-17 20:39:24,481 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2052 [2025-03-17 20:39:24,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:24,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:24,481 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:24,481 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:24,482 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-03-17 20:39:24,482 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2025-03-17 20:39:24,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,482 INFO L85 PathProgramCache]: Analyzing trace with hash 657964158, now seen corresponding path program 2 times [2025-03-17 20:39:24,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473819360] [2025-03-17 20:39:24,482 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:39:24,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,487 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 43 statements into 1 equivalence classes. [2025-03-17 20:39:24,489 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-17 20:39:24,489 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:39:24,489 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,489 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:24,491 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-17 20:39:24,492 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-17 20:39:24,493 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,493 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,495 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:24,496 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,496 INFO L85 PathProgramCache]: Analyzing trace with hash 745669891, now seen corresponding path program 1 times [2025-03-17 20:39:24,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793136151] [2025-03-17 20:39:24,496 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:24,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,498 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-03-17 20:39:24,499 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-03-17 20:39:24,499 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,499 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,499 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:24,499 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-03-17 20:39:24,500 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-03-17 20:39:24,500 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,500 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,501 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:24,502 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,502 INFO L85 PathProgramCache]: Analyzing trace with hash -404099584, now seen corresponding path program 1 times [2025-03-17 20:39:24,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,502 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152015446] [2025-03-17 20:39:24,502 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:24,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,506 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes. [2025-03-17 20:39:24,508 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements. [2025-03-17 20:39:24,508 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,508 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:24,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:24,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:24,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152015446] [2025-03-17 20:39:24,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1152015446] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:24,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:24,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:39:24,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76979042] [2025-03-17 20:39:24,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:24,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:24,561 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:24,561 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:24,561 INFO L87 Difference]: Start difference. First operand 2201 states and 2954 transitions. cyclomatic complexity: 765 Second operand has 3 states, 3 states have (on average 18.333333333333332) internal successors, (55), 3 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:24,589 INFO L93 Difference]: Finished difference Result 2628 states and 3502 transitions. [2025-03-17 20:39:24,589 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2628 states and 3502 transitions. [2025-03-17 20:39:24,594 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2381 [2025-03-17 20:39:24,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2628 states to 2628 states and 3502 transitions. [2025-03-17 20:39:24,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2628 [2025-03-17 20:39:24,600 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2628 [2025-03-17 20:39:24,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2628 states and 3502 transitions. [2025-03-17 20:39:24,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:24,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2628 states and 3502 transitions. [2025-03-17 20:39:24,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2628 states and 3502 transitions. [2025-03-17 20:39:24,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2628 to 2518. [2025-03-17 20:39:24,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2518 states, 2518 states have (on average 1.3339952343129469) internal successors, (3359), 2517 states have internal predecessors, (3359), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2518 states to 2518 states and 3359 transitions. [2025-03-17 20:39:24,628 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2518 states and 3359 transitions. [2025-03-17 20:39:24,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:24,629 INFO L432 stractBuchiCegarLoop]: Abstraction has 2518 states and 3359 transitions. [2025-03-17 20:39:24,629 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-17 20:39:24,629 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2518 states and 3359 transitions. [2025-03-17 20:39:24,633 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2271 [2025-03-17 20:39:24,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:24,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:24,633 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:24,633 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:24,633 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-03-17 20:39:24,633 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume !(0 == ~t3_st~0);" [2025-03-17 20:39:24,634 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,634 INFO L85 PathProgramCache]: Analyzing trace with hash 657964158, now seen corresponding path program 3 times [2025-03-17 20:39:24,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1153681018] [2025-03-17 20:39:24,634 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:39:24,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,638 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 43 statements into 1 equivalence classes. [2025-03-17 20:39:24,640 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-17 20:39:24,640 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:39:24,640 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,640 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:24,642 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-17 20:39:24,643 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-17 20:39:24,643 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,643 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,646 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:24,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,646 INFO L85 PathProgramCache]: Analyzing trace with hash -670745159, now seen corresponding path program 1 times [2025-03-17 20:39:24,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659217844] [2025-03-17 20:39:24,646 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:24,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,648 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 14 statements into 1 equivalence classes. [2025-03-17 20:39:24,649 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 14 of 14 statements. [2025-03-17 20:39:24,649 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,649 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,649 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:24,650 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 14 statements into 1 equivalence classes. [2025-03-17 20:39:24,650 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 14 of 14 statements. [2025-03-17 20:39:24,651 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,651 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,652 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:24,652 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,652 INFO L85 PathProgramCache]: Analyzing trace with hash -1792615562, now seen corresponding path program 1 times [2025-03-17 20:39:24,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,652 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1302199102] [2025-03-17 20:39:24,652 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:24,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,657 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 57 statements into 1 equivalence classes. [2025-03-17 20:39:24,658 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 57 of 57 statements. [2025-03-17 20:39:24,659 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,659 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:24,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:24,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:24,673 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1302199102] [2025-03-17 20:39:24,673 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1302199102] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:24,673 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:24,673 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:39:24,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [43129206] [2025-03-17 20:39:24,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:24,719 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:24,720 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:24,720 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:24,720 INFO L87 Difference]: Start difference. First operand 2518 states and 3359 transitions. cyclomatic complexity: 853 Second operand has 3 states, 2 states have (on average 28.5) internal successors, (57), 3 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:24,753 INFO L93 Difference]: Finished difference Result 4729 states and 6258 transitions. [2025-03-17 20:39:24,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4729 states and 6258 transitions. [2025-03-17 20:39:24,765 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4240 [2025-03-17 20:39:24,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4729 states to 4729 states and 6258 transitions. [2025-03-17 20:39:24,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4729 [2025-03-17 20:39:24,778 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4729 [2025-03-17 20:39:24,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4729 states and 6258 transitions. [2025-03-17 20:39:24,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:24,783 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4729 states and 6258 transitions. [2025-03-17 20:39:24,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4729 states and 6258 transitions. [2025-03-17 20:39:24,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4729 to 4729. [2025-03-17 20:39:24,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4729 states, 4729 states have (on average 1.3233241700148022) internal successors, (6258), 4728 states have internal predecessors, (6258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4729 states to 4729 states and 6258 transitions. [2025-03-17 20:39:24,841 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4729 states and 6258 transitions. [2025-03-17 20:39:24,842 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:24,842 INFO L432 stractBuchiCegarLoop]: Abstraction has 4729 states and 6258 transitions. [2025-03-17 20:39:24,842 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-17 20:39:24,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4729 states and 6258 transitions. [2025-03-17 20:39:24,851 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4240 [2025-03-17 20:39:24,851 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:24,851 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:24,852 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:24,852 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:24,852 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-03-17 20:39:24,852 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume !(0 == ~t3_st~0);" [2025-03-17 20:39:24,852 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,852 INFO L85 PathProgramCache]: Analyzing trace with hash -264719425, now seen corresponding path program 1 times [2025-03-17 20:39:24,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1048072793] [2025-03-17 20:39:24,852 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:24,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,856 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-17 20:39:24,857 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-17 20:39:24,857 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,857 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:39:24,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:39:24,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:39:24,867 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1048072793] [2025-03-17 20:39:24,867 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1048072793] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:39:24,867 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:39:24,867 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:39:24,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [459685826] [2025-03-17 20:39:24,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:39:24,868 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 20:39:24,868 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:24,868 INFO L85 PathProgramCache]: Analyzing trace with hash -670745159, now seen corresponding path program 2 times [2025-03-17 20:39:24,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:24,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353465962] [2025-03-17 20:39:24,868 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:39:24,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:24,870 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 14 statements into 1 equivalence classes. [2025-03-17 20:39:24,871 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 14 of 14 statements. [2025-03-17 20:39:24,871 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:39:24,871 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,871 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:24,872 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 14 statements into 1 equivalence classes. [2025-03-17 20:39:24,872 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 14 of 14 statements. [2025-03-17 20:39:24,872 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:24,872 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:24,873 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:24,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:39:24,914 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:39:24,914 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:39:24,914 INFO L87 Difference]: Start difference. First operand 4729 states and 6258 transitions. cyclomatic complexity: 1541 Second operand has 3 states, 3 states have (on average 14.333333333333334) internal successors, (43), 2 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:24,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:39:24,924 INFO L93 Difference]: Finished difference Result 4688 states and 6205 transitions. [2025-03-17 20:39:24,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4688 states and 6205 transitions. [2025-03-17 20:39:24,933 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4240 [2025-03-17 20:39:24,973 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4688 states to 4688 states and 6205 transitions. [2025-03-17 20:39:24,973 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4688 [2025-03-17 20:39:24,976 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4688 [2025-03-17 20:39:24,976 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4688 states and 6205 transitions. [2025-03-17 20:39:24,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:39:24,980 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4688 states and 6205 transitions. [2025-03-17 20:39:24,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4688 states and 6205 transitions. [2025-03-17 20:39:25,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4688 to 4688. [2025-03-17 20:39:25,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4688 states, 4688 states have (on average 1.3235921501706485) internal successors, (6205), 4687 states have internal predecessors, (6205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:39:25,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4688 states to 4688 states and 6205 transitions. [2025-03-17 20:39:25,018 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4688 states and 6205 transitions. [2025-03-17 20:39:25,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:39:25,019 INFO L432 stractBuchiCegarLoop]: Abstraction has 4688 states and 6205 transitions. [2025-03-17 20:39:25,019 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-03-17 20:39:25,019 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4688 states and 6205 transitions. [2025-03-17 20:39:25,026 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4240 [2025-03-17 20:39:25,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:39:25,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:39:25,027 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:25,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:39:25,028 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-03-17 20:39:25,028 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" [2025-03-17 20:39:25,029 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:25,029 INFO L85 PathProgramCache]: Analyzing trace with hash 657964158, now seen corresponding path program 4 times [2025-03-17 20:39:25,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:25,029 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533685110] [2025-03-17 20:39:25,029 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 20:39:25,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:25,034 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 43 statements into 2 equivalence classes. [2025-03-17 20:39:25,037 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 43 of 43 statements. [2025-03-17 20:39:25,037 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 20:39:25,037 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:25,037 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:25,039 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-17 20:39:25,040 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-17 20:39:25,040 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:25,040 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:25,044 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:25,044 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:25,044 INFO L85 PathProgramCache]: Analyzing trace with hash -340998549, now seen corresponding path program 1 times [2025-03-17 20:39:25,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:25,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123760311] [2025-03-17 20:39:25,044 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:25,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:25,048 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 16 statements into 1 equivalence classes. [2025-03-17 20:39:25,048 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 16 of 16 statements. [2025-03-17 20:39:25,048 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:25,048 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:25,048 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:25,049 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 16 statements into 1 equivalence classes. [2025-03-17 20:39:25,050 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 16 of 16 statements. [2025-03-17 20:39:25,050 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:25,050 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:25,051 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:25,051 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:39:25,051 INFO L85 PathProgramCache]: Analyzing trace with hash -421664536, now seen corresponding path program 1 times [2025-03-17 20:39:25,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:39:25,051 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1913222141] [2025-03-17 20:39:25,051 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:39:25,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:39:25,057 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 59 statements into 1 equivalence classes. [2025-03-17 20:39:25,059 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 59 of 59 statements. [2025-03-17 20:39:25,059 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:25,059 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:25,059 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:25,060 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 59 statements into 1 equivalence classes. [2025-03-17 20:39:25,062 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 59 of 59 statements. [2025-03-17 20:39:25,062 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:25,062 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:25,065 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:39:25,621 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-17 20:39:25,626 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-17 20:39:25,626 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:25,626 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:25,626 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:39:25,635 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-17 20:39:25,639 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-17 20:39:25,639 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:39:25,639 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:39:25,738 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.03 08:39:25 BoogieIcfgContainer [2025-03-17 20:39:25,738 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-17 20:39:25,738 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-17 20:39:25,738 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-17 20:39:25,739 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-17 20:39:25,739 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:39:21" (3/4) ... [2025-03-17 20:39:25,741 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-03-17 20:39:25,799 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-17 20:39:25,799 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-17 20:39:25,800 INFO L158 Benchmark]: Toolchain (without parser) took 5419.65ms. Allocated memory was 167.8MB in the beginning and 352.3MB in the end (delta: 184.5MB). Free memory was 125.6MB in the beginning and 138.4MB in the end (delta: -12.7MB). Peak memory consumption was 171.6MB. Max. memory is 16.1GB. [2025-03-17 20:39:25,800 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 201.3MB. Free memory is still 115.7MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 20:39:25,800 INFO L158 Benchmark]: CACSL2BoogieTranslator took 252.71ms. Allocated memory is still 167.8MB. Free memory was 125.6MB in the beginning and 111.1MB in the end (delta: 14.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-17 20:39:25,800 INFO L158 Benchmark]: Boogie Procedure Inliner took 55.30ms. Allocated memory is still 167.8MB. Free memory was 111.1MB in the beginning and 108.1MB in the end (delta: 3.0MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 20:39:25,800 INFO L158 Benchmark]: Boogie Preprocessor took 36.91ms. Allocated memory is still 167.8MB. Free memory was 108.1MB in the beginning and 105.9MB in the end (delta: 2.2MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 20:39:25,800 INFO L158 Benchmark]: IcfgBuilder took 581.61ms. Allocated memory is still 167.8MB. Free memory was 105.9MB in the beginning and 66.7MB in the end (delta: 39.2MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2025-03-17 20:39:25,801 INFO L158 Benchmark]: BuchiAutomizer took 4426.97ms. Allocated memory was 167.8MB in the beginning and 352.3MB in the end (delta: 184.5MB). Free memory was 65.9MB in the beginning and 146.8MB in the end (delta: -80.8MB). Peak memory consumption was 104.4MB. Max. memory is 16.1GB. [2025-03-17 20:39:25,801 INFO L158 Benchmark]: Witness Printer took 60.84ms. Allocated memory is still 352.3MB. Free memory was 146.8MB in the beginning and 138.4MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-17 20:39:25,803 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 201.3MB. Free memory is still 115.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 252.71ms. Allocated memory is still 167.8MB. Free memory was 125.6MB in the beginning and 111.1MB in the end (delta: 14.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 55.30ms. Allocated memory is still 167.8MB. Free memory was 111.1MB in the beginning and 108.1MB in the end (delta: 3.0MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 36.91ms. Allocated memory is still 167.8MB. Free memory was 108.1MB in the beginning and 105.9MB in the end (delta: 2.2MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 581.61ms. Allocated memory is still 167.8MB. Free memory was 105.9MB in the beginning and 66.7MB in the end (delta: 39.2MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 4426.97ms. Allocated memory was 167.8MB in the beginning and 352.3MB in the end (delta: 184.5MB). Free memory was 65.9MB in the beginning and 146.8MB in the end (delta: -80.8MB). Peak memory consumption was 104.4MB. Max. memory is 16.1GB. * Witness Printer took 60.84ms. Allocated memory is still 352.3MB. Free memory was 146.8MB in the beginning and 138.4MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 4 locations. The remainder module has 4688 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.3s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 2.4s. Construction of modules took 0.4s. Büchi inclusion checks took 1.2s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 0.5s AutomataMinimizationTime, 21 MinimizatonAttempts, 1531 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 5677 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 5677 mSDsluCounter, 14529 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 6182 mSDsCounter, 178 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 500 IncrementalHoareTripleChecker+Invalid, 678 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 178 mSolverCounterUnsat, 8347 mSDtfsCounter, 500 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI7 SFLT0 conc3 concLT0 SILN1 SILU0 SILI10 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 341]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 341]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L652] COND TRUE 1 [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L341] COND TRUE 1 [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-03-17 20:39:25,819 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)