./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8fc3dc66 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e4ea247b245ebcaf5e735452e89c4110c7b9dc9b43836e98484a894783fc3462 --- Real Ultimate output --- This is Ultimate 0.3.0-?-8fc3dc6-m [2025-03-17 20:55:08,406 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-17 20:55:08,463 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-17 20:55:08,467 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-17 20:55:08,467 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-17 20:55:08,468 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-17 20:55:08,486 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-17 20:55:08,487 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-17 20:55:08,487 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-17 20:55:08,488 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-17 20:55:08,488 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-17 20:55:08,489 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-17 20:55:08,489 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-17 20:55:08,489 INFO L153 SettingsManager]: * Use SBE=true [2025-03-17 20:55:08,489 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-17 20:55:08,489 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-17 20:55:08,489 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-17 20:55:08,489 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-17 20:55:08,490 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-17 20:55:08,490 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-17 20:55:08,490 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-17 20:55:08,490 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-17 20:55:08,490 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-17 20:55:08,490 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-17 20:55:08,490 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-17 20:55:08,490 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-17 20:55:08,490 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-17 20:55:08,490 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-17 20:55:08,490 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-17 20:55:08,490 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-17 20:55:08,491 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-17 20:55:08,491 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-17 20:55:08,491 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-17 20:55:08,491 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-17 20:55:08,491 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-17 20:55:08,491 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-17 20:55:08,491 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-17 20:55:08,491 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-17 20:55:08,491 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-17 20:55:08,492 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-17 20:55:08,492 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e4ea247b245ebcaf5e735452e89c4110c7b9dc9b43836e98484a894783fc3462 [2025-03-17 20:55:08,697 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-17 20:55:08,701 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-17 20:55:08,704 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-17 20:55:08,705 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-17 20:55:08,705 INFO L274 PluginConnector]: CDTParser initialized [2025-03-17 20:55:08,707 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i [2025-03-17 20:55:09,792 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c07ec5c0d/6e05519a25b14ce98a9da3b9cd85226f/FLAG261d341be [2025-03-17 20:55:10,088 INFO L384 CDTParser]: Found 1 translation units. [2025-03-17 20:55:10,088 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i [2025-03-17 20:55:10,099 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c07ec5c0d/6e05519a25b14ce98a9da3b9cd85226f/FLAG261d341be [2025-03-17 20:55:10,355 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c07ec5c0d/6e05519a25b14ce98a9da3b9cd85226f [2025-03-17 20:55:10,357 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-17 20:55:10,358 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-17 20:55:10,358 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-17 20:55:10,358 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-17 20:55:10,361 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-17 20:55:10,361 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:10,362 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@65d36e8b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10, skipping insertion in model container [2025-03-17 20:55:10,362 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:10,396 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-17 20:55:10,823 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 20:55:10,837 INFO L200 MainTranslator]: Completed pre-run [2025-03-17 20:55:10,921 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 20:55:10,960 INFO L204 MainTranslator]: Completed translation [2025-03-17 20:55:10,960 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10 WrapperNode [2025-03-17 20:55:10,960 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-17 20:55:10,961 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-17 20:55:10,961 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-17 20:55:10,961 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-17 20:55:10,965 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:10,981 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:11,026 INFO L138 Inliner]: procedures = 282, calls = 353, calls flagged for inlining = 25, calls inlined = 37, statements flattened = 1756 [2025-03-17 20:55:11,026 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-17 20:55:11,027 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-17 20:55:11,027 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-17 20:55:11,027 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-17 20:55:11,032 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:11,033 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:11,047 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:11,139 INFO L175 MemorySlicer]: Split 326 memory accesses to 4 slices as follows [2, 19, 34, 271]. 83 percent of accesses are in the largest equivalence class. The 12 initializations are split as follows [2, 10, 0, 0]. The 65 writes are split as follows [0, 3, 4, 58]. [2025-03-17 20:55:11,139 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:11,139 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:11,163 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:11,166 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:11,175 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:11,181 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:11,191 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-17 20:55:11,193 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-17 20:55:11,193 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-17 20:55:11,193 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-17 20:55:11,194 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (1/1) ... [2025-03-17 20:55:11,199 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 20:55:11,208 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 20:55:11,220 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 20:55:11,223 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-17 20:55:11,239 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#0 [2025-03-17 20:55:11,240 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#1 [2025-03-17 20:55:11,240 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#2 [2025-03-17 20:55:11,240 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#3 [2025-03-17 20:55:11,240 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#0 [2025-03-17 20:55:11,240 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#1 [2025-03-17 20:55:11,240 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#2 [2025-03-17 20:55:11,240 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#3 [2025-03-17 20:55:11,240 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-03-17 20:55:11,240 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#0 [2025-03-17 20:55:11,240 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#1 [2025-03-17 20:55:11,241 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#2 [2025-03-17 20:55:11,241 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#3 [2025-03-17 20:55:11,241 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-17 20:55:11,241 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-17 20:55:11,241 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-03-17 20:55:11,241 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2025-03-17 20:55:11,241 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#3 [2025-03-17 20:55:11,242 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-17 20:55:11,242 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-03-17 20:55:11,242 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2025-03-17 20:55:11,242 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#3 [2025-03-17 20:55:11,242 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2025-03-17 20:55:11,242 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-17 20:55:11,242 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#0 [2025-03-17 20:55:11,242 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#1 [2025-03-17 20:55:11,243 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#2 [2025-03-17 20:55:11,243 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#3 [2025-03-17 20:55:11,243 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-17 20:55:11,243 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-03-17 20:55:11,243 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#2 [2025-03-17 20:55:11,243 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#3 [2025-03-17 20:55:11,243 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-17 20:55:11,243 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-17 20:55:11,438 INFO L256 CfgBuilder]: Building ICFG [2025-03-17 20:55:11,440 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-17 20:55:12,601 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L969: havoc alt_memcmp_#t~nondet36#1; [2025-03-17 20:55:12,601 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L979: havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; [2025-03-17 20:55:12,601 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L987: call ULTIMATE.dealloc(main_~#i~0#1.base, main_~#i~0#1.offset);havoc main_~#i~0#1.base, main_~#i~0#1.offset; [2025-03-17 20:55:12,601 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L955: havoc alt_malloc_#t~malloc32#1.base, alt_malloc_#t~malloc32#1.offset; [2025-03-17 20:55:12,601 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L955-3: havoc alt_malloc_#t~malloc32#1.base, alt_malloc_#t~malloc32#1.offset; [2025-03-17 20:55:12,601 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L955-6: havoc alt_malloc_#t~malloc32#1.base, alt_malloc_#t~malloc32#1.offset; [2025-03-17 20:55:12,687 INFO L? ?]: Removed 476 outVars from TransFormulas that were not future-live. [2025-03-17 20:55:12,687 INFO L307 CfgBuilder]: Performing block encoding [2025-03-17 20:55:12,739 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-17 20:55:12,739 INFO L336 CfgBuilder]: Removed 1 assume(true) statements. [2025-03-17 20:55:12,739 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:55:12 BoogieIcfgContainer [2025-03-17 20:55:12,739 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-17 20:55:12,740 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-17 20:55:12,740 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-17 20:55:12,745 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-17 20:55:12,745 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 20:55:12,745 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.03 08:55:10" (1/3) ... [2025-03-17 20:55:12,746 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@844975d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 08:55:12, skipping insertion in model container [2025-03-17 20:55:12,747 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 20:55:12,747 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 08:55:10" (2/3) ... [2025-03-17 20:55:12,747 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@844975d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 08:55:12, skipping insertion in model container [2025-03-17 20:55:12,747 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 20:55:12,747 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 08:55:12" (3/3) ... [2025-03-17 20:55:12,748 INFO L363 chiAutomizerObserver]: Analyzing ICFG uthash_FNV_test6-2.i [2025-03-17 20:55:12,787 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-17 20:55:12,787 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-17 20:55:12,787 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-17 20:55:12,787 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-17 20:55:12,787 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-17 20:55:12,787 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-17 20:55:12,787 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-17 20:55:12,788 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-17 20:55:12,793 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 481 states, 476 states have (on average 1.6008403361344539) internal successors, (762), 476 states have internal predecessors, (762), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:12,817 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 457 [2025-03-17 20:55:12,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:12,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:12,824 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:12,824 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:12,824 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-17 20:55:12,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 481 states, 476 states have (on average 1.6008403361344539) internal successors, (762), 476 states have internal predecessors, (762), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:12,841 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 457 [2025-03-17 20:55:12,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:12,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:12,841 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:12,841 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:12,846 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:12,846 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false;" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume !true;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:12,849 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:12,849 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 1 times [2025-03-17 20:55:12,854 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:12,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278123313] [2025-03-17 20:55:12,854 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:12,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:12,918 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:12,941 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:12,942 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:12,942 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:12,942 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:12,952 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:12,964 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:12,966 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:12,966 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:12,993 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:12,995 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:12,995 INFO L85 PathProgramCache]: Analyzing trace with hash -1323948506, now seen corresponding path program 1 times [2025-03-17 20:55:12,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:12,995 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138057827] [2025-03-17 20:55:12,996 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:12,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:13,015 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-17 20:55:13,020 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-17 20:55:13,023 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:13,023 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:13,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:13,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:13,060 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2138057827] [2025-03-17 20:55:13,061 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2138057827] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:13,061 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:13,061 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 20:55:13,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [142686240] [2025-03-17 20:55:13,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:13,063 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:13,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:13,081 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-17 20:55:13,081 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-17 20:55:13,084 INFO L87 Difference]: Start difference. First operand has 481 states, 476 states have (on average 1.6008403361344539) internal successors, (762), 476 states have internal predecessors, (762), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:13,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:13,164 INFO L93 Difference]: Finished difference Result 464 states and 653 transitions. [2025-03-17 20:55:13,165 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 464 states and 653 transitions. [2025-03-17 20:55:13,173 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 432 [2025-03-17 20:55:13,184 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 464 states to 448 states and 637 transitions. [2025-03-17 20:55:13,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 448 [2025-03-17 20:55:13,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 448 [2025-03-17 20:55:13,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 448 states and 637 transitions. [2025-03-17 20:55:13,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:13,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 448 states and 637 transitions. [2025-03-17 20:55:13,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 448 states and 637 transitions. [2025-03-17 20:55:13,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 448 to 448. [2025-03-17 20:55:13,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 448 states, 444 states have (on average 1.4211711711711712) internal successors, (631), 443 states have internal predecessors, (631), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:13,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 448 states to 448 states and 637 transitions. [2025-03-17 20:55:13,228 INFO L240 hiAutomatonCegarLoop]: Abstraction has 448 states and 637 transitions. [2025-03-17 20:55:13,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-17 20:55:13,230 INFO L432 stractBuchiCegarLoop]: Abstraction has 448 states and 637 transitions. [2025-03-17 20:55:13,230 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-17 20:55:13,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 448 states and 637 transitions. [2025-03-17 20:55:13,232 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 432 [2025-03-17 20:55:13,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:13,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:13,234 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:13,234 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:13,234 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:13,235 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem67#1 := read~int#3(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem67#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem68#1 := read~int#3(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem68#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem69#1 := read~int#3(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem69#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem70#1 := read~int#3(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem70#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem71#1 := read~int#3(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem71#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem72#1 := read~int#3(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem72#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem73#1 := read~int#3(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + (if main_#t~mem73#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem73#1 % 256 % 4294967296 else main_#t~mem73#1 % 256 % 4294967296 - 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:13,236 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:13,238 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 2 times [2025-03-17 20:55:13,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:13,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277038466] [2025-03-17 20:55:13,239 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:55:13,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:13,249 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:13,260 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:13,260 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:55:13,260 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:13,260 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:13,268 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:13,278 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:13,279 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:13,280 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:13,288 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:13,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:13,289 INFO L85 PathProgramCache]: Analyzing trace with hash 220148323, now seen corresponding path program 1 times [2025-03-17 20:55:13,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:13,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68650792] [2025-03-17 20:55:13,289 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:13,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:13,351 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-17 20:55:13,373 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-17 20:55:13,374 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:13,374 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:13,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:13,669 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:13,669 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [68650792] [2025-03-17 20:55:13,669 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [68650792] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:13,670 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:13,670 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:55:13,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274043596] [2025-03-17 20:55:13,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:13,670 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:13,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:13,671 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:55:13,671 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:55:13,671 INFO L87 Difference]: Start difference. First operand 448 states and 637 transitions. cyclomatic complexity: 193 Second operand has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:13,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:13,845 INFO L93 Difference]: Finished difference Result 451 states and 633 transitions. [2025-03-17 20:55:13,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 451 states and 633 transitions. [2025-03-17 20:55:13,849 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 435 [2025-03-17 20:55:13,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 451 states to 451 states and 633 transitions. [2025-03-17 20:55:13,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 451 [2025-03-17 20:55:13,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 451 [2025-03-17 20:55:13,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 451 states and 633 transitions. [2025-03-17 20:55:13,855 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:13,856 INFO L218 hiAutomatonCegarLoop]: Abstraction has 451 states and 633 transitions. [2025-03-17 20:55:13,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states and 633 transitions. [2025-03-17 20:55:13,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 448. [2025-03-17 20:55:13,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 448 states, 444 states have (on average 1.4054054054054055) internal successors, (624), 443 states have internal predecessors, (624), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:13,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 448 states to 448 states and 630 transitions. [2025-03-17 20:55:13,871 INFO L240 hiAutomatonCegarLoop]: Abstraction has 448 states and 630 transitions. [2025-03-17 20:55:13,871 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:55:13,872 INFO L432 stractBuchiCegarLoop]: Abstraction has 448 states and 630 transitions. [2025-03-17 20:55:13,872 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-17 20:55:13,872 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 448 states and 630 transitions. [2025-03-17 20:55:13,873 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 432 [2025-03-17 20:55:13,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:13,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:13,874 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:13,874 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:13,875 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:13,875 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:13,875 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:13,875 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 3 times [2025-03-17 20:55:13,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:13,876 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051734616] [2025-03-17 20:55:13,876 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:55:13,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:13,886 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:13,891 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:13,891 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:55:13,891 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:13,891 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:13,897 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:13,902 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:13,903 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:13,903 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:13,910 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:13,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:13,911 INFO L85 PathProgramCache]: Analyzing trace with hash 1145271786, now seen corresponding path program 1 times [2025-03-17 20:55:13,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:13,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360724977] [2025-03-17 20:55:13,911 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:13,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:13,953 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-17 20:55:13,958 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-17 20:55:13,958 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:13,958 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:14,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:14,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:14,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1360724977] [2025-03-17 20:55:14,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1360724977] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:14,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:14,115 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 20:55:14,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [687221476] [2025-03-17 20:55:14,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:14,115 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:14,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:14,115 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 20:55:14,116 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 20:55:14,116 INFO L87 Difference]: Start difference. First operand 448 states and 630 transitions. cyclomatic complexity: 186 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:14,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:14,218 INFO L93 Difference]: Finished difference Result 454 states and 636 transitions. [2025-03-17 20:55:14,219 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 636 transitions. [2025-03-17 20:55:14,221 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 438 [2025-03-17 20:55:14,223 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 636 transitions. [2025-03-17 20:55:14,223 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 [2025-03-17 20:55:14,223 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 [2025-03-17 20:55:14,223 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 636 transitions. [2025-03-17 20:55:14,224 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:14,224 INFO L218 hiAutomatonCegarLoop]: Abstraction has 454 states and 636 transitions. [2025-03-17 20:55:14,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 636 transitions. [2025-03-17 20:55:14,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. [2025-03-17 20:55:14,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 454 states, 450 states have (on average 1.4) internal successors, (630), 449 states have internal predecessors, (630), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:14,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 636 transitions. [2025-03-17 20:55:14,230 INFO L240 hiAutomatonCegarLoop]: Abstraction has 454 states and 636 transitions. [2025-03-17 20:55:14,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 20:55:14,231 INFO L432 stractBuchiCegarLoop]: Abstraction has 454 states and 636 transitions. [2025-03-17 20:55:14,231 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-17 20:55:14,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 636 transitions. [2025-03-17 20:55:14,233 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 438 [2025-03-17 20:55:14,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:14,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:14,234 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:14,234 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:14,234 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:14,235 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:14,236 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:14,236 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 4 times [2025-03-17 20:55:14,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:14,237 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796094552] [2025-03-17 20:55:14,238 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 20:55:14,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:14,247 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-03-17 20:55:14,249 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:14,250 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 20:55:14,250 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:14,250 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:14,257 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:14,261 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:14,261 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:14,261 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:14,266 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:14,267 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:14,267 INFO L85 PathProgramCache]: Analyzing trace with hash 352929068, now seen corresponding path program 1 times [2025-03-17 20:55:14,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:14,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82724213] [2025-03-17 20:55:14,267 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:14,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:14,297 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-17 20:55:14,305 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-17 20:55:14,305 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:14,305 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:14,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:14,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:14,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82724213] [2025-03-17 20:55:14,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [82724213] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:14,397 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:14,397 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:55:14,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719587788] [2025-03-17 20:55:14,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:14,397 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:14,397 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:14,398 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:55:14,398 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:55:14,398 INFO L87 Difference]: Start difference. First operand 454 states and 636 transitions. cyclomatic complexity: 186 Second operand has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:14,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:14,513 INFO L93 Difference]: Finished difference Result 400 states and 550 transitions. [2025-03-17 20:55:14,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 400 states and 550 transitions. [2025-03-17 20:55:14,515 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 384 [2025-03-17 20:55:14,517 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 400 states to 400 states and 550 transitions. [2025-03-17 20:55:14,517 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 400 [2025-03-17 20:55:14,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 400 [2025-03-17 20:55:14,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 400 states and 550 transitions. [2025-03-17 20:55:14,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:14,518 INFO L218 hiAutomatonCegarLoop]: Abstraction has 400 states and 550 transitions. [2025-03-17 20:55:14,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 400 states and 550 transitions. [2025-03-17 20:55:14,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 400 to 400. [2025-03-17 20:55:14,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 400 states, 396 states have (on average 1.3737373737373737) internal successors, (544), 395 states have internal predecessors, (544), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:14,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 400 states to 400 states and 550 transitions. [2025-03-17 20:55:14,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 400 states and 550 transitions. [2025-03-17 20:55:14,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-17 20:55:14,524 INFO L432 stractBuchiCegarLoop]: Abstraction has 400 states and 550 transitions. [2025-03-17 20:55:14,524 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-17 20:55:14,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 400 states and 550 transitions. [2025-03-17 20:55:14,526 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 384 [2025-03-17 20:55:14,526 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:14,526 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:14,527 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:14,528 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:14,528 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:14,528 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:14,529 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:14,529 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 5 times [2025-03-17 20:55:14,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:14,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694825309] [2025-03-17 20:55:14,530 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 20:55:14,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:14,537 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:14,541 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:14,541 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:55:14,541 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:14,541 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:14,545 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:14,547 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:14,547 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:14,547 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:14,553 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:14,553 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:14,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1153031145, now seen corresponding path program 1 times [2025-03-17 20:55:14,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:14,553 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292966580] [2025-03-17 20:55:14,553 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:14,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:14,583 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-17 20:55:14,752 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-17 20:55:14,752 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:14,752 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:15,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:15,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:15,024 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [292966580] [2025-03-17 20:55:15,024 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [292966580] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:15,024 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:15,024 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-17 20:55:15,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027676467] [2025-03-17 20:55:15,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:15,024 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:15,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:15,024 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-17 20:55:15,024 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-17 20:55:15,025 INFO L87 Difference]: Start difference. First operand 400 states and 550 transitions. cyclomatic complexity: 154 Second operand has 6 states, 6 states have (on average 12.5) internal successors, (75), 6 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:15,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:15,438 INFO L93 Difference]: Finished difference Result 405 states and 557 transitions. [2025-03-17 20:55:15,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 405 states and 557 transitions. [2025-03-17 20:55:15,440 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 389 [2025-03-17 20:55:15,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 405 states to 405 states and 557 transitions. [2025-03-17 20:55:15,443 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 405 [2025-03-17 20:55:15,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 405 [2025-03-17 20:55:15,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 405 states and 557 transitions. [2025-03-17 20:55:15,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:15,445 INFO L218 hiAutomatonCegarLoop]: Abstraction has 405 states and 557 transitions. [2025-03-17 20:55:15,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 405 states and 557 transitions. [2025-03-17 20:55:15,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 405 to 402. [2025-03-17 20:55:15,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 402 states, 398 states have (on average 1.3718592964824121) internal successors, (546), 397 states have internal predecessors, (546), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:15,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 402 states to 402 states and 552 transitions. [2025-03-17 20:55:15,453 INFO L240 hiAutomatonCegarLoop]: Abstraction has 402 states and 552 transitions. [2025-03-17 20:55:15,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-17 20:55:15,454 INFO L432 stractBuchiCegarLoop]: Abstraction has 402 states and 552 transitions. [2025-03-17 20:55:15,454 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-17 20:55:15,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 402 states and 552 transitions. [2025-03-17 20:55:15,455 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 386 [2025-03-17 20:55:15,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:15,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:15,457 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:15,457 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:15,457 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:15,458 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:15,458 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:15,458 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 6 times [2025-03-17 20:55:15,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:15,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799702577] [2025-03-17 20:55:15,459 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 20:55:15,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:15,467 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:15,469 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:15,470 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 20:55:15,470 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:15,470 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:15,474 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:15,476 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:15,476 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:15,476 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:15,483 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:15,484 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:15,484 INFO L85 PathProgramCache]: Analyzing trace with hash 1628316365, now seen corresponding path program 1 times [2025-03-17 20:55:15,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:15,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1451701576] [2025-03-17 20:55:15,484 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:15,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:15,513 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-17 20:55:15,542 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-17 20:55:15,542 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:15,542 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:15,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:15,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:15,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1451701576] [2025-03-17 20:55:15,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1451701576] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:15,716 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:15,716 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-17 20:55:15,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [317058938] [2025-03-17 20:55:15,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:15,716 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:15,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:15,717 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-17 20:55:15,717 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-17 20:55:15,717 INFO L87 Difference]: Start difference. First operand 402 states and 552 transitions. cyclomatic complexity: 154 Second operand has 7 states, 7 states have (on average 10.857142857142858) internal successors, (76), 7 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:16,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:16,085 INFO L93 Difference]: Finished difference Result 407 states and 558 transitions. [2025-03-17 20:55:16,085 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 407 states and 558 transitions. [2025-03-17 20:55:16,087 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 391 [2025-03-17 20:55:16,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 407 states to 407 states and 558 transitions. [2025-03-17 20:55:16,090 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 407 [2025-03-17 20:55:16,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 407 [2025-03-17 20:55:16,090 INFO L73 IsDeterministic]: Start isDeterministic. Operand 407 states and 558 transitions. [2025-03-17 20:55:16,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:16,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 407 states and 558 transitions. [2025-03-17 20:55:16,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 407 states and 558 transitions. [2025-03-17 20:55:16,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 407 to 406. [2025-03-17 20:55:16,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 406 states, 402 states have (on average 1.3706467661691542) internal successors, (551), 401 states have internal predecessors, (551), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:16,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 406 states to 406 states and 557 transitions. [2025-03-17 20:55:16,098 INFO L240 hiAutomatonCegarLoop]: Abstraction has 406 states and 557 transitions. [2025-03-17 20:55:16,099 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-17 20:55:16,099 INFO L432 stractBuchiCegarLoop]: Abstraction has 406 states and 557 transitions. [2025-03-17 20:55:16,099 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-17 20:55:16,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 406 states and 557 transitions. [2025-03-17 20:55:16,100 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 390 [2025-03-17 20:55:16,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:16,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:16,101 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:16,101 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:16,101 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:16,101 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:16,101 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:16,101 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 7 times [2025-03-17 20:55:16,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:16,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82788440] [2025-03-17 20:55:16,101 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 20:55:16,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:16,107 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:16,109 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:16,109 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:16,109 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:16,110 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:16,112 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:16,113 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:16,113 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:16,113 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:16,117 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:16,118 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:16,118 INFO L85 PathProgramCache]: Analyzing trace with hash -14122828, now seen corresponding path program 1 times [2025-03-17 20:55:16,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:16,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402322838] [2025-03-17 20:55:16,118 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:16,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:16,141 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-17 20:55:16,219 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-17 20:55:16,219 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:16,219 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:16,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:16,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:16,399 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [402322838] [2025-03-17 20:55:16,399 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [402322838] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:16,399 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:16,400 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 20:55:16,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771497368] [2025-03-17 20:55:16,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:16,401 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:16,401 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:16,401 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 20:55:16,401 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 20:55:16,401 INFO L87 Difference]: Start difference. First operand 406 states and 557 transitions. cyclomatic complexity: 155 Second operand has 4 states, 4 states have (on average 19.0) internal successors, (76), 4 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:16,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:16,565 INFO L93 Difference]: Finished difference Result 406 states and 556 transitions. [2025-03-17 20:55:16,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 406 states and 556 transitions. [2025-03-17 20:55:16,567 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 390 [2025-03-17 20:55:16,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 406 states to 406 states and 556 transitions. [2025-03-17 20:55:16,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 406 [2025-03-17 20:55:16,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 406 [2025-03-17 20:55:16,569 INFO L73 IsDeterministic]: Start isDeterministic. Operand 406 states and 556 transitions. [2025-03-17 20:55:16,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:16,570 INFO L218 hiAutomatonCegarLoop]: Abstraction has 406 states and 556 transitions. [2025-03-17 20:55:16,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 406 states and 556 transitions. [2025-03-17 20:55:16,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 406 to 406. [2025-03-17 20:55:16,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 406 states, 402 states have (on average 1.3681592039800996) internal successors, (550), 401 states have internal predecessors, (550), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:16,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 406 states to 406 states and 556 transitions. [2025-03-17 20:55:16,581 INFO L240 hiAutomatonCegarLoop]: Abstraction has 406 states and 556 transitions. [2025-03-17 20:55:16,581 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 20:55:16,581 INFO L432 stractBuchiCegarLoop]: Abstraction has 406 states and 556 transitions. [2025-03-17 20:55:16,581 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-17 20:55:16,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 406 states and 556 transitions. [2025-03-17 20:55:16,582 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 390 [2025-03-17 20:55:16,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:16,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:16,583 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:16,583 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:16,583 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:16,585 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:16,586 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:16,586 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 8 times [2025-03-17 20:55:16,586 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:16,586 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415377419] [2025-03-17 20:55:16,586 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:55:16,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:16,593 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:16,595 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:16,595 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:55:16,595 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:16,595 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:16,598 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:16,599 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:16,599 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:16,599 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:16,605 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:16,606 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:16,606 INFO L85 PathProgramCache]: Analyzing trace with hash 203755526, now seen corresponding path program 1 times [2025-03-17 20:55:16,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:16,606 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793290962] [2025-03-17 20:55:16,606 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:16,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:16,639 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-17 20:55:16,736 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-17 20:55:16,737 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:16,737 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:17,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:17,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:17,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793290962] [2025-03-17 20:55:17,079 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1793290962] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:17,079 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:17,079 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2025-03-17 20:55:17,080 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [588703068] [2025-03-17 20:55:17,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:17,080 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:17,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:17,080 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-17 20:55:17,081 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2025-03-17 20:55:17,081 INFO L87 Difference]: Start difference. First operand 406 states and 556 transitions. cyclomatic complexity: 154 Second operand has 8 states, 8 states have (on average 9.625) internal successors, (77), 8 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:17,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:17,464 INFO L93 Difference]: Finished difference Result 413 states and 564 transitions. [2025-03-17 20:55:17,464 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 564 transitions. [2025-03-17 20:55:17,466 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 397 [2025-03-17 20:55:17,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 564 transitions. [2025-03-17 20:55:17,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2025-03-17 20:55:17,468 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2025-03-17 20:55:17,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 564 transitions. [2025-03-17 20:55:17,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:17,469 INFO L218 hiAutomatonCegarLoop]: Abstraction has 413 states and 564 transitions. [2025-03-17 20:55:17,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 564 transitions. [2025-03-17 20:55:17,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 411. [2025-03-17 20:55:17,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 411 states, 407 states have (on average 1.366093366093366) internal successors, (556), 406 states have internal predecessors, (556), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:17,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 411 states to 411 states and 562 transitions. [2025-03-17 20:55:17,474 INFO L240 hiAutomatonCegarLoop]: Abstraction has 411 states and 562 transitions. [2025-03-17 20:55:17,475 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-17 20:55:17,475 INFO L432 stractBuchiCegarLoop]: Abstraction has 411 states and 562 transitions. [2025-03-17 20:55:17,475 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-17 20:55:17,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 411 states and 562 transitions. [2025-03-17 20:55:17,476 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 395 [2025-03-17 20:55:17,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:17,476 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:17,476 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:17,477 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:17,477 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:17,477 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:17,478 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:17,478 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 9 times [2025-03-17 20:55:17,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:17,478 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683575020] [2025-03-17 20:55:17,478 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:55:17,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:17,485 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:17,487 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:17,487 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:55:17,487 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:17,487 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:17,489 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:17,494 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:17,494 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:17,494 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:17,499 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:17,499 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:17,499 INFO L85 PathProgramCache]: Analyzing trace with hash 540629414, now seen corresponding path program 1 times [2025-03-17 20:55:17,499 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:17,499 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23322480] [2025-03-17 20:55:17,499 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:17,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:17,529 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-17 20:55:17,547 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-17 20:55:17,547 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:17,547 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:17,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:17,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:17,715 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23322480] [2025-03-17 20:55:17,715 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23322480] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:17,715 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:17,715 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-17 20:55:17,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1597410542] [2025-03-17 20:55:17,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:17,716 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:17,716 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:17,716 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-17 20:55:17,716 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-03-17 20:55:17,716 INFO L87 Difference]: Start difference. First operand 411 states and 562 transitions. cyclomatic complexity: 155 Second operand has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 6 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:18,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:18,021 INFO L93 Difference]: Finished difference Result 414 states and 565 transitions. [2025-03-17 20:55:18,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 414 states and 565 transitions. [2025-03-17 20:55:18,023 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 398 [2025-03-17 20:55:18,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 414 states to 414 states and 565 transitions. [2025-03-17 20:55:18,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 414 [2025-03-17 20:55:18,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 414 [2025-03-17 20:55:18,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 414 states and 565 transitions. [2025-03-17 20:55:18,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:18,025 INFO L218 hiAutomatonCegarLoop]: Abstraction has 414 states and 565 transitions. [2025-03-17 20:55:18,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 414 states and 565 transitions. [2025-03-17 20:55:18,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 414 to 414. [2025-03-17 20:55:18,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 414 states, 410 states have (on average 1.3634146341463416) internal successors, (559), 409 states have internal predecessors, (559), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:18,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 414 states to 414 states and 565 transitions. [2025-03-17 20:55:18,030 INFO L240 hiAutomatonCegarLoop]: Abstraction has 414 states and 565 transitions. [2025-03-17 20:55:18,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-17 20:55:18,031 INFO L432 stractBuchiCegarLoop]: Abstraction has 414 states and 565 transitions. [2025-03-17 20:55:18,031 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-17 20:55:18,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 414 states and 565 transitions. [2025-03-17 20:55:18,032 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 398 [2025-03-17 20:55:18,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:18,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:18,033 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:18,033 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:18,033 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:18,034 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:18,035 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:18,035 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 10 times [2025-03-17 20:55:18,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:18,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592391942] [2025-03-17 20:55:18,035 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 20:55:18,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:18,042 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-03-17 20:55:18,043 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:18,043 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 20:55:18,043 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:18,044 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:18,046 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:18,047 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:18,047 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:18,047 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:18,051 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:18,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:18,052 INFO L85 PathProgramCache]: Analyzing trace with hash -34421079, now seen corresponding path program 1 times [2025-03-17 20:55:18,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:18,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668095386] [2025-03-17 20:55:18,052 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:18,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:18,079 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-17 20:55:18,094 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-17 20:55:18,094 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:18,094 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:18,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:18,360 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:18,360 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668095386] [2025-03-17 20:55:18,360 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [668095386] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:18,360 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:18,360 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-17 20:55:18,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231372445] [2025-03-17 20:55:18,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:18,361 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:18,361 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:18,361 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-17 20:55:18,361 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-17 20:55:18,361 INFO L87 Difference]: Start difference. First operand 414 states and 565 transitions. cyclomatic complexity: 155 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:18,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:18,874 INFO L93 Difference]: Finished difference Result 425 states and 580 transitions. [2025-03-17 20:55:18,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 580 transitions. [2025-03-17 20:55:18,876 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 409 [2025-03-17 20:55:18,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 580 transitions. [2025-03-17 20:55:18,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2025-03-17 20:55:18,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2025-03-17 20:55:18,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 580 transitions. [2025-03-17 20:55:18,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:18,879 INFO L218 hiAutomatonCegarLoop]: Abstraction has 425 states and 580 transitions. [2025-03-17 20:55:18,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 580 transitions. [2025-03-17 20:55:18,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 422. [2025-03-17 20:55:18,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 422 states, 418 states have (on average 1.3636363636363635) internal successors, (570), 417 states have internal predecessors, (570), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:18,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 422 states to 422 states and 576 transitions. [2025-03-17 20:55:18,884 INFO L240 hiAutomatonCegarLoop]: Abstraction has 422 states and 576 transitions. [2025-03-17 20:55:18,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-17 20:55:18,885 INFO L432 stractBuchiCegarLoop]: Abstraction has 422 states and 576 transitions. [2025-03-17 20:55:18,885 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-17 20:55:18,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 422 states and 576 transitions. [2025-03-17 20:55:18,886 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 406 [2025-03-17 20:55:18,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:18,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:18,886 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:18,886 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:18,886 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:18,887 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:18,887 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:18,888 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 11 times [2025-03-17 20:55:18,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:18,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187566747] [2025-03-17 20:55:18,888 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 20:55:18,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:18,895 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:18,897 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:18,897 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:55:18,897 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:18,897 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:18,900 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:18,901 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:18,901 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:18,901 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:18,905 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:18,905 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:18,906 INFO L85 PathProgramCache]: Analyzing trace with hash 3344253, now seen corresponding path program 1 times [2025-03-17 20:55:18,906 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:18,906 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239567930] [2025-03-17 20:55:18,906 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:18,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:18,930 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-17 20:55:19,018 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-17 20:55:19,018 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:19,018 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:19,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:19,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:19,547 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239567930] [2025-03-17 20:55:19,547 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239567930] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:19,547 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:19,547 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-17 20:55:19,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596454887] [2025-03-17 20:55:19,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:19,548 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:19,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:19,548 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-17 20:55:19,548 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-17 20:55:19,548 INFO L87 Difference]: Start difference. First operand 422 states and 576 transitions. cyclomatic complexity: 158 Second operand has 13 states, 13 states have (on average 6.0) internal successors, (78), 13 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:21,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:21,870 INFO L93 Difference]: Finished difference Result 500 states and 684 transitions. [2025-03-17 20:55:21,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 500 states and 684 transitions. [2025-03-17 20:55:21,873 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 484 [2025-03-17 20:55:21,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 500 states to 500 states and 684 transitions. [2025-03-17 20:55:21,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 500 [2025-03-17 20:55:21,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 500 [2025-03-17 20:55:21,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 500 states and 684 transitions. [2025-03-17 20:55:21,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:21,876 INFO L218 hiAutomatonCegarLoop]: Abstraction has 500 states and 684 transitions. [2025-03-17 20:55:21,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 500 states and 684 transitions. [2025-03-17 20:55:21,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 500 to 428. [2025-03-17 20:55:21,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 428 states, 424 states have (on average 1.3632075471698113) internal successors, (578), 423 states have internal predecessors, (578), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:21,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 428 states to 428 states and 584 transitions. [2025-03-17 20:55:21,882 INFO L240 hiAutomatonCegarLoop]: Abstraction has 428 states and 584 transitions. [2025-03-17 20:55:21,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-17 20:55:21,884 INFO L432 stractBuchiCegarLoop]: Abstraction has 428 states and 584 transitions. [2025-03-17 20:55:21,884 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-17 20:55:21,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 428 states and 584 transitions. [2025-03-17 20:55:21,885 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 412 [2025-03-17 20:55:21,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:21,885 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:21,885 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:21,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:21,886 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:21,886 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:21,886 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:21,886 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 12 times [2025-03-17 20:55:21,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:21,886 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019601897] [2025-03-17 20:55:21,887 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 20:55:21,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:21,894 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:21,895 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:21,896 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 20:55:21,896 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:21,896 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:21,898 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:21,901 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:21,901 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:21,901 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:21,907 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:21,907 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:21,907 INFO L85 PathProgramCache]: Analyzing trace with hash 339400427, now seen corresponding path program 1 times [2025-03-17 20:55:21,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:21,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878144814] [2025-03-17 20:55:21,908 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:21,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:21,952 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-17 20:55:21,999 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-17 20:55:22,000 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:22,000 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:22,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:22,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:22,169 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1878144814] [2025-03-17 20:55:22,169 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1878144814] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:22,169 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:22,169 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-17 20:55:22,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1967498776] [2025-03-17 20:55:22,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:22,170 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:22,170 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:22,170 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-17 20:55:22,170 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-17 20:55:22,170 INFO L87 Difference]: Start difference. First operand 428 states and 584 transitions. cyclomatic complexity: 160 Second operand has 7 states, 7 states have (on average 11.142857142857142) internal successors, (78), 7 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:22,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:22,558 INFO L93 Difference]: Finished difference Result 433 states and 590 transitions. [2025-03-17 20:55:22,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 433 states and 590 transitions. [2025-03-17 20:55:22,560 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 417 [2025-03-17 20:55:22,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 433 states to 433 states and 590 transitions. [2025-03-17 20:55:22,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 433 [2025-03-17 20:55:22,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 433 [2025-03-17 20:55:22,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 433 states and 590 transitions. [2025-03-17 20:55:22,563 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:22,563 INFO L218 hiAutomatonCegarLoop]: Abstraction has 433 states and 590 transitions. [2025-03-17 20:55:22,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 433 states and 590 transitions. [2025-03-17 20:55:22,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 433 to 428. [2025-03-17 20:55:22,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 428 states, 424 states have (on average 1.3632075471698113) internal successors, (578), 423 states have internal predecessors, (578), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:22,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 428 states to 428 states and 584 transitions. [2025-03-17 20:55:22,568 INFO L240 hiAutomatonCegarLoop]: Abstraction has 428 states and 584 transitions. [2025-03-17 20:55:22,569 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-17 20:55:22,569 INFO L432 stractBuchiCegarLoop]: Abstraction has 428 states and 584 transitions. [2025-03-17 20:55:22,570 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-17 20:55:22,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 428 states and 584 transitions. [2025-03-17 20:55:22,571 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 412 [2025-03-17 20:55:22,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:22,572 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:22,572 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:22,572 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:22,572 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:22,572 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:22,573 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:22,573 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 13 times [2025-03-17 20:55:22,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:22,573 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53479227] [2025-03-17 20:55:22,573 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 20:55:22,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:22,580 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:22,581 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:22,581 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:22,582 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:22,582 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:22,584 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:22,587 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:22,587 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:22,587 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:22,593 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:22,593 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:22,593 INFO L85 PathProgramCache]: Analyzing trace with hash 1469086463, now seen corresponding path program 1 times [2025-03-17 20:55:22,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:22,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [273818754] [2025-03-17 20:55:22,594 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:22,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:22,619 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-17 20:55:22,672 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-17 20:55:22,672 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:22,672 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:22,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:22,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:22,962 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [273818754] [2025-03-17 20:55:22,962 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [273818754] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:22,962 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:22,962 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-17 20:55:22,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302103981] [2025-03-17 20:55:22,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:22,963 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:22,963 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:22,963 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-17 20:55:22,963 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-03-17 20:55:22,963 INFO L87 Difference]: Start difference. First operand 428 states and 584 transitions. cyclomatic complexity: 160 Second operand has 6 states, 6 states have (on average 13.166666666666666) internal successors, (79), 6 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:23,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:23,329 INFO L93 Difference]: Finished difference Result 425 states and 580 transitions. [2025-03-17 20:55:23,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 580 transitions. [2025-03-17 20:55:23,331 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 409 [2025-03-17 20:55:23,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 580 transitions. [2025-03-17 20:55:23,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2025-03-17 20:55:23,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2025-03-17 20:55:23,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 580 transitions. [2025-03-17 20:55:23,334 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:23,334 INFO L218 hiAutomatonCegarLoop]: Abstraction has 425 states and 580 transitions. [2025-03-17 20:55:23,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 580 transitions. [2025-03-17 20:55:23,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2025-03-17 20:55:23,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 421 states have (on average 1.3634204275534443) internal successors, (574), 420 states have internal predecessors, (574), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:23,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 580 transitions. [2025-03-17 20:55:23,339 INFO L240 hiAutomatonCegarLoop]: Abstraction has 425 states and 580 transitions. [2025-03-17 20:55:23,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-17 20:55:23,340 INFO L432 stractBuchiCegarLoop]: Abstraction has 425 states and 580 transitions. [2025-03-17 20:55:23,340 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-17 20:55:23,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 580 transitions. [2025-03-17 20:55:23,341 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 409 [2025-03-17 20:55:23,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:23,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:23,342 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:23,342 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:23,343 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:23,343 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:23,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:23,343 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 14 times [2025-03-17 20:55:23,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:23,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330752974] [2025-03-17 20:55:23,344 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:55:23,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:23,350 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:23,352 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:23,352 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:55:23,352 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:23,352 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:23,356 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:23,357 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:23,357 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:23,357 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:23,361 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:23,362 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:23,362 INFO L85 PathProgramCache]: Analyzing trace with hash -1655155541, now seen corresponding path program 1 times [2025-03-17 20:55:23,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:23,363 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934467994] [2025-03-17 20:55:23,363 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:23,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:23,391 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-17 20:55:23,456 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-17 20:55:23,456 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:23,456 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:23,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:23,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:23,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934467994] [2025-03-17 20:55:23,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934467994] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:23,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:23,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2025-03-17 20:55:23,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [304874954] [2025-03-17 20:55:23,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:23,824 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:23,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:23,824 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-03-17 20:55:23,824 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2025-03-17 20:55:23,824 INFO L87 Difference]: Start difference. First operand 425 states and 580 transitions. cyclomatic complexity: 159 Second operand has 11 states, 11 states have (on average 7.181818181818182) internal successors, (79), 11 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:24,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:24,528 INFO L93 Difference]: Finished difference Result 450 states and 616 transitions. [2025-03-17 20:55:24,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 450 states and 616 transitions. [2025-03-17 20:55:24,529 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 434 [2025-03-17 20:55:24,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 450 states to 450 states and 616 transitions. [2025-03-17 20:55:24,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 450 [2025-03-17 20:55:24,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 450 [2025-03-17 20:55:24,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 450 states and 616 transitions. [2025-03-17 20:55:24,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:24,532 INFO L218 hiAutomatonCegarLoop]: Abstraction has 450 states and 616 transitions. [2025-03-17 20:55:24,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450 states and 616 transitions. [2025-03-17 20:55:24,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450 to 428. [2025-03-17 20:55:24,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 428 states, 424 states have (on average 1.3632075471698113) internal successors, (578), 423 states have internal predecessors, (578), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:24,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 428 states to 428 states and 584 transitions. [2025-03-17 20:55:24,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 428 states and 584 transitions. [2025-03-17 20:55:24,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-17 20:55:24,540 INFO L432 stractBuchiCegarLoop]: Abstraction has 428 states and 584 transitions. [2025-03-17 20:55:24,540 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-17 20:55:24,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 428 states and 584 transitions. [2025-03-17 20:55:24,541 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 412 [2025-03-17 20:55:24,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:24,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:24,541 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:24,541 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:24,542 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:24,542 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise83#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:24,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:24,542 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 15 times [2025-03-17 20:55:24,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:24,543 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101887214] [2025-03-17 20:55:24,543 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:55:24,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:24,551 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:24,553 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:24,553 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:55:24,553 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:24,553 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:24,556 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:24,557 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:24,557 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:24,557 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:24,563 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:24,563 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:24,563 INFO L85 PathProgramCache]: Analyzing trace with hash 544573597, now seen corresponding path program 1 times [2025-03-17 20:55:24,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:24,564 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940322841] [2025-03-17 20:55:24,564 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:24,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:24,616 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-17 20:55:24,705 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-17 20:55:24,706 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:24,706 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:25,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:25,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:25,271 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940322841] [2025-03-17 20:55:25,271 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [940322841] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:25,271 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:25,271 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-17 20:55:25,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741474806] [2025-03-17 20:55:25,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:25,272 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:25,272 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:25,272 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-17 20:55:25,272 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2025-03-17 20:55:25,272 INFO L87 Difference]: Start difference. First operand 428 states and 584 transitions. cyclomatic complexity: 160 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:25,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:25,561 INFO L93 Difference]: Finished difference Result 421 states and 574 transitions. [2025-03-17 20:55:25,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 421 states and 574 transitions. [2025-03-17 20:55:25,562 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 405 [2025-03-17 20:55:25,564 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 421 states to 421 states and 574 transitions. [2025-03-17 20:55:25,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 421 [2025-03-17 20:55:25,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 421 [2025-03-17 20:55:25,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 421 states and 574 transitions. [2025-03-17 20:55:25,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:25,566 INFO L218 hiAutomatonCegarLoop]: Abstraction has 421 states and 574 transitions. [2025-03-17 20:55:25,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 421 states and 574 transitions. [2025-03-17 20:55:25,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 421 to 419. [2025-03-17 20:55:25,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 419 states, 415 states have (on average 1.3614457831325302) internal successors, (565), 414 states have internal predecessors, (565), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:25,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 419 states to 419 states and 571 transitions. [2025-03-17 20:55:25,573 INFO L240 hiAutomatonCegarLoop]: Abstraction has 419 states and 571 transitions. [2025-03-17 20:55:25,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-17 20:55:25,574 INFO L432 stractBuchiCegarLoop]: Abstraction has 419 states and 571 transitions. [2025-03-17 20:55:25,574 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-17 20:55:25,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 419 states and 571 transitions. [2025-03-17 20:55:25,575 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 403 [2025-03-17 20:55:25,575 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:25,576 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:25,576 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:25,576 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:25,576 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:25,576 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:25,577 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:25,577 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 16 times [2025-03-17 20:55:25,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:25,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084942848] [2025-03-17 20:55:25,577 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 20:55:25,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:25,586 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-03-17 20:55:25,591 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:25,592 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 20:55:25,592 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:25,592 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:25,595 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:25,598 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:25,598 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:25,598 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:25,604 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:25,605 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:25,605 INFO L85 PathProgramCache]: Analyzing trace with hash 1069748031, now seen corresponding path program 1 times [2025-03-17 20:55:25,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:25,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6181741] [2025-03-17 20:55:25,605 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:25,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:25,634 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-17 20:55:25,650 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-17 20:55:25,650 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:25,650 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:25,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:25,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:25,812 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [6181741] [2025-03-17 20:55:25,812 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [6181741] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:25,812 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:25,813 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-17 20:55:25,813 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [138942616] [2025-03-17 20:55:25,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:25,813 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:25,813 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:25,813 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-17 20:55:25,813 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2025-03-17 20:55:25,814 INFO L87 Difference]: Start difference. First operand 419 states and 571 transitions. cyclomatic complexity: 156 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:26,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:26,171 INFO L93 Difference]: Finished difference Result 429 states and 583 transitions. [2025-03-17 20:55:26,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 429 states and 583 transitions. [2025-03-17 20:55:26,173 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 413 [2025-03-17 20:55:26,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 429 states to 429 states and 583 transitions. [2025-03-17 20:55:26,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 429 [2025-03-17 20:55:26,175 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 429 [2025-03-17 20:55:26,175 INFO L73 IsDeterministic]: Start isDeterministic. Operand 429 states and 583 transitions. [2025-03-17 20:55:26,176 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:26,176 INFO L218 hiAutomatonCegarLoop]: Abstraction has 429 states and 583 transitions. [2025-03-17 20:55:26,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 429 states and 583 transitions. [2025-03-17 20:55:26,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 429 to 422. [2025-03-17 20:55:26,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 422 states, 418 states have (on average 1.361244019138756) internal successors, (569), 417 states have internal predecessors, (569), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:26,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 422 states to 422 states and 575 transitions. [2025-03-17 20:55:26,181 INFO L240 hiAutomatonCegarLoop]: Abstraction has 422 states and 575 transitions. [2025-03-17 20:55:26,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-17 20:55:26,181 INFO L432 stractBuchiCegarLoop]: Abstraction has 422 states and 575 transitions. [2025-03-17 20:55:26,181 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-17 20:55:26,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 422 states and 575 transitions. [2025-03-17 20:55:26,183 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 406 [2025-03-17 20:55:26,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:26,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:26,183 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:26,183 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:26,184 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:26,184 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:26,184 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:26,184 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 17 times [2025-03-17 20:55:26,184 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:26,184 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467859219] [2025-03-17 20:55:26,185 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 20:55:26,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:26,191 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:26,193 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:26,193 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:55:26,193 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:26,193 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:26,195 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:26,198 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:26,198 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:26,198 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:26,203 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:26,204 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:26,204 INFO L85 PathProgramCache]: Analyzing trace with hash -124396444, now seen corresponding path program 1 times [2025-03-17 20:55:26,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:26,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795391295] [2025-03-17 20:55:26,204 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:26,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:26,230 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-17 20:55:26,290 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-17 20:55:26,290 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:26,290 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:26,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:26,472 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:26,472 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [795391295] [2025-03-17 20:55:26,472 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [795391295] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:26,472 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:26,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-17 20:55:26,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [387493927] [2025-03-17 20:55:26,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:26,472 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:26,472 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:26,472 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-17 20:55:26,473 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-17 20:55:26,473 INFO L87 Difference]: Start difference. First operand 422 states and 575 transitions. cyclomatic complexity: 157 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:26,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:26,957 INFO L93 Difference]: Finished difference Result 432 states and 587 transitions. [2025-03-17 20:55:26,957 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 432 states and 587 transitions. [2025-03-17 20:55:26,959 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 416 [2025-03-17 20:55:26,960 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 432 states to 432 states and 587 transitions. [2025-03-17 20:55:26,960 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 432 [2025-03-17 20:55:26,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 432 [2025-03-17 20:55:26,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 432 states and 587 transitions. [2025-03-17 20:55:26,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:26,962 INFO L218 hiAutomatonCegarLoop]: Abstraction has 432 states and 587 transitions. [2025-03-17 20:55:26,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432 states and 587 transitions. [2025-03-17 20:55:26,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432 to 422. [2025-03-17 20:55:26,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 422 states, 418 states have (on average 1.361244019138756) internal successors, (569), 417 states have internal predecessors, (569), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:26,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 422 states to 422 states and 575 transitions. [2025-03-17 20:55:26,970 INFO L240 hiAutomatonCegarLoop]: Abstraction has 422 states and 575 transitions. [2025-03-17 20:55:26,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 20:55:26,972 INFO L432 stractBuchiCegarLoop]: Abstraction has 422 states and 575 transitions. [2025-03-17 20:55:26,972 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-17 20:55:26,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 422 states and 575 transitions. [2025-03-17 20:55:26,973 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 406 [2025-03-17 20:55:26,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:26,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:26,974 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:26,974 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:26,974 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:26,974 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:26,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:26,975 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 18 times [2025-03-17 20:55:26,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:26,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676957157] [2025-03-17 20:55:26,975 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 20:55:26,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:26,982 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:26,984 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:26,984 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 20:55:26,984 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:26,984 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:26,987 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:26,988 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:26,988 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:26,988 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:26,996 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:26,999 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:26,999 INFO L85 PathProgramCache]: Analyzing trace with hash -1406700294, now seen corresponding path program 1 times [2025-03-17 20:55:26,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:26,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [135680689] [2025-03-17 20:55:26,999 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:26,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:27,025 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-17 20:55:27,096 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-17 20:55:27,096 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:27,096 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:27,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:27,483 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:27,483 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [135680689] [2025-03-17 20:55:27,483 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [135680689] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:27,483 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:27,483 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-17 20:55:27,483 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089704602] [2025-03-17 20:55:27,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:27,483 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:27,484 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:27,484 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-17 20:55:27,484 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2025-03-17 20:55:27,485 INFO L87 Difference]: Start difference. First operand 422 states and 575 transitions. cyclomatic complexity: 157 Second operand has 13 states, 13 states have (on average 6.153846153846154) internal successors, (80), 13 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:28,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:28,148 INFO L93 Difference]: Finished difference Result 451 states and 617 transitions. [2025-03-17 20:55:28,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 451 states and 617 transitions. [2025-03-17 20:55:28,150 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 435 [2025-03-17 20:55:28,151 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 451 states to 451 states and 617 transitions. [2025-03-17 20:55:28,151 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 451 [2025-03-17 20:55:28,152 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 451 [2025-03-17 20:55:28,152 INFO L73 IsDeterministic]: Start isDeterministic. Operand 451 states and 617 transitions. [2025-03-17 20:55:28,152 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:28,153 INFO L218 hiAutomatonCegarLoop]: Abstraction has 451 states and 617 transitions. [2025-03-17 20:55:28,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states and 617 transitions. [2025-03-17 20:55:28,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 430. [2025-03-17 20:55:28,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 426 states have (on average 1.3615023474178405) internal successors, (580), 425 states have internal predecessors, (580), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:28,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 586 transitions. [2025-03-17 20:55:28,159 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 586 transitions. [2025-03-17 20:55:28,159 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-17 20:55:28,159 INFO L432 stractBuchiCegarLoop]: Abstraction has 430 states and 586 transitions. [2025-03-17 20:55:28,159 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-17 20:55:28,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 586 transitions. [2025-03-17 20:55:28,160 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 414 [2025-03-17 20:55:28,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:28,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:28,161 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:28,161 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:28,161 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:28,161 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:28,162 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:28,162 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 19 times [2025-03-17 20:55:28,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:28,162 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312814569] [2025-03-17 20:55:28,162 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 20:55:28,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:28,170 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:28,171 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:28,172 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:28,172 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:28,172 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:28,174 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:28,175 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:28,175 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:28,175 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:28,180 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:28,181 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:28,181 INFO L85 PathProgramCache]: Analyzing trace with hash 2147381430, now seen corresponding path program 1 times [2025-03-17 20:55:28,181 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:28,181 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534853868] [2025-03-17 20:55:28,181 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:28,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:28,204 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-17 20:55:28,242 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-17 20:55:28,243 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:28,243 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:28,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:28,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:28,580 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534853868] [2025-03-17 20:55:28,580 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534853868] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:28,580 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:28,580 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-17 20:55:28,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2060428755] [2025-03-17 20:55:28,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:28,580 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:28,580 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:28,581 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-17 20:55:28,581 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-17 20:55:28,581 INFO L87 Difference]: Start difference. First operand 430 states and 586 transitions. cyclomatic complexity: 160 Second operand has 9 states, 9 states have (on average 8.88888888888889) internal successors, (80), 9 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:29,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:29,168 INFO L93 Difference]: Finished difference Result 437 states and 593 transitions. [2025-03-17 20:55:29,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 437 states and 593 transitions. [2025-03-17 20:55:29,169 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 421 [2025-03-17 20:55:29,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 437 states to 437 states and 593 transitions. [2025-03-17 20:55:29,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 437 [2025-03-17 20:55:29,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 437 [2025-03-17 20:55:29,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 437 states and 593 transitions. [2025-03-17 20:55:29,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:29,171 INFO L218 hiAutomatonCegarLoop]: Abstraction has 437 states and 593 transitions. [2025-03-17 20:55:29,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 437 states and 593 transitions. [2025-03-17 20:55:29,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 437 to 433. [2025-03-17 20:55:29,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 433 states, 429 states have (on average 1.358974358974359) internal successors, (583), 428 states have internal predecessors, (583), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:29,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 589 transitions. [2025-03-17 20:55:29,177 INFO L240 hiAutomatonCegarLoop]: Abstraction has 433 states and 589 transitions. [2025-03-17 20:55:29,177 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 20:55:29,177 INFO L432 stractBuchiCegarLoop]: Abstraction has 433 states and 589 transitions. [2025-03-17 20:55:29,177 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-17 20:55:29,177 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 433 states and 589 transitions. [2025-03-17 20:55:29,178 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 417 [2025-03-17 20:55:29,178 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:29,178 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:29,179 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:29,179 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:29,179 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:29,179 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:29,180 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:29,180 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 20 times [2025-03-17 20:55:29,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:29,180 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436471433] [2025-03-17 20:55:29,180 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:55:29,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:29,187 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:29,188 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:29,188 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:55:29,188 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:29,188 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:29,191 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:29,192 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:29,192 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:29,192 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:29,197 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:29,197 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:29,197 INFO L85 PathProgramCache]: Analyzing trace with hash 1338590505, now seen corresponding path program 1 times [2025-03-17 20:55:29,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:29,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455528511] [2025-03-17 20:55:29,198 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:29,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:29,221 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-17 20:55:29,234 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-17 20:55:29,234 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:29,234 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:29,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:29,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:29,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455528511] [2025-03-17 20:55:29,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [455528511] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:29,481 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:29,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-17 20:55:29,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974471953] [2025-03-17 20:55:29,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:29,481 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:29,481 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:29,482 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-17 20:55:29,482 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2025-03-17 20:55:29,482 INFO L87 Difference]: Start difference. First operand 433 states and 589 transitions. cyclomatic complexity: 160 Second operand has 10 states, 10 states have (on average 8.0) internal successors, (80), 10 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:30,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:30,034 INFO L93 Difference]: Finished difference Result 449 states and 610 transitions. [2025-03-17 20:55:30,034 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 610 transitions. [2025-03-17 20:55:30,035 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 433 [2025-03-17 20:55:30,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 610 transitions. [2025-03-17 20:55:30,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2025-03-17 20:55:30,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2025-03-17 20:55:30,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 610 transitions. [2025-03-17 20:55:30,038 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:30,038 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 610 transitions. [2025-03-17 20:55:30,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 610 transitions. [2025-03-17 20:55:30,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 443. [2025-03-17 20:55:30,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 443 states, 439 states have (on average 1.355353075170843) internal successors, (595), 438 states have internal predecessors, (595), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:30,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 443 states to 443 states and 601 transitions. [2025-03-17 20:55:30,044 INFO L240 hiAutomatonCegarLoop]: Abstraction has 443 states and 601 transitions. [2025-03-17 20:55:30,046 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 20:55:30,046 INFO L432 stractBuchiCegarLoop]: Abstraction has 443 states and 601 transitions. [2025-03-17 20:55:30,046 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-17 20:55:30,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 443 states and 601 transitions. [2025-03-17 20:55:30,047 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 427 [2025-03-17 20:55:30,048 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:30,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:30,048 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:30,048 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:30,048 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:30,049 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:30,049 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:30,049 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 21 times [2025-03-17 20:55:30,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:30,050 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522661721] [2025-03-17 20:55:30,050 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:55:30,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:30,059 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:30,060 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:30,061 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:55:30,061 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:30,062 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:30,064 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:30,066 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:30,066 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:30,066 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:30,071 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:30,072 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:30,072 INFO L85 PathProgramCache]: Analyzing trace with hash -1320149852, now seen corresponding path program 1 times [2025-03-17 20:55:30,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:30,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12807775] [2025-03-17 20:55:30,072 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:30,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:30,105 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-17 20:55:30,171 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-17 20:55:30,171 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:30,171 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:30,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:30,354 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:30,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12807775] [2025-03-17 20:55:30,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [12807775] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:30,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:30,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-17 20:55:30,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2052291370] [2025-03-17 20:55:30,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:30,354 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:30,354 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:30,354 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-17 20:55:30,355 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2025-03-17 20:55:30,355 INFO L87 Difference]: Start difference. First operand 443 states and 601 transitions. cyclomatic complexity: 162 Second operand has 10 states, 10 states have (on average 8.0) internal successors, (80), 10 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:30,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:30,873 INFO L93 Difference]: Finished difference Result 456 states and 619 transitions. [2025-03-17 20:55:30,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 456 states and 619 transitions. [2025-03-17 20:55:30,874 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 440 [2025-03-17 20:55:30,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 456 states to 456 states and 619 transitions. [2025-03-17 20:55:30,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 456 [2025-03-17 20:55:30,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 456 [2025-03-17 20:55:30,876 INFO L73 IsDeterministic]: Start isDeterministic. Operand 456 states and 619 transitions. [2025-03-17 20:55:30,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:30,876 INFO L218 hiAutomatonCegarLoop]: Abstraction has 456 states and 619 transitions. [2025-03-17 20:55:30,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 456 states and 619 transitions. [2025-03-17 20:55:30,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 456 to 443. [2025-03-17 20:55:30,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 443 states, 439 states have (on average 1.355353075170843) internal successors, (595), 438 states have internal predecessors, (595), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:30,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 443 states to 443 states and 601 transitions. [2025-03-17 20:55:30,882 INFO L240 hiAutomatonCegarLoop]: Abstraction has 443 states and 601 transitions. [2025-03-17 20:55:30,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 20:55:30,882 INFO L432 stractBuchiCegarLoop]: Abstraction has 443 states and 601 transitions. [2025-03-17 20:55:30,883 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-03-17 20:55:30,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 443 states and 601 transitions. [2025-03-17 20:55:30,883 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 427 [2025-03-17 20:55:30,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:30,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:30,885 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:30,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:30,885 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:30,885 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:30,886 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:30,886 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 22 times [2025-03-17 20:55:30,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:30,886 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641050064] [2025-03-17 20:55:30,886 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 20:55:30,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:30,893 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-03-17 20:55:30,895 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:30,895 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 20:55:30,895 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:30,895 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:30,897 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:30,898 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:30,898 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:30,898 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:30,902 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:30,903 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:30,903 INFO L85 PathProgramCache]: Analyzing trace with hash 962219844, now seen corresponding path program 1 times [2025-03-17 20:55:30,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:30,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7245426] [2025-03-17 20:55:30,903 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:30,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:30,927 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-17 20:55:30,975 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-17 20:55:30,975 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:30,975 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:31,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:31,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:31,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [7245426] [2025-03-17 20:55:31,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [7245426] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:31,157 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:31,157 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-17 20:55:31,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1091709615] [2025-03-17 20:55:31,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:31,159 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:31,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:31,159 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-17 20:55:31,159 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-17 20:55:31,159 INFO L87 Difference]: Start difference. First operand 443 states and 601 transitions. cyclomatic complexity: 162 Second operand has 7 states, 7 states have (on average 11.428571428571429) internal successors, (80), 7 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:31,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:31,491 INFO L93 Difference]: Finished difference Result 448 states and 605 transitions. [2025-03-17 20:55:31,491 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 448 states and 605 transitions. [2025-03-17 20:55:31,492 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 432 [2025-03-17 20:55:31,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 448 states to 448 states and 605 transitions. [2025-03-17 20:55:31,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 448 [2025-03-17 20:55:31,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 448 [2025-03-17 20:55:31,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 448 states and 605 transitions. [2025-03-17 20:55:31,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:31,495 INFO L218 hiAutomatonCegarLoop]: Abstraction has 448 states and 605 transitions. [2025-03-17 20:55:31,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 448 states and 605 transitions. [2025-03-17 20:55:31,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 448 to 443. [2025-03-17 20:55:31,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 443 states, 439 states have (on average 1.3530751708428246) internal successors, (594), 438 states have internal predecessors, (594), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:31,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 443 states to 443 states and 600 transitions. [2025-03-17 20:55:31,499 INFO L240 hiAutomatonCegarLoop]: Abstraction has 443 states and 600 transitions. [2025-03-17 20:55:31,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-17 20:55:31,500 INFO L432 stractBuchiCegarLoop]: Abstraction has 443 states and 600 transitions. [2025-03-17 20:55:31,500 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-03-17 20:55:31,500 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 443 states and 600 transitions. [2025-03-17 20:55:31,501 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 427 [2025-03-17 20:55:31,501 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:31,501 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:31,502 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:31,502 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:31,502 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:31,502 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:31,502 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:31,502 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 23 times [2025-03-17 20:55:31,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:31,503 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765527515] [2025-03-17 20:55:31,503 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 20:55:31,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:31,509 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:31,510 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:31,510 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:55:31,510 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:31,510 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:31,512 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:31,513 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:31,514 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:31,514 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:31,518 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:31,518 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:31,518 INFO L85 PathProgramCache]: Analyzing trace with hash -11316600, now seen corresponding path program 1 times [2025-03-17 20:55:31,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:31,519 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330280118] [2025-03-17 20:55:31,519 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:31,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:31,542 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-17 20:55:31,584 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-17 20:55:31,585 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:31,585 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:31,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:31,724 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:31,725 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [330280118] [2025-03-17 20:55:31,725 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [330280118] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:31,725 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:31,725 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-17 20:55:31,725 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1849130812] [2025-03-17 20:55:31,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:31,726 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:31,726 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:31,726 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-17 20:55:31,726 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-17 20:55:31,726 INFO L87 Difference]: Start difference. First operand 443 states and 600 transitions. cyclomatic complexity: 161 Second operand has 7 states, 7 states have (on average 11.428571428571429) internal successors, (80), 7 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:32,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:32,039 INFO L93 Difference]: Finished difference Result 446 states and 603 transitions. [2025-03-17 20:55:32,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 446 states and 603 transitions. [2025-03-17 20:55:32,041 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 430 [2025-03-17 20:55:32,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 446 states to 446 states and 603 transitions. [2025-03-17 20:55:32,042 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 446 [2025-03-17 20:55:32,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 446 [2025-03-17 20:55:32,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 446 states and 603 transitions. [2025-03-17 20:55:32,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:32,043 INFO L218 hiAutomatonCegarLoop]: Abstraction has 446 states and 603 transitions. [2025-03-17 20:55:32,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 446 states and 603 transitions. [2025-03-17 20:55:32,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 446 to 446. [2025-03-17 20:55:32,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 446 states, 442 states have (on average 1.3506787330316743) internal successors, (597), 441 states have internal predecessors, (597), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:32,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 603 transitions. [2025-03-17 20:55:32,048 INFO L240 hiAutomatonCegarLoop]: Abstraction has 446 states and 603 transitions. [2025-03-17 20:55:32,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-17 20:55:32,048 INFO L432 stractBuchiCegarLoop]: Abstraction has 446 states and 603 transitions. [2025-03-17 20:55:32,049 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-03-17 20:55:32,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 446 states and 603 transitions. [2025-03-17 20:55:32,050 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 430 [2025-03-17 20:55:32,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:32,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:32,050 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:32,050 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:32,050 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:32,051 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise80#1;assume main_#t~bitwise80#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:32,051 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:32,051 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 24 times [2025-03-17 20:55:32,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:32,051 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583202521] [2025-03-17 20:55:32,051 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 20:55:32,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:32,059 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:32,061 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:32,061 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 20:55:32,061 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:32,062 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:32,064 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:32,065 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:32,065 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:32,065 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:32,070 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:32,071 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:32,071 INFO L85 PathProgramCache]: Analyzing trace with hash 1914930074, now seen corresponding path program 1 times [2025-03-17 20:55:32,071 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:32,071 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246801422] [2025-03-17 20:55:32,071 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:32,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:32,094 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 20:55:32,254 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 20:55:32,254 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:32,254 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:32,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:32,761 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:32,761 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246801422] [2025-03-17 20:55:32,761 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246801422] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:32,761 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:32,761 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2025-03-17 20:55:32,761 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719266282] [2025-03-17 20:55:32,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:32,761 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:32,761 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:32,762 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2025-03-17 20:55:32,762 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=265, Unknown=0, NotChecked=0, Total=306 [2025-03-17 20:55:32,762 INFO L87 Difference]: Start difference. First operand 446 states and 603 transitions. cyclomatic complexity: 161 Second operand has 18 states, 18 states have (on average 4.5) internal successors, (81), 18 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:34,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:34,259 INFO L93 Difference]: Finished difference Result 539 states and 734 transitions. [2025-03-17 20:55:34,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 539 states and 734 transitions. [2025-03-17 20:55:34,260 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 523 [2025-03-17 20:55:34,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 539 states to 539 states and 734 transitions. [2025-03-17 20:55:34,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 539 [2025-03-17 20:55:34,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 539 [2025-03-17 20:55:34,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 539 states and 734 transitions. [2025-03-17 20:55:34,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:34,265 INFO L218 hiAutomatonCegarLoop]: Abstraction has 539 states and 734 transitions. [2025-03-17 20:55:34,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 539 states and 734 transitions. [2025-03-17 20:55:34,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 539 to 459. [2025-03-17 20:55:34,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 459 states, 455 states have (on average 1.3516483516483517) internal successors, (615), 454 states have internal predecessors, (615), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:34,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 621 transitions. [2025-03-17 20:55:34,304 INFO L240 hiAutomatonCegarLoop]: Abstraction has 459 states and 621 transitions. [2025-03-17 20:55:34,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2025-03-17 20:55:34,313 INFO L432 stractBuchiCegarLoop]: Abstraction has 459 states and 621 transitions. [2025-03-17 20:55:34,313 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-03-17 20:55:34,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 459 states and 621 transitions. [2025-03-17 20:55:34,314 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 443 [2025-03-17 20:55:34,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:34,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:34,315 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:34,315 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:34,315 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:34,315 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise83#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:34,316 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:34,316 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 25 times [2025-03-17 20:55:34,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:34,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949729110] [2025-03-17 20:55:34,316 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 20:55:34,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:34,325 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:34,327 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:34,327 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:34,328 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:34,328 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:34,330 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:34,332 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:34,332 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:34,332 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:34,338 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:34,339 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:34,339 INFO L85 PathProgramCache]: Analyzing trace with hash -217134400, now seen corresponding path program 1 times [2025-03-17 20:55:34,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:34,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288073779] [2025-03-17 20:55:34,339 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:34,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:34,405 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 20:55:34,639 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 20:55:34,640 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:34,640 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:35,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:35,293 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:35,294 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288073779] [2025-03-17 20:55:35,294 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1288073779] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:35,294 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:35,295 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2025-03-17 20:55:35,295 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1864619882] [2025-03-17 20:55:35,295 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:35,296 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:35,296 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:35,296 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2025-03-17 20:55:35,296 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=237, Unknown=0, NotChecked=0, Total=272 [2025-03-17 20:55:35,296 INFO L87 Difference]: Start difference. First operand 459 states and 621 transitions. cyclomatic complexity: 166 Second operand has 17 states, 17 states have (on average 4.764705882352941) internal successors, (81), 17 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:36,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:36,320 INFO L93 Difference]: Finished difference Result 475 states and 646 transitions. [2025-03-17 20:55:36,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 475 states and 646 transitions. [2025-03-17 20:55:36,322 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 459 [2025-03-17 20:55:36,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 475 states to 475 states and 646 transitions. [2025-03-17 20:55:36,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 475 [2025-03-17 20:55:36,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 475 [2025-03-17 20:55:36,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 475 states and 646 transitions. [2025-03-17 20:55:36,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:36,325 INFO L218 hiAutomatonCegarLoop]: Abstraction has 475 states and 646 transitions. [2025-03-17 20:55:36,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 475 states and 646 transitions. [2025-03-17 20:55:36,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 475 to 464. [2025-03-17 20:55:36,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 464 states, 460 states have (on average 1.3521739130434782) internal successors, (622), 459 states have internal predecessors, (622), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:36,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 628 transitions. [2025-03-17 20:55:36,329 INFO L240 hiAutomatonCegarLoop]: Abstraction has 464 states and 628 transitions. [2025-03-17 20:55:36,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2025-03-17 20:55:36,330 INFO L432 stractBuchiCegarLoop]: Abstraction has 464 states and 628 transitions. [2025-03-17 20:55:36,330 INFO L338 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-03-17 20:55:36,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 464 states and 628 transitions. [2025-03-17 20:55:36,332 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 448 [2025-03-17 20:55:36,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:36,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:36,332 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:36,332 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:36,333 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:36,333 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:36,333 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:36,333 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 26 times [2025-03-17 20:55:36,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:36,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1126766205] [2025-03-17 20:55:36,334 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:55:36,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:36,341 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:36,343 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:36,343 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:55:36,343 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:36,343 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:36,345 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:36,346 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:36,346 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:36,346 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:36,350 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:36,351 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:36,351 INFO L85 PathProgramCache]: Analyzing trace with hash 1878103758, now seen corresponding path program 1 times [2025-03-17 20:55:36,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:36,351 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076571710] [2025-03-17 20:55:36,351 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:36,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:36,374 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 20:55:36,415 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 20:55:36,415 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:36,415 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:36,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:36,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:36,737 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1076571710] [2025-03-17 20:55:36,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1076571710] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:36,737 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:36,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2025-03-17 20:55:36,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [95985159] [2025-03-17 20:55:36,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:36,737 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:36,737 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:36,738 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-17 20:55:36,738 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2025-03-17 20:55:36,738 INFO L87 Difference]: Start difference. First operand 464 states and 628 transitions. cyclomatic complexity: 168 Second operand has 8 states, 8 states have (on average 10.125) internal successors, (81), 8 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:48,860 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 12.00s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2025-03-17 20:55:48,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:48,973 INFO L93 Difference]: Finished difference Result 543 states and 736 transitions. [2025-03-17 20:55:48,973 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 543 states and 736 transitions. [2025-03-17 20:55:48,974 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 527 [2025-03-17 20:55:48,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 543 states to 543 states and 736 transitions. [2025-03-17 20:55:48,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 543 [2025-03-17 20:55:48,976 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 543 [2025-03-17 20:55:48,976 INFO L73 IsDeterministic]: Start isDeterministic. Operand 543 states and 736 transitions. [2025-03-17 20:55:48,977 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:48,977 INFO L218 hiAutomatonCegarLoop]: Abstraction has 543 states and 736 transitions. [2025-03-17 20:55:48,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states and 736 transitions. [2025-03-17 20:55:48,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 470. [2025-03-17 20:55:48,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 470 states, 466 states have (on average 1.351931330472103) internal successors, (630), 465 states have internal predecessors, (630), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:48,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 636 transitions. [2025-03-17 20:55:48,981 INFO L240 hiAutomatonCegarLoop]: Abstraction has 470 states and 636 transitions. [2025-03-17 20:55:48,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-17 20:55:48,983 INFO L432 stractBuchiCegarLoop]: Abstraction has 470 states and 636 transitions. [2025-03-17 20:55:48,983 INFO L338 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2025-03-17 20:55:48,983 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 470 states and 636 transitions. [2025-03-17 20:55:48,984 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 454 [2025-03-17 20:55:48,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:48,984 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:48,984 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:48,984 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:48,984 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:48,986 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise82#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:48,987 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:48,987 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 27 times [2025-03-17 20:55:48,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:48,988 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709911604] [2025-03-17 20:55:48,988 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 20:55:48,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:48,994 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:48,996 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:48,996 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 20:55:48,996 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:48,996 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:48,998 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:48,999 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:48,999 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:48,999 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:49,004 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:49,004 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:49,005 INFO L85 PathProgramCache]: Analyzing trace with hash -1898119257, now seen corresponding path program 1 times [2025-03-17 20:55:49,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:49,005 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032323016] [2025-03-17 20:55:49,005 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:49,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:49,032 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 20:55:49,097 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 20:55:49,097 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:49,097 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:49,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:49,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:49,378 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032323016] [2025-03-17 20:55:49,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2032323016] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:49,379 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:49,379 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-17 20:55:49,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1082466024] [2025-03-17 20:55:49,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:49,379 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:49,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:49,379 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-17 20:55:49,380 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-17 20:55:49,380 INFO L87 Difference]: Start difference. First operand 470 states and 636 transitions. cyclomatic complexity: 170 Second operand has 13 states, 13 states have (on average 6.230769230769231) internal successors, (81), 13 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:49,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:49,886 INFO L93 Difference]: Finished difference Result 479 states and 648 transitions. [2025-03-17 20:55:49,886 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 479 states and 648 transitions. [2025-03-17 20:55:49,887 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 463 [2025-03-17 20:55:49,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 479 states to 479 states and 648 transitions. [2025-03-17 20:55:49,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 479 [2025-03-17 20:55:49,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 479 [2025-03-17 20:55:49,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 479 states and 648 transitions. [2025-03-17 20:55:49,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:49,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 479 states and 648 transitions. [2025-03-17 20:55:49,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 479 states and 648 transitions. [2025-03-17 20:55:49,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 479 to 475. [2025-03-17 20:55:49,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 475 states, 471 states have (on average 1.3524416135881103) internal successors, (637), 470 states have internal predecessors, (637), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:49,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 475 states to 475 states and 643 transitions. [2025-03-17 20:55:49,893 INFO L240 hiAutomatonCegarLoop]: Abstraction has 475 states and 643 transitions. [2025-03-17 20:55:49,894 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-17 20:55:49,894 INFO L432 stractBuchiCegarLoop]: Abstraction has 475 states and 643 transitions. [2025-03-17 20:55:49,894 INFO L338 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2025-03-17 20:55:49,894 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 475 states and 643 transitions. [2025-03-17 20:55:49,895 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 459 [2025-03-17 20:55:49,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:49,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:49,895 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:49,895 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:49,896 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:49,896 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise80#1;assume main_#t~bitwise80#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:49,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:49,896 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 28 times [2025-03-17 20:55:49,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:49,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132355668] [2025-03-17 20:55:49,896 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 20:55:49,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:49,903 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-03-17 20:55:49,904 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:49,904 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 20:55:49,904 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:49,904 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:49,906 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:49,906 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:49,906 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:49,907 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:49,911 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:49,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:49,911 INFO L85 PathProgramCache]: Analyzing trace with hash -1682752121, now seen corresponding path program 1 times [2025-03-17 20:55:49,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:49,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320539086] [2025-03-17 20:55:49,911 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:49,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:49,934 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 20:55:49,959 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 20:55:49,959 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:49,959 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:50,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:50,325 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:50,325 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320539086] [2025-03-17 20:55:50,325 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320539086] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:50,325 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:50,325 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-17 20:55:50,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [631934285] [2025-03-17 20:55:50,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:50,325 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:50,325 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:50,325 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-17 20:55:50,325 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-03-17 20:55:50,326 INFO L87 Difference]: Start difference. First operand 475 states and 643 transitions. cyclomatic complexity: 172 Second operand has 10 states, 10 states have (on average 8.1) internal successors, (81), 10 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:50,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:50,898 INFO L93 Difference]: Finished difference Result 487 states and 660 transitions. [2025-03-17 20:55:50,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 487 states and 660 transitions. [2025-03-17 20:55:50,899 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 471 [2025-03-17 20:55:50,900 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 487 states to 487 states and 660 transitions. [2025-03-17 20:55:50,900 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 487 [2025-03-17 20:55:50,901 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 487 [2025-03-17 20:55:50,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 487 states and 660 transitions. [2025-03-17 20:55:50,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:50,901 INFO L218 hiAutomatonCegarLoop]: Abstraction has 487 states and 660 transitions. [2025-03-17 20:55:50,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 487 states and 660 transitions. [2025-03-17 20:55:50,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 487 to 479. [2025-03-17 20:55:50,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 479 states, 475 states have (on average 1.351578947368421) internal successors, (642), 474 states have internal predecessors, (642), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:50,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 479 states to 479 states and 648 transitions. [2025-03-17 20:55:50,906 INFO L240 hiAutomatonCegarLoop]: Abstraction has 479 states and 648 transitions. [2025-03-17 20:55:50,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 20:55:50,907 INFO L432 stractBuchiCegarLoop]: Abstraction has 479 states and 648 transitions. [2025-03-17 20:55:50,907 INFO L338 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2025-03-17 20:55:50,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 479 states and 648 transitions. [2025-03-17 20:55:50,908 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 463 [2025-03-17 20:55:50,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:50,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:50,908 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:50,908 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:50,908 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:50,909 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise80#1;assume main_#t~bitwise80#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:50,909 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:50,909 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 29 times [2025-03-17 20:55:50,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:50,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632136129] [2025-03-17 20:55:50,909 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 20:55:50,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:50,916 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:50,917 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:50,917 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:55:50,917 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:50,917 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:50,919 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:50,919 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:50,919 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:50,919 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:50,923 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:50,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:50,924 INFO L85 PathProgramCache]: Analyzing trace with hash 1795642732, now seen corresponding path program 1 times [2025-03-17 20:55:50,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:50,924 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29501197] [2025-03-17 20:55:50,924 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:50,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:50,945 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 20:55:51,036 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 20:55:51,036 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:51,036 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:51,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:51,300 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:51,300 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [29501197] [2025-03-17 20:55:51,300 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [29501197] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:51,300 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:51,300 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-17 20:55:51,300 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [848334817] [2025-03-17 20:55:51,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:51,301 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:51,301 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:51,301 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-17 20:55:51,301 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-03-17 20:55:51,301 INFO L87 Difference]: Start difference. First operand 479 states and 648 transitions. cyclomatic complexity: 173 Second operand has 10 states, 10 states have (on average 8.1) internal successors, (81), 10 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:54,171 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.51s for a HTC check with result VALID. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2025-03-17 20:55:54,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:54,618 INFO L93 Difference]: Finished difference Result 484 states and 653 transitions. [2025-03-17 20:55:54,618 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 484 states and 653 transitions. [2025-03-17 20:55:54,619 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 468 [2025-03-17 20:55:54,620 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 484 states to 484 states and 653 transitions. [2025-03-17 20:55:54,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 484 [2025-03-17 20:55:54,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 484 [2025-03-17 20:55:54,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 484 states and 653 transitions. [2025-03-17 20:55:54,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:54,623 INFO L218 hiAutomatonCegarLoop]: Abstraction has 484 states and 653 transitions. [2025-03-17 20:55:54,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 484 states and 653 transitions. [2025-03-17 20:55:54,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 484 to 477. [2025-03-17 20:55:54,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 477 states, 473 states have (on average 1.3509513742071881) internal successors, (639), 472 states have internal predecessors, (639), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:54,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 477 states and 645 transitions. [2025-03-17 20:55:54,629 INFO L240 hiAutomatonCegarLoop]: Abstraction has 477 states and 645 transitions. [2025-03-17 20:55:54,630 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 20:55:54,630 INFO L432 stractBuchiCegarLoop]: Abstraction has 477 states and 645 transitions. [2025-03-17 20:55:54,630 INFO L338 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2025-03-17 20:55:54,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 477 states and 645 transitions. [2025-03-17 20:55:54,631 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 461 [2025-03-17 20:55:54,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:54,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:54,632 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:54,632 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:54,632 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:54,632 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise82#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:54,632 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:54,632 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 30 times [2025-03-17 20:55:54,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:54,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323349766] [2025-03-17 20:55:54,633 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 20:55:54,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:54,639 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:54,640 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:54,640 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 20:55:54,640 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:54,640 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:54,641 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:54,642 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:54,642 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:54,642 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:54,647 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:54,647 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:54,647 INFO L85 PathProgramCache]: Analyzing trace with hash 784944445, now seen corresponding path program 1 times [2025-03-17 20:55:54,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:54,647 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343212958] [2025-03-17 20:55:54,647 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:54,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:54,671 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 20:55:54,691 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 20:55:54,691 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:54,691 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:55,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:55,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:55,011 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1343212958] [2025-03-17 20:55:55,011 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1343212958] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:55,011 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:55,011 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2025-03-17 20:55:55,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164977364] [2025-03-17 20:55:55,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:55,011 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:55,012 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:55,012 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-03-17 20:55:55,012 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2025-03-17 20:55:55,012 INFO L87 Difference]: Start difference. First operand 477 states and 645 transitions. cyclomatic complexity: 172 Second operand has 11 states, 11 states have (on average 7.363636363636363) internal successors, (81), 11 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:55,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:55,556 INFO L93 Difference]: Finished difference Result 493 states and 666 transitions. [2025-03-17 20:55:55,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 493 states and 666 transitions. [2025-03-17 20:55:55,557 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 477 [2025-03-17 20:55:55,559 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 493 states to 493 states and 666 transitions. [2025-03-17 20:55:55,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 493 [2025-03-17 20:55:55,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 493 [2025-03-17 20:55:55,559 INFO L73 IsDeterministic]: Start isDeterministic. Operand 493 states and 666 transitions. [2025-03-17 20:55:55,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:55,559 INFO L218 hiAutomatonCegarLoop]: Abstraction has 493 states and 666 transitions. [2025-03-17 20:55:55,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 493 states and 666 transitions. [2025-03-17 20:55:55,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 493 to 483. [2025-03-17 20:55:55,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 483 states, 479 states have (on average 1.3486430062630481) internal successors, (646), 478 states have internal predecessors, (646), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:55,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 483 states to 483 states and 652 transitions. [2025-03-17 20:55:55,563 INFO L240 hiAutomatonCegarLoop]: Abstraction has 483 states and 652 transitions. [2025-03-17 20:55:55,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 20:55:55,564 INFO L432 stractBuchiCegarLoop]: Abstraction has 483 states and 652 transitions. [2025-03-17 20:55:55,564 INFO L338 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2025-03-17 20:55:55,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 483 states and 652 transitions. [2025-03-17 20:55:55,564 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 467 [2025-03-17 20:55:55,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:55,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:55,565 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:55,565 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:55,565 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:55,566 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:55,566 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:55,566 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 31 times [2025-03-17 20:55:55,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:55,567 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1727968940] [2025-03-17 20:55:55,567 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 20:55:55,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:55,574 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:55,575 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:55,576 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:55,576 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:55,576 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:55,577 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:55,579 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:55,579 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:55,580 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:55,584 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:55,584 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:55,584 INFO L85 PathProgramCache]: Analyzing trace with hash 1888277607, now seen corresponding path program 1 times [2025-03-17 20:55:55,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:55,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669009821] [2025-03-17 20:55:55,584 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:55,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:55,605 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 20:55:55,633 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 20:55:55,634 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:55,634 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:55:55,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 20:55:55,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 20:55:55,788 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669009821] [2025-03-17 20:55:55,788 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669009821] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 20:55:55,789 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 20:55:55,789 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-17 20:55:55,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696946239] [2025-03-17 20:55:55,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 20:55:55,789 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 20:55:55,789 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 20:55:55,789 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-17 20:55:55,789 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-17 20:55:55,789 INFO L87 Difference]: Start difference. First operand 483 states and 652 transitions. cyclomatic complexity: 173 Second operand has 9 states, 9 states have (on average 9.0) internal successors, (81), 9 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 20:55:56,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 20:55:56,222 INFO L93 Difference]: Finished difference Result 488 states and 658 transitions. [2025-03-17 20:55:56,222 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 488 states and 658 transitions. [2025-03-17 20:55:56,223 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 472 [2025-03-17 20:55:56,224 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 488 states to 488 states and 658 transitions. [2025-03-17 20:55:56,224 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 488 [2025-03-17 20:55:56,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 488 [2025-03-17 20:55:56,225 INFO L73 IsDeterministic]: Start isDeterministic. Operand 488 states and 658 transitions. [2025-03-17 20:55:56,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 20:55:56,226 INFO L218 hiAutomatonCegarLoop]: Abstraction has 488 states and 658 transitions. [2025-03-17 20:55:56,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states and 658 transitions. [2025-03-17 20:55:56,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 486. [2025-03-17 20:55:56,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 486 states, 482 states have (on average 1.3485477178423237) internal successors, (650), 481 states have internal predecessors, (650), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 20:55:56,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 486 states and 656 transitions. [2025-03-17 20:55:56,230 INFO L240 hiAutomatonCegarLoop]: Abstraction has 486 states and 656 transitions. [2025-03-17 20:55:56,230 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 20:55:56,231 INFO L432 stractBuchiCegarLoop]: Abstraction has 486 states and 656 transitions. [2025-03-17 20:55:56,231 INFO L338 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2025-03-17 20:55:56,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 486 states and 656 transitions. [2025-03-17 20:55:56,232 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 470 [2025-03-17 20:55:56,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 20:55:56,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 20:55:56,232 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 20:55:56,232 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 20:55:56,232 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 20:55:56,232 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 20:55:56,233 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:56,233 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 32 times [2025-03-17 20:55:56,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:56,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1582465955] [2025-03-17 20:55:56,233 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 20:55:56,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:56,239 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:56,240 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:56,240 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 20:55:56,240 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:56,240 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 20:55:56,242 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 20:55:56,243 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 20:55:56,243 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:56,243 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 20:55:56,248 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 20:55:56,248 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 20:55:56,248 INFO L85 PathProgramCache]: Analyzing trace with hash 1926042939, now seen corresponding path program 1 times [2025-03-17 20:55:56,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 20:55:56,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154773179] [2025-03-17 20:55:56,248 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 20:55:56,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 20:55:56,270 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 20:55:56,318 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 20:55:56,318 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 20:55:56,318 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 20:56:08,575 WARN L286 SmtUtils]: Spent 12.00s on a formula simplification that was a NOOP. DAG size: 32 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-03-17 20:56:20,584 WARN L286 SmtUtils]: Spent 12.00s on a formula simplification that was a NOOP. DAG size: 10 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-03-17 20:56:32,718 WARN L286 SmtUtils]: Spent 12.12s on a formula simplification that was a NOOP. DAG size: 39 (called from [L 388] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate)