./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test6-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8fc3dc66 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test6-2.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1d2a98d270a821b4275b6b35f502458543f3a892fcdda158c69925a18d34f6cf --- Real Ultimate output --- This is Ultimate 0.3.0-?-8fc3dc6-m [2025-03-17 21:09:17,853 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-17 21:09:17,906 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-17 21:09:17,910 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-17 21:09:17,910 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-17 21:09:17,910 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-17 21:09:17,930 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-17 21:09:17,931 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-17 21:09:17,931 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-17 21:09:17,931 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-17 21:09:17,932 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-17 21:09:17,933 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-17 21:09:17,933 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-17 21:09:17,933 INFO L153 SettingsManager]: * Use SBE=true [2025-03-17 21:09:17,933 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-17 21:09:17,933 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-17 21:09:17,933 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-17 21:09:17,933 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-17 21:09:17,933 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-17 21:09:17,933 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-17 21:09:17,934 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-17 21:09:17,934 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-17 21:09:17,934 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-17 21:09:17,934 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-17 21:09:17,934 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-17 21:09:17,934 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-17 21:09:17,934 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-17 21:09:17,934 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-17 21:09:17,934 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-17 21:09:17,934 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-17 21:09:17,935 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-17 21:09:17,935 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-17 21:09:17,935 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-17 21:09:17,935 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-17 21:09:17,935 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-17 21:09:17,935 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-17 21:09:17,935 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-17 21:09:17,935 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-17 21:09:17,935 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-17 21:09:17,935 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-17 21:09:17,936 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1d2a98d270a821b4275b6b35f502458543f3a892fcdda158c69925a18d34f6cf [2025-03-17 21:09:18,299 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-17 21:09:18,308 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-17 21:09:18,310 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-17 21:09:18,311 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-17 21:09:18,311 INFO L274 PluginConnector]: CDTParser initialized [2025-03-17 21:09:18,312 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test6-2.i [2025-03-17 21:09:19,400 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ab66eb3d2/359eef893cd94c6584c167acd8e7818e/FLAG74cd4f685 [2025-03-17 21:09:19,737 INFO L384 CDTParser]: Found 1 translation units. [2025-03-17 21:09:19,739 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test6-2.i [2025-03-17 21:09:19,752 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ab66eb3d2/359eef893cd94c6584c167acd8e7818e/FLAG74cd4f685 [2025-03-17 21:09:19,762 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ab66eb3d2/359eef893cd94c6584c167acd8e7818e [2025-03-17 21:09:19,764 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-17 21:09:19,765 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-17 21:09:19,765 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-17 21:09:19,765 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-17 21:09:19,768 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-17 21:09:19,769 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 09:09:19" (1/1) ... [2025-03-17 21:09:19,769 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@203e2983 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:19, skipping insertion in model container [2025-03-17 21:09:19,769 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 09:09:19" (1/1) ... [2025-03-17 21:09:19,802 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-17 21:09:20,177 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 21:09:20,191 INFO L200 MainTranslator]: Completed pre-run [2025-03-17 21:09:20,285 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 21:09:20,324 INFO L204 MainTranslator]: Completed translation [2025-03-17 21:09:20,324 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20 WrapperNode [2025-03-17 21:09:20,324 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-17 21:09:20,325 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-17 21:09:20,325 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-17 21:09:20,325 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-17 21:09:20,329 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (1/1) ... [2025-03-17 21:09:20,351 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (1/1) ... [2025-03-17 21:09:20,394 INFO L138 Inliner]: procedures = 282, calls = 353, calls flagged for inlining = 25, calls inlined = 37, statements flattened = 1756 [2025-03-17 21:09:20,395 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-17 21:09:20,395 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-17 21:09:20,396 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-17 21:09:20,396 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-17 21:09:20,402 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (1/1) ... [2025-03-17 21:09:20,403 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (1/1) ... [2025-03-17 21:09:20,416 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (1/1) ... [2025-03-17 21:09:20,504 INFO L175 MemorySlicer]: Split 326 memory accesses to 4 slices as follows [2, 271, 19, 34]. 83 percent of accesses are in the largest equivalence class. The 12 initializations are split as follows [2, 0, 10, 0]. The 65 writes are split as follows [0, 58, 3, 4]. [2025-03-17 21:09:20,505 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (1/1) ... [2025-03-17 21:09:20,505 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (1/1) ... [2025-03-17 21:09:20,551 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (1/1) ... [2025-03-17 21:09:20,555 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (1/1) ... [2025-03-17 21:09:20,564 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (1/1) ... [2025-03-17 21:09:20,570 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (1/1) ... [2025-03-17 21:09:20,579 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-17 21:09:20,580 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-17 21:09:20,580 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-17 21:09:20,580 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-17 21:09:20,581 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (1/1) ... [2025-03-17 21:09:20,589 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 21:09:20,601 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 21:09:20,615 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 21:09:20,619 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-17 21:09:20,636 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#0 [2025-03-17 21:09:20,636 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#1 [2025-03-17 21:09:20,636 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#2 [2025-03-17 21:09:20,636 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#3 [2025-03-17 21:09:20,637 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#0 [2025-03-17 21:09:20,637 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#1 [2025-03-17 21:09:20,637 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#2 [2025-03-17 21:09:20,637 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#3 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#0 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#1 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#2 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#3 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#3 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#3 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#0 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#1 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#2 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#3 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#2 [2025-03-17 21:09:20,637 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#3 [2025-03-17 21:09:20,638 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-17 21:09:20,638 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-17 21:09:20,881 INFO L256 CfgBuilder]: Building ICFG [2025-03-17 21:09:20,882 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-17 21:09:22,116 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L969: havoc alt_memcmp_#t~nondet36#1; [2025-03-17 21:09:22,116 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L979: havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; [2025-03-17 21:09:22,116 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L987: call ULTIMATE.dealloc(main_~#i~0#1.base, main_~#i~0#1.offset);havoc main_~#i~0#1.base, main_~#i~0#1.offset; [2025-03-17 21:09:22,116 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L955: havoc alt_malloc_#t~malloc32#1.base, alt_malloc_#t~malloc32#1.offset; [2025-03-17 21:09:22,116 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L955-3: havoc alt_malloc_#t~malloc32#1.base, alt_malloc_#t~malloc32#1.offset; [2025-03-17 21:09:22,116 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L955-6: havoc alt_malloc_#t~malloc32#1.base, alt_malloc_#t~malloc32#1.offset; [2025-03-17 21:09:22,218 INFO L? ?]: Removed 476 outVars from TransFormulas that were not future-live. [2025-03-17 21:09:22,218 INFO L307 CfgBuilder]: Performing block encoding [2025-03-17 21:09:22,260 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-17 21:09:22,261 INFO L336 CfgBuilder]: Removed 1 assume(true) statements. [2025-03-17 21:09:22,261 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 09:09:22 BoogieIcfgContainer [2025-03-17 21:09:22,261 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-17 21:09:22,262 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-17 21:09:22,262 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-17 21:09:22,269 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-17 21:09:22,270 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 21:09:22,270 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.03 09:09:19" (1/3) ... [2025-03-17 21:09:22,271 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4f7e3163 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 09:09:22, skipping insertion in model container [2025-03-17 21:09:22,271 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 21:09:22,271 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 09:09:20" (2/3) ... [2025-03-17 21:09:22,272 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4f7e3163 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 09:09:22, skipping insertion in model container [2025-03-17 21:09:22,272 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 21:09:22,272 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 09:09:22" (3/3) ... [2025-03-17 21:09:22,273 INFO L363 chiAutomizerObserver]: Analyzing ICFG uthash_SFH_test6-2.i [2025-03-17 21:09:22,322 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-17 21:09:22,322 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-17 21:09:22,322 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-17 21:09:22,322 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-17 21:09:22,322 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-17 21:09:22,322 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-17 21:09:22,322 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-17 21:09:22,322 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-17 21:09:22,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 481 states, 476 states have (on average 1.6008403361344539) internal successors, (762), 476 states have internal predecessors, (762), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:22,362 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 457 [2025-03-17 21:09:22,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:22,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:22,367 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:22,368 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:22,368 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-17 21:09:22,369 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 481 states, 476 states have (on average 1.6008403361344539) internal successors, (762), 476 states have internal predecessors, (762), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:22,386 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 457 [2025-03-17 21:09:22,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:22,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:22,387 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:22,387 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:22,391 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:22,392 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false;" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume !true;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:22,397 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:22,398 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 1 times [2025-03-17 21:09:22,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:22,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282149124] [2025-03-17 21:09:22,404 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:22,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:22,477 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:22,501 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:22,505 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:22,505 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:22,505 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:22,514 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:22,528 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:22,529 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:22,529 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:22,553 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:22,557 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:22,557 INFO L85 PathProgramCache]: Analyzing trace with hash -1323948506, now seen corresponding path program 1 times [2025-03-17 21:09:22,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:22,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975361070] [2025-03-17 21:09:22,557 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:22,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:22,572 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-17 21:09:22,579 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-17 21:09:22,580 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:22,580 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:22,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:22,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:22,618 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [975361070] [2025-03-17 21:09:22,618 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [975361070] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:22,618 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:22,619 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 21:09:22,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1001221719] [2025-03-17 21:09:22,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:22,622 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:22,623 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:22,642 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-17 21:09:22,642 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-17 21:09:22,645 INFO L87 Difference]: Start difference. First operand has 481 states, 476 states have (on average 1.6008403361344539) internal successors, (762), 476 states have internal predecessors, (762), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:22,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:22,733 INFO L93 Difference]: Finished difference Result 464 states and 653 transitions. [2025-03-17 21:09:22,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 464 states and 653 transitions. [2025-03-17 21:09:22,739 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 432 [2025-03-17 21:09:22,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 464 states to 448 states and 637 transitions. [2025-03-17 21:09:22,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 448 [2025-03-17 21:09:22,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 448 [2025-03-17 21:09:22,753 INFO L73 IsDeterministic]: Start isDeterministic. Operand 448 states and 637 transitions. [2025-03-17 21:09:22,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:22,756 INFO L218 hiAutomatonCegarLoop]: Abstraction has 448 states and 637 transitions. [2025-03-17 21:09:22,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 448 states and 637 transitions. [2025-03-17 21:09:22,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 448 to 448. [2025-03-17 21:09:22,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 448 states, 444 states have (on average 1.4211711711711712) internal successors, (631), 443 states have internal predecessors, (631), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:22,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 448 states to 448 states and 637 transitions. [2025-03-17 21:09:22,798 INFO L240 hiAutomatonCegarLoop]: Abstraction has 448 states and 637 transitions. [2025-03-17 21:09:22,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-17 21:09:22,802 INFO L432 stractBuchiCegarLoop]: Abstraction has 448 states and 637 transitions. [2025-03-17 21:09:22,802 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-17 21:09:22,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 448 states and 637 transitions. [2025-03-17 21:09:22,805 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 432 [2025-03-17 21:09:22,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:22,806 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:22,807 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:22,807 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:22,808 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:22,812 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem67#1 := read~int#1(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem67#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem68#1 := read~int#1(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem68#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem69#1 := read~int#1(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem69#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem70#1 := read~int#1(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem70#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem71#1 := read~int#1(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem71#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem72#1 := read~int#1(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem72#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem73#1 := read~int#1(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + (if main_#t~mem73#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem73#1 % 256 % 4294967296 else main_#t~mem73#1 % 256 % 4294967296 - 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:22,812 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:22,812 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 2 times [2025-03-17 21:09:22,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:22,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409748688] [2025-03-17 21:09:22,812 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 21:09:22,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:22,827 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:22,838 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:22,838 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 21:09:22,838 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:22,838 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:22,842 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:22,847 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:22,847 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:22,847 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:22,858 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:22,863 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:22,863 INFO L85 PathProgramCache]: Analyzing trace with hash 220148323, now seen corresponding path program 1 times [2025-03-17 21:09:22,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:22,863 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [396644154] [2025-03-17 21:09:22,863 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:22,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:22,926 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-17 21:09:22,943 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-17 21:09:22,943 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:22,943 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:23,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:23,194 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:23,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [396644154] [2025-03-17 21:09:23,194 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [396644154] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:23,194 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:23,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 21:09:23,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [640824012] [2025-03-17 21:09:23,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:23,195 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:23,195 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:23,195 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 21:09:23,195 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 21:09:23,195 INFO L87 Difference]: Start difference. First operand 448 states and 637 transitions. cyclomatic complexity: 193 Second operand has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:23,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:23,376 INFO L93 Difference]: Finished difference Result 451 states and 633 transitions. [2025-03-17 21:09:23,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 451 states and 633 transitions. [2025-03-17 21:09:23,380 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 435 [2025-03-17 21:09:23,385 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 451 states to 451 states and 633 transitions. [2025-03-17 21:09:23,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 451 [2025-03-17 21:09:23,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 451 [2025-03-17 21:09:23,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 451 states and 633 transitions. [2025-03-17 21:09:23,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:23,390 INFO L218 hiAutomatonCegarLoop]: Abstraction has 451 states and 633 transitions. [2025-03-17 21:09:23,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states and 633 transitions. [2025-03-17 21:09:23,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 448. [2025-03-17 21:09:23,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 448 states, 444 states have (on average 1.4054054054054055) internal successors, (624), 443 states have internal predecessors, (624), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:23,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 448 states to 448 states and 630 transitions. [2025-03-17 21:09:23,408 INFO L240 hiAutomatonCegarLoop]: Abstraction has 448 states and 630 transitions. [2025-03-17 21:09:23,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 21:09:23,409 INFO L432 stractBuchiCegarLoop]: Abstraction has 448 states and 630 transitions. [2025-03-17 21:09:23,409 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-17 21:09:23,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 448 states and 630 transitions. [2025-03-17 21:09:23,410 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 432 [2025-03-17 21:09:23,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:23,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:23,411 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:23,411 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:23,411 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:23,411 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:23,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:23,412 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 3 times [2025-03-17 21:09:23,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:23,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706218985] [2025-03-17 21:09:23,412 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 21:09:23,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:23,442 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:23,449 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:23,449 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 21:09:23,449 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:23,449 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:23,455 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:23,461 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:23,461 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:23,461 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:23,469 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:23,470 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:23,470 INFO L85 PathProgramCache]: Analyzing trace with hash 1145271786, now seen corresponding path program 1 times [2025-03-17 21:09:23,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:23,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449369743] [2025-03-17 21:09:23,470 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:23,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:23,506 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-17 21:09:23,511 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-17 21:09:23,511 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:23,511 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:23,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:23,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:23,677 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1449369743] [2025-03-17 21:09:23,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1449369743] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:23,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:23,678 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 21:09:23,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1390033650] [2025-03-17 21:09:23,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:23,678 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:23,678 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:23,678 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-17 21:09:23,678 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-17 21:09:23,679 INFO L87 Difference]: Start difference. First operand 448 states and 630 transitions. cyclomatic complexity: 186 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:23,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:23,791 INFO L93 Difference]: Finished difference Result 454 states and 636 transitions. [2025-03-17 21:09:23,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 636 transitions. [2025-03-17 21:09:23,793 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 438 [2025-03-17 21:09:23,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 636 transitions. [2025-03-17 21:09:23,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 [2025-03-17 21:09:23,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 [2025-03-17 21:09:23,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 636 transitions. [2025-03-17 21:09:23,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:23,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 454 states and 636 transitions. [2025-03-17 21:09:23,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 636 transitions. [2025-03-17 21:09:23,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. [2025-03-17 21:09:23,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 454 states, 450 states have (on average 1.4) internal successors, (630), 449 states have internal predecessors, (630), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:23,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 636 transitions. [2025-03-17 21:09:23,812 INFO L240 hiAutomatonCegarLoop]: Abstraction has 454 states and 636 transitions. [2025-03-17 21:09:23,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-17 21:09:23,813 INFO L432 stractBuchiCegarLoop]: Abstraction has 454 states and 636 transitions. [2025-03-17 21:09:23,814 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-17 21:09:23,814 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 636 transitions. [2025-03-17 21:09:23,816 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 438 [2025-03-17 21:09:23,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:23,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:23,817 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:23,817 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:23,817 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:23,817 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:23,818 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:23,819 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 4 times [2025-03-17 21:09:23,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:23,819 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143106053] [2025-03-17 21:09:23,819 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 21:09:23,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:23,830 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-03-17 21:09:23,832 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:23,835 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 21:09:23,835 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:23,835 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:23,843 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:23,845 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:23,846 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:23,846 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:23,852 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:23,853 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:23,853 INFO L85 PathProgramCache]: Analyzing trace with hash 352929068, now seen corresponding path program 1 times [2025-03-17 21:09:23,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:23,853 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454064943] [2025-03-17 21:09:23,853 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:23,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:23,888 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-17 21:09:23,894 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-17 21:09:23,894 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:23,894 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:24,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:24,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:24,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454064943] [2025-03-17 21:09:24,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1454064943] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:24,013 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:24,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 21:09:24,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163108254] [2025-03-17 21:09:24,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:24,013 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:24,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:24,013 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 21:09:24,014 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 21:09:24,014 INFO L87 Difference]: Start difference. First operand 454 states and 636 transitions. cyclomatic complexity: 186 Second operand has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:24,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:24,134 INFO L93 Difference]: Finished difference Result 400 states and 550 transitions. [2025-03-17 21:09:24,134 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 400 states and 550 transitions. [2025-03-17 21:09:24,136 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 384 [2025-03-17 21:09:24,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 400 states to 400 states and 550 transitions. [2025-03-17 21:09:24,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 400 [2025-03-17 21:09:24,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 400 [2025-03-17 21:09:24,138 INFO L73 IsDeterministic]: Start isDeterministic. Operand 400 states and 550 transitions. [2025-03-17 21:09:24,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:24,139 INFO L218 hiAutomatonCegarLoop]: Abstraction has 400 states and 550 transitions. [2025-03-17 21:09:24,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 400 states and 550 transitions. [2025-03-17 21:09:24,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 400 to 400. [2025-03-17 21:09:24,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 400 states, 396 states have (on average 1.3737373737373737) internal successors, (544), 395 states have internal predecessors, (544), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:24,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 400 states to 400 states and 550 transitions. [2025-03-17 21:09:24,144 INFO L240 hiAutomatonCegarLoop]: Abstraction has 400 states and 550 transitions. [2025-03-17 21:09:24,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-17 21:09:24,145 INFO L432 stractBuchiCegarLoop]: Abstraction has 400 states and 550 transitions. [2025-03-17 21:09:24,145 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-17 21:09:24,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 400 states and 550 transitions. [2025-03-17 21:09:24,146 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 384 [2025-03-17 21:09:24,147 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:24,147 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:24,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:24,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:24,147 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:24,148 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:24,148 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:24,148 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 5 times [2025-03-17 21:09:24,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:24,148 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954352420] [2025-03-17 21:09:24,148 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 21:09:24,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:24,158 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:24,161 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:24,162 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 21:09:24,162 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:24,162 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:24,165 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:24,168 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:24,169 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:24,169 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:24,174 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:24,175 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:24,175 INFO L85 PathProgramCache]: Analyzing trace with hash 1153031145, now seen corresponding path program 1 times [2025-03-17 21:09:24,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:24,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601084651] [2025-03-17 21:09:24,176 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:24,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:24,209 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-17 21:09:24,579 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-17 21:09:24,579 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:24,579 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:24,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:24,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:24,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [601084651] [2025-03-17 21:09:24,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [601084651] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:24,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:24,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-17 21:09:24,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8002099] [2025-03-17 21:09:24,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:24,886 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:24,886 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:24,886 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-17 21:09:24,886 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-17 21:09:24,887 INFO L87 Difference]: Start difference. First operand 400 states and 550 transitions. cyclomatic complexity: 154 Second operand has 6 states, 6 states have (on average 12.5) internal successors, (75), 6 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:25,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:25,298 INFO L93 Difference]: Finished difference Result 405 states and 557 transitions. [2025-03-17 21:09:25,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 405 states and 557 transitions. [2025-03-17 21:09:25,300 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 389 [2025-03-17 21:09:25,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 405 states to 405 states and 557 transitions. [2025-03-17 21:09:25,305 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 405 [2025-03-17 21:09:25,305 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 405 [2025-03-17 21:09:25,305 INFO L73 IsDeterministic]: Start isDeterministic. Operand 405 states and 557 transitions. [2025-03-17 21:09:25,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:25,307 INFO L218 hiAutomatonCegarLoop]: Abstraction has 405 states and 557 transitions. [2025-03-17 21:09:25,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 405 states and 557 transitions. [2025-03-17 21:09:25,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 405 to 402. [2025-03-17 21:09:25,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 402 states, 398 states have (on average 1.3718592964824121) internal successors, (546), 397 states have internal predecessors, (546), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:25,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 402 states to 402 states and 552 transitions. [2025-03-17 21:09:25,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 402 states and 552 transitions. [2025-03-17 21:09:25,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-17 21:09:25,318 INFO L432 stractBuchiCegarLoop]: Abstraction has 402 states and 552 transitions. [2025-03-17 21:09:25,320 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-17 21:09:25,320 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 402 states and 552 transitions. [2025-03-17 21:09:25,321 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 386 [2025-03-17 21:09:25,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:25,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:25,322 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:25,323 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:25,323 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:25,324 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:25,324 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:25,324 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 6 times [2025-03-17 21:09:25,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:25,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336244870] [2025-03-17 21:09:25,324 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 21:09:25,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:25,335 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:25,338 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:25,338 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 21:09:25,339 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:25,339 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:25,342 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:25,344 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:25,345 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:25,345 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:25,355 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:25,358 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:25,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1628316365, now seen corresponding path program 1 times [2025-03-17 21:09:25,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:25,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070946104] [2025-03-17 21:09:25,358 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:25,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:25,394 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-17 21:09:25,417 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-17 21:09:25,418 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:25,419 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:25,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:25,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:25,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070946104] [2025-03-17 21:09:25,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070946104] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:25,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:25,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-17 21:09:25,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485600072] [2025-03-17 21:09:25,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:25,645 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:25,645 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:25,646 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-17 21:09:25,646 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-17 21:09:25,646 INFO L87 Difference]: Start difference. First operand 402 states and 552 transitions. cyclomatic complexity: 154 Second operand has 7 states, 7 states have (on average 10.857142857142858) internal successors, (76), 7 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:26,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:26,038 INFO L93 Difference]: Finished difference Result 407 states and 558 transitions. [2025-03-17 21:09:26,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 407 states and 558 transitions. [2025-03-17 21:09:26,041 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 391 [2025-03-17 21:09:26,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 407 states to 407 states and 558 transitions. [2025-03-17 21:09:26,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 407 [2025-03-17 21:09:26,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 407 [2025-03-17 21:09:26,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 407 states and 558 transitions. [2025-03-17 21:09:26,046 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:26,047 INFO L218 hiAutomatonCegarLoop]: Abstraction has 407 states and 558 transitions. [2025-03-17 21:09:26,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 407 states and 558 transitions. [2025-03-17 21:09:26,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 407 to 406. [2025-03-17 21:09:26,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 406 states, 402 states have (on average 1.3706467661691542) internal successors, (551), 401 states have internal predecessors, (551), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:26,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 406 states to 406 states and 557 transitions. [2025-03-17 21:09:26,054 INFO L240 hiAutomatonCegarLoop]: Abstraction has 406 states and 557 transitions. [2025-03-17 21:09:26,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-17 21:09:26,055 INFO L432 stractBuchiCegarLoop]: Abstraction has 406 states and 557 transitions. [2025-03-17 21:09:26,055 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-17 21:09:26,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 406 states and 557 transitions. [2025-03-17 21:09:26,056 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 390 [2025-03-17 21:09:26,057 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:26,057 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:26,057 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:26,057 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:26,057 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:26,060 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:26,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:26,060 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 7 times [2025-03-17 21:09:26,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:26,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005116024] [2025-03-17 21:09:26,060 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 21:09:26,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:26,068 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:26,070 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:26,070 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:26,070 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:26,070 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:26,073 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:26,074 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:26,074 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:26,074 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:26,079 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:26,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:26,080 INFO L85 PathProgramCache]: Analyzing trace with hash -14122828, now seen corresponding path program 1 times [2025-03-17 21:09:26,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:26,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713431627] [2025-03-17 21:09:26,080 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:26,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:26,107 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-17 21:09:26,186 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-17 21:09:26,186 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:26,186 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:26,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:26,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:26,420 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713431627] [2025-03-17 21:09:26,420 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713431627] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:26,420 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:26,420 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 21:09:26,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431548743] [2025-03-17 21:09:26,420 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:26,421 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:26,422 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:26,422 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 21:09:26,422 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 21:09:26,422 INFO L87 Difference]: Start difference. First operand 406 states and 557 transitions. cyclomatic complexity: 155 Second operand has 4 states, 4 states have (on average 19.0) internal successors, (76), 4 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:26,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:26,574 INFO L93 Difference]: Finished difference Result 406 states and 556 transitions. [2025-03-17 21:09:26,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 406 states and 556 transitions. [2025-03-17 21:09:26,576 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 390 [2025-03-17 21:09:26,578 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 406 states to 406 states and 556 transitions. [2025-03-17 21:09:26,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 406 [2025-03-17 21:09:26,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 406 [2025-03-17 21:09:26,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 406 states and 556 transitions. [2025-03-17 21:09:26,580 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:26,580 INFO L218 hiAutomatonCegarLoop]: Abstraction has 406 states and 556 transitions. [2025-03-17 21:09:26,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 406 states and 556 transitions. [2025-03-17 21:09:26,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 406 to 406. [2025-03-17 21:09:26,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 406 states, 402 states have (on average 1.3681592039800996) internal successors, (550), 401 states have internal predecessors, (550), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:26,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 406 states to 406 states and 556 transitions. [2025-03-17 21:09:26,591 INFO L240 hiAutomatonCegarLoop]: Abstraction has 406 states and 556 transitions. [2025-03-17 21:09:26,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 21:09:26,592 INFO L432 stractBuchiCegarLoop]: Abstraction has 406 states and 556 transitions. [2025-03-17 21:09:26,592 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-17 21:09:26,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 406 states and 556 transitions. [2025-03-17 21:09:26,593 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 390 [2025-03-17 21:09:26,594 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:26,594 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:26,594 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:26,594 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:26,596 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:26,596 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:26,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:26,597 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 8 times [2025-03-17 21:09:26,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:26,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389463654] [2025-03-17 21:09:26,597 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 21:09:26,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:26,607 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:26,610 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:26,611 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 21:09:26,611 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:26,611 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:26,615 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:26,616 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:26,617 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:26,617 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:26,623 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:26,624 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:26,624 INFO L85 PathProgramCache]: Analyzing trace with hash 1177291970, now seen corresponding path program 1 times [2025-03-17 21:09:26,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:26,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785194985] [2025-03-17 21:09:26,624 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:26,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:26,654 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-17 21:09:26,679 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-17 21:09:26,679 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:26,679 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:27,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:27,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:27,035 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1785194985] [2025-03-17 21:09:27,035 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1785194985] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:27,035 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:27,036 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-17 21:09:27,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1600209961] [2025-03-17 21:09:27,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:27,036 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:27,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:27,036 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-17 21:09:27,036 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-17 21:09:27,037 INFO L87 Difference]: Start difference. First operand 406 states and 556 transitions. cyclomatic complexity: 154 Second operand has 9 states, 9 states have (on average 8.555555555555555) internal successors, (77), 9 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:27,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:27,687 INFO L93 Difference]: Finished difference Result 419 states and 574 transitions. [2025-03-17 21:09:27,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 419 states and 574 transitions. [2025-03-17 21:09:27,690 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 403 [2025-03-17 21:09:27,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 419 states to 419 states and 574 transitions. [2025-03-17 21:09:27,694 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 419 [2025-03-17 21:09:27,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 419 [2025-03-17 21:09:27,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 419 states and 574 transitions. [2025-03-17 21:09:27,696 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:27,696 INFO L218 hiAutomatonCegarLoop]: Abstraction has 419 states and 574 transitions. [2025-03-17 21:09:27,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 419 states and 574 transitions. [2025-03-17 21:09:27,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 419 to 416. [2025-03-17 21:09:27,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 416 states, 412 states have (on average 1.3689320388349515) internal successors, (564), 411 states have internal predecessors, (564), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:27,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 416 states to 416 states and 570 transitions. [2025-03-17 21:09:27,705 INFO L240 hiAutomatonCegarLoop]: Abstraction has 416 states and 570 transitions. [2025-03-17 21:09:27,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-17 21:09:27,708 INFO L432 stractBuchiCegarLoop]: Abstraction has 416 states and 570 transitions. [2025-03-17 21:09:27,708 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-17 21:09:27,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 416 states and 570 transitions. [2025-03-17 21:09:27,710 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 400 [2025-03-17 21:09:27,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:27,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:27,710 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:27,710 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:27,711 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:27,711 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:27,712 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:27,712 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 9 times [2025-03-17 21:09:27,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:27,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713818827] [2025-03-17 21:09:27,712 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 21:09:27,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:27,723 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:27,726 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:27,727 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 21:09:27,727 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:27,727 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:27,731 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:27,734 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:27,734 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:27,734 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:27,742 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:27,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:27,743 INFO L85 PathProgramCache]: Analyzing trace with hash 203755526, now seen corresponding path program 1 times [2025-03-17 21:09:27,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:27,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684799720] [2025-03-17 21:09:27,743 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:27,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:27,772 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-17 21:09:27,833 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-17 21:09:27,834 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:27,834 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:28,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:28,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:28,274 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684799720] [2025-03-17 21:09:28,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684799720] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:28,274 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:28,274 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2025-03-17 21:09:28,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378023839] [2025-03-17 21:09:28,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:28,275 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:28,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:28,275 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-17 21:09:28,275 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2025-03-17 21:09:28,275 INFO L87 Difference]: Start difference. First operand 416 states and 570 transitions. cyclomatic complexity: 158 Second operand has 8 states, 8 states have (on average 9.625) internal successors, (77), 8 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:28,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:28,669 INFO L93 Difference]: Finished difference Result 419 states and 573 transitions. [2025-03-17 21:09:28,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 419 states and 573 transitions. [2025-03-17 21:09:28,671 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 403 [2025-03-17 21:09:28,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 419 states to 419 states and 573 transitions. [2025-03-17 21:09:28,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 419 [2025-03-17 21:09:28,674 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 419 [2025-03-17 21:09:28,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 419 states and 573 transitions. [2025-03-17 21:09:28,674 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:28,674 INFO L218 hiAutomatonCegarLoop]: Abstraction has 419 states and 573 transitions. [2025-03-17 21:09:28,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 419 states and 573 transitions. [2025-03-17 21:09:28,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 419 to 419. [2025-03-17 21:09:28,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 419 states, 415 states have (on average 1.3662650602409638) internal successors, (567), 414 states have internal predecessors, (567), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:28,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 419 states to 419 states and 573 transitions. [2025-03-17 21:09:28,680 INFO L240 hiAutomatonCegarLoop]: Abstraction has 419 states and 573 transitions. [2025-03-17 21:09:28,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-17 21:09:28,681 INFO L432 stractBuchiCegarLoop]: Abstraction has 419 states and 573 transitions. [2025-03-17 21:09:28,681 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-17 21:09:28,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 419 states and 573 transitions. [2025-03-17 21:09:28,682 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 403 [2025-03-17 21:09:28,682 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:28,682 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:28,682 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:28,682 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:28,682 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:28,683 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:28,684 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:28,684 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 10 times [2025-03-17 21:09:28,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:28,684 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147023420] [2025-03-17 21:09:28,685 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 21:09:28,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:28,692 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-03-17 21:09:28,698 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:28,698 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 21:09:28,698 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:28,698 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:28,701 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:28,706 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:28,706 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:28,706 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:28,712 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:28,713 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:28,713 INFO L85 PathProgramCache]: Analyzing trace with hash 540629414, now seen corresponding path program 1 times [2025-03-17 21:09:28,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:28,713 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256587860] [2025-03-17 21:09:28,713 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:28,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:28,742 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-17 21:09:28,760 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-17 21:09:28,761 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:28,761 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:28,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:28,937 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:28,937 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256587860] [2025-03-17 21:09:28,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [256587860] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:28,937 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:28,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-17 21:09:28,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366458953] [2025-03-17 21:09:28,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:28,938 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:28,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:28,938 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-17 21:09:28,938 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-03-17 21:09:28,938 INFO L87 Difference]: Start difference. First operand 419 states and 573 transitions. cyclomatic complexity: 158 Second operand has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 6 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:29,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:29,176 INFO L93 Difference]: Finished difference Result 422 states and 576 transitions. [2025-03-17 21:09:29,176 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 422 states and 576 transitions. [2025-03-17 21:09:29,178 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 406 [2025-03-17 21:09:29,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 422 states to 422 states and 576 transitions. [2025-03-17 21:09:29,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 422 [2025-03-17 21:09:29,180 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 422 [2025-03-17 21:09:29,180 INFO L73 IsDeterministic]: Start isDeterministic. Operand 422 states and 576 transitions. [2025-03-17 21:09:29,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:29,181 INFO L218 hiAutomatonCegarLoop]: Abstraction has 422 states and 576 transitions. [2025-03-17 21:09:29,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 422 states and 576 transitions. [2025-03-17 21:09:29,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 422 to 422. [2025-03-17 21:09:29,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 422 states, 418 states have (on average 1.3636363636363635) internal successors, (570), 417 states have internal predecessors, (570), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:29,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 422 states to 422 states and 576 transitions. [2025-03-17 21:09:29,187 INFO L240 hiAutomatonCegarLoop]: Abstraction has 422 states and 576 transitions. [2025-03-17 21:09:29,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-17 21:09:29,187 INFO L432 stractBuchiCegarLoop]: Abstraction has 422 states and 576 transitions. [2025-03-17 21:09:29,188 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-17 21:09:29,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 422 states and 576 transitions. [2025-03-17 21:09:29,189 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 406 [2025-03-17 21:09:29,189 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:29,189 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:29,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:29,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:29,190 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:29,190 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:29,190 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:29,190 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 11 times [2025-03-17 21:09:29,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:29,190 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635208277] [2025-03-17 21:09:29,190 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 21:09:29,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:29,197 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:29,199 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:29,199 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 21:09:29,199 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:29,199 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:29,202 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:29,203 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:29,203 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:29,203 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:29,208 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:29,209 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:29,209 INFO L85 PathProgramCache]: Analyzing trace with hash 3344253, now seen corresponding path program 1 times [2025-03-17 21:09:29,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:29,209 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051226929] [2025-03-17 21:09:29,209 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:29,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:29,234 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-17 21:09:29,351 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-17 21:09:29,351 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:29,351 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:29,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:29,875 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:29,875 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051226929] [2025-03-17 21:09:29,875 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051226929] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:29,875 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:29,875 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-17 21:09:29,875 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [144269941] [2025-03-17 21:09:29,875 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:29,875 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:29,876 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:29,876 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-17 21:09:29,876 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-17 21:09:29,876 INFO L87 Difference]: Start difference. First operand 422 states and 576 transitions. cyclomatic complexity: 158 Second operand has 13 states, 13 states have (on average 6.0) internal successors, (78), 13 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:31,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:31,506 INFO L93 Difference]: Finished difference Result 500 states and 684 transitions. [2025-03-17 21:09:31,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 500 states and 684 transitions. [2025-03-17 21:09:31,508 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 484 [2025-03-17 21:09:31,510 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 500 states to 500 states and 684 transitions. [2025-03-17 21:09:31,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 500 [2025-03-17 21:09:31,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 500 [2025-03-17 21:09:31,511 INFO L73 IsDeterministic]: Start isDeterministic. Operand 500 states and 684 transitions. [2025-03-17 21:09:31,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:31,512 INFO L218 hiAutomatonCegarLoop]: Abstraction has 500 states and 684 transitions. [2025-03-17 21:09:31,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 500 states and 684 transitions. [2025-03-17 21:09:31,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 500 to 428. [2025-03-17 21:09:31,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 428 states, 424 states have (on average 1.3632075471698113) internal successors, (578), 423 states have internal predecessors, (578), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:31,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 428 states to 428 states and 584 transitions. [2025-03-17 21:09:31,518 INFO L240 hiAutomatonCegarLoop]: Abstraction has 428 states and 584 transitions. [2025-03-17 21:09:31,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-17 21:09:31,519 INFO L432 stractBuchiCegarLoop]: Abstraction has 428 states and 584 transitions. [2025-03-17 21:09:31,519 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-17 21:09:31,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 428 states and 584 transitions. [2025-03-17 21:09:31,520 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 412 [2025-03-17 21:09:31,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:31,520 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:31,521 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:31,521 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:31,521 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:31,521 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:31,521 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:31,522 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 12 times [2025-03-17 21:09:31,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:31,522 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238331169] [2025-03-17 21:09:31,522 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 21:09:31,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:31,528 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:31,530 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:31,530 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 21:09:31,530 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:31,530 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:31,533 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:31,535 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:31,535 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:31,535 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:31,540 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:31,541 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:31,541 INFO L85 PathProgramCache]: Analyzing trace with hash 339400427, now seen corresponding path program 1 times [2025-03-17 21:09:31,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:31,541 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2060637557] [2025-03-17 21:09:31,541 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:31,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:31,566 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-17 21:09:31,637 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-17 21:09:31,638 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:31,638 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:31,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:31,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:31,811 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2060637557] [2025-03-17 21:09:31,811 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2060637557] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:31,811 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:31,811 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-17 21:09:31,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [464029955] [2025-03-17 21:09:31,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:31,811 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:31,811 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:31,811 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-17 21:09:31,811 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-17 21:09:31,811 INFO L87 Difference]: Start difference. First operand 428 states and 584 transitions. cyclomatic complexity: 160 Second operand has 7 states, 7 states have (on average 11.142857142857142) internal successors, (78), 7 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:32,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:32,229 INFO L93 Difference]: Finished difference Result 433 states and 590 transitions. [2025-03-17 21:09:32,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 433 states and 590 transitions. [2025-03-17 21:09:32,231 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 417 [2025-03-17 21:09:32,233 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 433 states to 433 states and 590 transitions. [2025-03-17 21:09:32,233 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 433 [2025-03-17 21:09:32,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 433 [2025-03-17 21:09:32,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 433 states and 590 transitions. [2025-03-17 21:09:32,234 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:32,234 INFO L218 hiAutomatonCegarLoop]: Abstraction has 433 states and 590 transitions. [2025-03-17 21:09:32,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 433 states and 590 transitions. [2025-03-17 21:09:32,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 433 to 428. [2025-03-17 21:09:32,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 428 states, 424 states have (on average 1.3632075471698113) internal successors, (578), 423 states have internal predecessors, (578), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:32,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 428 states to 428 states and 584 transitions. [2025-03-17 21:09:32,240 INFO L240 hiAutomatonCegarLoop]: Abstraction has 428 states and 584 transitions. [2025-03-17 21:09:32,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-17 21:09:32,241 INFO L432 stractBuchiCegarLoop]: Abstraction has 428 states and 584 transitions. [2025-03-17 21:09:32,241 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-17 21:09:32,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 428 states and 584 transitions. [2025-03-17 21:09:32,243 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 412 [2025-03-17 21:09:32,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:32,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:32,243 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:32,243 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:32,244 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:32,244 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise82#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:32,244 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:32,244 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 13 times [2025-03-17 21:09:32,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:32,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564393929] [2025-03-17 21:09:32,245 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 21:09:32,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:32,252 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:32,253 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:32,253 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:32,253 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:32,253 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:32,256 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:32,257 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:32,257 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:32,257 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:32,263 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:32,263 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:32,263 INFO L85 PathProgramCache]: Analyzing trace with hash -1136411260, now seen corresponding path program 1 times [2025-03-17 21:09:32,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:32,264 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901094847] [2025-03-17 21:09:32,264 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:32,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:32,296 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-17 21:09:32,456 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-17 21:09:32,457 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:32,457 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:32,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:32,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:32,927 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1901094847] [2025-03-17 21:09:32,927 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1901094847] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:32,927 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:32,927 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-17 21:09:32,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1600617561] [2025-03-17 21:09:32,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:32,928 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:32,928 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:32,928 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-17 21:09:32,928 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-17 21:09:32,928 INFO L87 Difference]: Start difference. First operand 428 states and 584 transitions. cyclomatic complexity: 160 Second operand has 13 states, 13 states have (on average 6.076923076923077) internal successors, (79), 13 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:33,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:33,899 INFO L93 Difference]: Finished difference Result 502 states and 686 transitions. [2025-03-17 21:09:33,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 502 states and 686 transitions. [2025-03-17 21:09:33,901 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 486 [2025-03-17 21:09:33,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 502 states to 502 states and 686 transitions. [2025-03-17 21:09:33,903 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 502 [2025-03-17 21:09:33,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 502 [2025-03-17 21:09:33,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 502 states and 686 transitions. [2025-03-17 21:09:33,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:33,904 INFO L218 hiAutomatonCegarLoop]: Abstraction has 502 states and 686 transitions. [2025-03-17 21:09:33,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 502 states and 686 transitions. [2025-03-17 21:09:33,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 502 to 429. [2025-03-17 21:09:33,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 429 states, 425 states have (on average 1.3647058823529412) internal successors, (580), 424 states have internal predecessors, (580), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:33,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 429 states to 429 states and 586 transitions. [2025-03-17 21:09:33,910 INFO L240 hiAutomatonCegarLoop]: Abstraction has 429 states and 586 transitions. [2025-03-17 21:09:33,911 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-17 21:09:33,911 INFO L432 stractBuchiCegarLoop]: Abstraction has 429 states and 586 transitions. [2025-03-17 21:09:33,911 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-17 21:09:33,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 429 states and 586 transitions. [2025-03-17 21:09:33,913 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 413 [2025-03-17 21:09:33,913 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:33,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:33,913 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:33,914 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:33,914 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:33,914 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:33,915 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:33,915 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 14 times [2025-03-17 21:09:33,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:33,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012017119] [2025-03-17 21:09:33,915 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 21:09:33,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:33,923 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:33,925 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:33,925 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 21:09:33,925 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:33,925 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:33,928 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:33,929 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:33,929 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:33,929 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:33,934 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:33,935 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:33,935 INFO L85 PathProgramCache]: Analyzing trace with hash 1069748031, now seen corresponding path program 1 times [2025-03-17 21:09:33,936 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:33,936 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1069689339] [2025-03-17 21:09:33,936 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:33,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:33,968 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-17 21:09:34,003 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-17 21:09:34,004 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:34,004 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:34,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:34,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:34,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1069689339] [2025-03-17 21:09:34,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1069689339] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:34,188 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:34,188 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-17 21:09:34,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437231596] [2025-03-17 21:09:34,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:34,189 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:34,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:34,189 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-17 21:09:34,189 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2025-03-17 21:09:34,189 INFO L87 Difference]: Start difference. First operand 429 states and 586 transitions. cyclomatic complexity: 161 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:34,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:34,631 INFO L93 Difference]: Finished difference Result 439 states and 598 transitions. [2025-03-17 21:09:34,631 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 439 states and 598 transitions. [2025-03-17 21:09:34,633 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 423 [2025-03-17 21:09:34,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 439 states to 439 states and 598 transitions. [2025-03-17 21:09:34,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 439 [2025-03-17 21:09:34,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 439 [2025-03-17 21:09:34,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 439 states and 598 transitions. [2025-03-17 21:09:34,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:34,636 INFO L218 hiAutomatonCegarLoop]: Abstraction has 439 states and 598 transitions. [2025-03-17 21:09:34,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 439 states and 598 transitions. [2025-03-17 21:09:34,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 439 to 432. [2025-03-17 21:09:34,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 432 states, 428 states have (on average 1.3644859813084111) internal successors, (584), 427 states have internal predecessors, (584), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:34,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 590 transitions. [2025-03-17 21:09:34,642 INFO L240 hiAutomatonCegarLoop]: Abstraction has 432 states and 590 transitions. [2025-03-17 21:09:34,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-17 21:09:34,643 INFO L432 stractBuchiCegarLoop]: Abstraction has 432 states and 590 transitions. [2025-03-17 21:09:34,643 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-17 21:09:34,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432 states and 590 transitions. [2025-03-17 21:09:34,644 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 416 [2025-03-17 21:09:34,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:34,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:34,644 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:34,644 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:34,644 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:34,645 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:34,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:34,645 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 15 times [2025-03-17 21:09:34,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:34,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389051238] [2025-03-17 21:09:34,646 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 21:09:34,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:34,653 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:34,655 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:34,655 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 21:09:34,655 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:34,655 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:34,661 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:34,662 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:34,662 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:34,662 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:34,667 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:34,668 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:34,668 INFO L85 PathProgramCache]: Analyzing trace with hash -124396444, now seen corresponding path program 1 times [2025-03-17 21:09:34,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:34,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737177126] [2025-03-17 21:09:34,668 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:34,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:34,694 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-17 21:09:34,752 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-17 21:09:34,752 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:34,752 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:34,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:34,980 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:34,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [737177126] [2025-03-17 21:09:34,980 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [737177126] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:34,980 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:34,980 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-17 21:09:34,980 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [434462815] [2025-03-17 21:09:34,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:34,981 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:34,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:34,981 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-17 21:09:34,981 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-17 21:09:34,981 INFO L87 Difference]: Start difference. First operand 432 states and 590 transitions. cyclomatic complexity: 162 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:35,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:35,549 INFO L93 Difference]: Finished difference Result 442 states and 602 transitions. [2025-03-17 21:09:35,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 442 states and 602 transitions. [2025-03-17 21:09:35,551 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 426 [2025-03-17 21:09:35,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 442 states to 442 states and 602 transitions. [2025-03-17 21:09:35,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 442 [2025-03-17 21:09:35,554 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 442 [2025-03-17 21:09:35,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 442 states and 602 transitions. [2025-03-17 21:09:35,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:35,555 INFO L218 hiAutomatonCegarLoop]: Abstraction has 442 states and 602 transitions. [2025-03-17 21:09:35,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 442 states and 602 transitions. [2025-03-17 21:09:35,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 442 to 432. [2025-03-17 21:09:35,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 432 states, 428 states have (on average 1.3644859813084111) internal successors, (584), 427 states have internal predecessors, (584), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:35,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 590 transitions. [2025-03-17 21:09:35,563 INFO L240 hiAutomatonCegarLoop]: Abstraction has 432 states and 590 transitions. [2025-03-17 21:09:35,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 21:09:35,564 INFO L432 stractBuchiCegarLoop]: Abstraction has 432 states and 590 transitions. [2025-03-17 21:09:35,565 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-17 21:09:35,565 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432 states and 590 transitions. [2025-03-17 21:09:35,566 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 416 [2025-03-17 21:09:35,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:35,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:35,567 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:35,567 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:35,567 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:35,567 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:35,568 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:35,568 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 16 times [2025-03-17 21:09:35,568 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:35,568 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1613003810] [2025-03-17 21:09:35,568 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 21:09:35,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:35,579 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-03-17 21:09:35,581 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:35,581 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 21:09:35,581 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:35,581 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:35,586 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:35,587 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:35,587 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:35,587 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:35,594 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:35,595 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:35,595 INFO L85 PathProgramCache]: Analyzing trace with hash 1469086463, now seen corresponding path program 1 times [2025-03-17 21:09:35,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:35,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233593458] [2025-03-17 21:09:35,595 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:35,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:35,630 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-17 21:09:35,680 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-17 21:09:35,682 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:35,682 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:35,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:35,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:35,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1233593458] [2025-03-17 21:09:35,897 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1233593458] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:35,897 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:35,897 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-17 21:09:35,897 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2027666303] [2025-03-17 21:09:35,897 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:35,897 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:35,897 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:35,898 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-17 21:09:35,898 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-03-17 21:09:35,898 INFO L87 Difference]: Start difference. First operand 432 states and 590 transitions. cyclomatic complexity: 162 Second operand has 6 states, 6 states have (on average 13.166666666666666) internal successors, (79), 6 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:36,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:36,286 INFO L93 Difference]: Finished difference Result 429 states and 586 transitions. [2025-03-17 21:09:36,286 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 429 states and 586 transitions. [2025-03-17 21:09:36,288 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 413 [2025-03-17 21:09:36,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 429 states to 429 states and 586 transitions. [2025-03-17 21:09:36,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 429 [2025-03-17 21:09:36,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 429 [2025-03-17 21:09:36,290 INFO L73 IsDeterministic]: Start isDeterministic. Operand 429 states and 586 transitions. [2025-03-17 21:09:36,290 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:36,290 INFO L218 hiAutomatonCegarLoop]: Abstraction has 429 states and 586 transitions. [2025-03-17 21:09:36,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 429 states and 586 transitions. [2025-03-17 21:09:36,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 429 to 429. [2025-03-17 21:09:36,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 429 states, 425 states have (on average 1.3647058823529412) internal successors, (580), 424 states have internal predecessors, (580), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:36,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 429 states to 429 states and 586 transitions. [2025-03-17 21:09:36,295 INFO L240 hiAutomatonCegarLoop]: Abstraction has 429 states and 586 transitions. [2025-03-17 21:09:36,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-17 21:09:36,296 INFO L432 stractBuchiCegarLoop]: Abstraction has 429 states and 586 transitions. [2025-03-17 21:09:36,296 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-17 21:09:36,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 429 states and 586 transitions. [2025-03-17 21:09:36,297 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 413 [2025-03-17 21:09:36,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:36,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:36,297 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:36,297 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:36,298 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:36,298 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:36,298 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:36,298 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 17 times [2025-03-17 21:09:36,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:36,298 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255394385] [2025-03-17 21:09:36,299 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 21:09:36,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:36,305 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:36,306 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:36,306 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 21:09:36,306 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:36,307 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:36,309 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:36,310 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:36,310 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:36,310 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:36,315 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:36,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:36,315 INFO L85 PathProgramCache]: Analyzing trace with hash -1655155541, now seen corresponding path program 1 times [2025-03-17 21:09:36,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:36,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005899481] [2025-03-17 21:09:36,315 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:36,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:36,339 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-17 21:09:36,442 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-17 21:09:36,444 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:36,444 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:36,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:36,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:36,811 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005899481] [2025-03-17 21:09:36,811 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2005899481] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:36,811 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:36,812 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2025-03-17 21:09:36,812 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2121828793] [2025-03-17 21:09:36,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:36,812 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:36,812 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:36,812 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-03-17 21:09:36,812 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2025-03-17 21:09:36,813 INFO L87 Difference]: Start difference. First operand 429 states and 586 transitions. cyclomatic complexity: 161 Second operand has 11 states, 11 states have (on average 7.181818181818182) internal successors, (79), 11 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:37,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:37,442 INFO L93 Difference]: Finished difference Result 454 states and 622 transitions. [2025-03-17 21:09:37,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 622 transitions. [2025-03-17 21:09:37,444 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 438 [2025-03-17 21:09:37,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 622 transitions. [2025-03-17 21:09:37,447 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 [2025-03-17 21:09:37,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 [2025-03-17 21:09:37,447 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 622 transitions. [2025-03-17 21:09:37,448 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:37,448 INFO L218 hiAutomatonCegarLoop]: Abstraction has 454 states and 622 transitions. [2025-03-17 21:09:37,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 622 transitions. [2025-03-17 21:09:37,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 432. [2025-03-17 21:09:37,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 432 states, 428 states have (on average 1.3644859813084111) internal successors, (584), 427 states have internal predecessors, (584), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:37,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 590 transitions. [2025-03-17 21:09:37,455 INFO L240 hiAutomatonCegarLoop]: Abstraction has 432 states and 590 transitions. [2025-03-17 21:09:37,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-17 21:09:37,456 INFO L432 stractBuchiCegarLoop]: Abstraction has 432 states and 590 transitions. [2025-03-17 21:09:37,456 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-17 21:09:37,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432 states and 590 transitions. [2025-03-17 21:09:37,459 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 416 [2025-03-17 21:09:37,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:37,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:37,459 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:37,459 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:37,459 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:37,460 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise83#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:37,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:37,461 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 18 times [2025-03-17 21:09:37,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:37,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093026004] [2025-03-17 21:09:37,461 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 21:09:37,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:37,472 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:37,474 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:37,474 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 21:09:37,474 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:37,474 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:37,477 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:37,478 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:37,479 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:37,479 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:37,484 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:37,484 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:37,484 INFO L85 PathProgramCache]: Analyzing trace with hash 544573597, now seen corresponding path program 1 times [2025-03-17 21:09:37,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:37,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549373674] [2025-03-17 21:09:37,484 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:37,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:37,509 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-17 21:09:37,586 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-17 21:09:37,586 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:37,586 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:38,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:38,140 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:38,140 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549373674] [2025-03-17 21:09:38,140 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [549373674] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:38,140 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:38,140 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-17 21:09:38,141 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814613817] [2025-03-17 21:09:38,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:38,141 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:38,141 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:38,141 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-17 21:09:38,141 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2025-03-17 21:09:38,141 INFO L87 Difference]: Start difference. First operand 432 states and 590 transitions. cyclomatic complexity: 162 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:38,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:38,634 INFO L93 Difference]: Finished difference Result 424 states and 578 transitions. [2025-03-17 21:09:38,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 424 states and 578 transitions. [2025-03-17 21:09:38,636 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 408 [2025-03-17 21:09:38,637 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 424 states to 424 states and 578 transitions. [2025-03-17 21:09:38,637 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 424 [2025-03-17 21:09:38,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 424 [2025-03-17 21:09:38,637 INFO L73 IsDeterministic]: Start isDeterministic. Operand 424 states and 578 transitions. [2025-03-17 21:09:38,638 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:38,638 INFO L218 hiAutomatonCegarLoop]: Abstraction has 424 states and 578 transitions. [2025-03-17 21:09:38,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 424 states and 578 transitions. [2025-03-17 21:09:38,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 424 to 422. [2025-03-17 21:09:38,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 422 states, 418 states have (on average 1.361244019138756) internal successors, (569), 417 states have internal predecessors, (569), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:38,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 422 states to 422 states and 575 transitions. [2025-03-17 21:09:38,643 INFO L240 hiAutomatonCegarLoop]: Abstraction has 422 states and 575 transitions. [2025-03-17 21:09:38,643 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-17 21:09:38,643 INFO L432 stractBuchiCegarLoop]: Abstraction has 422 states and 575 transitions. [2025-03-17 21:09:38,643 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-17 21:09:38,644 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 422 states and 575 transitions. [2025-03-17 21:09:38,644 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 406 [2025-03-17 21:09:38,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:38,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:38,645 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:38,645 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:38,645 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:38,645 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:38,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:38,646 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 19 times [2025-03-17 21:09:38,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:38,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361584304] [2025-03-17 21:09:38,646 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 21:09:38,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:38,652 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:38,654 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:38,654 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:38,654 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:38,654 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:38,656 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:38,657 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:38,657 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:38,657 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:38,662 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:38,663 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:38,663 INFO L85 PathProgramCache]: Analyzing trace with hash 1338590505, now seen corresponding path program 1 times [2025-03-17 21:09:38,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:38,663 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476173856] [2025-03-17 21:09:38,663 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:38,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:38,688 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-17 21:09:38,700 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-17 21:09:38,700 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:38,700 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:38,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:38,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:38,935 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476173856] [2025-03-17 21:09:38,935 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476173856] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:38,935 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:38,935 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-17 21:09:38,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1356506587] [2025-03-17 21:09:38,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:38,936 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:38,936 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:38,936 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-17 21:09:38,937 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2025-03-17 21:09:38,937 INFO L87 Difference]: Start difference. First operand 422 states and 575 transitions. cyclomatic complexity: 157 Second operand has 10 states, 10 states have (on average 8.0) internal successors, (80), 10 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:39,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:39,413 INFO L93 Difference]: Finished difference Result 438 states and 596 transitions. [2025-03-17 21:09:39,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 438 states and 596 transitions. [2025-03-17 21:09:39,415 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 422 [2025-03-17 21:09:39,416 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 438 states to 438 states and 596 transitions. [2025-03-17 21:09:39,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 438 [2025-03-17 21:09:39,416 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 438 [2025-03-17 21:09:39,416 INFO L73 IsDeterministic]: Start isDeterministic. Operand 438 states and 596 transitions. [2025-03-17 21:09:39,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:39,417 INFO L218 hiAutomatonCegarLoop]: Abstraction has 438 states and 596 transitions. [2025-03-17 21:09:39,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438 states and 596 transitions. [2025-03-17 21:09:39,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438 to 432. [2025-03-17 21:09:39,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 432 states, 428 states have (on average 1.3574766355140186) internal successors, (581), 427 states have internal predecessors, (581), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:39,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 587 transitions. [2025-03-17 21:09:39,422 INFO L240 hiAutomatonCegarLoop]: Abstraction has 432 states and 587 transitions. [2025-03-17 21:09:39,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 21:09:39,423 INFO L432 stractBuchiCegarLoop]: Abstraction has 432 states and 587 transitions. [2025-03-17 21:09:39,423 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-17 21:09:39,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432 states and 587 transitions. [2025-03-17 21:09:39,424 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 416 [2025-03-17 21:09:39,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:39,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:39,425 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:39,425 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:39,425 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:39,425 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:39,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:39,426 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 20 times [2025-03-17 21:09:39,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:39,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1736635247] [2025-03-17 21:09:39,426 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 21:09:39,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:39,434 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:39,437 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:39,437 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 21:09:39,437 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:39,437 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:39,440 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:39,441 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:39,441 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:39,441 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:39,448 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:39,449 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:39,449 INFO L85 PathProgramCache]: Analyzing trace with hash 2147381430, now seen corresponding path program 1 times [2025-03-17 21:09:39,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:39,449 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554690426] [2025-03-17 21:09:39,449 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:39,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:39,483 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-17 21:09:39,535 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-17 21:09:39,536 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:39,536 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:39,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:39,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:39,826 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554690426] [2025-03-17 21:09:39,826 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1554690426] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:39,826 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:39,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-17 21:09:39,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1286815315] [2025-03-17 21:09:39,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:39,827 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:39,827 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:39,827 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-17 21:09:39,827 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-17 21:09:39,827 INFO L87 Difference]: Start difference. First operand 432 states and 587 transitions. cyclomatic complexity: 159 Second operand has 9 states, 9 states have (on average 8.88888888888889) internal successors, (80), 9 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:40,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:40,449 INFO L93 Difference]: Finished difference Result 440 states and 596 transitions. [2025-03-17 21:09:40,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 440 states and 596 transitions. [2025-03-17 21:09:40,450 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 424 [2025-03-17 21:09:40,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 440 states to 440 states and 596 transitions. [2025-03-17 21:09:40,451 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 440 [2025-03-17 21:09:40,452 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 440 [2025-03-17 21:09:40,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 440 states and 596 transitions. [2025-03-17 21:09:40,452 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:40,452 INFO L218 hiAutomatonCegarLoop]: Abstraction has 440 states and 596 transitions. [2025-03-17 21:09:40,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 440 states and 596 transitions. [2025-03-17 21:09:40,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 440 to 435. [2025-03-17 21:09:40,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 431 states have (on average 1.3549883990719258) internal successors, (584), 430 states have internal predecessors, (584), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:40,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 590 transitions. [2025-03-17 21:09:40,457 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 590 transitions. [2025-03-17 21:09:40,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 21:09:40,461 INFO L432 stractBuchiCegarLoop]: Abstraction has 435 states and 590 transitions. [2025-03-17 21:09:40,461 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-17 21:09:40,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 590 transitions. [2025-03-17 21:09:40,462 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 419 [2025-03-17 21:09:40,462 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:40,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:40,463 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:40,463 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:40,463 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:40,463 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:40,464 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:40,464 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 21 times [2025-03-17 21:09:40,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:40,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617336530] [2025-03-17 21:09:40,464 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 21:09:40,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:40,471 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:40,472 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:40,472 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 21:09:40,472 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:40,472 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:40,474 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:40,475 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:40,475 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:40,475 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:40,480 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:40,480 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:40,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1406700294, now seen corresponding path program 1 times [2025-03-17 21:09:40,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:40,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022995627] [2025-03-17 21:09:40,481 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:40,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:40,506 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-17 21:09:40,564 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-17 21:09:40,564 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:40,564 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:40,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:40,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:40,910 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022995627] [2025-03-17 21:09:40,910 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1022995627] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:40,911 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:40,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-17 21:09:40,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899564475] [2025-03-17 21:09:40,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:40,911 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:40,911 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:40,911 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-17 21:09:40,911 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2025-03-17 21:09:40,912 INFO L87 Difference]: Start difference. First operand 435 states and 590 transitions. cyclomatic complexity: 159 Second operand has 13 states, 13 states have (on average 6.153846153846154) internal successors, (80), 13 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:41,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:41,514 INFO L93 Difference]: Finished difference Result 463 states and 631 transitions. [2025-03-17 21:09:41,514 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 463 states and 631 transitions. [2025-03-17 21:09:41,515 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 447 [2025-03-17 21:09:41,516 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 463 states to 463 states and 631 transitions. [2025-03-17 21:09:41,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 463 [2025-03-17 21:09:41,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 463 [2025-03-17 21:09:41,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 463 states and 631 transitions. [2025-03-17 21:09:41,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:41,518 INFO L218 hiAutomatonCegarLoop]: Abstraction has 463 states and 631 transitions. [2025-03-17 21:09:41,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463 states and 631 transitions. [2025-03-17 21:09:41,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463 to 443. [2025-03-17 21:09:41,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 443 states, 439 states have (on average 1.355353075170843) internal successors, (595), 438 states have internal predecessors, (595), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:41,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 443 states to 443 states and 601 transitions. [2025-03-17 21:09:41,524 INFO L240 hiAutomatonCegarLoop]: Abstraction has 443 states and 601 transitions. [2025-03-17 21:09:41,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-17 21:09:41,525 INFO L432 stractBuchiCegarLoop]: Abstraction has 443 states and 601 transitions. [2025-03-17 21:09:41,525 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-03-17 21:09:41,525 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 443 states and 601 transitions. [2025-03-17 21:09:41,526 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 427 [2025-03-17 21:09:41,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:41,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:41,528 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:41,528 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:41,528 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:41,528 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:41,529 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:41,529 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 22 times [2025-03-17 21:09:41,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:41,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361226838] [2025-03-17 21:09:41,529 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 21:09:41,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:41,537 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-03-17 21:09:41,538 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:41,538 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 21:09:41,538 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:41,538 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:41,540 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:41,542 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:41,542 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:41,542 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:41,550 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:41,551 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:41,551 INFO L85 PathProgramCache]: Analyzing trace with hash -11316600, now seen corresponding path program 1 times [2025-03-17 21:09:41,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:41,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1606672245] [2025-03-17 21:09:41,551 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:41,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:41,577 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-17 21:09:41,606 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-17 21:09:41,607 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:41,607 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:41,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:41,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:41,750 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1606672245] [2025-03-17 21:09:41,750 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1606672245] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:41,750 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:41,750 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-17 21:09:41,750 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1158229320] [2025-03-17 21:09:41,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:41,751 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:41,751 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:41,751 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-17 21:09:41,751 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-17 21:09:41,752 INFO L87 Difference]: Start difference. First operand 443 states and 601 transitions. cyclomatic complexity: 162 Second operand has 7 states, 7 states have (on average 11.428571428571429) internal successors, (80), 7 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:42,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:42,108 INFO L93 Difference]: Finished difference Result 446 states and 604 transitions. [2025-03-17 21:09:42,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 446 states and 604 transitions. [2025-03-17 21:09:42,110 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 430 [2025-03-17 21:09:42,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 446 states to 446 states and 604 transitions. [2025-03-17 21:09:42,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 446 [2025-03-17 21:09:42,111 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 446 [2025-03-17 21:09:42,111 INFO L73 IsDeterministic]: Start isDeterministic. Operand 446 states and 604 transitions. [2025-03-17 21:09:42,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:42,112 INFO L218 hiAutomatonCegarLoop]: Abstraction has 446 states and 604 transitions. [2025-03-17 21:09:42,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 446 states and 604 transitions. [2025-03-17 21:09:42,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 446 to 446. [2025-03-17 21:09:42,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 446 states, 442 states have (on average 1.3529411764705883) internal successors, (598), 441 states have internal predecessors, (598), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:42,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 604 transitions. [2025-03-17 21:09:42,116 INFO L240 hiAutomatonCegarLoop]: Abstraction has 446 states and 604 transitions. [2025-03-17 21:09:42,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-17 21:09:42,117 INFO L432 stractBuchiCegarLoop]: Abstraction has 446 states and 604 transitions. [2025-03-17 21:09:42,117 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-03-17 21:09:42,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 446 states and 604 transitions. [2025-03-17 21:09:42,140 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 430 [2025-03-17 21:09:42,140 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:42,140 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:42,141 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:42,141 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:42,141 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:42,142 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:42,143 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:42,143 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 23 times [2025-03-17 21:09:42,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:42,143 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140114069] [2025-03-17 21:09:42,143 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 21:09:42,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:42,152 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:42,154 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:42,154 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 21:09:42,155 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:42,155 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:42,162 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:42,163 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:42,167 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:42,167 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:42,177 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:42,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:42,177 INFO L85 PathProgramCache]: Analyzing trace with hash 962219844, now seen corresponding path program 1 times [2025-03-17 21:09:42,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:42,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414830764] [2025-03-17 21:09:42,178 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:42,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:42,237 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-17 21:09:42,361 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-17 21:09:42,361 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:42,361 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:42,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:42,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:42,598 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414830764] [2025-03-17 21:09:42,598 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [414830764] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:42,598 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:42,598 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-17 21:09:42,598 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [829391742] [2025-03-17 21:09:42,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:42,598 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:42,598 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:42,599 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-17 21:09:42,599 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-17 21:09:42,599 INFO L87 Difference]: Start difference. First operand 446 states and 604 transitions. cyclomatic complexity: 162 Second operand has 7 states, 7 states have (on average 11.428571428571429) internal successors, (80), 7 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:42,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:42,919 INFO L93 Difference]: Finished difference Result 449 states and 606 transitions. [2025-03-17 21:09:42,919 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 606 transitions. [2025-03-17 21:09:42,921 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 433 [2025-03-17 21:09:42,922 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 606 transitions. [2025-03-17 21:09:42,922 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2025-03-17 21:09:42,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2025-03-17 21:09:42,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 606 transitions. [2025-03-17 21:09:42,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:42,924 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 606 transitions. [2025-03-17 21:09:42,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 606 transitions. [2025-03-17 21:09:42,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 446. [2025-03-17 21:09:42,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 446 states, 442 states have (on average 1.3506787330316743) internal successors, (597), 441 states have internal predecessors, (597), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:42,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 603 transitions. [2025-03-17 21:09:42,930 INFO L240 hiAutomatonCegarLoop]: Abstraction has 446 states and 603 transitions. [2025-03-17 21:09:42,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-17 21:09:42,931 INFO L432 stractBuchiCegarLoop]: Abstraction has 446 states and 603 transitions. [2025-03-17 21:09:42,931 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-03-17 21:09:42,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 446 states and 603 transitions. [2025-03-17 21:09:42,932 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 430 [2025-03-17 21:09:42,933 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:42,933 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:42,933 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:42,933 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:42,934 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:42,934 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:42,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:42,934 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 24 times [2025-03-17 21:09:42,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:42,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101438142] [2025-03-17 21:09:42,935 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 21:09:42,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:42,945 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:42,946 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:42,947 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 21:09:42,947 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:42,947 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:42,951 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:42,953 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:42,953 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:42,953 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:42,959 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:42,959 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:42,960 INFO L85 PathProgramCache]: Analyzing trace with hash -1320149852, now seen corresponding path program 1 times [2025-03-17 21:09:42,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:42,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519412103] [2025-03-17 21:09:42,960 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:42,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:42,989 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-17 21:09:43,143 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-17 21:09:43,144 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:43,144 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:43,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:43,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:43,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [519412103] [2025-03-17 21:09:43,373 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [519412103] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:43,373 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:43,373 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-17 21:09:43,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1869376557] [2025-03-17 21:09:43,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:43,374 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:43,374 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:43,374 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-17 21:09:43,374 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2025-03-17 21:09:43,374 INFO L87 Difference]: Start difference. First operand 446 states and 603 transitions. cyclomatic complexity: 161 Second operand has 10 states, 10 states have (on average 8.0) internal successors, (80), 10 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:43,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:43,901 INFO L93 Difference]: Finished difference Result 459 states and 621 transitions. [2025-03-17 21:09:43,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 459 states and 621 transitions. [2025-03-17 21:09:43,902 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 443 [2025-03-17 21:09:43,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 459 states to 459 states and 621 transitions. [2025-03-17 21:09:43,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 459 [2025-03-17 21:09:43,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 459 [2025-03-17 21:09:43,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 459 states and 621 transitions. [2025-03-17 21:09:43,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:43,904 INFO L218 hiAutomatonCegarLoop]: Abstraction has 459 states and 621 transitions. [2025-03-17 21:09:43,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 459 states and 621 transitions. [2025-03-17 21:09:43,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 459 to 446. [2025-03-17 21:09:43,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 446 states, 442 states have (on average 1.3506787330316743) internal successors, (597), 441 states have internal predecessors, (597), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:43,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 603 transitions. [2025-03-17 21:09:43,909 INFO L240 hiAutomatonCegarLoop]: Abstraction has 446 states and 603 transitions. [2025-03-17 21:09:43,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 21:09:43,910 INFO L432 stractBuchiCegarLoop]: Abstraction has 446 states and 603 transitions. [2025-03-17 21:09:43,910 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-03-17 21:09:43,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 446 states and 603 transitions. [2025-03-17 21:09:43,911 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 430 [2025-03-17 21:09:43,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:43,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:43,912 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:43,912 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:43,912 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:43,912 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:43,912 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:43,913 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 25 times [2025-03-17 21:09:43,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:43,913 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409315977] [2025-03-17 21:09:43,913 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 21:09:43,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:43,922 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:43,923 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:43,924 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:43,924 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:43,924 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:43,926 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:43,927 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:43,928 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:43,928 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:43,933 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:43,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:43,934 INFO L85 PathProgramCache]: Analyzing trace with hash 1878103758, now seen corresponding path program 1 times [2025-03-17 21:09:43,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:43,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1471401584] [2025-03-17 21:09:43,934 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:43,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:43,967 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 21:09:44,070 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 21:09:44,070 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:44,070 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:44,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:44,235 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:44,235 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1471401584] [2025-03-17 21:09:44,235 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1471401584] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:44,235 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:44,235 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2025-03-17 21:09:44,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [191954275] [2025-03-17 21:09:44,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:44,235 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:44,235 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:44,236 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-17 21:09:44,236 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2025-03-17 21:09:44,236 INFO L87 Difference]: Start difference. First operand 446 states and 603 transitions. cyclomatic complexity: 161 Second operand has 8 states, 8 states have (on average 10.125) internal successors, (81), 8 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:56,460 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 12.00s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2025-03-17 21:09:56,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:56,678 INFO L93 Difference]: Finished difference Result 525 states and 711 transitions. [2025-03-17 21:09:56,678 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 525 states and 711 transitions. [2025-03-17 21:09:56,679 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 509 [2025-03-17 21:09:56,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 525 states to 525 states and 711 transitions. [2025-03-17 21:09:56,681 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 525 [2025-03-17 21:09:56,681 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 525 [2025-03-17 21:09:56,681 INFO L73 IsDeterministic]: Start isDeterministic. Operand 525 states and 711 transitions. [2025-03-17 21:09:56,682 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:56,682 INFO L218 hiAutomatonCegarLoop]: Abstraction has 525 states and 711 transitions. [2025-03-17 21:09:56,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 525 states and 711 transitions. [2025-03-17 21:09:56,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 525 to 448. [2025-03-17 21:09:56,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 448 states, 444 states have (on average 1.3513513513513513) internal successors, (600), 443 states have internal predecessors, (600), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:56,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 448 states to 448 states and 606 transitions. [2025-03-17 21:09:56,687 INFO L240 hiAutomatonCegarLoop]: Abstraction has 448 states and 606 transitions. [2025-03-17 21:09:56,687 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-17 21:09:56,687 INFO L432 stractBuchiCegarLoop]: Abstraction has 448 states and 606 transitions. [2025-03-17 21:09:56,687 INFO L338 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-03-17 21:09:56,688 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 448 states and 606 transitions. [2025-03-17 21:09:56,689 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 432 [2025-03-17 21:09:56,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:56,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:56,689 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:56,689 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:56,690 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:56,690 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise83#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:56,690 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:56,690 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 26 times [2025-03-17 21:09:56,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:56,691 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1644383280] [2025-03-17 21:09:56,691 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 21:09:56,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:56,698 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:56,699 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:56,699 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 21:09:56,699 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:56,699 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:56,701 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:56,702 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:56,702 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:56,702 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:56,706 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:56,707 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:56,707 INFO L85 PathProgramCache]: Analyzing trace with hash -217134400, now seen corresponding path program 1 times [2025-03-17 21:09:56,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:56,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081278833] [2025-03-17 21:09:56,707 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:56,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:56,731 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 21:09:56,809 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 21:09:56,809 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:56,809 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:57,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:57,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:57,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081278833] [2025-03-17 21:09:57,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081278833] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:57,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:57,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2025-03-17 21:09:57,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763644489] [2025-03-17 21:09:57,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:57,468 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:57,468 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:57,469 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2025-03-17 21:09:57,469 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=237, Unknown=0, NotChecked=0, Total=272 [2025-03-17 21:09:57,469 INFO L87 Difference]: Start difference. First operand 448 states and 606 transitions. cyclomatic complexity: 162 Second operand has 17 states, 17 states have (on average 4.764705882352941) internal successors, (81), 17 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:58,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:58,688 INFO L93 Difference]: Finished difference Result 471 states and 639 transitions. [2025-03-17 21:09:58,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 471 states and 639 transitions. [2025-03-17 21:09:58,690 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 455 [2025-03-17 21:09:58,691 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 471 states to 471 states and 639 transitions. [2025-03-17 21:09:58,691 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 471 [2025-03-17 21:09:58,691 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 471 [2025-03-17 21:09:58,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 471 states and 639 transitions. [2025-03-17 21:09:58,692 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:58,692 INFO L218 hiAutomatonCegarLoop]: Abstraction has 471 states and 639 transitions. [2025-03-17 21:09:58,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states and 639 transitions. [2025-03-17 21:09:58,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 457. [2025-03-17 21:09:58,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 457 states, 453 states have (on average 1.3509933774834437) internal successors, (612), 452 states have internal predecessors, (612), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:58,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 457 states to 457 states and 618 transitions. [2025-03-17 21:09:58,696 INFO L240 hiAutomatonCegarLoop]: Abstraction has 457 states and 618 transitions. [2025-03-17 21:09:58,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2025-03-17 21:09:58,697 INFO L432 stractBuchiCegarLoop]: Abstraction has 457 states and 618 transitions. [2025-03-17 21:09:58,697 INFO L338 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2025-03-17 21:09:58,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 457 states and 618 transitions. [2025-03-17 21:09:58,698 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 441 [2025-03-17 21:09:58,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:58,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:58,699 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:58,699 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:58,699 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:58,700 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise82#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:58,700 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:58,700 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 27 times [2025-03-17 21:09:58,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:58,700 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948985686] [2025-03-17 21:09:58,700 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 21:09:58,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:58,707 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:58,708 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:58,708 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 21:09:58,708 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:58,708 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:58,709 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:58,710 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:58,710 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:58,710 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:58,714 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:58,714 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:58,715 INFO L85 PathProgramCache]: Analyzing trace with hash -1898119257, now seen corresponding path program 1 times [2025-03-17 21:09:58,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:58,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968350240] [2025-03-17 21:09:58,715 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:58,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:58,738 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 21:09:58,823 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 21:09:58,823 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:58,823 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:09:59,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:09:59,116 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:09:59,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [968350240] [2025-03-17 21:09:59,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [968350240] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:09:59,116 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:09:59,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-17 21:09:59,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619260866] [2025-03-17 21:09:59,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:09:59,116 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:09:59,116 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:09:59,117 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-17 21:09:59,117 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-17 21:09:59,117 INFO L87 Difference]: Start difference. First operand 457 states and 618 transitions. cyclomatic complexity: 165 Second operand has 13 states, 13 states have (on average 6.230769230769231) internal successors, (81), 13 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:09:59,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:09:59,617 INFO L93 Difference]: Finished difference Result 468 states and 632 transitions. [2025-03-17 21:09:59,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 468 states and 632 transitions. [2025-03-17 21:09:59,618 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2025-03-17 21:09:59,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 468 states to 468 states and 632 transitions. [2025-03-17 21:09:59,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 468 [2025-03-17 21:09:59,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 468 [2025-03-17 21:09:59,619 INFO L73 IsDeterministic]: Start isDeterministic. Operand 468 states and 632 transitions. [2025-03-17 21:09:59,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:09:59,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 468 states and 632 transitions. [2025-03-17 21:09:59,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 468 states and 632 transitions. [2025-03-17 21:09:59,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 468 to 462. [2025-03-17 21:09:59,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 462 states, 458 states have (on average 1.351528384279476) internal successors, (619), 457 states have internal predecessors, (619), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:09:59,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 462 states to 462 states and 625 transitions. [2025-03-17 21:09:59,627 INFO L240 hiAutomatonCegarLoop]: Abstraction has 462 states and 625 transitions. [2025-03-17 21:09:59,627 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-17 21:09:59,628 INFO L432 stractBuchiCegarLoop]: Abstraction has 462 states and 625 transitions. [2025-03-17 21:09:59,628 INFO L338 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2025-03-17 21:09:59,628 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 462 states and 625 transitions. [2025-03-17 21:09:59,628 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 446 [2025-03-17 21:09:59,628 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:09:59,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:09:59,629 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:09:59,629 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:09:59,629 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:09:59,630 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise80#1;assume main_#t~bitwise80#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:09:59,630 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:59,630 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 28 times [2025-03-17 21:09:59,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:59,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073551067] [2025-03-17 21:09:59,631 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 21:09:59,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:59,637 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-03-17 21:09:59,638 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:59,638 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 21:09:59,638 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:59,638 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:09:59,640 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:09:59,641 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:09:59,641 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:59,641 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:09:59,645 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:09:59,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:09:59,646 INFO L85 PathProgramCache]: Analyzing trace with hash 1914930074, now seen corresponding path program 1 times [2025-03-17 21:09:59,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:09:59,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724109359] [2025-03-17 21:09:59,646 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:09:59,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:09:59,668 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 21:09:59,786 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 21:09:59,786 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:09:59,786 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:10:00,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:10:00,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:10:00,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [724109359] [2025-03-17 21:10:00,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [724109359] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:10:00,324 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:10:00,324 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2025-03-17 21:10:00,324 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1862554752] [2025-03-17 21:10:00,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:10:00,325 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:10:00,325 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:10:00,325 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2025-03-17 21:10:00,325 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=265, Unknown=0, NotChecked=0, Total=306 [2025-03-17 21:10:00,325 INFO L87 Difference]: Start difference. First operand 462 states and 625 transitions. cyclomatic complexity: 167 Second operand has 18 states, 18 states have (on average 4.5) internal successors, (81), 18 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:10:01,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:10:01,735 INFO L93 Difference]: Finished difference Result 556 states and 757 transitions. [2025-03-17 21:10:01,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 556 states and 757 transitions. [2025-03-17 21:10:01,736 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 540 [2025-03-17 21:10:01,738 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 556 states to 556 states and 757 transitions. [2025-03-17 21:10:01,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 556 [2025-03-17 21:10:01,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 556 [2025-03-17 21:10:01,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 556 states and 757 transitions. [2025-03-17 21:10:01,738 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:10:01,738 INFO L218 hiAutomatonCegarLoop]: Abstraction has 556 states and 757 transitions. [2025-03-17 21:10:01,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 556 states and 757 transitions. [2025-03-17 21:10:01,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 556 to 475. [2025-03-17 21:10:01,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 475 states, 471 states have (on average 1.3524416135881103) internal successors, (637), 470 states have internal predecessors, (637), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:10:01,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 475 states to 475 states and 643 transitions. [2025-03-17 21:10:01,742 INFO L240 hiAutomatonCegarLoop]: Abstraction has 475 states and 643 transitions. [2025-03-17 21:10:01,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2025-03-17 21:10:01,743 INFO L432 stractBuchiCegarLoop]: Abstraction has 475 states and 643 transitions. [2025-03-17 21:10:01,743 INFO L338 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2025-03-17 21:10:01,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 475 states and 643 transitions. [2025-03-17 21:10:01,744 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 459 [2025-03-17 21:10:01,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:10:01,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:10:01,744 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:10:01,744 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:10:01,745 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:10:01,745 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise80#1;assume main_#t~bitwise80#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:10:01,745 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:10:01,745 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 29 times [2025-03-17 21:10:01,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:10:01,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [594241856] [2025-03-17 21:10:01,745 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 21:10:01,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:10:01,751 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:10:01,752 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:10:01,753 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 21:10:01,753 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:10:01,753 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:10:01,754 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:10:01,755 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:10:01,755 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:10:01,755 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:10:01,759 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:10:01,759 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:10:01,760 INFO L85 PathProgramCache]: Analyzing trace with hash -1682752121, now seen corresponding path program 1 times [2025-03-17 21:10:01,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:10:01,760 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947847450] [2025-03-17 21:10:01,760 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:10:01,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:10:01,782 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 21:10:01,849 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 21:10:01,849 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:10:01,849 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:10:02,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:10:02,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:10:02,078 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1947847450] [2025-03-17 21:10:02,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1947847450] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:10:02,078 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:10:02,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-17 21:10:02,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [100303615] [2025-03-17 21:10:02,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:10:02,079 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:10:02,079 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:10:02,079 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-17 21:10:02,079 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-03-17 21:10:02,079 INFO L87 Difference]: Start difference. First operand 475 states and 643 transitions. cyclomatic complexity: 172 Second operand has 10 states, 10 states have (on average 8.1) internal successors, (81), 10 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:10:02,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:10:02,618 INFO L93 Difference]: Finished difference Result 487 states and 660 transitions. [2025-03-17 21:10:02,619 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 487 states and 660 transitions. [2025-03-17 21:10:02,620 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 471 [2025-03-17 21:10:02,621 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 487 states to 487 states and 660 transitions. [2025-03-17 21:10:02,621 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 487 [2025-03-17 21:10:02,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 487 [2025-03-17 21:10:02,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 487 states and 660 transitions. [2025-03-17 21:10:02,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:10:02,622 INFO L218 hiAutomatonCegarLoop]: Abstraction has 487 states and 660 transitions. [2025-03-17 21:10:02,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 487 states and 660 transitions. [2025-03-17 21:10:02,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 487 to 479. [2025-03-17 21:10:02,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 479 states, 475 states have (on average 1.351578947368421) internal successors, (642), 474 states have internal predecessors, (642), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:10:02,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 479 states to 479 states and 648 transitions. [2025-03-17 21:10:02,629 INFO L240 hiAutomatonCegarLoop]: Abstraction has 479 states and 648 transitions. [2025-03-17 21:10:02,630 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 21:10:02,630 INFO L432 stractBuchiCegarLoop]: Abstraction has 479 states and 648 transitions. [2025-03-17 21:10:02,631 INFO L338 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2025-03-17 21:10:02,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 479 states and 648 transitions. [2025-03-17 21:10:02,632 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 463 [2025-03-17 21:10:02,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:10:02,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:10:02,632 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:10:02,632 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:10:02,632 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:10:02,632 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:10:02,633 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:10:02,633 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 30 times [2025-03-17 21:10:02,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:10:02,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70770399] [2025-03-17 21:10:02,633 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 21:10:02,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:10:02,639 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:10:02,640 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:10:02,641 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 21:10:02,641 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:10:02,641 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:10:02,642 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:10:02,643 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:10:02,643 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:10:02,643 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:10:02,648 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:10:02,648 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:10:02,648 INFO L85 PathProgramCache]: Analyzing trace with hash 1888277607, now seen corresponding path program 1 times [2025-03-17 21:10:02,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:10:02,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183331569] [2025-03-17 21:10:02,649 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:10:02,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:10:02,672 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 21:10:02,700 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 21:10:02,700 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:10:02,700 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:10:02,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 21:10:02,824 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 21:10:02,824 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [183331569] [2025-03-17 21:10:02,824 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [183331569] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 21:10:02,824 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 21:10:02,824 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-17 21:10:02,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1622098792] [2025-03-17 21:10:02,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 21:10:02,824 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 21:10:02,825 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 21:10:02,825 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-17 21:10:02,825 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-17 21:10:02,825 INFO L87 Difference]: Start difference. First operand 479 states and 648 transitions. cyclomatic complexity: 173 Second operand has 9 states, 9 states have (on average 9.0) internal successors, (81), 9 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 21:10:03,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 21:10:03,261 INFO L93 Difference]: Finished difference Result 484 states and 654 transitions. [2025-03-17 21:10:03,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 484 states and 654 transitions. [2025-03-17 21:10:03,262 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 468 [2025-03-17 21:10:03,263 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 484 states to 484 states and 654 transitions. [2025-03-17 21:10:03,263 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 484 [2025-03-17 21:10:03,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 484 [2025-03-17 21:10:03,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 484 states and 654 transitions. [2025-03-17 21:10:03,264 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 21:10:03,264 INFO L218 hiAutomatonCegarLoop]: Abstraction has 484 states and 654 transitions. [2025-03-17 21:10:03,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 484 states and 654 transitions. [2025-03-17 21:10:03,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 484 to 482. [2025-03-17 21:10:03,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 482 states, 478 states have (on average 1.3514644351464435) internal successors, (646), 477 states have internal predecessors, (646), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-17 21:10:03,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 482 states and 652 transitions. [2025-03-17 21:10:03,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 482 states and 652 transitions. [2025-03-17 21:10:03,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 21:10:03,268 INFO L432 stractBuchiCegarLoop]: Abstraction has 482 states and 652 transitions. [2025-03-17 21:10:03,268 INFO L338 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2025-03-17 21:10:03,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 482 states and 652 transitions. [2025-03-17 21:10:03,269 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 466 [2025-03-17 21:10:03,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 21:10:03,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 21:10:03,269 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 21:10:03,269 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 21:10:03,269 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-17 21:10:03,269 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#1(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#1(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#1(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#1(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#1(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#1(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#1(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#1(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#1(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#1(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-17 21:10:03,270 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:10:03,270 INFO L85 PathProgramCache]: Analyzing trace with hash 868, now seen corresponding path program 31 times [2025-03-17 21:10:03,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:10:03,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532191506] [2025-03-17 21:10:03,270 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 21:10:03,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:10:03,277 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:10:03,278 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:10:03,278 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:10:03,278 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:10:03,278 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 21:10:03,280 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 21:10:03,280 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 21:10:03,280 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:10:03,280 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 21:10:03,284 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 21:10:03,285 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 21:10:03,285 INFO L85 PathProgramCache]: Analyzing trace with hash 1926042939, now seen corresponding path program 1 times [2025-03-17 21:10:03,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 21:10:03,285 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788964680] [2025-03-17 21:10:03,285 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 21:10:03,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 21:10:03,308 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-17 21:10:03,352 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-17 21:10:03,352 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 21:10:03,352 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 21:10:15,596 WARN L286 SmtUtils]: Spent 12.00s on a formula simplification that was a NOOP. DAG size: 32 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-03-17 21:10:34,577 WARN L286 SmtUtils]: Spent 14.55s on a formula simplification that was a NOOP. DAG size: 39 (called from [L 388] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2025-03-17 21:10:46,586 WARN L286 SmtUtils]: Spent 12.01s on a formula simplification that was a NOOP. DAG size: 26 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify)