./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 8fc3dc66 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ac8e60fb32c268c01bf0cc1d1cd76454411c67e3ab15d16b4eca5e74b982e97f --- Real Ultimate output --- This is Ultimate 0.3.0-?-8fc3dc6-m [2025-03-16 19:04:37,842 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-16 19:04:37,893 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2025-03-16 19:04:37,898 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-16 19:04:37,898 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-16 19:04:37,921 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-16 19:04:37,922 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-16 19:04:37,922 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-16 19:04:37,922 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-16 19:04:37,923 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-16 19:04:37,923 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2025-03-16 19:04:37,923 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2025-03-16 19:04:37,923 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-16 19:04:37,923 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-16 19:04:37,924 INFO L153 SettingsManager]: * Use SBE=true [2025-03-16 19:04:37,924 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-16 19:04:37,925 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2025-03-16 19:04:37,925 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-16 19:04:37,925 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-16 19:04:37,925 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-16 19:04:37,925 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-16 19:04:37,925 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2025-03-16 19:04:37,925 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2025-03-16 19:04:37,925 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2025-03-16 19:04:37,925 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-16 19:04:37,925 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-16 19:04:37,925 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-16 19:04:37,925 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-16 19:04:37,926 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-16 19:04:37,926 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-16 19:04:37,926 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2025-03-16 19:04:37,926 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2025-03-16 19:04:37,926 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2025-03-16 19:04:37,926 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-16 19:04:37,926 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2025-03-16 19:04:37,926 INFO L153 SettingsManager]: * Compute procedure contracts=false [2025-03-16 19:04:37,926 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2025-03-16 19:04:37,926 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-16 19:04:37,926 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2025-03-16 19:04:37,926 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2025-03-16 19:04:37,927 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2025-03-16 19:04:37,927 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2025-03-16 19:04:37,927 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2025-03-16 19:04:37,927 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ac8e60fb32c268c01bf0cc1d1cd76454411c67e3ab15d16b4eca5e74b982e97f [2025-03-16 19:04:38,149 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-16 19:04:38,155 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-16 19:04:38,156 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-16 19:04:38,157 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-16 19:04:38,157 INFO L274 PluginConnector]: CDTParser initialized [2025-03-16 19:04:38,158 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2025-03-16 19:04:39,315 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cdb7ce535/68377aff73694b6b957930bb8e1044c2/FLAG7b42cbe87 [2025-03-16 19:04:39,619 INFO L384 CDTParser]: Found 1 translation units. [2025-03-16 19:04:39,621 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2025-03-16 19:04:39,633 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cdb7ce535/68377aff73694b6b957930bb8e1044c2/FLAG7b42cbe87 [2025-03-16 19:04:39,650 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cdb7ce535/68377aff73694b6b957930bb8e1044c2 [2025-03-16 19:04:39,652 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-16 19:04:39,653 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-16 19:04:39,656 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-16 19:04:39,656 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-16 19:04:39,659 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-16 19:04:39,660 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:39,662 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@36336043 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39, skipping insertion in model container [2025-03-16 19:04:39,662 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:39,687 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-16 19:04:39,851 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c[14522,14535] [2025-03-16 19:04:39,854 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-16 19:04:39,862 INFO L200 MainTranslator]: Completed pre-run [2025-03-16 19:04:39,910 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c[14522,14535] [2025-03-16 19:04:39,911 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-16 19:04:39,922 INFO L204 MainTranslator]: Completed translation [2025-03-16 19:04:39,922 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39 WrapperNode [2025-03-16 19:04:39,923 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-16 19:04:39,923 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-16 19:04:39,923 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-16 19:04:39,923 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-16 19:04:39,928 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:39,941 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:39,979 INFO L138 Inliner]: procedures = 32, calls = 48, calls flagged for inlining = 12, calls inlined = 12, statements flattened = 499 [2025-03-16 19:04:39,979 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-16 19:04:39,982 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-16 19:04:39,982 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-16 19:04:39,982 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-16 19:04:39,988 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:39,989 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:39,997 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:40,014 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-16 19:04:40,014 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:40,015 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:40,027 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:40,031 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:40,033 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:40,033 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:40,039 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-16 19:04:40,040 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-16 19:04:40,040 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-16 19:04:40,040 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-16 19:04:40,042 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (1/1) ... [2025-03-16 19:04:40,045 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2025-03-16 19:04:40,053 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:04:40,065 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2025-03-16 19:04:40,067 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2025-03-16 19:04:40,084 INFO L130 BoogieDeclarations]: Found specification of procedure read_manual_selection_history [2025-03-16 19:04:40,084 INFO L138 BoogieDeclarations]: Found implementation of procedure read_manual_selection_history [2025-03-16 19:04:40,084 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-16 19:04:40,084 INFO L130 BoogieDeclarations]: Found specification of procedure read_side2_failed_history [2025-03-16 19:04:40,084 INFO L138 BoogieDeclarations]: Found implementation of procedure read_side2_failed_history [2025-03-16 19:04:40,084 INFO L130 BoogieDeclarations]: Found specification of procedure assert [2025-03-16 19:04:40,085 INFO L138 BoogieDeclarations]: Found implementation of procedure assert [2025-03-16 19:04:40,085 INFO L130 BoogieDeclarations]: Found specification of procedure flip_the_side [2025-03-16 19:04:40,085 INFO L138 BoogieDeclarations]: Found implementation of procedure flip_the_side [2025-03-16 19:04:40,085 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2025-03-16 19:04:40,085 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2025-03-16 19:04:40,086 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-16 19:04:40,086 INFO L130 BoogieDeclarations]: Found specification of procedure read_side1_failed_history [2025-03-16 19:04:40,086 INFO L138 BoogieDeclarations]: Found implementation of procedure read_side1_failed_history [2025-03-16 19:04:40,086 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-16 19:04:40,086 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-16 19:04:40,086 INFO L130 BoogieDeclarations]: Found specification of procedure read_active_side_history [2025-03-16 19:04:40,087 INFO L138 BoogieDeclarations]: Found implementation of procedure read_active_side_history [2025-03-16 19:04:40,170 INFO L256 CfgBuilder]: Building ICFG [2025-03-16 19:04:40,172 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-16 19:04:40,650 INFO L? ?]: Removed 100 outVars from TransFormulas that were not future-live. [2025-03-16 19:04:40,650 INFO L307 CfgBuilder]: Performing block encoding [2025-03-16 19:04:40,660 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-16 19:04:40,662 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-16 19:04:40,662 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 16.03 07:04:40 BoogieIcfgContainer [2025-03-16 19:04:40,662 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-16 19:04:40,664 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2025-03-16 19:04:40,664 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2025-03-16 19:04:40,667 INFO L274 PluginConnector]: TraceAbstraction initialized [2025-03-16 19:04:40,667 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 16.03 07:04:39" (1/3) ... [2025-03-16 19:04:40,668 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@37ec1b7f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.03 07:04:40, skipping insertion in model container [2025-03-16 19:04:40,668 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:39" (2/3) ... [2025-03-16 19:04:40,668 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@37ec1b7f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.03 07:04:40, skipping insertion in model container [2025-03-16 19:04:40,668 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 16.03 07:04:40" (3/3) ... [2025-03-16 19:04:40,669 INFO L128 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2025-03-16 19:04:40,680 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2025-03-16 19:04:40,681 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c that has 8 procedures, 169 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2025-03-16 19:04:40,749 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2025-03-16 19:04:40,757 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@1b2cb782, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2025-03-16 19:04:40,758 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2025-03-16 19:04:40,762 INFO L276 IsEmpty]: Start isEmpty. Operand has 169 states, 129 states have (on average 1.5813953488372092) internal successors, (204), 131 states have internal predecessors, (204), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-16 19:04:40,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2025-03-16 19:04:40,767 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:40,768 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:40,768 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:40,771 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:40,772 INFO L85 PathProgramCache]: Analyzing trace with hash -298517816, now seen corresponding path program 1 times [2025-03-16 19:04:40,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:40,778 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173608527] [2025-03-16 19:04:40,778 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:40,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:40,836 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes. [2025-03-16 19:04:40,875 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements. [2025-03-16 19:04:40,875 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:40,875 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:40,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-16 19:04:40,977 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:40,977 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1173608527] [2025-03-16 19:04:40,978 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1173608527] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:40,978 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:40,978 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-16 19:04:40,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499699213] [2025-03-16 19:04:40,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:40,982 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2025-03-16 19:04:40,983 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:40,994 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-16 19:04:40,995 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-16 19:04:40,998 INFO L87 Difference]: Start difference. First operand has 169 states, 129 states have (on average 1.5813953488372092) internal successors, (204), 131 states have internal predecessors, (204), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) Second operand has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-16 19:04:41,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:41,033 INFO L93 Difference]: Finished difference Result 321 states and 532 transitions. [2025-03-16 19:04:41,034 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-16 19:04:41,035 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2025-03-16 19:04:41,035 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:41,039 INFO L225 Difference]: With dead ends: 321 [2025-03-16 19:04:41,039 INFO L226 Difference]: Without dead ends: 167 [2025-03-16 19:04:41,042 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-16 19:04:41,043 INFO L435 NwaCegarLoop]: 262 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 262 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:41,044 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 262 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:41,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2025-03-16 19:04:41,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 167. [2025-03-16 19:04:41,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 167 states, 128 states have (on average 1.5625) internal successors, (200), 129 states have internal predecessors, (200), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-16 19:04:41,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 262 transitions. [2025-03-16 19:04:41,086 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 262 transitions. Word has length 23 [2025-03-16 19:04:41,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:41,086 INFO L471 AbstractCegarLoop]: Abstraction has 167 states and 262 transitions. [2025-03-16 19:04:41,087 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-16 19:04:41,087 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 262 transitions. [2025-03-16 19:04:41,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2025-03-16 19:04:41,089 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:41,089 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:41,089 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2025-03-16 19:04:41,089 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:41,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:41,090 INFO L85 PathProgramCache]: Analyzing trace with hash -1295590169, now seen corresponding path program 1 times [2025-03-16 19:04:41,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:41,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452878380] [2025-03-16 19:04:41,090 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:41,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:41,106 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes. [2025-03-16 19:04:41,138 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements. [2025-03-16 19:04:41,138 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:41,138 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:41,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-16 19:04:41,298 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:41,298 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452878380] [2025-03-16 19:04:41,298 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [452878380] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:41,299 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:41,299 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-16 19:04:41,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1471899527] [2025-03-16 19:04:41,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:41,300 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-03-16 19:04:41,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:41,301 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-16 19:04:41,301 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-16 19:04:41,301 INFO L87 Difference]: Start difference. First operand 167 states and 262 transitions. Second operand has 6 states, 5 states have (on average 3.8) internal successors, (19), 6 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-16 19:04:41,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:41,380 INFO L93 Difference]: Finished difference Result 321 states and 499 transitions. [2025-03-16 19:04:41,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-16 19:04:41,381 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 3.8) internal successors, (19), 6 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2025-03-16 19:04:41,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:41,383 INFO L225 Difference]: With dead ends: 321 [2025-03-16 19:04:41,383 INFO L226 Difference]: Without dead ends: 167 [2025-03-16 19:04:41,384 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-16 19:04:41,384 INFO L435 NwaCegarLoop]: 258 mSDtfsCounter, 0 mSDsluCounter, 1010 mSDsCounter, 0 mSdLazyCounter, 27 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1268 SdHoareTripleChecker+Invalid, 38 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 27 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:41,386 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1268 Invalid, 38 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 27 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:41,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2025-03-16 19:04:41,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 167. [2025-03-16 19:04:41,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 167 states, 128 states have (on average 1.46875) internal successors, (188), 129 states have internal predecessors, (188), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-16 19:04:41,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 250 transitions. [2025-03-16 19:04:41,405 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 250 transitions. Word has length 23 [2025-03-16 19:04:41,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:41,405 INFO L471 AbstractCegarLoop]: Abstraction has 167 states and 250 transitions. [2025-03-16 19:04:41,405 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 3.8) internal successors, (19), 6 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-16 19:04:41,405 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 250 transitions. [2025-03-16 19:04:41,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2025-03-16 19:04:41,406 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:41,406 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:41,406 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2025-03-16 19:04:41,406 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:41,406 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:41,406 INFO L85 PathProgramCache]: Analyzing trace with hash 480364570, now seen corresponding path program 1 times [2025-03-16 19:04:41,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:41,406 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511443663] [2025-03-16 19:04:41,407 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:41,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:41,418 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-16 19:04:41,468 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-16 19:04:41,469 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:41,469 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:41,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-16 19:04:41,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:41,629 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511443663] [2025-03-16 19:04:41,630 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511443663] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:41,630 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:41,630 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:41,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923781389] [2025-03-16 19:04:41,630 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:41,631 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:41,631 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:41,632 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:41,632 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:41,632 INFO L87 Difference]: Start difference. First operand 167 states and 250 transitions. Second operand has 4 states, 4 states have (on average 7.5) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-16 19:04:41,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:41,682 INFO L93 Difference]: Finished difference Result 322 states and 491 transitions. [2025-03-16 19:04:41,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:41,683 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 7.5) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 34 [2025-03-16 19:04:41,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:41,684 INFO L225 Difference]: With dead ends: 322 [2025-03-16 19:04:41,684 INFO L226 Difference]: Without dead ends: 171 [2025-03-16 19:04:41,685 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:41,685 INFO L435 NwaCegarLoop]: 244 mSDtfsCounter, 3 mSDsluCounter, 478 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 722 SdHoareTripleChecker+Invalid, 27 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:41,685 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 722 Invalid, 27 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 24 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:41,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2025-03-16 19:04:41,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 171. [2025-03-16 19:04:41,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 171 states, 131 states have (on average 1.4580152671755726) internal successors, (191), 132 states have internal predecessors, (191), 31 states have call successors, (31), 8 states have call predecessors, (31), 8 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-16 19:04:41,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 253 transitions. [2025-03-16 19:04:41,700 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 253 transitions. Word has length 34 [2025-03-16 19:04:41,700 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:41,701 INFO L471 AbstractCegarLoop]: Abstraction has 171 states and 253 transitions. [2025-03-16 19:04:41,701 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 7.5) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-16 19:04:41,701 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 253 transitions. [2025-03-16 19:04:41,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2025-03-16 19:04:41,702 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:41,702 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:41,703 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2025-03-16 19:04:41,703 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:41,703 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:41,703 INFO L85 PathProgramCache]: Analyzing trace with hash -2092282983, now seen corresponding path program 1 times [2025-03-16 19:04:41,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:41,703 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436751186] [2025-03-16 19:04:41,703 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:41,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:41,714 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 48 statements into 1 equivalence classes. [2025-03-16 19:04:41,725 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 48 of 48 statements. [2025-03-16 19:04:41,725 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:41,725 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:41,794 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:41,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:41,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436751186] [2025-03-16 19:04:41,794 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1436751186] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:41,795 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:41,795 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-16 19:04:41,795 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987934142] [2025-03-16 19:04:41,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:41,795 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-03-16 19:04:41,795 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:41,795 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-16 19:04:41,795 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-16 19:04:41,795 INFO L87 Difference]: Start difference. First operand 171 states and 253 transitions. Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:41,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:41,830 INFO L93 Difference]: Finished difference Result 470 states and 705 transitions. [2025-03-16 19:04:41,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-16 19:04:41,830 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 48 [2025-03-16 19:04:41,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:41,832 INFO L225 Difference]: With dead ends: 470 [2025-03-16 19:04:41,832 INFO L226 Difference]: Without dead ends: 315 [2025-03-16 19:04:41,833 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-16 19:04:41,833 INFO L435 NwaCegarLoop]: 258 mSDtfsCounter, 206 mSDsluCounter, 242 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 206 SdHoareTripleChecker+Valid, 500 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:41,833 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [206 Valid, 500 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:41,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 315 states. [2025-03-16 19:04:41,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 315 to 312. [2025-03-16 19:04:41,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 312 states, 235 states have (on average 1.4723404255319148) internal successors, (346), 237 states have internal predecessors, (346), 60 states have call successors, (60), 16 states have call predecessors, (60), 16 states have return successors, (60), 59 states have call predecessors, (60), 60 states have call successors, (60) [2025-03-16 19:04:41,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 312 states and 466 transitions. [2025-03-16 19:04:41,865 INFO L78 Accepts]: Start accepts. Automaton has 312 states and 466 transitions. Word has length 48 [2025-03-16 19:04:41,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:41,865 INFO L471 AbstractCegarLoop]: Abstraction has 312 states and 466 transitions. [2025-03-16 19:04:41,866 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:41,866 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 466 transitions. [2025-03-16 19:04:41,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2025-03-16 19:04:41,867 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:41,867 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:41,868 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2025-03-16 19:04:41,868 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:41,868 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:41,868 INFO L85 PathProgramCache]: Analyzing trace with hash -1797449454, now seen corresponding path program 1 times [2025-03-16 19:04:41,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:41,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140818494] [2025-03-16 19:04:41,868 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:41,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:41,881 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-03-16 19:04:41,893 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-03-16 19:04:41,895 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:41,895 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:41,933 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:41,933 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:41,933 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140818494] [2025-03-16 19:04:41,933 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140818494] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:41,933 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:41,933 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-16 19:04:41,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415544557] [2025-03-16 19:04:41,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:41,934 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-03-16 19:04:41,934 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:41,934 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-16 19:04:41,934 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-16 19:04:41,934 INFO L87 Difference]: Start difference. First operand 312 states and 466 transitions. Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:41,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:41,986 INFO L93 Difference]: Finished difference Result 879 states and 1323 transitions. [2025-03-16 19:04:41,986 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-16 19:04:41,986 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 49 [2025-03-16 19:04:41,986 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:41,991 INFO L225 Difference]: With dead ends: 879 [2025-03-16 19:04:41,991 INFO L226 Difference]: Without dead ends: 583 [2025-03-16 19:04:41,992 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-16 19:04:41,993 INFO L435 NwaCegarLoop]: 277 mSDtfsCounter, 207 mSDsluCounter, 244 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 207 SdHoareTripleChecker+Valid, 521 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:41,993 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [207 Valid, 521 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:41,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 583 states. [2025-03-16 19:04:42,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 583 to 577. [2025-03-16 19:04:42,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 577 states, 428 states have (on average 1.4813084112149533) internal successors, (634), 432 states have internal predecessors, (634), 117 states have call successors, (117), 31 states have call predecessors, (117), 31 states have return successors, (117), 114 states have call predecessors, (117), 117 states have call successors, (117) [2025-03-16 19:04:42,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 577 states to 577 states and 868 transitions. [2025-03-16 19:04:42,032 INFO L78 Accepts]: Start accepts. Automaton has 577 states and 868 transitions. Word has length 49 [2025-03-16 19:04:42,033 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:42,034 INFO L471 AbstractCegarLoop]: Abstraction has 577 states and 868 transitions. [2025-03-16 19:04:42,034 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:42,034 INFO L276 IsEmpty]: Start isEmpty. Operand 577 states and 868 transitions. [2025-03-16 19:04:42,036 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2025-03-16 19:04:42,037 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:42,037 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:42,037 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2025-03-16 19:04:42,037 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:42,038 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:42,038 INFO L85 PathProgramCache]: Analyzing trace with hash -289897645, now seen corresponding path program 1 times [2025-03-16 19:04:42,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:42,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772693308] [2025-03-16 19:04:42,038 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:42,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:42,048 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-03-16 19:04:42,095 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-03-16 19:04:42,095 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:42,095 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:42,175 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:42,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:42,175 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1772693308] [2025-03-16 19:04:42,175 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1772693308] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:42,175 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:42,175 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-16 19:04:42,175 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577559361] [2025-03-16 19:04:42,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:42,176 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-03-16 19:04:42,176 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:42,176 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-16 19:04:42,176 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:42,176 INFO L87 Difference]: Start difference. First operand 577 states and 868 transitions. Second operand has 5 states, 5 states have (on average 7.6) internal successors, (38), 5 states have internal predecessors, (38), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:42,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:42,347 INFO L93 Difference]: Finished difference Result 1225 states and 1842 transitions. [2025-03-16 19:04:42,347 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-16 19:04:42,347 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 7.6) internal successors, (38), 5 states have internal predecessors, (38), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 49 [2025-03-16 19:04:42,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:42,353 INFO L225 Difference]: With dead ends: 1225 [2025-03-16 19:04:42,353 INFO L226 Difference]: Without dead ends: 664 [2025-03-16 19:04:42,355 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:04:42,355 INFO L435 NwaCegarLoop]: 219 mSDtfsCounter, 337 mSDsluCounter, 430 mSDsCounter, 0 mSdLazyCounter, 91 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 337 SdHoareTripleChecker+Valid, 649 SdHoareTripleChecker+Invalid, 105 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 91 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:42,356 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [337 Valid, 649 Invalid, 105 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 91 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:42,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 664 states. [2025-03-16 19:04:42,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 664 to 660. [2025-03-16 19:04:42,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 660 states, 498 states have (on average 1.4678714859437751) internal successors, (731), 501 states have internal predecessors, (731), 124 states have call successors, (124), 37 states have call predecessors, (124), 37 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:42,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 660 states to 660 states and 979 transitions. [2025-03-16 19:04:42,409 INFO L78 Accepts]: Start accepts. Automaton has 660 states and 979 transitions. Word has length 49 [2025-03-16 19:04:42,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:42,410 INFO L471 AbstractCegarLoop]: Abstraction has 660 states and 979 transitions. [2025-03-16 19:04:42,410 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 7.6) internal successors, (38), 5 states have internal predecessors, (38), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:42,410 INFO L276 IsEmpty]: Start isEmpty. Operand 660 states and 979 transitions. [2025-03-16 19:04:42,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2025-03-16 19:04:42,414 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:42,414 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:42,414 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2025-03-16 19:04:42,414 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:42,414 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:42,415 INFO L85 PathProgramCache]: Analyzing trace with hash -1486629471, now seen corresponding path program 1 times [2025-03-16 19:04:42,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:42,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456291086] [2025-03-16 19:04:42,415 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:42,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:42,427 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-03-16 19:04:42,449 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-16 19:04:42,449 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:42,449 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:42,549 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:42,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:42,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456291086] [2025-03-16 19:04:42,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [456291086] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:42,550 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:42,550 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-16 19:04:42,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [989921466] [2025-03-16 19:04:42,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:42,550 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-03-16 19:04:42,550 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:42,550 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-16 19:04:42,550 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:42,551 INFO L87 Difference]: Start difference. First operand 660 states and 979 transitions. Second operand has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:42,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:42,705 INFO L93 Difference]: Finished difference Result 1225 states and 1834 transitions. [2025-03-16 19:04:42,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-16 19:04:42,705 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 50 [2025-03-16 19:04:42,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:42,710 INFO L225 Difference]: With dead ends: 1225 [2025-03-16 19:04:42,710 INFO L226 Difference]: Without dead ends: 664 [2025-03-16 19:04:42,712 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:04:42,713 INFO L435 NwaCegarLoop]: 220 mSDtfsCounter, 334 mSDsluCounter, 432 mSDsCounter, 0 mSdLazyCounter, 88 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 334 SdHoareTripleChecker+Valid, 652 SdHoareTripleChecker+Invalid, 101 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 88 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:42,713 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [334 Valid, 652 Invalid, 101 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 88 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:42,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 664 states. [2025-03-16 19:04:42,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 664 to 660. [2025-03-16 19:04:42,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 660 states, 498 states have (on average 1.4598393574297188) internal successors, (727), 501 states have internal predecessors, (727), 124 states have call successors, (124), 37 states have call predecessors, (124), 37 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:42,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 660 states to 660 states and 975 transitions. [2025-03-16 19:04:42,757 INFO L78 Accepts]: Start accepts. Automaton has 660 states and 975 transitions. Word has length 50 [2025-03-16 19:04:42,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:42,757 INFO L471 AbstractCegarLoop]: Abstraction has 660 states and 975 transitions. [2025-03-16 19:04:42,757 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:42,757 INFO L276 IsEmpty]: Start isEmpty. Operand 660 states and 975 transitions. [2025-03-16 19:04:42,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2025-03-16 19:04:42,759 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:42,759 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:42,759 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2025-03-16 19:04:42,759 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:42,759 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:42,759 INFO L85 PathProgramCache]: Analyzing trace with hash -1232883730, now seen corresponding path program 1 times [2025-03-16 19:04:42,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:42,759 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [638551171] [2025-03-16 19:04:42,760 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:42,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:42,773 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-03-16 19:04:42,792 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-16 19:04:42,793 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:42,793 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:42,926 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:42,926 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:42,926 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [638551171] [2025-03-16 19:04:42,926 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [638551171] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:42,926 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:42,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:42,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1862956221] [2025-03-16 19:04:42,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:42,927 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:42,927 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:42,927 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:42,927 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:42,927 INFO L87 Difference]: Start difference. First operand 660 states and 975 transitions. Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (5), 3 states have call predecessors, (5), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2025-03-16 19:04:42,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:42,981 INFO L93 Difference]: Finished difference Result 1241 states and 1854 transitions. [2025-03-16 19:04:42,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:42,982 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (5), 3 states have call predecessors, (5), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 51 [2025-03-16 19:04:42,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:42,985 INFO L225 Difference]: With dead ends: 1241 [2025-03-16 19:04:42,987 INFO L226 Difference]: Without dead ends: 680 [2025-03-16 19:04:42,990 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:42,990 INFO L435 NwaCegarLoop]: 246 mSDtfsCounter, 4 mSDsluCounter, 488 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 734 SdHoareTripleChecker+Invalid, 16 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:42,990 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 734 Invalid, 16 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:42,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 680 states. [2025-03-16 19:04:43,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 680 to 680. [2025-03-16 19:04:43,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 680 states, 514 states have (on average 1.4455252918287937) internal successors, (743), 517 states have internal predecessors, (743), 124 states have call successors, (124), 41 states have call predecessors, (124), 41 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:43,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 991 transitions. [2025-03-16 19:04:43,025 INFO L78 Accepts]: Start accepts. Automaton has 680 states and 991 transitions. Word has length 51 [2025-03-16 19:04:43,025 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:43,025 INFO L471 AbstractCegarLoop]: Abstraction has 680 states and 991 transitions. [2025-03-16 19:04:43,026 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (5), 3 states have call predecessors, (5), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2025-03-16 19:04:43,026 INFO L276 IsEmpty]: Start isEmpty. Operand 680 states and 991 transitions. [2025-03-16 19:04:43,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2025-03-16 19:04:43,026 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:43,026 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:43,027 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2025-03-16 19:04:43,027 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:43,027 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:43,027 INFO L85 PathProgramCache]: Analyzing trace with hash 397604752, now seen corresponding path program 1 times [2025-03-16 19:04:43,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:43,027 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876438999] [2025-03-16 19:04:43,027 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:43,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:43,037 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 59 statements into 1 equivalence classes. [2025-03-16 19:04:43,047 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 59 of 59 statements. [2025-03-16 19:04:43,047 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:43,047 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:43,172 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:43,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:43,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [876438999] [2025-03-16 19:04:43,173 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [876438999] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:43,173 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:43,173 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:43,173 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [283246117] [2025-03-16 19:04:43,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:43,173 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:43,173 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:43,173 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:43,173 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:43,174 INFO L87 Difference]: Start difference. First operand 680 states and 991 transitions. Second operand has 4 states, 4 states have (on average 11.5) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (4), 1 states have call predecessors, (4), 1 states have call successors, (4) [2025-03-16 19:04:43,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:43,237 INFO L93 Difference]: Finished difference Result 1281 states and 1898 transitions. [2025-03-16 19:04:43,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:43,238 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 11.5) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (4), 1 states have call predecessors, (4), 1 states have call successors, (4) Word has length 59 [2025-03-16 19:04:43,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:43,242 INFO L225 Difference]: With dead ends: 1281 [2025-03-16 19:04:43,242 INFO L226 Difference]: Without dead ends: 700 [2025-03-16 19:04:43,243 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:43,246 INFO L435 NwaCegarLoop]: 243 mSDtfsCounter, 4 mSDsluCounter, 477 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 720 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:43,247 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 720 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:43,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 700 states. [2025-03-16 19:04:43,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 700 to 700. [2025-03-16 19:04:43,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 700 states, 530 states have (on average 1.4320754716981132) internal successors, (759), 533 states have internal predecessors, (759), 124 states have call successors, (124), 45 states have call predecessors, (124), 45 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:43,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 700 states to 700 states and 1007 transitions. [2025-03-16 19:04:43,284 INFO L78 Accepts]: Start accepts. Automaton has 700 states and 1007 transitions. Word has length 59 [2025-03-16 19:04:43,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:43,284 INFO L471 AbstractCegarLoop]: Abstraction has 700 states and 1007 transitions. [2025-03-16 19:04:43,284 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 11.5) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (4), 1 states have call predecessors, (4), 1 states have call successors, (4) [2025-03-16 19:04:43,284 INFO L276 IsEmpty]: Start isEmpty. Operand 700 states and 1007 transitions. [2025-03-16 19:04:43,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-03-16 19:04:43,285 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:43,285 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:43,285 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2025-03-16 19:04:43,285 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:43,286 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:43,286 INFO L85 PathProgramCache]: Analyzing trace with hash 747515766, now seen corresponding path program 1 times [2025-03-16 19:04:43,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:43,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441783046] [2025-03-16 19:04:43,286 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:43,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:43,296 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-03-16 19:04:43,309 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-03-16 19:04:43,309 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:43,309 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:43,415 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:43,415 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:43,415 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1441783046] [2025-03-16 19:04:43,415 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1441783046] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:43,415 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:43,415 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:43,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095141582] [2025-03-16 19:04:43,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:43,416 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:43,416 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:43,416 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:43,416 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:43,416 INFO L87 Difference]: Start difference. First operand 700 states and 1007 transitions. Second operand has 4 states, 4 states have (on average 13.0) internal successors, (52), 3 states have internal predecessors, (52), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-16 19:04:43,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:43,471 INFO L93 Difference]: Finished difference Result 1317 states and 1914 transitions. [2025-03-16 19:04:43,471 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:43,471 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 13.0) internal successors, (52), 3 states have internal predecessors, (52), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 67 [2025-03-16 19:04:43,472 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:43,476 INFO L225 Difference]: With dead ends: 1317 [2025-03-16 19:04:43,476 INFO L226 Difference]: Without dead ends: 716 [2025-03-16 19:04:43,478 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:43,478 INFO L435 NwaCegarLoop]: 248 mSDtfsCounter, 3 mSDsluCounter, 482 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 730 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:43,478 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 730 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:43,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 716 states. [2025-03-16 19:04:43,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 716 to 716. [2025-03-16 19:04:43,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 716 states, 542 states have (on average 1.4225092250922509) internal successors, (771), 545 states have internal predecessors, (771), 124 states have call successors, (124), 49 states have call predecessors, (124), 49 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:43,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 716 states and 1019 transitions. [2025-03-16 19:04:43,521 INFO L78 Accepts]: Start accepts. Automaton has 716 states and 1019 transitions. Word has length 67 [2025-03-16 19:04:43,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:43,522 INFO L471 AbstractCegarLoop]: Abstraction has 716 states and 1019 transitions. [2025-03-16 19:04:43,522 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 13.0) internal successors, (52), 3 states have internal predecessors, (52), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-16 19:04:43,522 INFO L276 IsEmpty]: Start isEmpty. Operand 716 states and 1019 transitions. [2025-03-16 19:04:43,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2025-03-16 19:04:43,523 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:43,523 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:43,523 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2025-03-16 19:04:43,523 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:43,523 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:43,523 INFO L85 PathProgramCache]: Analyzing trace with hash 115587503, now seen corresponding path program 1 times [2025-03-16 19:04:43,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:43,524 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297281292] [2025-03-16 19:04:43,524 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:43,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:43,534 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-03-16 19:04:43,549 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-03-16 19:04:43,550 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:43,550 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:43,654 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:43,655 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:43,655 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297281292] [2025-03-16 19:04:43,655 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1297281292] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:43,655 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:43,655 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:43,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [44081432] [2025-03-16 19:04:43,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:43,655 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:43,655 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:43,656 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:43,656 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:43,656 INFO L87 Difference]: Start difference. First operand 716 states and 1019 transitions. Second operand has 4 states, 4 states have (on average 13.0) internal successors, (52), 3 states have internal predecessors, (52), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-16 19:04:43,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:43,714 INFO L93 Difference]: Finished difference Result 1353 states and 1954 transitions. [2025-03-16 19:04:43,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:43,715 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 13.0) internal successors, (52), 3 states have internal predecessors, (52), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 67 [2025-03-16 19:04:43,715 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:43,720 INFO L225 Difference]: With dead ends: 1353 [2025-03-16 19:04:43,720 INFO L226 Difference]: Without dead ends: 736 [2025-03-16 19:04:43,721 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:43,722 INFO L435 NwaCegarLoop]: 243 mSDtfsCounter, 4 mSDsluCounter, 477 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 720 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:43,722 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 720 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:43,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 736 states. [2025-03-16 19:04:43,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 736 to 736. [2025-03-16 19:04:43,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 736 states, 558 states have (on average 1.4103942652329748) internal successors, (787), 561 states have internal predecessors, (787), 124 states have call successors, (124), 53 states have call predecessors, (124), 53 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:43,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 736 states to 736 states and 1035 transitions. [2025-03-16 19:04:43,757 INFO L78 Accepts]: Start accepts. Automaton has 736 states and 1035 transitions. Word has length 67 [2025-03-16 19:04:43,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:43,758 INFO L471 AbstractCegarLoop]: Abstraction has 736 states and 1035 transitions. [2025-03-16 19:04:43,758 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 13.0) internal successors, (52), 3 states have internal predecessors, (52), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-16 19:04:43,758 INFO L276 IsEmpty]: Start isEmpty. Operand 736 states and 1035 transitions. [2025-03-16 19:04:43,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2025-03-16 19:04:43,771 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:43,771 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:43,771 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2025-03-16 19:04:43,771 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:43,771 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:43,771 INFO L85 PathProgramCache]: Analyzing trace with hash 1082329389, now seen corresponding path program 1 times [2025-03-16 19:04:43,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:43,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672801948] [2025-03-16 19:04:43,771 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:43,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:43,780 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-16 19:04:43,790 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-16 19:04:43,790 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:43,790 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:43,906 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-16 19:04:43,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:43,907 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [672801948] [2025-03-16 19:04:43,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [672801948] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:43,907 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:43,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:43,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [24403513] [2025-03-16 19:04:43,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:43,907 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:43,907 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:43,907 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:43,907 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:43,907 INFO L87 Difference]: Start difference. First operand 736 states and 1035 transitions. Second operand has 4 states, 4 states have (on average 13.5) internal successors, (54), 3 states have internal predecessors, (54), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 1 states have call predecessors, (6), 1 states have call successors, (6) [2025-03-16 19:04:43,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:43,958 INFO L93 Difference]: Finished difference Result 1397 states and 1982 transitions. [2025-03-16 19:04:43,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:43,959 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 13.5) internal successors, (54), 3 states have internal predecessors, (54), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 1 states have call predecessors, (6), 1 states have call successors, (6) Word has length 75 [2025-03-16 19:04:43,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:43,962 INFO L225 Difference]: With dead ends: 1397 [2025-03-16 19:04:43,962 INFO L226 Difference]: Without dead ends: 760 [2025-03-16 19:04:43,964 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:43,964 INFO L435 NwaCegarLoop]: 247 mSDtfsCounter, 5 mSDsluCounter, 485 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 732 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:43,964 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 732 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 20 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:43,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 760 states. [2025-03-16 19:04:43,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 760 to 760. [2025-03-16 19:04:43,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 760 states, 578 states have (on average 1.3961937716262975) internal successors, (807), 581 states have internal predecessors, (807), 124 states have call successors, (124), 57 states have call predecessors, (124), 57 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:43,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 760 states to 760 states and 1055 transitions. [2025-03-16 19:04:43,995 INFO L78 Accepts]: Start accepts. Automaton has 760 states and 1055 transitions. Word has length 75 [2025-03-16 19:04:43,995 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:43,995 INFO L471 AbstractCegarLoop]: Abstraction has 760 states and 1055 transitions. [2025-03-16 19:04:43,996 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 13.5) internal successors, (54), 3 states have internal predecessors, (54), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 1 states have call predecessors, (6), 1 states have call successors, (6) [2025-03-16 19:04:43,996 INFO L276 IsEmpty]: Start isEmpty. Operand 760 states and 1055 transitions. [2025-03-16 19:04:43,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2025-03-16 19:04:43,997 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:43,997 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:43,997 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2025-03-16 19:04:43,997 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:43,997 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:43,998 INFO L85 PathProgramCache]: Analyzing trace with hash -1566868948, now seen corresponding path program 1 times [2025-03-16 19:04:43,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:43,998 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585932642] [2025-03-16 19:04:43,998 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:43,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:44,006 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-16 19:04:44,054 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-16 19:04:44,054 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:44,054 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:44,404 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2025-03-16 19:04:44,405 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:44,405 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1585932642] [2025-03-16 19:04:44,405 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1585932642] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:44,405 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:44,405 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-16 19:04:44,405 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854365925] [2025-03-16 19:04:44,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:44,405 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-16 19:04:44,405 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:44,406 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-16 19:04:44,406 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:04:44,406 INFO L87 Difference]: Start difference. First operand 760 states and 1055 transitions. Second operand has 7 states, 7 states have (on average 8.142857142857142) internal successors, (57), 6 states have internal predecessors, (57), 3 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 4 states have call predecessors, (7), 3 states have call successors, (7) [2025-03-16 19:04:44,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:44,646 INFO L93 Difference]: Finished difference Result 1979 states and 2733 transitions. [2025-03-16 19:04:44,646 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-16 19:04:44,646 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 8.142857142857142) internal successors, (57), 6 states have internal predecessors, (57), 3 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 4 states have call predecessors, (7), 3 states have call successors, (7) Word has length 78 [2025-03-16 19:04:44,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:44,652 INFO L225 Difference]: With dead ends: 1979 [2025-03-16 19:04:44,652 INFO L226 Difference]: Without dead ends: 1318 [2025-03-16 19:04:44,654 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2025-03-16 19:04:44,654 INFO L435 NwaCegarLoop]: 250 mSDtfsCounter, 194 mSDsluCounter, 1155 mSDsCounter, 0 mSdLazyCounter, 101 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 198 SdHoareTripleChecker+Valid, 1405 SdHoareTripleChecker+Invalid, 102 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 101 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:44,654 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [198 Valid, 1405 Invalid, 102 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 101 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:44,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1318 states. [2025-03-16 19:04:44,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1318 to 1036. [2025-03-16 19:04:44,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1036 states, 781 states have (on average 1.3841229193341869) internal successors, (1081), 786 states have internal predecessors, (1081), 172 states have call successors, (172), 82 states have call predecessors, (172), 82 states have return successors, (172), 167 states have call predecessors, (172), 172 states have call successors, (172) [2025-03-16 19:04:44,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1036 states to 1036 states and 1425 transitions. [2025-03-16 19:04:44,705 INFO L78 Accepts]: Start accepts. Automaton has 1036 states and 1425 transitions. Word has length 78 [2025-03-16 19:04:44,705 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:44,705 INFO L471 AbstractCegarLoop]: Abstraction has 1036 states and 1425 transitions. [2025-03-16 19:04:44,706 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 8.142857142857142) internal successors, (57), 6 states have internal predecessors, (57), 3 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 4 states have call predecessors, (7), 3 states have call successors, (7) [2025-03-16 19:04:44,706 INFO L276 IsEmpty]: Start isEmpty. Operand 1036 states and 1425 transitions. [2025-03-16 19:04:44,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2025-03-16 19:04:44,706 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:44,707 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:44,707 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2025-03-16 19:04:44,707 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:44,707 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:44,707 INFO L85 PathProgramCache]: Analyzing trace with hash 934757295, now seen corresponding path program 1 times [2025-03-16 19:04:44,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:44,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341166564] [2025-03-16 19:04:44,707 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:44,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:44,715 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 82 statements into 1 equivalence classes. [2025-03-16 19:04:44,730 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 82 of 82 statements. [2025-03-16 19:04:44,730 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:44,730 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:44,837 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2025-03-16 19:04:44,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:44,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [341166564] [2025-03-16 19:04:44,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [341166564] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:44,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:44,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:44,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246219029] [2025-03-16 19:04:44,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:44,837 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:44,837 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:44,838 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:44,838 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:44,838 INFO L87 Difference]: Start difference. First operand 1036 states and 1425 transitions. Second operand has 4 states, 4 states have (on average 15.25) internal successors, (61), 3 states have internal predecessors, (61), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-16 19:04:44,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:44,906 INFO L93 Difference]: Finished difference Result 1937 states and 2682 transitions. [2025-03-16 19:04:44,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:44,906 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.25) internal successors, (61), 3 states have internal predecessors, (61), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) Word has length 82 [2025-03-16 19:04:44,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:44,915 INFO L225 Difference]: With dead ends: 1937 [2025-03-16 19:04:44,915 INFO L226 Difference]: Without dead ends: 1060 [2025-03-16 19:04:44,917 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:44,917 INFO L435 NwaCegarLoop]: 248 mSDtfsCounter, 3 mSDsluCounter, 482 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 730 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:44,917 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 730 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:44,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1060 states. [2025-03-16 19:04:44,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1060 to 1060. [2025-03-16 19:04:44,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1060 states, 799 states have (on average 1.3754693366708386) internal successors, (1099), 804 states have internal predecessors, (1099), 172 states have call successors, (172), 88 states have call predecessors, (172), 88 states have return successors, (172), 167 states have call predecessors, (172), 172 states have call successors, (172) [2025-03-16 19:04:44,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1060 states to 1060 states and 1443 transitions. [2025-03-16 19:04:44,968 INFO L78 Accepts]: Start accepts. Automaton has 1060 states and 1443 transitions. Word has length 82 [2025-03-16 19:04:44,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:44,969 INFO L471 AbstractCegarLoop]: Abstraction has 1060 states and 1443 transitions. [2025-03-16 19:04:44,969 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.25) internal successors, (61), 3 states have internal predecessors, (61), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-16 19:04:44,969 INFO L276 IsEmpty]: Start isEmpty. Operand 1060 states and 1443 transitions. [2025-03-16 19:04:44,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2025-03-16 19:04:44,970 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:44,970 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:44,970 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2025-03-16 19:04:44,970 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:44,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:44,970 INFO L85 PathProgramCache]: Analyzing trace with hash -1083845131, now seen corresponding path program 1 times [2025-03-16 19:04:44,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:44,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439029219] [2025-03-16 19:04:44,970 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:44,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:44,978 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-16 19:04:44,988 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-16 19:04:44,988 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:44,989 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:45,188 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2025-03-16 19:04:45,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:45,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [439029219] [2025-03-16 19:04:45,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [439029219] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:04:45,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [449034531] [2025-03-16 19:04:45,189 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:45,189 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:04:45,189 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:04:45,191 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:04:45,192 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2025-03-16 19:04:45,260 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-16 19:04:45,300 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-16 19:04:45,300 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:45,301 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:45,303 INFO L256 TraceCheckSpWp]: Trace formula consists of 417 conjuncts, 14 conjuncts are in the unsatisfiable core [2025-03-16 19:04:45,307 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:04:45,397 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2025-03-16 19:04:45,397 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-03-16 19:04:45,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [449034531] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:45,398 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-03-16 19:04:45,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [10] total 15 [2025-03-16 19:04:45,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1851014988] [2025-03-16 19:04:45,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:45,398 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2025-03-16 19:04:45,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:45,399 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-16 19:04:45,399 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=180, Unknown=0, NotChecked=0, Total=210 [2025-03-16 19:04:45,399 INFO L87 Difference]: Start difference. First operand 1060 states and 1443 transitions. Second operand has 8 states, 7 states have (on average 8.142857142857142) internal successors, (57), 7 states have internal predecessors, (57), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-16 19:04:45,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:45,574 INFO L93 Difference]: Finished difference Result 2277 states and 3217 transitions. [2025-03-16 19:04:45,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-16 19:04:45,574 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 8.142857142857142) internal successors, (57), 7 states have internal predecessors, (57), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) Word has length 81 [2025-03-16 19:04:45,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:45,582 INFO L225 Difference]: With dead ends: 2277 [2025-03-16 19:04:45,582 INFO L226 Difference]: Without dead ends: 1464 [2025-03-16 19:04:45,584 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 78 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=261, Unknown=0, NotChecked=0, Total=306 [2025-03-16 19:04:45,585 INFO L435 NwaCegarLoop]: 417 mSDtfsCounter, 129 mSDsluCounter, 2312 mSDsCounter, 0 mSdLazyCounter, 124 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 155 SdHoareTripleChecker+Valid, 2729 SdHoareTripleChecker+Invalid, 126 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 124 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:45,585 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [155 Valid, 2729 Invalid, 126 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 124 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:45,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1464 states. [2025-03-16 19:04:45,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1464 to 1068. [2025-03-16 19:04:45,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1068 states, 803 states have (on average 1.3661270236612701) internal successors, (1097), 810 states have internal predecessors, (1097), 174 states have call successors, (174), 90 states have call predecessors, (174), 90 states have return successors, (174), 167 states have call predecessors, (174), 174 states have call successors, (174) [2025-03-16 19:04:45,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1068 states to 1068 states and 1445 transitions. [2025-03-16 19:04:45,658 INFO L78 Accepts]: Start accepts. Automaton has 1068 states and 1445 transitions. Word has length 81 [2025-03-16 19:04:45,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:45,658 INFO L471 AbstractCegarLoop]: Abstraction has 1068 states and 1445 transitions. [2025-03-16 19:04:45,658 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 8.142857142857142) internal successors, (57), 7 states have internal predecessors, (57), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-16 19:04:45,658 INFO L276 IsEmpty]: Start isEmpty. Operand 1068 states and 1445 transitions. [2025-03-16 19:04:45,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2025-03-16 19:04:45,659 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:45,659 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:45,669 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2025-03-16 19:04:45,860 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable14 [2025-03-16 19:04:45,860 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:45,860 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:45,860 INFO L85 PathProgramCache]: Analyzing trace with hash -1969924481, now seen corresponding path program 1 times [2025-03-16 19:04:45,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:45,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1419682703] [2025-03-16 19:04:45,861 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:45,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:45,876 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 84 statements into 1 equivalence classes. [2025-03-16 19:04:45,888 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 84 of 84 statements. [2025-03-16 19:04:45,889 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:45,889 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:45,973 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2025-03-16 19:04:45,973 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:45,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1419682703] [2025-03-16 19:04:45,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1419682703] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:45,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:45,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-16 19:04:45,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181820822] [2025-03-16 19:04:45,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:45,975 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-16 19:04:45,975 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:45,975 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-16 19:04:45,975 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:04:45,975 INFO L87 Difference]: Start difference. First operand 1068 states and 1445 transitions. Second operand has 7 states, 7 states have (on average 8.571428571428571) internal successors, (60), 6 states have internal predecessors, (60), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) [2025-03-16 19:04:46,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:46,147 INFO L93 Difference]: Finished difference Result 1924 states and 2606 transitions. [2025-03-16 19:04:46,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-16 19:04:46,148 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 8.571428571428571) internal successors, (60), 6 states have internal predecessors, (60), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) Word has length 84 [2025-03-16 19:04:46,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:46,153 INFO L225 Difference]: With dead ends: 1924 [2025-03-16 19:04:46,153 INFO L226 Difference]: Without dead ends: 1097 [2025-03-16 19:04:46,154 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-16 19:04:46,155 INFO L435 NwaCegarLoop]: 248 mSDtfsCounter, 241 mSDsluCounter, 1176 mSDsCounter, 0 mSdLazyCounter, 70 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 242 SdHoareTripleChecker+Valid, 1424 SdHoareTripleChecker+Invalid, 85 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 70 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:46,155 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [242 Valid, 1424 Invalid, 85 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 70 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:46,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1097 states. [2025-03-16 19:04:46,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1097 to 1063. [2025-03-16 19:04:46,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1063 states, 809 states have (on average 1.362175525339926) internal successors, (1102), 821 states have internal predecessors, (1102), 162 states have call successors, (162), 91 states have call predecessors, (162), 91 states have return successors, (162), 150 states have call predecessors, (162), 162 states have call successors, (162) [2025-03-16 19:04:46,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1063 states to 1063 states and 1426 transitions. [2025-03-16 19:04:46,212 INFO L78 Accepts]: Start accepts. Automaton has 1063 states and 1426 transitions. Word has length 84 [2025-03-16 19:04:46,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:46,212 INFO L471 AbstractCegarLoop]: Abstraction has 1063 states and 1426 transitions. [2025-03-16 19:04:46,212 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 8.571428571428571) internal successors, (60), 6 states have internal predecessors, (60), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) [2025-03-16 19:04:46,213 INFO L276 IsEmpty]: Start isEmpty. Operand 1063 states and 1426 transitions. [2025-03-16 19:04:46,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2025-03-16 19:04:46,213 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:46,214 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:46,214 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2025-03-16 19:04:46,214 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:46,215 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:46,215 INFO L85 PathProgramCache]: Analyzing trace with hash 2116073333, now seen corresponding path program 1 times [2025-03-16 19:04:46,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:46,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217349241] [2025-03-16 19:04:46,215 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:46,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:46,225 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 86 statements into 1 equivalence classes. [2025-03-16 19:04:46,270 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 86 of 86 statements. [2025-03-16 19:04:46,270 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:46,270 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:46,611 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2025-03-16 19:04:46,611 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:46,611 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217349241] [2025-03-16 19:04:46,611 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1217349241] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:46,611 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:46,612 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-16 19:04:46,612 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123452070] [2025-03-16 19:04:46,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:46,612 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-16 19:04:46,612 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:46,612 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-16 19:04:46,612 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:04:46,613 INFO L87 Difference]: Start difference. First operand 1063 states and 1426 transitions. Second operand has 7 states, 7 states have (on average 8.428571428571429) internal successors, (59), 6 states have internal predecessors, (59), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-16 19:04:46,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:46,828 INFO L93 Difference]: Finished difference Result 1903 states and 2559 transitions. [2025-03-16 19:04:46,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-16 19:04:46,829 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 8.428571428571429) internal successors, (59), 6 states have internal predecessors, (59), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) Word has length 86 [2025-03-16 19:04:46,829 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:46,835 INFO L225 Difference]: With dead ends: 1903 [2025-03-16 19:04:46,835 INFO L226 Difference]: Without dead ends: 1061 [2025-03-16 19:04:46,837 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2025-03-16 19:04:46,838 INFO L435 NwaCegarLoop]: 274 mSDtfsCounter, 147 mSDsluCounter, 1252 mSDsCounter, 0 mSdLazyCounter, 77 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 149 SdHoareTripleChecker+Valid, 1526 SdHoareTripleChecker+Invalid, 77 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 77 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:46,838 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [149 Valid, 1526 Invalid, 77 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 77 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:46,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1061 states. [2025-03-16 19:04:46,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1061 to 957. [2025-03-16 19:04:46,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 957 states, 730 states have (on average 1.3643835616438356) internal successors, (996), 740 states have internal predecessors, (996), 145 states have call successors, (145), 81 states have call predecessors, (145), 81 states have return successors, (145), 135 states have call predecessors, (145), 145 states have call successors, (145) [2025-03-16 19:04:46,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 957 states to 957 states and 1286 transitions. [2025-03-16 19:04:46,894 INFO L78 Accepts]: Start accepts. Automaton has 957 states and 1286 transitions. Word has length 86 [2025-03-16 19:04:46,894 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:46,894 INFO L471 AbstractCegarLoop]: Abstraction has 957 states and 1286 transitions. [2025-03-16 19:04:46,895 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 8.428571428571429) internal successors, (59), 6 states have internal predecessors, (59), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-16 19:04:46,895 INFO L276 IsEmpty]: Start isEmpty. Operand 957 states and 1286 transitions. [2025-03-16 19:04:46,895 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2025-03-16 19:04:46,896 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:46,896 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:46,896 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2025-03-16 19:04:46,896 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:46,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:46,896 INFO L85 PathProgramCache]: Analyzing trace with hash 663537944, now seen corresponding path program 1 times [2025-03-16 19:04:46,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:46,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925165196] [2025-03-16 19:04:46,897 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:46,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:46,905 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 87 statements into 1 equivalence classes. [2025-03-16 19:04:46,920 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 87 of 87 statements. [2025-03-16 19:04:46,920 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:46,921 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:47,256 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2025-03-16 19:04:47,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:47,257 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1925165196] [2025-03-16 19:04:47,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1925165196] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:47,257 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:47,257 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2025-03-16 19:04:47,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [324170396] [2025-03-16 19:04:47,257 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:47,257 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2025-03-16 19:04:47,258 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:47,258 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-16 19:04:47,258 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2025-03-16 19:04:47,258 INFO L87 Difference]: Start difference. First operand 957 states and 1286 transitions. Second operand has 8 states, 8 states have (on average 8.0) internal successors, (64), 7 states have internal predecessors, (64), 4 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 5 states have call predecessors, (8), 4 states have call successors, (8) [2025-03-16 19:04:47,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:47,634 INFO L93 Difference]: Finished difference Result 1834 states and 2446 transitions. [2025-03-16 19:04:47,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-16 19:04:47,634 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 8.0) internal successors, (64), 7 states have internal predecessors, (64), 4 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 5 states have call predecessors, (8), 4 states have call successors, (8) Word has length 87 [2025-03-16 19:04:47,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:47,639 INFO L225 Difference]: With dead ends: 1834 [2025-03-16 19:04:47,640 INFO L226 Difference]: Without dead ends: 1018 [2025-03-16 19:04:47,641 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2025-03-16 19:04:47,642 INFO L435 NwaCegarLoop]: 265 mSDtfsCounter, 405 mSDsluCounter, 1104 mSDsCounter, 0 mSdLazyCounter, 249 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 411 SdHoareTripleChecker+Valid, 1369 SdHoareTripleChecker+Invalid, 250 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 249 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:47,642 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [411 Valid, 1369 Invalid, 250 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 249 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-03-16 19:04:47,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1018 states. [2025-03-16 19:04:47,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1018 to 973. [2025-03-16 19:04:47,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 973 states, 738 states have (on average 1.3401084010840107) internal successors, (989), 749 states have internal predecessors, (989), 148 states have call successors, (148), 86 states have call predecessors, (148), 86 states have return successors, (148), 137 states have call predecessors, (148), 148 states have call successors, (148) [2025-03-16 19:04:47,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1285 transitions. [2025-03-16 19:04:47,699 INFO L78 Accepts]: Start accepts. Automaton has 973 states and 1285 transitions. Word has length 87 [2025-03-16 19:04:47,700 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:47,700 INFO L471 AbstractCegarLoop]: Abstraction has 973 states and 1285 transitions. [2025-03-16 19:04:47,700 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 8.0) internal successors, (64), 7 states have internal predecessors, (64), 4 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 5 states have call predecessors, (8), 4 states have call successors, (8) [2025-03-16 19:04:47,700 INFO L276 IsEmpty]: Start isEmpty. Operand 973 states and 1285 transitions. [2025-03-16 19:04:47,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2025-03-16 19:04:47,701 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:47,701 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:47,701 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2025-03-16 19:04:47,701 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:47,701 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:47,701 INFO L85 PathProgramCache]: Analyzing trace with hash -36013975, now seen corresponding path program 1 times [2025-03-16 19:04:47,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:47,702 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179309172] [2025-03-16 19:04:47,702 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:47,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:47,710 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 88 statements into 1 equivalence classes. [2025-03-16 19:04:47,717 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 88 of 88 statements. [2025-03-16 19:04:47,717 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:47,717 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:47,762 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-16 19:04:47,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:47,762 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179309172] [2025-03-16 19:04:47,762 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179309172] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:47,762 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:47,762 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:47,763 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449092779] [2025-03-16 19:04:47,763 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:47,763 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:47,763 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:47,763 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:47,763 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:47,763 INFO L87 Difference]: Start difference. First operand 973 states and 1285 transitions. Second operand has 4 states, 4 states have (on average 16.0) internal successors, (64), 4 states have internal predecessors, (64), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:47,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:47,909 INFO L93 Difference]: Finished difference Result 2585 states and 3430 transitions. [2025-03-16 19:04:47,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-16 19:04:47,909 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 16.0) internal successors, (64), 4 states have internal predecessors, (64), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 88 [2025-03-16 19:04:47,910 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:47,917 INFO L225 Difference]: With dead ends: 2585 [2025-03-16 19:04:47,917 INFO L226 Difference]: Without dead ends: 1804 [2025-03-16 19:04:47,919 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:47,919 INFO L435 NwaCegarLoop]: 447 mSDtfsCounter, 196 mSDsluCounter, 668 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 196 SdHoareTripleChecker+Valid, 1115 SdHoareTripleChecker+Invalid, 41 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:47,920 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [196 Valid, 1115 Invalid, 41 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 34 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:47,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1804 states. [2025-03-16 19:04:48,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1804 to 1695. [2025-03-16 19:04:48,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1695 states, 1270 states have (on average 1.3299212598425196) internal successors, (1689), 1289 states have internal predecessors, (1689), 272 states have call successors, (272), 152 states have call predecessors, (272), 152 states have return successors, (272), 253 states have call predecessors, (272), 272 states have call successors, (272) [2025-03-16 19:04:48,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1695 states to 1695 states and 2233 transitions. [2025-03-16 19:04:48,014 INFO L78 Accepts]: Start accepts. Automaton has 1695 states and 2233 transitions. Word has length 88 [2025-03-16 19:04:48,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:48,014 INFO L471 AbstractCegarLoop]: Abstraction has 1695 states and 2233 transitions. [2025-03-16 19:04:48,015 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 16.0) internal successors, (64), 4 states have internal predecessors, (64), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:48,015 INFO L276 IsEmpty]: Start isEmpty. Operand 1695 states and 2233 transitions. [2025-03-16 19:04:48,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2025-03-16 19:04:48,016 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:48,016 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:48,016 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2025-03-16 19:04:48,016 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:48,016 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:48,016 INFO L85 PathProgramCache]: Analyzing trace with hash -1937241466, now seen corresponding path program 1 times [2025-03-16 19:04:48,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:48,017 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952523316] [2025-03-16 19:04:48,017 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:48,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:48,025 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 90 statements into 1 equivalence classes. [2025-03-16 19:04:48,033 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 90 of 90 statements. [2025-03-16 19:04:48,033 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:48,033 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:48,082 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-16 19:04:48,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:48,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952523316] [2025-03-16 19:04:48,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952523316] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:48,082 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:48,082 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:48,082 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [771385964] [2025-03-16 19:04:48,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:48,083 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:48,083 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:48,083 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:48,083 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:48,083 INFO L87 Difference]: Start difference. First operand 1695 states and 2233 transitions. Second operand has 4 states, 4 states have (on average 16.5) internal successors, (66), 4 states have internal predecessors, (66), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:48,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:48,273 INFO L93 Difference]: Finished difference Result 3950 states and 5224 transitions. [2025-03-16 19:04:48,273 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-16 19:04:48,273 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 16.5) internal successors, (66), 4 states have internal predecessors, (66), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 90 [2025-03-16 19:04:48,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:48,285 INFO L225 Difference]: With dead ends: 3950 [2025-03-16 19:04:48,285 INFO L226 Difference]: Without dead ends: 2525 [2025-03-16 19:04:48,288 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:48,289 INFO L435 NwaCegarLoop]: 465 mSDtfsCounter, 197 mSDsluCounter, 684 mSDsCounter, 0 mSdLazyCounter, 40 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 197 SdHoareTripleChecker+Valid, 1149 SdHoareTripleChecker+Invalid, 45 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 40 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:48,289 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [197 Valid, 1149 Invalid, 45 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 40 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:48,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2525 states. [2025-03-16 19:04:48,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2525 to 2414. [2025-03-16 19:04:48,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2414 states, 1799 states have (on average 1.3229571984435797) internal successors, (2380), 1826 states have internal predecessors, (2380), 396 states have call successors, (396), 218 states have call predecessors, (396), 218 states have return successors, (396), 369 states have call predecessors, (396), 396 states have call successors, (396) [2025-03-16 19:04:48,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2414 states to 2414 states and 3172 transitions. [2025-03-16 19:04:48,424 INFO L78 Accepts]: Start accepts. Automaton has 2414 states and 3172 transitions. Word has length 90 [2025-03-16 19:04:48,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:48,424 INFO L471 AbstractCegarLoop]: Abstraction has 2414 states and 3172 transitions. [2025-03-16 19:04:48,424 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 16.5) internal successors, (66), 4 states have internal predecessors, (66), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:48,424 INFO L276 IsEmpty]: Start isEmpty. Operand 2414 states and 3172 transitions. [2025-03-16 19:04:48,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2025-03-16 19:04:48,426 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:48,426 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:48,426 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2025-03-16 19:04:48,426 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:48,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:48,426 INFO L85 PathProgramCache]: Analyzing trace with hash -1235743698, now seen corresponding path program 1 times [2025-03-16 19:04:48,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:48,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251820404] [2025-03-16 19:04:48,427 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:48,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:48,435 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 90 statements into 1 equivalence classes. [2025-03-16 19:04:48,452 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 90 of 90 statements. [2025-03-16 19:04:48,453 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:48,453 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:48,777 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2025-03-16 19:04:48,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:48,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1251820404] [2025-03-16 19:04:48,777 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1251820404] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:48,777 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:48,777 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-16 19:04:48,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1604099425] [2025-03-16 19:04:48,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:48,778 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-16 19:04:48,778 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:48,778 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-16 19:04:48,778 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:04:48,778 INFO L87 Difference]: Start difference. First operand 2414 states and 3172 transitions. Second operand has 7 states, 7 states have (on average 9.571428571428571) internal successors, (67), 6 states have internal predecessors, (67), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 3 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:49,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:49,282 INFO L93 Difference]: Finished difference Result 4725 states and 6201 transitions. [2025-03-16 19:04:49,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-16 19:04:49,283 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 9.571428571428571) internal successors, (67), 6 states have internal predecessors, (67), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 3 states have call predecessors, (8), 2 states have call successors, (8) Word has length 90 [2025-03-16 19:04:49,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:49,294 INFO L225 Difference]: With dead ends: 4725 [2025-03-16 19:04:49,295 INFO L226 Difference]: Without dead ends: 2667 [2025-03-16 19:04:49,299 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2025-03-16 19:04:49,300 INFO L435 NwaCegarLoop]: 303 mSDtfsCounter, 471 mSDsluCounter, 1082 mSDsCounter, 0 mSdLazyCounter, 183 mSolverCounterSat, 109 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 474 SdHoareTripleChecker+Valid, 1385 SdHoareTripleChecker+Invalid, 292 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 109 IncrementalHoareTripleChecker+Valid, 183 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:49,300 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [474 Valid, 1385 Invalid, 292 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [109 Valid, 183 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2025-03-16 19:04:49,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2667 states. [2025-03-16 19:04:49,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2667 to 2429. [2025-03-16 19:04:49,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2429 states, 1803 states have (on average 1.3200221852468108) internal successors, (2380), 1831 states have internal predecessors, (2380), 403 states have call successors, (403), 222 states have call predecessors, (403), 222 states have return successors, (403), 375 states have call predecessors, (403), 403 states have call successors, (403) [2025-03-16 19:04:49,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2429 states to 2429 states and 3186 transitions. [2025-03-16 19:04:49,461 INFO L78 Accepts]: Start accepts. Automaton has 2429 states and 3186 transitions. Word has length 90 [2025-03-16 19:04:49,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:49,461 INFO L471 AbstractCegarLoop]: Abstraction has 2429 states and 3186 transitions. [2025-03-16 19:04:49,465 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 9.571428571428571) internal successors, (67), 6 states have internal predecessors, (67), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 3 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:49,466 INFO L276 IsEmpty]: Start isEmpty. Operand 2429 states and 3186 transitions. [2025-03-16 19:04:49,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2025-03-16 19:04:49,467 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:49,467 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:49,467 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2025-03-16 19:04:49,469 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:49,469 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:49,469 INFO L85 PathProgramCache]: Analyzing trace with hash 1211470159, now seen corresponding path program 1 times [2025-03-16 19:04:49,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:49,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [997973163] [2025-03-16 19:04:49,469 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:49,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:49,482 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-03-16 19:04:49,489 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-03-16 19:04:49,490 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:49,490 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:49,538 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-16 19:04:49,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:49,538 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [997973163] [2025-03-16 19:04:49,538 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [997973163] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:49,538 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:49,538 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:49,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704385011] [2025-03-16 19:04:49,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:49,539 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:49,539 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:49,539 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:49,539 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:49,539 INFO L87 Difference]: Start difference. First operand 2429 states and 3186 transitions. Second operand has 4 states, 4 states have (on average 17.0) internal successors, (68), 4 states have internal predecessors, (68), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:49,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:49,816 INFO L93 Difference]: Finished difference Result 6242 states and 8221 transitions. [2025-03-16 19:04:49,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-16 19:04:49,816 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 17.0) internal successors, (68), 4 states have internal predecessors, (68), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 92 [2025-03-16 19:04:49,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:49,836 INFO L225 Difference]: With dead ends: 6242 [2025-03-16 19:04:49,836 INFO L226 Difference]: Without dead ends: 4222 [2025-03-16 19:04:49,841 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:49,847 INFO L435 NwaCegarLoop]: 455 mSDtfsCounter, 200 mSDsluCounter, 682 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 200 SdHoareTripleChecker+Valid, 1137 SdHoareTripleChecker+Invalid, 34 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:49,847 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [200 Valid, 1137 Invalid, 34 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:49,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4222 states. [2025-03-16 19:04:50,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4222 to 3915. [2025-03-16 19:04:50,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3915 states, 2878 states have (on average 1.3054204308547603) internal successors, (3757), 2922 states have internal predecessors, (3757), 672 states have call successors, (672), 364 states have call predecessors, (672), 364 states have return successors, (672), 628 states have call predecessors, (672), 672 states have call successors, (672) [2025-03-16 19:04:50,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3915 states to 3915 states and 5101 transitions. [2025-03-16 19:04:50,118 INFO L78 Accepts]: Start accepts. Automaton has 3915 states and 5101 transitions. Word has length 92 [2025-03-16 19:04:50,118 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:50,118 INFO L471 AbstractCegarLoop]: Abstraction has 3915 states and 5101 transitions. [2025-03-16 19:04:50,118 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 17.0) internal successors, (68), 4 states have internal predecessors, (68), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:50,119 INFO L276 IsEmpty]: Start isEmpty. Operand 3915 states and 5101 transitions. [2025-03-16 19:04:50,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2025-03-16 19:04:50,120 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:50,121 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:50,121 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2025-03-16 19:04:50,121 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:50,121 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:50,122 INFO L85 PathProgramCache]: Analyzing trace with hash 1023239563, now seen corresponding path program 1 times [2025-03-16 19:04:50,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:50,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389833641] [2025-03-16 19:04:50,122 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:50,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:50,132 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 93 statements into 1 equivalence classes. [2025-03-16 19:04:50,137 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 93 of 93 statements. [2025-03-16 19:04:50,137 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:50,137 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:50,163 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-16 19:04:50,163 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:50,163 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [389833641] [2025-03-16 19:04:50,163 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [389833641] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:50,163 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:50,163 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-16 19:04:50,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436561592] [2025-03-16 19:04:50,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:50,164 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-03-16 19:04:50,164 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:50,164 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-16 19:04:50,164 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-16 19:04:50,164 INFO L87 Difference]: Start difference. First operand 3915 states and 5101 transitions. Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:50,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:50,401 INFO L93 Difference]: Finished difference Result 7540 states and 9864 transitions. [2025-03-16 19:04:50,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-16 19:04:50,402 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 93 [2025-03-16 19:04:50,402 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:50,437 INFO L225 Difference]: With dead ends: 7540 [2025-03-16 19:04:50,437 INFO L226 Difference]: Without dead ends: 3948 [2025-03-16 19:04:50,447 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-16 19:04:50,447 INFO L435 NwaCegarLoop]: 249 mSDtfsCounter, 6 mSDsluCounter, 217 mSDsCounter, 0 mSdLazyCounter, 38 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 466 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 38 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:50,448 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 466 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 38 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:50,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3948 states. [2025-03-16 19:04:50,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3948 to 3921. [2025-03-16 19:04:50,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3921 states, 2884 states have (on average 1.3047850208044383) internal successors, (3763), 2928 states have internal predecessors, (3763), 672 states have call successors, (672), 364 states have call predecessors, (672), 364 states have return successors, (672), 628 states have call predecessors, (672), 672 states have call successors, (672) [2025-03-16 19:04:50,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3921 states to 3921 states and 5107 transitions. [2025-03-16 19:04:50,855 INFO L78 Accepts]: Start accepts. Automaton has 3921 states and 5107 transitions. Word has length 93 [2025-03-16 19:04:50,855 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:50,855 INFO L471 AbstractCegarLoop]: Abstraction has 3921 states and 5107 transitions. [2025-03-16 19:04:50,856 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:50,856 INFO L276 IsEmpty]: Start isEmpty. Operand 3921 states and 5107 transitions. [2025-03-16 19:04:50,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2025-03-16 19:04:50,858 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:50,859 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:50,859 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2025-03-16 19:04:50,859 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:50,859 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:50,859 INFO L85 PathProgramCache]: Analyzing trace with hash 2009679848, now seen corresponding path program 1 times [2025-03-16 19:04:50,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:50,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954025715] [2025-03-16 19:04:50,860 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:50,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:50,875 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 94 statements into 1 equivalence classes. [2025-03-16 19:04:50,892 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 94 of 94 statements. [2025-03-16 19:04:50,893 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:50,893 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:50,970 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-16 19:04:50,970 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:50,970 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [954025715] [2025-03-16 19:04:50,970 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [954025715] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:50,970 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:50,971 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:50,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [33520151] [2025-03-16 19:04:50,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:50,971 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:50,971 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:50,972 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:50,972 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:50,973 INFO L87 Difference]: Start difference. First operand 3921 states and 5107 transitions. Second operand has 4 states, 4 states have (on average 17.5) internal successors, (70), 4 states have internal predecessors, (70), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:51,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:51,191 INFO L93 Difference]: Finished difference Result 7505 states and 9791 transitions. [2025-03-16 19:04:51,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:51,191 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 17.5) internal successors, (70), 4 states have internal predecessors, (70), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 94 [2025-03-16 19:04:51,191 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:51,208 INFO L225 Difference]: With dead ends: 7505 [2025-03-16 19:04:51,208 INFO L226 Difference]: Without dead ends: 3647 [2025-03-16 19:04:51,216 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:51,217 INFO L435 NwaCegarLoop]: 253 mSDtfsCounter, 75 mSDsluCounter, 457 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 75 SdHoareTripleChecker+Valid, 710 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:51,217 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [75 Valid, 710 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:51,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3647 states. [2025-03-16 19:04:51,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3647 to 3584. [2025-03-16 19:04:51,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3584 states, 2630 states have (on average 1.3129277566539923) internal successors, (3453), 2664 states have internal predecessors, (3453), 620 states have call successors, (620), 333 states have call predecessors, (620), 333 states have return successors, (620), 586 states have call predecessors, (620), 620 states have call successors, (620) [2025-03-16 19:04:51,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3584 states to 3584 states and 4693 transitions. [2025-03-16 19:04:51,423 INFO L78 Accepts]: Start accepts. Automaton has 3584 states and 4693 transitions. Word has length 94 [2025-03-16 19:04:51,423 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:51,423 INFO L471 AbstractCegarLoop]: Abstraction has 3584 states and 4693 transitions. [2025-03-16 19:04:51,424 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 17.5) internal successors, (70), 4 states have internal predecessors, (70), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:51,424 INFO L276 IsEmpty]: Start isEmpty. Operand 3584 states and 4693 transitions. [2025-03-16 19:04:51,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2025-03-16 19:04:51,425 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:51,425 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:51,425 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2025-03-16 19:04:51,425 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:51,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:51,426 INFO L85 PathProgramCache]: Analyzing trace with hash 1456411104, now seen corresponding path program 1 times [2025-03-16 19:04:51,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:51,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458373490] [2025-03-16 19:04:51,426 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:51,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:51,435 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 95 statements into 1 equivalence classes. [2025-03-16 19:04:51,446 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 95 of 95 statements. [2025-03-16 19:04:51,446 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:51,446 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:51,518 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-16 19:04:51,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:51,518 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458373490] [2025-03-16 19:04:51,518 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1458373490] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:51,518 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:51,518 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:51,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945943317] [2025-03-16 19:04:51,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:51,519 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:51,519 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:51,520 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:51,520 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:51,520 INFO L87 Difference]: Start difference. First operand 3584 states and 4693 transitions. Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 4 states have internal predecessors, (71), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:51,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:51,736 INFO L93 Difference]: Finished difference Result 6989 states and 9167 transitions. [2025-03-16 19:04:51,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:51,737 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 17.75) internal successors, (71), 4 states have internal predecessors, (71), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 95 [2025-03-16 19:04:51,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:51,754 INFO L225 Difference]: With dead ends: 6989 [2025-03-16 19:04:51,754 INFO L226 Difference]: Without dead ends: 3510 [2025-03-16 19:04:51,762 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:51,763 INFO L435 NwaCegarLoop]: 258 mSDtfsCounter, 57 mSDsluCounter, 462 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 57 SdHoareTripleChecker+Valid, 720 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:51,763 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [57 Valid, 720 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:51,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3510 states. [2025-03-16 19:04:51,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3510 to 2698. [2025-03-16 19:04:51,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2698 states, 1978 states have (on average 1.3048533872598584) internal successors, (2581), 1997 states have internal predecessors, (2581), 469 states have call successors, (469), 250 states have call predecessors, (469), 250 states have return successors, (469), 450 states have call predecessors, (469), 469 states have call successors, (469) [2025-03-16 19:04:51,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2698 states to 2698 states and 3519 transitions. [2025-03-16 19:04:51,930 INFO L78 Accepts]: Start accepts. Automaton has 2698 states and 3519 transitions. Word has length 95 [2025-03-16 19:04:51,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:51,931 INFO L471 AbstractCegarLoop]: Abstraction has 2698 states and 3519 transitions. [2025-03-16 19:04:51,931 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 17.75) internal successors, (71), 4 states have internal predecessors, (71), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:51,931 INFO L276 IsEmpty]: Start isEmpty. Operand 2698 states and 3519 transitions. [2025-03-16 19:04:51,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2025-03-16 19:04:51,935 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:51,935 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:51,935 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24 [2025-03-16 19:04:51,935 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:51,935 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:51,936 INFO L85 PathProgramCache]: Analyzing trace with hash 119360947, now seen corresponding path program 1 times [2025-03-16 19:04:51,936 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:51,936 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [985099685] [2025-03-16 19:04:51,936 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:51,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:51,948 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 138 statements into 1 equivalence classes. [2025-03-16 19:04:51,973 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 138 of 138 statements. [2025-03-16 19:04:51,973 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:51,973 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:52,201 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 14 proven. 8 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-16 19:04:52,201 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:52,201 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [985099685] [2025-03-16 19:04:52,201 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [985099685] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:04:52,201 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1757314800] [2025-03-16 19:04:52,201 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:52,201 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:04:52,201 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:04:52,204 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:04:52,205 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2025-03-16 19:04:52,299 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 138 statements into 1 equivalence classes. [2025-03-16 19:04:52,364 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 138 of 138 statements. [2025-03-16 19:04:52,364 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:52,364 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:52,367 INFO L256 TraceCheckSpWp]: Trace formula consists of 645 conjuncts, 23 conjuncts are in the unsatisfiable core [2025-03-16 19:04:52,371 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:04:52,582 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 27 proven. 42 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-16 19:04:52,582 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:04:52,860 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 7 proven. 15 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-16 19:04:52,860 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1757314800] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-16 19:04:52,861 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-16 19:04:52,861 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 11, 8] total 22 [2025-03-16 19:04:52,861 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [848201457] [2025-03-16 19:04:52,861 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-16 19:04:52,861 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 22 states [2025-03-16 19:04:52,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:52,862 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-03-16 19:04:52,863 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=401, Unknown=0, NotChecked=0, Total=462 [2025-03-16 19:04:52,863 INFO L87 Difference]: Start difference. First operand 2698 states and 3519 transitions. Second operand has 22 states, 22 states have (on average 9.772727272727273) internal successors, (215), 20 states have internal predecessors, (215), 9 states have call successors, (41), 4 states have call predecessors, (41), 7 states have return successors, (40), 11 states have call predecessors, (40), 9 states have call successors, (40) [2025-03-16 19:04:56,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:56,633 INFO L93 Difference]: Finished difference Result 11211 states and 14562 transitions. [2025-03-16 19:04:56,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2025-03-16 19:04:56,634 INFO L78 Accepts]: Start accepts. Automaton has has 22 states, 22 states have (on average 9.772727272727273) internal successors, (215), 20 states have internal predecessors, (215), 9 states have call successors, (41), 4 states have call predecessors, (41), 7 states have return successors, (40), 11 states have call predecessors, (40), 9 states have call successors, (40) Word has length 138 [2025-03-16 19:04:56,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:56,671 INFO L225 Difference]: With dead ends: 11211 [2025-03-16 19:04:56,671 INFO L226 Difference]: Without dead ends: 8767 [2025-03-16 19:04:56,684 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 365 GetRequests, 286 SyntacticMatches, 0 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1846 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1180, Invalid=5300, Unknown=0, NotChecked=0, Total=6480 [2025-03-16 19:04:56,684 INFO L435 NwaCegarLoop]: 346 mSDtfsCounter, 4685 mSDsluCounter, 3379 mSDsCounter, 0 mSdLazyCounter, 1495 mSolverCounterSat, 1886 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4685 SdHoareTripleChecker+Valid, 3725 SdHoareTripleChecker+Invalid, 3381 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1886 IncrementalHoareTripleChecker+Valid, 1495 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.8s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:56,685 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4685 Valid, 3725 Invalid, 3381 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1886 Valid, 1495 Invalid, 0 Unknown, 0 Unchecked, 1.8s Time] [2025-03-16 19:04:56,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8767 states. [2025-03-16 19:04:57,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8767 to 7291. [2025-03-16 19:04:57,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7291 states, 5334 states have (on average 1.2971503562054743) internal successors, (6919), 5386 states have internal predecessors, (6919), 1259 states have call successors, (1259), 697 states have call predecessors, (1259), 697 states have return successors, (1259), 1207 states have call predecessors, (1259), 1259 states have call successors, (1259) [2025-03-16 19:04:57,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7291 states to 7291 states and 9437 transitions. [2025-03-16 19:04:57,223 INFO L78 Accepts]: Start accepts. Automaton has 7291 states and 9437 transitions. Word has length 138 [2025-03-16 19:04:57,223 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:57,223 INFO L471 AbstractCegarLoop]: Abstraction has 7291 states and 9437 transitions. [2025-03-16 19:04:57,223 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 22 states, 22 states have (on average 9.772727272727273) internal successors, (215), 20 states have internal predecessors, (215), 9 states have call successors, (41), 4 states have call predecessors, (41), 7 states have return successors, (40), 11 states have call predecessors, (40), 9 states have call successors, (40) [2025-03-16 19:04:57,223 INFO L276 IsEmpty]: Start isEmpty. Operand 7291 states and 9437 transitions. [2025-03-16 19:04:57,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2025-03-16 19:04:57,234 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:57,234 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:57,243 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2025-03-16 19:04:57,435 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable25 [2025-03-16 19:04:57,436 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:57,437 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:57,437 INFO L85 PathProgramCache]: Analyzing trace with hash -369617461, now seen corresponding path program 1 times [2025-03-16 19:04:57,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:57,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280270821] [2025-03-16 19:04:57,437 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:57,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:57,454 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 141 statements into 1 equivalence classes. [2025-03-16 19:04:57,467 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 141 of 141 statements. [2025-03-16 19:04:57,468 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:57,468 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:57,570 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 59 trivial. 0 not checked. [2025-03-16 19:04:57,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:57,570 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280270821] [2025-03-16 19:04:57,570 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280270821] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:57,570 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:57,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-16 19:04:57,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1363350853] [2025-03-16 19:04:57,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:57,571 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-16 19:04:57,571 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:57,572 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-16 19:04:57,572 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:04:57,572 INFO L87 Difference]: Start difference. First operand 7291 states and 9437 transitions. Second operand has 7 states, 7 states have (on average 11.714285714285714) internal successors, (82), 6 states have internal predecessors, (82), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 3 states have call predecessors, (13), 2 states have call successors, (13) [2025-03-16 19:04:58,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:58,592 INFO L93 Difference]: Finished difference Result 21185 states and 27519 transitions. [2025-03-16 19:04:58,592 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-16 19:04:58,593 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 11.714285714285714) internal successors, (82), 6 states have internal predecessors, (82), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 3 states have call predecessors, (13), 2 states have call successors, (13) Word has length 141 [2025-03-16 19:04:58,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:58,650 INFO L225 Difference]: With dead ends: 21185 [2025-03-16 19:04:58,650 INFO L226 Difference]: Without dead ends: 14354 [2025-03-16 19:04:58,670 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-16 19:04:58,670 INFO L435 NwaCegarLoop]: 386 mSDtfsCounter, 216 mSDsluCounter, 1695 mSDsCounter, 0 mSdLazyCounter, 121 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 221 SdHoareTripleChecker+Valid, 2081 SdHoareTripleChecker+Invalid, 121 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 121 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:58,671 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [221 Valid, 2081 Invalid, 121 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 121 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:58,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14354 states. [2025-03-16 19:04:59,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14354 to 12120. [2025-03-16 19:04:59,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12120 states, 8799 states have (on average 1.2963973178770314) internal successors, (11407), 8889 states have internal predecessors, (11407), 2161 states have call successors, (2161), 1159 states have call predecessors, (2161), 1159 states have return successors, (2161), 2071 states have call predecessors, (2161), 2161 states have call successors, (2161) [2025-03-16 19:04:59,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12120 states to 12120 states and 15729 transitions. [2025-03-16 19:04:59,684 INFO L78 Accepts]: Start accepts. Automaton has 12120 states and 15729 transitions. Word has length 141 [2025-03-16 19:04:59,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:59,685 INFO L471 AbstractCegarLoop]: Abstraction has 12120 states and 15729 transitions. [2025-03-16 19:04:59,685 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 11.714285714285714) internal successors, (82), 6 states have internal predecessors, (82), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 3 states have call predecessors, (13), 2 states have call successors, (13) [2025-03-16 19:04:59,685 INFO L276 IsEmpty]: Start isEmpty. Operand 12120 states and 15729 transitions. [2025-03-16 19:04:59,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2025-03-16 19:04:59,705 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:59,705 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:59,705 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable26 [2025-03-16 19:04:59,706 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:59,706 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:59,706 INFO L85 PathProgramCache]: Analyzing trace with hash -1263559743, now seen corresponding path program 1 times [2025-03-16 19:04:59,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:59,706 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546200812] [2025-03-16 19:04:59,706 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:59,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:59,726 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 141 statements into 1 equivalence classes. [2025-03-16 19:04:59,771 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 141 of 141 statements. [2025-03-16 19:04:59,771 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:59,771 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:00,510 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 9 proven. 16 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2025-03-16 19:05:00,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:00,510 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546200812] [2025-03-16 19:05:00,510 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [546200812] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:00,510 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1115951271] [2025-03-16 19:05:00,510 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:00,511 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:00,511 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:05:00,513 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:05:00,514 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2025-03-16 19:05:00,608 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 141 statements into 1 equivalence classes. [2025-03-16 19:05:00,672 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 141 of 141 statements. [2025-03-16 19:05:00,673 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:00,673 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:00,676 INFO L256 TraceCheckSpWp]: Trace formula consists of 679 conjuncts, 31 conjuncts are in the unsatisfiable core [2025-03-16 19:05:00,680 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:00,892 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 48 proven. 20 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-16 19:05:00,892 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:05:01,096 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2025-03-16 19:05:01,096 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1115951271] provided 1 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:01,096 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2025-03-16 19:05:01,097 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [9, 11] total 25 [2025-03-16 19:05:01,097 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575428874] [2025-03-16 19:05:01,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:05:01,097 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2025-03-16 19:05:01,097 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:01,098 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-16 19:05:01,098 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=533, Unknown=0, NotChecked=0, Total=600 [2025-03-16 19:05:01,098 INFO L87 Difference]: Start difference. First operand 12120 states and 15729 transitions. Second operand has 9 states, 8 states have (on average 10.5) internal successors, (84), 8 states have internal predecessors, (84), 4 states have call successors, (14), 2 states have call predecessors, (14), 3 states have return successors, (13), 4 states have call predecessors, (13), 4 states have call successors, (13) [2025-03-16 19:05:01,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:01,976 INFO L93 Difference]: Finished difference Result 23845 states and 30965 transitions. [2025-03-16 19:05:01,976 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-16 19:05:01,976 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 8 states have (on average 10.5) internal successors, (84), 8 states have internal predecessors, (84), 4 states have call successors, (14), 2 states have call predecessors, (14), 3 states have return successors, (13), 4 states have call predecessors, (13), 4 states have call successors, (13) Word has length 141 [2025-03-16 19:05:01,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:02,030 INFO L225 Difference]: With dead ends: 23845 [2025-03-16 19:05:02,030 INFO L226 Difference]: Without dead ends: 12185 [2025-03-16 19:05:02,055 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 292 GetRequests, 266 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 127 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=88, Invalid=668, Unknown=0, NotChecked=0, Total=756 [2025-03-16 19:05:02,056 INFO L435 NwaCegarLoop]: 259 mSDtfsCounter, 268 mSDsluCounter, 1170 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 45 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 272 SdHoareTripleChecker+Valid, 1429 SdHoareTripleChecker+Invalid, 171 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 45 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:02,056 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [272 Valid, 1429 Invalid, 171 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [45 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:05:02,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12185 states. [2025-03-16 19:05:02,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12185 to 8240. [2025-03-16 19:05:02,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8240 states, 6013 states have (on average 1.2991850989522702) internal successors, (7812), 6068 states have internal predecessors, (7812), 1444 states have call successors, (1444), 782 states have call predecessors, (1444), 782 states have return successors, (1444), 1389 states have call predecessors, (1444), 1444 states have call successors, (1444) [2025-03-16 19:05:02,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8240 states to 8240 states and 10700 transitions. [2025-03-16 19:05:02,723 INFO L78 Accepts]: Start accepts. Automaton has 8240 states and 10700 transitions. Word has length 141 [2025-03-16 19:05:02,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:02,724 INFO L471 AbstractCegarLoop]: Abstraction has 8240 states and 10700 transitions. [2025-03-16 19:05:02,724 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 8 states have (on average 10.5) internal successors, (84), 8 states have internal predecessors, (84), 4 states have call successors, (14), 2 states have call predecessors, (14), 3 states have return successors, (13), 4 states have call predecessors, (13), 4 states have call successors, (13) [2025-03-16 19:05:02,724 INFO L276 IsEmpty]: Start isEmpty. Operand 8240 states and 10700 transitions. [2025-03-16 19:05:02,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2025-03-16 19:05:02,734 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:02,734 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:02,742 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2025-03-16 19:05:02,935 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable27,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:02,935 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:02,936 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:02,936 INFO L85 PathProgramCache]: Analyzing trace with hash -1022024250, now seen corresponding path program 1 times [2025-03-16 19:05:02,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:02,937 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10196009] [2025-03-16 19:05:02,937 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:02,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:02,951 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 142 statements into 1 equivalence classes. [2025-03-16 19:05:02,978 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 142 of 142 statements. [2025-03-16 19:05:02,978 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:02,979 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:03,370 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 21 proven. 4 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2025-03-16 19:05:03,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:03,371 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10196009] [2025-03-16 19:05:03,371 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10196009] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:03,371 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1853272664] [2025-03-16 19:05:03,371 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:03,371 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:03,371 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:05:03,373 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:05:03,375 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2025-03-16 19:05:03,457 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 142 statements into 1 equivalence classes. [2025-03-16 19:05:03,517 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 142 of 142 statements. [2025-03-16 19:05:03,517 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:03,517 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:03,524 INFO L256 TraceCheckSpWp]: Trace formula consists of 696 conjuncts, 27 conjuncts are in the unsatisfiable core [2025-03-16 19:05:03,527 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:03,734 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 17 proven. 53 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-16 19:05:03,734 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:05:03,974 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 9 proven. 18 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2025-03-16 19:05:03,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1853272664] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-16 19:05:03,974 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-16 19:05:03,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 11, 9] total 23 [2025-03-16 19:05:03,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844030901] [2025-03-16 19:05:03,974 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-16 19:05:03,975 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2025-03-16 19:05:03,975 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:03,975 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2025-03-16 19:05:03,976 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=440, Unknown=0, NotChecked=0, Total=506 [2025-03-16 19:05:03,976 INFO L87 Difference]: Start difference. First operand 8240 states and 10700 transitions. Second operand has 23 states, 23 states have (on average 10.043478260869565) internal successors, (231), 19 states have internal predecessors, (231), 7 states have call successors, (40), 5 states have call predecessors, (40), 9 states have return successors, (39), 11 states have call predecessors, (39), 7 states have call successors, (39) [2025-03-16 19:05:06,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:06,886 INFO L93 Difference]: Finished difference Result 22003 states and 28550 transitions. [2025-03-16 19:05:06,886 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2025-03-16 19:05:06,886 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 10.043478260869565) internal successors, (231), 19 states have internal predecessors, (231), 7 states have call successors, (40), 5 states have call predecessors, (40), 9 states have return successors, (39), 11 states have call predecessors, (39), 7 states have call successors, (39) Word has length 142 [2025-03-16 19:05:06,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:06,937 INFO L225 Difference]: With dead ends: 22003 [2025-03-16 19:05:06,937 INFO L226 Difference]: Without dead ends: 14033 [2025-03-16 19:05:06,951 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 346 GetRequests, 286 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 849 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=658, Invalid=3124, Unknown=0, NotChecked=0, Total=3782 [2025-03-16 19:05:06,955 INFO L435 NwaCegarLoop]: 528 mSDtfsCounter, 1422 mSDsluCounter, 5336 mSDsCounter, 0 mSdLazyCounter, 2560 mSolverCounterSat, 550 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1422 SdHoareTripleChecker+Valid, 5864 SdHoareTripleChecker+Invalid, 3110 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 550 IncrementalHoareTripleChecker+Valid, 2560 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:06,956 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1422 Valid, 5864 Invalid, 3110 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [550 Valid, 2560 Invalid, 0 Unknown, 0 Unchecked, 1.3s Time] [2025-03-16 19:05:06,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14033 states. [2025-03-16 19:05:07,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14033 to 7583. [2025-03-16 19:05:07,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7583 states, 5546 states have (on average 1.2944464478903714) internal successors, (7179), 5598 states have internal predecessors, (7179), 1319 states have call successors, (1319), 717 states have call predecessors, (1319), 717 states have return successors, (1319), 1267 states have call predecessors, (1319), 1319 states have call successors, (1319) [2025-03-16 19:05:07,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7583 states to 7583 states and 9817 transitions. [2025-03-16 19:05:07,576 INFO L78 Accepts]: Start accepts. Automaton has 7583 states and 9817 transitions. Word has length 142 [2025-03-16 19:05:07,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:07,576 INFO L471 AbstractCegarLoop]: Abstraction has 7583 states and 9817 transitions. [2025-03-16 19:05:07,577 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 10.043478260869565) internal successors, (231), 19 states have internal predecessors, (231), 7 states have call successors, (40), 5 states have call predecessors, (40), 9 states have return successors, (39), 11 states have call predecessors, (39), 7 states have call successors, (39) [2025-03-16 19:05:07,577 INFO L276 IsEmpty]: Start isEmpty. Operand 7583 states and 9817 transitions. [2025-03-16 19:05:07,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2025-03-16 19:05:07,587 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:07,587 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:07,597 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2025-03-16 19:05:07,787 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable28 [2025-03-16 19:05:07,788 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:07,788 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:07,789 INFO L85 PathProgramCache]: Analyzing trace with hash -2136407435, now seen corresponding path program 1 times [2025-03-16 19:05:07,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:07,789 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566915061] [2025-03-16 19:05:07,789 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:07,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:07,799 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 151 statements into 1 equivalence classes. [2025-03-16 19:05:07,822 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 151 of 151 statements. [2025-03-16 19:05:07,822 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:07,822 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:08,383 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 21 proven. 2 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2025-03-16 19:05:08,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:08,384 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1566915061] [2025-03-16 19:05:08,384 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1566915061] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:08,384 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [762563820] [2025-03-16 19:05:08,384 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:08,384 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:08,384 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:05:08,387 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:05:08,389 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2025-03-16 19:05:08,477 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 151 statements into 1 equivalence classes. [2025-03-16 19:05:08,538 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 151 of 151 statements. [2025-03-16 19:05:08,538 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:08,538 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:08,542 INFO L256 TraceCheckSpWp]: Trace formula consists of 700 conjuncts, 11 conjuncts are in the unsatisfiable core [2025-03-16 19:05:08,545 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:08,634 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 41 proven. 4 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2025-03-16 19:05:08,635 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:05:08,717 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 18 proven. 2 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2025-03-16 19:05:08,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [762563820] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-16 19:05:08,718 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-16 19:05:08,718 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 7, 7] total 15 [2025-03-16 19:05:08,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551520117] [2025-03-16 19:05:08,718 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-16 19:05:08,719 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2025-03-16 19:05:08,719 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:08,720 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2025-03-16 19:05:08,720 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=180, Unknown=0, NotChecked=0, Total=210 [2025-03-16 19:05:08,720 INFO L87 Difference]: Start difference. First operand 7583 states and 9817 transitions. Second operand has 15 states, 15 states have (on average 11.333333333333334) internal successors, (170), 14 states have internal predecessors, (170), 6 states have call successors, (37), 4 states have call predecessors, (37), 6 states have return successors, (37), 7 states have call predecessors, (37), 6 states have call successors, (37) [2025-03-16 19:05:10,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:10,738 INFO L93 Difference]: Finished difference Result 16460 states and 21283 transitions. [2025-03-16 19:05:10,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2025-03-16 19:05:10,739 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 11.333333333333334) internal successors, (170), 14 states have internal predecessors, (170), 6 states have call successors, (37), 4 states have call predecessors, (37), 6 states have return successors, (37), 7 states have call predecessors, (37), 6 states have call successors, (37) Word has length 151 [2025-03-16 19:05:10,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:10,779 INFO L225 Difference]: With dead ends: 16460 [2025-03-16 19:05:10,779 INFO L226 Difference]: Without dead ends: 9075 [2025-03-16 19:05:10,795 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 350 GetRequests, 309 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 392 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=277, Invalid=1529, Unknown=0, NotChecked=0, Total=1806 [2025-03-16 19:05:10,796 INFO L435 NwaCegarLoop]: 428 mSDtfsCounter, 1076 mSDsluCounter, 3671 mSDsCounter, 0 mSdLazyCounter, 1113 mSolverCounterSat, 385 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1076 SdHoareTripleChecker+Valid, 4099 SdHoareTripleChecker+Invalid, 1498 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 385 IncrementalHoareTripleChecker+Valid, 1113 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:10,796 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1076 Valid, 4099 Invalid, 1498 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [385 Valid, 1113 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2025-03-16 19:05:10,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9075 states. [2025-03-16 19:05:12,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9075 to 8794. [2025-03-16 19:05:12,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8794 states, 6421 states have (on average 1.2920105902507397) internal successors, (8296), 6483 states have internal predecessors, (8296), 1532 states have call successors, (1532), 840 states have call predecessors, (1532), 840 states have return successors, (1532), 1470 states have call predecessors, (1532), 1532 states have call successors, (1532) [2025-03-16 19:05:12,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8794 states to 8794 states and 11360 transitions. [2025-03-16 19:05:12,066 INFO L78 Accepts]: Start accepts. Automaton has 8794 states and 11360 transitions. Word has length 151 [2025-03-16 19:05:12,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:12,067 INFO L471 AbstractCegarLoop]: Abstraction has 8794 states and 11360 transitions. [2025-03-16 19:05:12,067 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 11.333333333333334) internal successors, (170), 14 states have internal predecessors, (170), 6 states have call successors, (37), 4 states have call predecessors, (37), 6 states have return successors, (37), 7 states have call predecessors, (37), 6 states have call successors, (37) [2025-03-16 19:05:12,067 INFO L276 IsEmpty]: Start isEmpty. Operand 8794 states and 11360 transitions. [2025-03-16 19:05:12,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 161 [2025-03-16 19:05:12,075 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:12,075 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:12,083 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2025-03-16 19:05:12,275 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:12,275 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:12,276 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:12,276 INFO L85 PathProgramCache]: Analyzing trace with hash 1915173708, now seen corresponding path program 1 times [2025-03-16 19:05:12,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:12,276 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405983981] [2025-03-16 19:05:12,276 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:12,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:12,288 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 160 statements into 1 equivalence classes. [2025-03-16 19:05:12,312 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 160 of 160 statements. [2025-03-16 19:05:12,312 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:12,312 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:12,983 INFO L134 CoverageAnalysis]: Checked inductivity of 102 backedges. 21 proven. 5 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2025-03-16 19:05:12,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:12,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1405983981] [2025-03-16 19:05:12,984 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1405983981] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:12,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [713584305] [2025-03-16 19:05:12,984 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:12,984 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:12,984 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:05:12,992 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:05:12,993 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2025-03-16 19:05:13,137 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 160 statements into 1 equivalence classes. [2025-03-16 19:05:13,201 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 160 of 160 statements. [2025-03-16 19:05:13,201 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:13,201 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:13,205 INFO L256 TraceCheckSpWp]: Trace formula consists of 719 conjuncts, 47 conjuncts are in the unsatisfiable core [2025-03-16 19:05:13,208 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:13,681 INFO L134 CoverageAnalysis]: Checked inductivity of 102 backedges. 70 proven. 13 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2025-03-16 19:05:13,681 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:05:14,303 INFO L134 CoverageAnalysis]: Checked inductivity of 102 backedges. 14 proven. 12 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2025-03-16 19:05:14,303 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [713584305] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-16 19:05:14,303 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-16 19:05:14,303 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10, 12] total 27 [2025-03-16 19:05:14,303 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415177937] [2025-03-16 19:05:14,303 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-16 19:05:14,304 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 27 states [2025-03-16 19:05:14,304 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:14,305 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2025-03-16 19:05:14,305 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=96, Invalid=606, Unknown=0, NotChecked=0, Total=702 [2025-03-16 19:05:14,306 INFO L87 Difference]: Start difference. First operand 8794 states and 11360 transitions. Second operand has 27 states, 27 states have (on average 8.518518518518519) internal successors, (230), 27 states have internal predecessors, (230), 10 states have call successors, (44), 5 states have call predecessors, (44), 6 states have return successors, (43), 10 states have call predecessors, (43), 10 states have call successors, (43) [2025-03-16 19:05:17,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:17,869 INFO L93 Difference]: Finished difference Result 19332 states and 25066 transitions. [2025-03-16 19:05:17,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2025-03-16 19:05:17,870 INFO L78 Accepts]: Start accepts. Automaton has has 27 states, 27 states have (on average 8.518518518518519) internal successors, (230), 27 states have internal predecessors, (230), 10 states have call successors, (44), 5 states have call predecessors, (44), 6 states have return successors, (43), 10 states have call predecessors, (43), 10 states have call successors, (43) Word has length 160 [2025-03-16 19:05:17,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:17,907 INFO L225 Difference]: With dead ends: 19332 [2025-03-16 19:05:17,907 INFO L226 Difference]: Without dead ends: 10888 [2025-03-16 19:05:17,919 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 378 GetRequests, 316 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1054 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=589, Invalid=3443, Unknown=0, NotChecked=0, Total=4032 [2025-03-16 19:05:17,919 INFO L435 NwaCegarLoop]: 427 mSDtfsCounter, 1609 mSDsluCounter, 4253 mSDsCounter, 0 mSdLazyCounter, 2021 mSolverCounterSat, 464 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1609 SdHoareTripleChecker+Valid, 4680 SdHoareTripleChecker+Invalid, 2485 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 464 IncrementalHoareTripleChecker+Valid, 2021 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:17,920 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1609 Valid, 4680 Invalid, 2485 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [464 Valid, 2021 Invalid, 0 Unknown, 0 Unchecked, 1.2s Time] [2025-03-16 19:05:17,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10888 states. [2025-03-16 19:05:19,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10888 to 10616. [2025-03-16 19:05:19,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10616 states, 7775 states have (on average 1.292475884244373) internal successors, (10049), 7851 states have internal predecessors, (10049), 1827 states have call successors, (1827), 1013 states have call predecessors, (1827), 1013 states have return successors, (1827), 1751 states have call predecessors, (1827), 1827 states have call successors, (1827) [2025-03-16 19:05:19,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10616 states to 10616 states and 13703 transitions. [2025-03-16 19:05:19,484 INFO L78 Accepts]: Start accepts. Automaton has 10616 states and 13703 transitions. Word has length 160 [2025-03-16 19:05:19,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:19,485 INFO L471 AbstractCegarLoop]: Abstraction has 10616 states and 13703 transitions. [2025-03-16 19:05:19,485 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 27 states, 27 states have (on average 8.518518518518519) internal successors, (230), 27 states have internal predecessors, (230), 10 states have call successors, (44), 5 states have call predecessors, (44), 6 states have return successors, (43), 10 states have call predecessors, (43), 10 states have call successors, (43) [2025-03-16 19:05:19,485 INFO L276 IsEmpty]: Start isEmpty. Operand 10616 states and 13703 transitions. [2025-03-16 19:05:19,501 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2025-03-16 19:05:19,501 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:19,502 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:19,512 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2025-03-16 19:05:19,702 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:19,702 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:19,703 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:19,703 INFO L85 PathProgramCache]: Analyzing trace with hash -507760352, now seen corresponding path program 1 times [2025-03-16 19:05:19,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:19,703 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11598215] [2025-03-16 19:05:19,703 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:19,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:19,750 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 161 statements into 1 equivalence classes. [2025-03-16 19:05:20,026 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 161 of 161 statements. [2025-03-16 19:05:20,027 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:20,027 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:20,894 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 21 proven. 8 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2025-03-16 19:05:20,895 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:20,895 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11598215] [2025-03-16 19:05:20,895 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [11598215] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:20,895 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [348185408] [2025-03-16 19:05:20,895 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:20,895 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:20,895 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:05:20,897 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:05:20,899 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2025-03-16 19:05:20,999 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 161 statements into 1 equivalence classes. [2025-03-16 19:05:21,067 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 161 of 161 statements. [2025-03-16 19:05:21,067 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:21,067 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:21,075 INFO L256 TraceCheckSpWp]: Trace formula consists of 720 conjuncts, 28 conjuncts are in the unsatisfiable core [2025-03-16 19:05:21,085 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:21,260 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 69 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2025-03-16 19:05:21,263 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:05:21,459 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 23 proven. 8 refuted. 0 times theorem prover too weak. 68 trivial. 0 not checked. [2025-03-16 19:05:21,460 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [348185408] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-16 19:05:21,460 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-16 19:05:21,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 12, 9] total 21 [2025-03-16 19:05:21,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [253297003] [2025-03-16 19:05:21,460 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-16 19:05:21,461 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 21 states [2025-03-16 19:05:21,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:21,462 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2025-03-16 19:05:21,462 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=356, Unknown=0, NotChecked=0, Total=420 [2025-03-16 19:05:21,462 INFO L87 Difference]: Start difference. First operand 10616 states and 13703 transitions. Second operand has 21 states, 21 states have (on average 7.619047619047619) internal successors, (160), 16 states have internal predecessors, (160), 4 states have call successors, (29), 4 states have call predecessors, (29), 9 states have return successors, (32), 9 states have call predecessors, (32), 4 states have call successors, (32) [2025-03-16 19:05:24,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:24,560 INFO L93 Difference]: Finished difference Result 28293 states and 37509 transitions. [2025-03-16 19:05:24,560 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2025-03-16 19:05:24,560 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 7.619047619047619) internal successors, (160), 16 states have internal predecessors, (160), 4 states have call successors, (29), 4 states have call predecessors, (29), 9 states have return successors, (32), 9 states have call predecessors, (32), 4 states have call successors, (32) Word has length 161 [2025-03-16 19:05:24,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:24,620 INFO L225 Difference]: With dead ends: 28293 [2025-03-16 19:05:24,620 INFO L226 Difference]: Without dead ends: 17753 [2025-03-16 19:05:24,637 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 350 GetRequests, 316 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 207 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=181, Invalid=1079, Unknown=0, NotChecked=0, Total=1260 [2025-03-16 19:05:24,638 INFO L435 NwaCegarLoop]: 358 mSDtfsCounter, 602 mSDsluCounter, 3611 mSDsCounter, 0 mSdLazyCounter, 1272 mSolverCounterSat, 169 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 607 SdHoareTripleChecker+Valid, 3969 SdHoareTripleChecker+Invalid, 1441 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 169 IncrementalHoareTripleChecker+Valid, 1272 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:24,638 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [607 Valid, 3969 Invalid, 1441 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [169 Valid, 1272 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2025-03-16 19:05:24,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17753 states. [2025-03-16 19:05:26,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17753 to 12310. [2025-03-16 19:05:26,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12310 states, 8989 states have (on average 1.2882411836689287) internal successors, (11580), 9083 states have internal predecessors, (11580), 2135 states have call successors, (2135), 1185 states have call predecessors, (2135), 1185 states have return successors, (2135), 2041 states have call predecessors, (2135), 2135 states have call successors, (2135) [2025-03-16 19:05:26,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12310 states to 12310 states and 15850 transitions. [2025-03-16 19:05:26,384 INFO L78 Accepts]: Start accepts. Automaton has 12310 states and 15850 transitions. Word has length 161 [2025-03-16 19:05:26,385 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:26,385 INFO L471 AbstractCegarLoop]: Abstraction has 12310 states and 15850 transitions. [2025-03-16 19:05:26,385 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 21 states, 21 states have (on average 7.619047619047619) internal successors, (160), 16 states have internal predecessors, (160), 4 states have call successors, (29), 4 states have call predecessors, (29), 9 states have return successors, (32), 9 states have call predecessors, (32), 4 states have call successors, (32) [2025-03-16 19:05:26,385 INFO L276 IsEmpty]: Start isEmpty. Operand 12310 states and 15850 transitions. [2025-03-16 19:05:26,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2025-03-16 19:05:26,393 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:26,394 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:26,401 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2025-03-16 19:05:26,594 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:26,594 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:26,595 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:26,595 INFO L85 PathProgramCache]: Analyzing trace with hash 1453279735, now seen corresponding path program 1 times [2025-03-16 19:05:26,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:26,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381892741] [2025-03-16 19:05:26,595 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:26,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:26,611 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 168 statements into 1 equivalence classes. [2025-03-16 19:05:26,736 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 168 of 168 statements. [2025-03-16 19:05:26,736 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:26,737 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-16 19:05:26,737 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-16 19:05:26,749 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 168 statements into 1 equivalence classes. [2025-03-16 19:05:26,836 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 168 of 168 statements. [2025-03-16 19:05:26,836 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:26,836 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-16 19:05:26,927 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-16 19:05:26,927 INFO L340 BasicCegarLoop]: Counterexample is feasible [2025-03-16 19:05:26,928 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location assertErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2025-03-16 19:05:26,935 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable32 [2025-03-16 19:05:26,942 INFO L422 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:27,144 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2025-03-16 19:05:27,146 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 16.03 07:05:27 BoogieIcfgContainer [2025-03-16 19:05:27,146 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2025-03-16 19:05:27,147 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-16 19:05:27,147 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-16 19:05:27,147 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-16 19:05:27,150 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 16.03 07:04:40" (3/4) ... [2025-03-16 19:05:27,151 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2025-03-16 19:05:27,327 INFO L127 tionWitnessGenerator]: Generated YAML witness of length 144. [2025-03-16 19:05:27,457 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-16 19:05:27,458 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.yml [2025-03-16 19:05:27,458 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-16 19:05:27,459 INFO L158 Benchmark]: Toolchain (without parser) took 47806.03ms. Allocated memory was 142.6MB in the beginning and 1.8GB in the end (delta: 1.7GB). Free memory was 104.4MB in the beginning and 1.1GB in the end (delta: -965.3MB). Peak memory consumption was 692.3MB. Max. memory is 16.1GB. [2025-03-16 19:05:27,459 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 201.3MB. Free memory is still 126.5MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-16 19:05:27,459 INFO L158 Benchmark]: CACSL2BoogieTranslator took 267.37ms. Allocated memory is still 142.6MB. Free memory was 103.1MB in the beginning and 85.4MB in the end (delta: 17.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-16 19:05:27,459 INFO L158 Benchmark]: Boogie Procedure Inliner took 55.76ms. Allocated memory is still 142.6MB. Free memory was 85.4MB in the beginning and 82.2MB in the end (delta: 3.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-16 19:05:27,459 INFO L158 Benchmark]: Boogie Preprocessor took 57.54ms. Allocated memory is still 142.6MB. Free memory was 82.2MB in the beginning and 79.2MB in the end (delta: 3.1MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-16 19:05:27,460 INFO L158 Benchmark]: IcfgBuilder took 622.17ms. Allocated memory is still 142.6MB. Free memory was 79.2MB in the beginning and 38.3MB in the end (delta: 40.9MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2025-03-16 19:05:27,462 INFO L158 Benchmark]: TraceAbstraction took 46482.20ms. Allocated memory was 142.6MB in the beginning and 1.8GB in the end (delta: 1.7GB). Free memory was 37.2MB in the beginning and 1.1GB in the end (delta: -1.1GB). Peak memory consumption was 583.2MB. Max. memory is 16.1GB. [2025-03-16 19:05:27,463 INFO L158 Benchmark]: Witness Printer took 311.19ms. Allocated memory is still 1.8GB. Free memory was 1.1GB in the beginning and 1.1GB in the end (delta: 41.9MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2025-03-16 19:05:27,463 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 201.3MB. Free memory is still 126.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 267.37ms. Allocated memory is still 142.6MB. Free memory was 103.1MB in the beginning and 85.4MB in the end (delta: 17.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 55.76ms. Allocated memory is still 142.6MB. Free memory was 85.4MB in the beginning and 82.2MB in the end (delta: 3.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 57.54ms. Allocated memory is still 142.6MB. Free memory was 82.2MB in the beginning and 79.2MB in the end (delta: 3.1MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 622.17ms. Allocated memory is still 142.6MB. Free memory was 79.2MB in the beginning and 38.3MB in the end (delta: 40.9MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * TraceAbstraction took 46482.20ms. Allocated memory was 142.6MB in the beginning and 1.8GB in the end (delta: 1.7GB). Free memory was 37.2MB in the beginning and 1.1GB in the end (delta: -1.1GB). Peak memory consumption was 583.2MB. Max. memory is 16.1GB. * Witness Printer took 311.19ms. Allocated memory is still 1.8GB. Free memory was 1.1GB in the beginning and 1.1GB in the end (delta: 41.9MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 610]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L24] msg_t nomsg = (msg_t )-1; [L25] port_t cs1 ; [L26] int8_t cs1_old ; [L27] int8_t cs1_new ; [L28] port_t cs2 ; [L29] int8_t cs2_old ; [L30] int8_t cs2_new ; [L31] port_t s1s2 ; [L32] int8_t s1s2_old ; [L33] int8_t s1s2_new ; [L34] port_t s1s1 ; [L35] int8_t s1s1_old ; [L36] int8_t s1s1_new ; [L37] port_t s2s1 ; [L38] int8_t s2s1_old ; [L39] int8_t s2s1_new ; [L40] port_t s2s2 ; [L41] int8_t s2s2_old ; [L42] int8_t s2s2_new ; [L43] port_t s1p ; [L44] int8_t s1p_old ; [L45] int8_t s1p_new ; [L46] port_t s2p ; [L47] int8_t s2p_old ; [L48] int8_t s2p_new ; [L51] _Bool side1Failed ; [L52] _Bool side2Failed ; [L53] msg_t side1_written ; [L54] msg_t side2_written ; [L60] static _Bool side1Failed_History_0 ; [L61] static _Bool side1Failed_History_1 ; [L62] static _Bool side1Failed_History_2 ; [L63] static _Bool side2Failed_History_0 ; [L64] static _Bool side2Failed_History_1 ; [L65] static _Bool side2Failed_History_2 ; [L66] static int8_t active_side_History_0 ; [L67] static int8_t active_side_History_1 ; [L68] static int8_t active_side_History_2 ; [L69] static msg_t manual_selection_History_0 ; [L70] static msg_t manual_selection_History_1 ; [L71] static msg_t manual_selection_History_2 ; [L534] int c1 ; [L535] int i2 ; [L538] c1 = 0 [L539] side1Failed = __VERIFIER_nondet_bool() [L540] side2Failed = __VERIFIER_nondet_bool() [L541] side1_written = __VERIFIER_nondet_char() [L542] side2_written = __VERIFIER_nondet_char() [L543] side1Failed_History_0 = __VERIFIER_nondet_bool() [L544] side1Failed_History_1 = __VERIFIER_nondet_bool() [L545] side1Failed_History_2 = __VERIFIER_nondet_bool() [L546] side2Failed_History_0 = __VERIFIER_nondet_bool() [L547] side2Failed_History_1 = __VERIFIER_nondet_bool() [L548] side2Failed_History_2 = __VERIFIER_nondet_bool() [L549] active_side_History_0 = __VERIFIER_nondet_char() [L550] active_side_History_1 = __VERIFIER_nondet_char() [L551] active_side_History_2 = __VERIFIER_nondet_char() [L552] manual_selection_History_0 = __VERIFIER_nondet_char() [L553] manual_selection_History_1 = __VERIFIER_nondet_char() [L554] manual_selection_History_2 = __VERIFIER_nondet_char() [L555] CALL, EXPR init() [L197] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L200] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L203] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L206] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L209] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L212] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L215] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L218] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L221] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L224] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L227] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L230] COND FALSE !((int )manual_selection_History_2 != 0) [L233] return (1); VAL [\result=1, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L555] RET, EXPR init() [L555] i2 = init() [L556] CALL assume_abort_if_not(i2) VAL [\old(cond)=1, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L58] COND FALSE !(!cond) VAL [\old(cond)=1, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L556] RET assume_abort_if_not(i2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, i2=1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L557] cs1_old = nomsg [L558] cs1_new = nomsg [L559] cs2_old = nomsg [L560] cs2_new = nomsg [L561] s1s2_old = nomsg [L562] s1s2_new = nomsg [L563] s1s1_old = nomsg [L564] s1s1_new = nomsg [L565] s2s1_old = nomsg [L566] s2s1_new = nomsg [L567] s2s2_old = nomsg [L568] s2s2_new = nomsg [L569] s1p_old = nomsg [L570] s1p_new = nomsg [L571] s2p_old = nomsg [L572] s2p_new = nomsg [L573] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, i2=1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L574] COND TRUE 1 [L576] CALL Console_task_each_pals_period() [L251] msg_t manual_selection ; [L252] char tmp ; [L255] tmp = __VERIFIER_nondet_char() [L256] manual_selection = tmp [L257] CALL write_manual_selection_history(manual_selection) [L167] manual_selection_History_2 = manual_selection_History_1 [L168] manual_selection_History_1 = manual_selection_History_0 [L169] manual_selection_History_0 = val [L257] RET write_manual_selection_history(manual_selection) [L258] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L259] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L260] manual_selection = (msg_t )0 [L576] RET Console_task_each_pals_period() [L577] CALL Side1_activestandby_task_each_pals_period() [L266] int8_t side1 ; [L267] int8_t side2 ; [L268] msg_t manual_selection ; [L269] int8_t next_state ; [L272] side1 = nomsg [L273] side2 = nomsg [L274] manual_selection = (msg_t )0 [L275] side1Failed = __VERIFIER_nondet_bool() [L276] CALL write_side1_failed_history(side1Failed) [L77] side1Failed_History_2 = side1Failed_History_1 [L78] side1Failed_History_1 = side1Failed_History_0 [L79] side1Failed_History_0 = val [L276] RET write_side1_failed_history(side1Failed) [L277] COND TRUE \read(side1Failed) [L278] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L279] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L280] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L281] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L577] RET Side1_activestandby_task_each_pals_period() [L578] CALL Side2_activestandby_task_each_pals_period() [L323] int8_t side1 ; [L324] int8_t side2 ; [L325] msg_t manual_selection ; [L326] int8_t next_state ; [L329] side1 = nomsg [L330] side2 = nomsg [L331] manual_selection = (msg_t )0 [L332] side2Failed = __VERIFIER_nondet_bool() [L333] CALL write_side2_failed_history(side2Failed) [L107] side2Failed_History_2 = side2Failed_History_1 [L108] side2Failed_History_1 = side2Failed_History_0 [L109] side2Failed_History_0 = val [L333] RET write_side2_failed_history(side2Failed) [L334] COND FALSE !(\read(side2Failed)) [L341] side1 = s1s2_old [L342] s1s2_old = nomsg [L343] side2 = s2s2_old [L344] s2s2_old = nomsg [L345] manual_selection = cs2_old [L346] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L347] COND TRUE (int )side1 == (int )side2 [L348] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, next_state=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L371] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L372] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L373] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L374] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L578] RET Side2_activestandby_task_each_pals_period() [L579] CALL Pendulum_prism_task_each_pals_period() [L380] int8_t active_side ; [L381] int8_t tmp ; [L382] int8_t side1 ; [L383] int8_t side2 ; VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [\old(index)=0, \result=-2, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] RET, EXPR read_active_side_history((unsigned char)0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] tmp = read_active_side_history((unsigned char)0) [L387] active_side = tmp [L388] side1 = nomsg [L389] side2 = nomsg [L390] side1 = s1p_old [L391] s1p_old = nomsg [L392] side2 = s2p_old [L393] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L394] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L397] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L400] COND FALSE !((int )side1 == 0) [L407] active_side = (int8_t )0 VAL [active_side=0, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L409] CALL write_active_side_history(active_side) [L137] active_side_History_2 = active_side_History_1 [L138] active_side_History_1 = active_side_History_0 [L139] active_side_History_0 = val [L409] RET write_active_side_history(active_side) [L579] RET Pendulum_prism_task_each_pals_period() [L580] cs1_old = cs1_new [L581] cs1_new = nomsg [L582] cs2_old = cs2_new [L583] cs2_new = nomsg [L584] s1s2_old = s1s2_new [L585] s1s2_new = nomsg [L586] s1s1_old = s1s1_new [L587] s1s1_new = nomsg [L588] s2s1_old = s2s1_new [L589] s2s1_new = nomsg [L590] s2s2_old = s2s2_new [L591] s2s2_new = nomsg [L592] s1p_old = s1p_new [L593] s1p_new = nomsg [L594] s2p_old = s2p_new [L595] s2p_new = nomsg [L596] CALL, EXPR check() [L415] int tmp ; [L416] msg_t tmp___0 ; [L417] _Bool tmp___1 ; [L418] _Bool tmp___2 ; [L419] _Bool tmp___3 ; [L420] _Bool tmp___4 ; [L421] int8_t tmp___5 ; [L422] _Bool tmp___6 ; [L423] _Bool tmp___7 ; [L424] _Bool tmp___8 ; [L425] int8_t tmp___9 ; [L426] _Bool tmp___10 ; [L427] _Bool tmp___11 ; [L428] _Bool tmp___12 ; [L429] msg_t tmp___13 ; [L430] _Bool tmp___14 ; [L431] _Bool tmp___15 ; [L432] _Bool tmp___16 ; [L433] _Bool tmp___17 ; [L434] int8_t tmp___18 ; [L435] int8_t tmp___19 ; [L436] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L439] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L442] COND TRUE ! side2Failed [L443] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L447] CALL assume_abort_if_not((_Bool )tmp) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L58] COND FALSE !(!cond) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L447] RET assume_abort_if_not((_Bool )tmp) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L448] CALL, EXPR read_manual_selection_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L178] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L181] COND TRUE (int )index == 1 [L182] return (manual_selection_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L448] RET, EXPR read_manual_selection_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L448] tmp___0 = read_manual_selection_history((unsigned char)1) [L449] COND TRUE ! tmp___0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L450] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L450] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L450] tmp___1 = read_side1_failed_history((unsigned char)1) [L451] COND TRUE ! tmp___1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L452] CALL, EXPR read_side1_failed_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND TRUE (int )index == 0 [L89] return (side1Failed_History_0); VAL [\old(index)=0, \result=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L452] RET, EXPR read_side1_failed_history((unsigned char)0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L452] tmp___2 = read_side1_failed_history((unsigned char)0) [L453] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L478] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L478] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L478] tmp___7 = read_side1_failed_history((unsigned char)1) [L479] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L494] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L494] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L494] tmp___11 = read_side1_failed_history((unsigned char)1) [L495] COND TRUE ! tmp___11 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L496] CALL, EXPR read_side2_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L118] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L121] COND TRUE (int )index == 1 [L122] return (side2Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L496] RET, EXPR read_side2_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L496] tmp___12 = read_side2_failed_history((unsigned char)1) [L497] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L510] CALL, EXPR read_active_side_history((unsigned char)2) VAL [\old(index)=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L148] COND FALSE !((int )index == 0) VAL [\old(index)=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=2, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L151] COND FALSE !((int )index == 1) VAL [\old(index)=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=2, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L154] COND TRUE (int )index == 2 [L155] return (active_side_History_2); VAL [\old(index)=2, \result=-2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L510] RET, EXPR read_active_side_history((unsigned char)2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L510] tmp___20 = read_active_side_history((unsigned char)2) [L511] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L529] return (1); VAL [\result=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L596] RET, EXPR check() [L596] c1 = check() [L597] CALL assert(c1) VAL [\old(arg)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L608] COND FALSE !(! arg) VAL [\old(arg)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L597] RET assert(c1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, c1=1, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, i2=1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L574] COND TRUE 1 [L576] CALL Console_task_each_pals_period() [L251] msg_t manual_selection ; [L252] char tmp ; [L255] tmp = __VERIFIER_nondet_char() [L256] manual_selection = tmp [L257] CALL write_manual_selection_history(manual_selection) [L167] manual_selection_History_2 = manual_selection_History_1 [L168] manual_selection_History_1 = manual_selection_History_0 [L169] manual_selection_History_0 = val [L257] RET write_manual_selection_history(manual_selection) [L258] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L259] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L260] manual_selection = (msg_t )0 [L576] RET Console_task_each_pals_period() [L577] CALL Side1_activestandby_task_each_pals_period() [L266] int8_t side1 ; [L267] int8_t side2 ; [L268] msg_t manual_selection ; [L269] int8_t next_state ; [L272] side1 = nomsg [L273] side2 = nomsg [L274] manual_selection = (msg_t )0 [L275] side1Failed = __VERIFIER_nondet_bool() [L276] CALL write_side1_failed_history(side1Failed) [L77] side1Failed_History_2 = side1Failed_History_1 [L78] side1Failed_History_1 = side1Failed_History_0 [L79] side1Failed_History_0 = val [L276] RET write_side1_failed_history(side1Failed) [L277] COND FALSE !(\read(side1Failed)) [L284] side1 = s1s1_old [L285] s1s1_old = nomsg [L286] side2 = s2s1_old [L287] s2s1_old = nomsg [L288] manual_selection = cs1_old [L289] cs1_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L290] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L293] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L294] COND TRUE (int )side2 != (int )nomsg [L295] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, next_state=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L314] s1s1_new = next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new [L315] s1s2_new = next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new [L316] s1p_new = next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new [L317] side1_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L577] RET Side1_activestandby_task_each_pals_period() [L578] CALL Side2_activestandby_task_each_pals_period() [L323] int8_t side1 ; [L324] int8_t side2 ; [L325] msg_t manual_selection ; [L326] int8_t next_state ; [L329] side1 = nomsg [L330] side2 = nomsg [L331] manual_selection = (msg_t )0 [L332] side2Failed = __VERIFIER_nondet_bool() [L333] CALL write_side2_failed_history(side2Failed) [L107] side2Failed_History_2 = side2Failed_History_1 [L108] side2Failed_History_1 = side2Failed_History_0 [L109] side2Failed_History_0 = val [L333] RET write_side2_failed_history(side2Failed) [L334] COND TRUE \read(side2Failed) [L335] s2s1_new = nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new [L336] s2s2_new = nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new [L337] s2p_new = nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new [L338] side2_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L578] RET Side2_activestandby_task_each_pals_period() [L579] CALL Pendulum_prism_task_each_pals_period() [L380] int8_t active_side ; [L381] int8_t tmp ; [L382] int8_t side1 ; [L383] int8_t side2 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L386] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [\old(index)=0, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L386] RET, EXPR read_active_side_history((unsigned char)0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L386] tmp = read_active_side_history((unsigned char)0) [L387] active_side = tmp [L388] side1 = nomsg [L389] side2 = nomsg [L390] side1 = s1p_old [L391] s1p_old = nomsg [L392] side2 = s2p_old [L393] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L394] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L397] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L400] COND FALSE !((int )side1 == 0) [L407] active_side = (int8_t )0 VAL [active_side=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=-1, cs2=0, cs2_new=0, cs2_old=-1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L409] CALL write_active_side_history(active_side) [L137] active_side_History_2 = active_side_History_1 [L138] active_side_History_1 = active_side_History_0 [L139] active_side_History_0 = val [L409] RET write_active_side_history(active_side) [L579] RET Pendulum_prism_task_each_pals_period() [L580] cs1_old = cs1_new [L581] cs1_new = nomsg [L582] cs2_old = cs2_new [L583] cs2_new = nomsg [L584] s1s2_old = s1s2_new [L585] s1s2_new = nomsg [L586] s1s1_old = s1s1_new [L587] s1s1_new = nomsg [L588] s2s1_old = s2s1_new [L589] s2s1_new = nomsg [L590] s2s2_old = s2s2_new [L591] s2s2_new = nomsg [L592] s1p_old = s1p_new [L593] s1p_new = nomsg [L594] s2p_old = s2p_new [L595] s2p_new = nomsg [L596] CALL, EXPR check() [L415] int tmp ; [L416] msg_t tmp___0 ; [L417] _Bool tmp___1 ; [L418] _Bool tmp___2 ; [L419] _Bool tmp___3 ; [L420] _Bool tmp___4 ; [L421] int8_t tmp___5 ; [L422] _Bool tmp___6 ; [L423] _Bool tmp___7 ; [L424] _Bool tmp___8 ; [L425] int8_t tmp___9 ; [L426] _Bool tmp___10 ; [L427] _Bool tmp___11 ; [L428] _Bool tmp___12 ; [L429] msg_t tmp___13 ; [L430] _Bool tmp___14 ; [L431] _Bool tmp___15 ; [L432] _Bool tmp___16 ; [L433] _Bool tmp___17 ; [L434] int8_t tmp___18 ; [L435] int8_t tmp___19 ; [L436] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L439] COND TRUE ! side1Failed [L440] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L447] CALL assume_abort_if_not((_Bool )tmp) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L58] COND FALSE !(!cond) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L447] RET assume_abort_if_not((_Bool )tmp) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L448] CALL, EXPR read_manual_selection_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L178] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, index=1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L181] COND TRUE (int )index == 1 [L182] return (manual_selection_History_1); VAL [\old(index)=1, \result=-1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L448] RET, EXPR read_manual_selection_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L448] tmp___0 = read_manual_selection_history((unsigned char)1) [L449] COND FALSE !(! tmp___0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L478] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, index=1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L478] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L478] tmp___7 = read_side1_failed_history((unsigned char)1) [L479] COND TRUE \read(tmp___7) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L480] CALL, EXPR read_side2_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L118] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, index=1, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L121] COND TRUE (int )index == 1 [L122] return (side2Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L480] RET, EXPR read_side2_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L480] tmp___8 = read_side2_failed_history((unsigned char)1) [L481] COND TRUE ! tmp___8 VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L482] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [\old(index)=0, \result=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L482] RET, EXPR read_active_side_history((unsigned char)0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L482] tmp___5 = read_active_side_history((unsigned char)0) [L483] COND TRUE ! ((int )tmp___5 == 2) [L484] return (0); VAL [\result=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L596] RET, EXPR check() [L596] c1 = check() [L597] CALL assert(c1) VAL [\old(arg)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L608] COND TRUE ! arg VAL [\old(arg)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L610] reach_error() VAL [\old(arg)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=0, cs2=0, cs2_new=-1, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 8 procedures, 169 locations, 297 edges, 1 error locations. Started 1 CEGAR loops. OverallTime: 46.2s, OverallIterations: 33, TraceHistogramMax: 5, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.1s, AutomataDifference: 22.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 13363 SdHoareTripleChecker+Valid, 7.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 13306 mSDsluCounter, 49922 SdHoareTripleChecker+Invalid, 6.0s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 40093 mSDsCounter, 3706 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 10057 IncrementalHoareTripleChecker+Invalid, 13763 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 3706 mSolverCounterUnsat, 9829 mSDtfsCounter, 10057 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 2355 GetRequests, 1930 SyntacticMatches, 0 SemanticMatches, 425 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4525 ImplicationChecksByTransitivity, 5.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=12310occurred in iteration=32, InterpolantAutomatonStates: 342, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 9.4s AutomataMinimizationTime, 32 MinimizatonAttempts, 22646 StatesRemovedByMinimization, 23 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.4s SsaConstructionTime, 1.5s SatisfiabilityAnalysisTime, 10.0s InterpolantComputationTime, 3911 NumberOfCodeBlocks, 3911 NumberOfCodeBlocksAsserted, 40 NumberOfCheckSat, 4591 ConstructedInterpolants, 0 QuantifiedInterpolants, 11890 SizeOfPredicates, 33 NumberOfNonLiveVariables, 4576 ConjunctsInSsa, 181 ConjunctsInUnsatCore, 45 InterpolantComputations, 27 PerfectInterpolantSequences, 1613/1852 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2025-03-16 19:05:27,490 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE