./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 8fc3dc66 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 01a21536345230b7194ff5017879c469eb8be909ba72352bb81feb2f101a934f --- Real Ultimate output --- This is Ultimate 0.3.0-?-8fc3dc6-m [2025-03-16 19:04:41,243 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-16 19:04:41,300 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2025-03-16 19:04:41,304 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-16 19:04:41,304 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-16 19:04:41,326 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-16 19:04:41,327 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-16 19:04:41,327 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-16 19:04:41,328 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-16 19:04:41,328 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-16 19:04:41,328 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2025-03-16 19:04:41,329 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2025-03-16 19:04:41,329 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-16 19:04:41,329 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-16 19:04:41,329 INFO L153 SettingsManager]: * Use SBE=true [2025-03-16 19:04:41,329 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-16 19:04:41,329 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-16 19:04:41,330 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2025-03-16 19:04:41,330 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Compute procedure contracts=false [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2025-03-16 19:04:41,330 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2025-03-16 19:04:41,331 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2025-03-16 19:04:41,331 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2025-03-16 19:04:41,331 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2025-03-16 19:04:41,331 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 01a21536345230b7194ff5017879c469eb8be909ba72352bb81feb2f101a934f [2025-03-16 19:04:41,721 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-16 19:04:41,727 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-16 19:04:41,728 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-16 19:04:41,729 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-16 19:04:41,729 INFO L274 PluginConnector]: CDTParser initialized [2025-03-16 19:04:41,730 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c [2025-03-16 19:04:42,869 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5410f7521/33880d66caba471ea3c2e7baf34ff178/FLAG56a18b3e4 [2025-03-16 19:04:43,146 INFO L384 CDTParser]: Found 1 translation units. [2025-03-16 19:04:43,148 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c [2025-03-16 19:04:43,161 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5410f7521/33880d66caba471ea3c2e7baf34ff178/FLAG56a18b3e4 [2025-03-16 19:04:43,179 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5410f7521/33880d66caba471ea3c2e7baf34ff178 [2025-03-16 19:04:43,180 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-16 19:04:43,181 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-16 19:04:43,183 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-16 19:04:43,186 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-16 19:04:43,195 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-16 19:04:43,196 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,196 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@74aa84db and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43, skipping insertion in model container [2025-03-16 19:04:43,198 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,219 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-16 19:04:43,428 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c[14684,14697] [2025-03-16 19:04:43,435 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-16 19:04:43,443 INFO L200 MainTranslator]: Completed pre-run [2025-03-16 19:04:43,495 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c[14684,14697] [2025-03-16 19:04:43,499 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-16 19:04:43,515 INFO L204 MainTranslator]: Completed translation [2025-03-16 19:04:43,516 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43 WrapperNode [2025-03-16 19:04:43,516 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-16 19:04:43,517 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-16 19:04:43,517 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-16 19:04:43,518 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-16 19:04:43,522 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,536 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,573 INFO L138 Inliner]: procedures = 32, calls = 48, calls flagged for inlining = 12, calls inlined = 12, statements flattened = 504 [2025-03-16 19:04:43,574 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-16 19:04:43,574 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-16 19:04:43,575 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-16 19:04:43,575 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-16 19:04:43,582 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,582 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,587 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,619 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-16 19:04:43,619 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,619 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,631 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,638 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,640 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,641 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,646 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-16 19:04:43,647 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-16 19:04:43,647 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-16 19:04:43,647 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-16 19:04:43,648 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (1/1) ... [2025-03-16 19:04:43,652 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2025-03-16 19:04:43,660 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:04:43,673 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2025-03-16 19:04:43,675 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2025-03-16 19:04:43,696 INFO L130 BoogieDeclarations]: Found specification of procedure read_manual_selection_history [2025-03-16 19:04:43,696 INFO L138 BoogieDeclarations]: Found implementation of procedure read_manual_selection_history [2025-03-16 19:04:43,696 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-16 19:04:43,696 INFO L130 BoogieDeclarations]: Found specification of procedure read_side2_failed_history [2025-03-16 19:04:43,696 INFO L138 BoogieDeclarations]: Found implementation of procedure read_side2_failed_history [2025-03-16 19:04:43,696 INFO L130 BoogieDeclarations]: Found specification of procedure assert [2025-03-16 19:04:43,696 INFO L138 BoogieDeclarations]: Found implementation of procedure assert [2025-03-16 19:04:43,697 INFO L130 BoogieDeclarations]: Found specification of procedure flip_the_side [2025-03-16 19:04:43,697 INFO L138 BoogieDeclarations]: Found implementation of procedure flip_the_side [2025-03-16 19:04:43,697 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2025-03-16 19:04:43,697 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2025-03-16 19:04:43,697 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-16 19:04:43,697 INFO L130 BoogieDeclarations]: Found specification of procedure read_side1_failed_history [2025-03-16 19:04:43,697 INFO L138 BoogieDeclarations]: Found implementation of procedure read_side1_failed_history [2025-03-16 19:04:43,697 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-16 19:04:43,697 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-16 19:04:43,697 INFO L130 BoogieDeclarations]: Found specification of procedure read_active_side_history [2025-03-16 19:04:43,697 INFO L138 BoogieDeclarations]: Found implementation of procedure read_active_side_history [2025-03-16 19:04:43,777 INFO L256 CfgBuilder]: Building ICFG [2025-03-16 19:04:43,779 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-16 19:04:44,262 INFO L? ?]: Removed 102 outVars from TransFormulas that were not future-live. [2025-03-16 19:04:44,263 INFO L307 CfgBuilder]: Performing block encoding [2025-03-16 19:04:44,273 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-16 19:04:44,274 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-16 19:04:44,275 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 16.03 07:04:44 BoogieIcfgContainer [2025-03-16 19:04:44,275 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-16 19:04:44,277 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2025-03-16 19:04:44,278 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2025-03-16 19:04:44,281 INFO L274 PluginConnector]: TraceAbstraction initialized [2025-03-16 19:04:44,282 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 16.03 07:04:43" (1/3) ... [2025-03-16 19:04:44,282 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@356fdfd7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.03 07:04:44, skipping insertion in model container [2025-03-16 19:04:44,282 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.03 07:04:43" (2/3) ... [2025-03-16 19:04:44,283 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@356fdfd7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.03 07:04:44, skipping insertion in model container [2025-03-16 19:04:44,283 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 16.03 07:04:44" (3/3) ... [2025-03-16 19:04:44,284 INFO L128 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c [2025-03-16 19:04:44,294 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2025-03-16 19:04:44,295 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG pals_STARTPALS_ActiveStandby.4_2.ufo.UNBOUNDED.pals.c that has 8 procedures, 171 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2025-03-16 19:04:44,365 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2025-03-16 19:04:44,373 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@7d2a0c2b, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2025-03-16 19:04:44,374 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2025-03-16 19:04:44,378 INFO L276 IsEmpty]: Start isEmpty. Operand has 171 states, 131 states have (on average 1.5877862595419847) internal successors, (208), 133 states have internal predecessors, (208), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-16 19:04:44,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2025-03-16 19:04:44,383 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:44,383 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:44,384 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:44,388 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:44,388 INFO L85 PathProgramCache]: Analyzing trace with hash 1121965192, now seen corresponding path program 1 times [2025-03-16 19:04:44,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:44,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304010234] [2025-03-16 19:04:44,396 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:44,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:44,457 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes. [2025-03-16 19:04:44,499 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements. [2025-03-16 19:04:44,500 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:44,500 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:44,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-16 19:04:44,601 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:44,601 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1304010234] [2025-03-16 19:04:44,601 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1304010234] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:44,601 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:44,601 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-16 19:04:44,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269166376] [2025-03-16 19:04:44,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:44,606 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2025-03-16 19:04:44,607 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:44,621 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-16 19:04:44,622 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-16 19:04:44,623 INFO L87 Difference]: Start difference. First operand has 171 states, 131 states have (on average 1.5877862595419847) internal successors, (208), 133 states have internal predecessors, (208), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) Second operand has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-16 19:04:44,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:44,651 INFO L93 Difference]: Finished difference Result 325 states and 540 transitions. [2025-03-16 19:04:44,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-16 19:04:44,653 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2025-03-16 19:04:44,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:44,657 INFO L225 Difference]: With dead ends: 325 [2025-03-16 19:04:44,658 INFO L226 Difference]: Without dead ends: 169 [2025-03-16 19:04:44,660 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-16 19:04:44,662 INFO L435 NwaCegarLoop]: 266 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 266 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:44,662 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 266 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:44,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2025-03-16 19:04:44,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 169. [2025-03-16 19:04:44,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 169 states, 130 states have (on average 1.5692307692307692) internal successors, (204), 131 states have internal predecessors, (204), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-16 19:04:44,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 266 transitions. [2025-03-16 19:04:44,693 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 266 transitions. Word has length 23 [2025-03-16 19:04:44,694 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:44,694 INFO L471 AbstractCegarLoop]: Abstraction has 169 states and 266 transitions. [2025-03-16 19:04:44,694 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-16 19:04:44,694 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 266 transitions. [2025-03-16 19:04:44,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2025-03-16 19:04:44,695 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:44,695 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:44,695 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2025-03-16 19:04:44,696 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:44,696 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:44,696 INFO L85 PathProgramCache]: Analyzing trace with hash 124892839, now seen corresponding path program 1 times [2025-03-16 19:04:44,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:44,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081532172] [2025-03-16 19:04:44,696 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:44,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:44,714 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes. [2025-03-16 19:04:44,749 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements. [2025-03-16 19:04:44,749 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:44,750 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:44,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-16 19:04:44,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:44,907 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081532172] [2025-03-16 19:04:44,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2081532172] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:44,907 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:44,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-16 19:04:44,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1658486346] [2025-03-16 19:04:44,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:44,908 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-03-16 19:04:44,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:44,908 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-16 19:04:44,908 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-16 19:04:44,909 INFO L87 Difference]: Start difference. First operand 169 states and 266 transitions. Second operand has 6 states, 5 states have (on average 3.8) internal successors, (19), 6 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-16 19:04:44,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:44,988 INFO L93 Difference]: Finished difference Result 325 states and 507 transitions. [2025-03-16 19:04:44,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-16 19:04:44,989 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 3.8) internal successors, (19), 6 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2025-03-16 19:04:44,989 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:44,990 INFO L225 Difference]: With dead ends: 325 [2025-03-16 19:04:44,990 INFO L226 Difference]: Without dead ends: 169 [2025-03-16 19:04:44,991 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-16 19:04:44,991 INFO L435 NwaCegarLoop]: 262 mSDtfsCounter, 0 mSDsluCounter, 1026 mSDsCounter, 0 mSdLazyCounter, 27 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1288 SdHoareTripleChecker+Invalid, 38 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 27 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:44,992 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1288 Invalid, 38 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 27 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:44,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2025-03-16 19:04:45,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 169. [2025-03-16 19:04:45,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 169 states, 130 states have (on average 1.476923076923077) internal successors, (192), 131 states have internal predecessors, (192), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-16 19:04:45,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 254 transitions. [2025-03-16 19:04:45,009 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 254 transitions. Word has length 23 [2025-03-16 19:04:45,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:45,009 INFO L471 AbstractCegarLoop]: Abstraction has 169 states and 254 transitions. [2025-03-16 19:04:45,010 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 3.8) internal successors, (19), 6 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-16 19:04:45,010 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 254 transitions. [2025-03-16 19:04:45,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2025-03-16 19:04:45,011 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:45,011 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:45,011 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2025-03-16 19:04:45,011 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:45,011 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:45,012 INFO L85 PathProgramCache]: Analyzing trace with hash 1483767637, now seen corresponding path program 1 times [2025-03-16 19:04:45,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:45,012 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [474564062] [2025-03-16 19:04:45,012 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:45,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:45,029 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-16 19:04:45,084 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-16 19:04:45,084 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:45,084 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:45,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-16 19:04:45,245 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:45,245 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [474564062] [2025-03-16 19:04:45,245 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [474564062] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:45,246 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:45,246 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:45,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083079243] [2025-03-16 19:04:45,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:45,246 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:45,246 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:45,248 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:45,248 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:45,248 INFO L87 Difference]: Start difference. First operand 169 states and 254 transitions. Second operand has 4 states, 4 states have (on average 7.5) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-16 19:04:45,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:45,303 INFO L93 Difference]: Finished difference Result 326 states and 499 transitions. [2025-03-16 19:04:45,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:45,303 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 7.5) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 34 [2025-03-16 19:04:45,304 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:45,305 INFO L225 Difference]: With dead ends: 326 [2025-03-16 19:04:45,305 INFO L226 Difference]: Without dead ends: 173 [2025-03-16 19:04:45,306 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:45,306 INFO L435 NwaCegarLoop]: 248 mSDtfsCounter, 3 mSDsluCounter, 486 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 734 SdHoareTripleChecker+Invalid, 27 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:45,306 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 734 Invalid, 27 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 24 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:45,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2025-03-16 19:04:45,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 173. [2025-03-16 19:04:45,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 173 states, 133 states have (on average 1.4661654135338347) internal successors, (195), 134 states have internal predecessors, (195), 31 states have call successors, (31), 8 states have call predecessors, (31), 8 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-16 19:04:45,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 257 transitions. [2025-03-16 19:04:45,323 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 257 transitions. Word has length 34 [2025-03-16 19:04:45,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:45,323 INFO L471 AbstractCegarLoop]: Abstraction has 173 states and 257 transitions. [2025-03-16 19:04:45,323 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 7.5) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-16 19:04:45,323 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 257 transitions. [2025-03-16 19:04:45,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2025-03-16 19:04:45,325 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:45,325 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:45,325 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2025-03-16 19:04:45,325 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:45,326 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:45,326 INFO L85 PathProgramCache]: Analyzing trace with hash 1488564047, now seen corresponding path program 1 times [2025-03-16 19:04:45,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:45,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501720249] [2025-03-16 19:04:45,326 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:45,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:45,341 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 48 statements into 1 equivalence classes. [2025-03-16 19:04:45,355 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 48 of 48 statements. [2025-03-16 19:04:45,358 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:45,358 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:45,414 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:45,415 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:45,415 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501720249] [2025-03-16 19:04:45,415 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [501720249] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:45,415 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:45,415 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-16 19:04:45,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1313855762] [2025-03-16 19:04:45,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:45,415 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-03-16 19:04:45,415 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:45,416 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-16 19:04:45,416 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-16 19:04:45,416 INFO L87 Difference]: Start difference. First operand 173 states and 257 transitions. Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:45,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:45,452 INFO L93 Difference]: Finished difference Result 476 states and 717 transitions. [2025-03-16 19:04:45,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-16 19:04:45,455 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 48 [2025-03-16 19:04:45,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:45,457 INFO L225 Difference]: With dead ends: 476 [2025-03-16 19:04:45,457 INFO L226 Difference]: Without dead ends: 319 [2025-03-16 19:04:45,457 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-16 19:04:45,458 INFO L435 NwaCegarLoop]: 262 mSDtfsCounter, 210 mSDsluCounter, 246 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 210 SdHoareTripleChecker+Valid, 508 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:45,459 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [210 Valid, 508 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:45,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states. [2025-03-16 19:04:45,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 316. [2025-03-16 19:04:45,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 316 states, 239 states have (on average 1.4811715481171548) internal successors, (354), 241 states have internal predecessors, (354), 60 states have call successors, (60), 16 states have call predecessors, (60), 16 states have return successors, (60), 59 states have call predecessors, (60), 60 states have call successors, (60) [2025-03-16 19:04:45,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 316 states to 316 states and 474 transitions. [2025-03-16 19:04:45,488 INFO L78 Accepts]: Start accepts. Automaton has 316 states and 474 transitions. Word has length 48 [2025-03-16 19:04:45,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:45,488 INFO L471 AbstractCegarLoop]: Abstraction has 316 states and 474 transitions. [2025-03-16 19:04:45,489 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:45,489 INFO L276 IsEmpty]: Start isEmpty. Operand 316 states and 474 transitions. [2025-03-16 19:04:45,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2025-03-16 19:04:45,491 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:45,491 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:45,491 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2025-03-16 19:04:45,491 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:45,491 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:45,491 INFO L85 PathProgramCache]: Analyzing trace with hash -1859972046, now seen corresponding path program 1 times [2025-03-16 19:04:45,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:45,492 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [200649156] [2025-03-16 19:04:45,492 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:45,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:45,506 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-03-16 19:04:45,520 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-03-16 19:04:45,522 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:45,522 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:45,568 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:45,569 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:45,569 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [200649156] [2025-03-16 19:04:45,569 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [200649156] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:45,569 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:45,569 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-16 19:04:45,569 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462369193] [2025-03-16 19:04:45,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:45,569 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-03-16 19:04:45,569 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:45,569 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-16 19:04:45,570 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-16 19:04:45,570 INFO L87 Difference]: Start difference. First operand 316 states and 474 transitions. Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:45,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:45,618 INFO L93 Difference]: Finished difference Result 891 states and 1347 transitions. [2025-03-16 19:04:45,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-16 19:04:45,619 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 49 [2025-03-16 19:04:45,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:45,623 INFO L225 Difference]: With dead ends: 891 [2025-03-16 19:04:45,624 INFO L226 Difference]: Without dead ends: 591 [2025-03-16 19:04:45,625 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-16 19:04:45,625 INFO L435 NwaCegarLoop]: 281 mSDtfsCounter, 211 mSDsluCounter, 248 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 211 SdHoareTripleChecker+Valid, 529 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:45,626 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [211 Valid, 529 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:45,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 591 states. [2025-03-16 19:04:45,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 591 to 585. [2025-03-16 19:04:45,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 585 states, 436 states have (on average 1.4908256880733946) internal successors, (650), 440 states have internal predecessors, (650), 117 states have call successors, (117), 31 states have call predecessors, (117), 31 states have return successors, (117), 114 states have call predecessors, (117), 117 states have call successors, (117) [2025-03-16 19:04:45,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 585 states to 585 states and 884 transitions. [2025-03-16 19:04:45,670 INFO L78 Accepts]: Start accepts. Automaton has 585 states and 884 transitions. Word has length 49 [2025-03-16 19:04:45,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:45,671 INFO L471 AbstractCegarLoop]: Abstraction has 585 states and 884 transitions. [2025-03-16 19:04:45,671 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:45,672 INFO L276 IsEmpty]: Start isEmpty. Operand 585 states and 884 transitions. [2025-03-16 19:04:45,673 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2025-03-16 19:04:45,676 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:45,676 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:45,676 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2025-03-16 19:04:45,676 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:45,677 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:45,677 INFO L85 PathProgramCache]: Analyzing trace with hash -352420237, now seen corresponding path program 1 times [2025-03-16 19:04:45,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:45,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61348944] [2025-03-16 19:04:45,677 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:45,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:45,689 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-03-16 19:04:45,715 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-03-16 19:04:45,715 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:45,715 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:45,808 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:45,808 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:45,808 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [61348944] [2025-03-16 19:04:45,808 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [61348944] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:45,808 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:45,808 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-16 19:04:45,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416166497] [2025-03-16 19:04:45,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:45,809 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-03-16 19:04:45,809 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:45,809 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-16 19:04:45,809 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:45,809 INFO L87 Difference]: Start difference. First operand 585 states and 884 transitions. Second operand has 5 states, 5 states have (on average 7.6) internal successors, (38), 5 states have internal predecessors, (38), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:45,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:45,965 INFO L93 Difference]: Finished difference Result 1245 states and 1882 transitions. [2025-03-16 19:04:45,965 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-16 19:04:45,965 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 7.6) internal successors, (38), 5 states have internal predecessors, (38), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 49 [2025-03-16 19:04:45,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:45,971 INFO L225 Difference]: With dead ends: 1245 [2025-03-16 19:04:45,972 INFO L226 Difference]: Without dead ends: 676 [2025-03-16 19:04:45,974 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:04:45,975 INFO L435 NwaCegarLoop]: 221 mSDtfsCounter, 350 mSDsluCounter, 432 mSDsCounter, 0 mSdLazyCounter, 95 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 350 SdHoareTripleChecker+Valid, 653 SdHoareTripleChecker+Invalid, 109 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 95 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:45,975 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [350 Valid, 653 Invalid, 109 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 95 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:45,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 676 states. [2025-03-16 19:04:46,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 676 to 668. [2025-03-16 19:04:46,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 668 states, 506 states have (on average 1.476284584980237) internal successors, (747), 509 states have internal predecessors, (747), 124 states have call successors, (124), 37 states have call predecessors, (124), 37 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:46,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 668 states and 995 transitions. [2025-03-16 19:04:46,016 INFO L78 Accepts]: Start accepts. Automaton has 668 states and 995 transitions. Word has length 49 [2025-03-16 19:04:46,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:46,017 INFO L471 AbstractCegarLoop]: Abstraction has 668 states and 995 transitions. [2025-03-16 19:04:46,017 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 7.6) internal successors, (38), 5 states have internal predecessors, (38), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:46,017 INFO L276 IsEmpty]: Start isEmpty. Operand 668 states and 995 transitions. [2025-03-16 19:04:46,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2025-03-16 19:04:46,020 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:46,020 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:46,020 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2025-03-16 19:04:46,020 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:46,020 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:46,020 INFO L85 PathProgramCache]: Analyzing trace with hash 1543114588, now seen corresponding path program 1 times [2025-03-16 19:04:46,020 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:46,020 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532353002] [2025-03-16 19:04:46,021 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:46,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:46,032 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-03-16 19:04:46,056 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-16 19:04:46,059 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:46,059 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:46,132 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:46,133 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:46,133 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1532353002] [2025-03-16 19:04:46,133 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1532353002] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:46,133 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:46,133 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-16 19:04:46,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [182180553] [2025-03-16 19:04:46,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:46,134 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-03-16 19:04:46,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:46,134 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-16 19:04:46,135 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:46,135 INFO L87 Difference]: Start difference. First operand 668 states and 995 transitions. Second operand has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:46,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:46,275 INFO L93 Difference]: Finished difference Result 1249 states and 1882 transitions. [2025-03-16 19:04:46,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-16 19:04:46,276 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 50 [2025-03-16 19:04:46,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:46,280 INFO L225 Difference]: With dead ends: 1249 [2025-03-16 19:04:46,280 INFO L226 Difference]: Without dead ends: 680 [2025-03-16 19:04:46,282 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:04:46,283 INFO L435 NwaCegarLoop]: 221 mSDtfsCounter, 350 mSDsluCounter, 432 mSDsCounter, 0 mSdLazyCounter, 95 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 350 SdHoareTripleChecker+Valid, 653 SdHoareTripleChecker+Invalid, 109 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 95 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:46,283 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [350 Valid, 653 Invalid, 109 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 95 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:46,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 680 states. [2025-03-16 19:04:46,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 680 to 676. [2025-03-16 19:04:46,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 676 states, 514 states have (on average 1.4688715953307394) internal successors, (755), 517 states have internal predecessors, (755), 124 states have call successors, (124), 37 states have call predecessors, (124), 37 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:46,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 676 states to 676 states and 1003 transitions. [2025-03-16 19:04:46,340 INFO L78 Accepts]: Start accepts. Automaton has 676 states and 1003 transitions. Word has length 50 [2025-03-16 19:04:46,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:46,341 INFO L471 AbstractCegarLoop]: Abstraction has 676 states and 1003 transitions. [2025-03-16 19:04:46,341 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:46,341 INFO L276 IsEmpty]: Start isEmpty. Operand 676 states and 1003 transitions. [2025-03-16 19:04:46,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2025-03-16 19:04:46,342 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:46,342 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:46,342 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2025-03-16 19:04:46,343 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:46,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:46,343 INFO L85 PathProgramCache]: Analyzing trace with hash -1913384715, now seen corresponding path program 1 times [2025-03-16 19:04:46,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:46,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227978413] [2025-03-16 19:04:46,343 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:46,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:46,352 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 52 statements into 1 equivalence classes. [2025-03-16 19:04:46,366 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-03-16 19:04:46,371 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:46,371 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:46,445 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:46,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:46,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [227978413] [2025-03-16 19:04:46,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [227978413] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:46,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:46,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:46,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1604453334] [2025-03-16 19:04:46,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:46,446 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:46,446 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:46,446 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:46,446 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:46,446 INFO L87 Difference]: Start difference. First operand 676 states and 1003 transitions. Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:46,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:46,566 INFO L93 Difference]: Finished difference Result 1245 states and 1870 transitions. [2025-03-16 19:04:46,566 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:46,566 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 52 [2025-03-16 19:04:46,566 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:46,570 INFO L225 Difference]: With dead ends: 1245 [2025-03-16 19:04:46,570 INFO L226 Difference]: Without dead ends: 676 [2025-03-16 19:04:46,571 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:46,572 INFO L435 NwaCegarLoop]: 222 mSDtfsCounter, 59 mSDsluCounter, 425 mSDsCounter, 0 mSdLazyCounter, 101 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 59 SdHoareTripleChecker+Valid, 647 SdHoareTripleChecker+Invalid, 103 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 101 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:46,572 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [59 Valid, 647 Invalid, 103 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 101 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:46,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 676 states. [2025-03-16 19:04:46,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 676 to 676. [2025-03-16 19:04:46,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 676 states, 514 states have (on average 1.461089494163424) internal successors, (751), 517 states have internal predecessors, (751), 124 states have call successors, (124), 37 states have call predecessors, (124), 37 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:46,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 676 states to 676 states and 999 transitions. [2025-03-16 19:04:46,604 INFO L78 Accepts]: Start accepts. Automaton has 676 states and 999 transitions. Word has length 52 [2025-03-16 19:04:46,604 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:46,604 INFO L471 AbstractCegarLoop]: Abstraction has 676 states and 999 transitions. [2025-03-16 19:04:46,604 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-16 19:04:46,605 INFO L276 IsEmpty]: Start isEmpty. Operand 676 states and 999 transitions. [2025-03-16 19:04:46,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2025-03-16 19:04:46,605 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:46,605 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:46,605 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2025-03-16 19:04:46,606 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:46,606 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:46,606 INFO L85 PathProgramCache]: Analyzing trace with hash 406717546, now seen corresponding path program 1 times [2025-03-16 19:04:46,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:46,606 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613900808] [2025-03-16 19:04:46,606 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:46,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:46,615 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 53 statements into 1 equivalence classes. [2025-03-16 19:04:46,624 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 53 of 53 statements. [2025-03-16 19:04:46,624 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:46,624 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:46,762 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:46,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:46,763 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613900808] [2025-03-16 19:04:46,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [613900808] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:46,763 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:46,763 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:46,763 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062783798] [2025-03-16 19:04:46,763 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:46,763 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:46,763 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:46,763 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:46,763 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:46,763 INFO L87 Difference]: Start difference. First operand 676 states and 999 transitions. Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (5), 3 states have call predecessors, (5), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2025-03-16 19:04:46,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:46,808 INFO L93 Difference]: Finished difference Result 1265 states and 1894 transitions. [2025-03-16 19:04:46,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:46,809 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 10.5) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (5), 3 states have call predecessors, (5), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 53 [2025-03-16 19:04:46,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:46,812 INFO L225 Difference]: With dead ends: 1265 [2025-03-16 19:04:46,812 INFO L226 Difference]: Without dead ends: 696 [2025-03-16 19:04:46,814 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:46,817 INFO L435 NwaCegarLoop]: 250 mSDtfsCounter, 4 mSDsluCounter, 496 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 746 SdHoareTripleChecker+Invalid, 16 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:46,817 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 746 Invalid, 16 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:46,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 696 states. [2025-03-16 19:04:46,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 696 to 696. [2025-03-16 19:04:46,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 696 states, 530 states have (on average 1.4471698113207547) internal successors, (767), 533 states have internal predecessors, (767), 124 states have call successors, (124), 41 states have call predecessors, (124), 41 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:46,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 696 states to 696 states and 1015 transitions. [2025-03-16 19:04:46,851 INFO L78 Accepts]: Start accepts. Automaton has 696 states and 1015 transitions. Word has length 53 [2025-03-16 19:04:46,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:46,851 INFO L471 AbstractCegarLoop]: Abstraction has 696 states and 1015 transitions. [2025-03-16 19:04:46,851 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 10.5) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (5), 3 states have call predecessors, (5), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2025-03-16 19:04:46,851 INFO L276 IsEmpty]: Start isEmpty. Operand 696 states and 1015 transitions. [2025-03-16 19:04:46,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2025-03-16 19:04:46,852 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:46,853 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:46,853 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2025-03-16 19:04:46,853 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:46,853 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:46,853 INFO L85 PathProgramCache]: Analyzing trace with hash 1247248620, now seen corresponding path program 1 times [2025-03-16 19:04:46,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:46,853 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488803079] [2025-03-16 19:04:46,853 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:46,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:46,866 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 61 statements into 1 equivalence classes. [2025-03-16 19:04:46,880 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 61 of 61 statements. [2025-03-16 19:04:46,884 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:46,884 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:47,001 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:47,001 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:47,001 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488803079] [2025-03-16 19:04:47,002 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1488803079] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:47,002 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:47,002 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:47,002 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [60293340] [2025-03-16 19:04:47,002 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:47,002 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:47,002 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:47,002 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:47,002 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:47,002 INFO L87 Difference]: Start difference. First operand 696 states and 1015 transitions. Second operand has 4 states, 4 states have (on average 12.0) internal successors, (48), 3 states have internal predecessors, (48), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (4), 1 states have call predecessors, (4), 1 states have call successors, (4) [2025-03-16 19:04:47,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:47,059 INFO L93 Difference]: Finished difference Result 1305 states and 1938 transitions. [2025-03-16 19:04:47,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:47,060 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 12.0) internal successors, (48), 3 states have internal predecessors, (48), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (4), 1 states have call predecessors, (4), 1 states have call successors, (4) Word has length 61 [2025-03-16 19:04:47,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:47,063 INFO L225 Difference]: With dead ends: 1305 [2025-03-16 19:04:47,063 INFO L226 Difference]: Without dead ends: 716 [2025-03-16 19:04:47,065 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:47,066 INFO L435 NwaCegarLoop]: 247 mSDtfsCounter, 4 mSDsluCounter, 485 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 732 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:47,066 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 732 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:47,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 716 states. [2025-03-16 19:04:47,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 716 to 716. [2025-03-16 19:04:47,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 716 states, 546 states have (on average 1.434065934065934) internal successors, (783), 549 states have internal predecessors, (783), 124 states have call successors, (124), 45 states have call predecessors, (124), 45 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:47,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 716 states and 1031 transitions. [2025-03-16 19:04:47,098 INFO L78 Accepts]: Start accepts. Automaton has 716 states and 1031 transitions. Word has length 61 [2025-03-16 19:04:47,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:47,098 INFO L471 AbstractCegarLoop]: Abstraction has 716 states and 1031 transitions. [2025-03-16 19:04:47,098 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 12.0) internal successors, (48), 3 states have internal predecessors, (48), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (4), 1 states have call predecessors, (4), 1 states have call successors, (4) [2025-03-16 19:04:47,099 INFO L276 IsEmpty]: Start isEmpty. Operand 716 states and 1031 transitions. [2025-03-16 19:04:47,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2025-03-16 19:04:47,099 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:47,099 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:47,100 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2025-03-16 19:04:47,100 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:47,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:47,100 INFO L85 PathProgramCache]: Analyzing trace with hash 1217007026, now seen corresponding path program 1 times [2025-03-16 19:04:47,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:47,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017297959] [2025-03-16 19:04:47,100 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:47,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:47,109 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 69 statements into 1 equivalence classes. [2025-03-16 19:04:47,130 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 69 of 69 statements. [2025-03-16 19:04:47,131 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:47,131 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:47,205 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:47,205 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:47,205 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017297959] [2025-03-16 19:04:47,205 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1017297959] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:47,205 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:47,205 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:47,206 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832002595] [2025-03-16 19:04:47,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:47,206 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:47,206 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:47,206 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:47,206 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:47,207 INFO L87 Difference]: Start difference. First operand 716 states and 1031 transitions. Second operand has 4 states, 4 states have (on average 13.5) internal successors, (54), 3 states have internal predecessors, (54), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-16 19:04:47,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:47,251 INFO L93 Difference]: Finished difference Result 1341 states and 1954 transitions. [2025-03-16 19:04:47,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:47,252 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 13.5) internal successors, (54), 3 states have internal predecessors, (54), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 69 [2025-03-16 19:04:47,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:47,255 INFO L225 Difference]: With dead ends: 1341 [2025-03-16 19:04:47,255 INFO L226 Difference]: Without dead ends: 732 [2025-03-16 19:04:47,257 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:47,257 INFO L435 NwaCegarLoop]: 252 mSDtfsCounter, 3 mSDsluCounter, 490 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 742 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:47,257 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 742 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:47,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 732 states. [2025-03-16 19:04:47,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 732 to 732. [2025-03-16 19:04:47,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 732 states, 558 states have (on average 1.424731182795699) internal successors, (795), 561 states have internal predecessors, (795), 124 states have call successors, (124), 49 states have call predecessors, (124), 49 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:47,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 732 states to 732 states and 1043 transitions. [2025-03-16 19:04:47,288 INFO L78 Accepts]: Start accepts. Automaton has 732 states and 1043 transitions. Word has length 69 [2025-03-16 19:04:47,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:47,288 INFO L471 AbstractCegarLoop]: Abstraction has 732 states and 1043 transitions. [2025-03-16 19:04:47,288 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 13.5) internal successors, (54), 3 states have internal predecessors, (54), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-16 19:04:47,288 INFO L276 IsEmpty]: Start isEmpty. Operand 732 states and 1043 transitions. [2025-03-16 19:04:47,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2025-03-16 19:04:47,291 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:47,291 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:47,292 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2025-03-16 19:04:47,292 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:47,292 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:47,292 INFO L85 PathProgramCache]: Analyzing trace with hash 585078763, now seen corresponding path program 1 times [2025-03-16 19:04:47,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:47,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247735280] [2025-03-16 19:04:47,292 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:47,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:47,302 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 69 statements into 1 equivalence classes. [2025-03-16 19:04:47,319 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 69 of 69 statements. [2025-03-16 19:04:47,319 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:47,320 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:47,435 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:04:47,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:47,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247735280] [2025-03-16 19:04:47,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [247735280] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:47,436 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:47,436 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:47,436 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [219719388] [2025-03-16 19:04:47,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:47,437 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:47,437 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:47,437 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:47,437 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:47,437 INFO L87 Difference]: Start difference. First operand 732 states and 1043 transitions. Second operand has 4 states, 4 states have (on average 13.5) internal successors, (54), 3 states have internal predecessors, (54), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-16 19:04:47,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:47,506 INFO L93 Difference]: Finished difference Result 1377 states and 1994 transitions. [2025-03-16 19:04:47,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:47,506 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 13.5) internal successors, (54), 3 states have internal predecessors, (54), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 69 [2025-03-16 19:04:47,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:47,510 INFO L225 Difference]: With dead ends: 1377 [2025-03-16 19:04:47,510 INFO L226 Difference]: Without dead ends: 752 [2025-03-16 19:04:47,512 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:47,512 INFO L435 NwaCegarLoop]: 247 mSDtfsCounter, 4 mSDsluCounter, 485 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 732 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:47,513 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 732 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:47,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 752 states. [2025-03-16 19:04:47,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 752 to 752. [2025-03-16 19:04:47,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 752 states, 574 states have (on average 1.4128919860627178) internal successors, (811), 577 states have internal predecessors, (811), 124 states have call successors, (124), 53 states have call predecessors, (124), 53 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:47,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 752 states to 752 states and 1059 transitions. [2025-03-16 19:04:47,545 INFO L78 Accepts]: Start accepts. Automaton has 752 states and 1059 transitions. Word has length 69 [2025-03-16 19:04:47,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:47,545 INFO L471 AbstractCegarLoop]: Abstraction has 752 states and 1059 transitions. [2025-03-16 19:04:47,545 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 13.5) internal successors, (54), 3 states have internal predecessors, (54), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-16 19:04:47,545 INFO L276 IsEmpty]: Start isEmpty. Operand 752 states and 1059 transitions. [2025-03-16 19:04:47,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2025-03-16 19:04:47,546 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:47,547 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:47,547 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2025-03-16 19:04:47,547 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:47,547 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:47,547 INFO L85 PathProgramCache]: Analyzing trace with hash 1205278089, now seen corresponding path program 1 times [2025-03-16 19:04:47,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:47,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102258708] [2025-03-16 19:04:47,547 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:47,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:47,555 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-16 19:04:47,566 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-16 19:04:47,566 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:47,566 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:47,682 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-16 19:04:47,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:47,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102258708] [2025-03-16 19:04:47,682 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102258708] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:47,682 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:47,682 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:47,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237370217] [2025-03-16 19:04:47,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:47,683 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:47,683 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:47,683 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:47,683 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:47,683 INFO L87 Difference]: Start difference. First operand 752 states and 1059 transitions. Second operand has 4 states, 4 states have (on average 14.0) internal successors, (56), 3 states have internal predecessors, (56), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 1 states have call predecessors, (6), 1 states have call successors, (6) [2025-03-16 19:04:47,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:47,738 INFO L93 Difference]: Finished difference Result 1421 states and 2022 transitions. [2025-03-16 19:04:47,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:47,739 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.0) internal successors, (56), 3 states have internal predecessors, (56), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 1 states have call predecessors, (6), 1 states have call successors, (6) Word has length 77 [2025-03-16 19:04:47,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:47,743 INFO L225 Difference]: With dead ends: 1421 [2025-03-16 19:04:47,743 INFO L226 Difference]: Without dead ends: 776 [2025-03-16 19:04:47,744 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:47,745 INFO L435 NwaCegarLoop]: 251 mSDtfsCounter, 5 mSDsluCounter, 493 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 744 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:47,745 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 744 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 20 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:47,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states. [2025-03-16 19:04:47,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2025-03-16 19:04:47,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 594 states have (on average 1.398989898989899) internal successors, (831), 597 states have internal predecessors, (831), 124 states have call successors, (124), 57 states have call predecessors, (124), 57 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-16 19:04:47,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1079 transitions. [2025-03-16 19:04:47,776 INFO L78 Accepts]: Start accepts. Automaton has 776 states and 1079 transitions. Word has length 77 [2025-03-16 19:04:47,776 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:47,776 INFO L471 AbstractCegarLoop]: Abstraction has 776 states and 1079 transitions. [2025-03-16 19:04:47,776 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.0) internal successors, (56), 3 states have internal predecessors, (56), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 1 states have call predecessors, (6), 1 states have call successors, (6) [2025-03-16 19:04:47,776 INFO L276 IsEmpty]: Start isEmpty. Operand 776 states and 1079 transitions. [2025-03-16 19:04:47,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2025-03-16 19:04:47,778 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:47,778 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:47,778 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2025-03-16 19:04:47,778 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:47,778 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:47,778 INFO L85 PathProgramCache]: Analyzing trace with hash 1743314406, now seen corresponding path program 1 times [2025-03-16 19:04:47,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:47,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354699212] [2025-03-16 19:04:47,779 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:47,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:47,788 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-16 19:04:47,833 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-16 19:04:47,833 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:47,833 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:48,156 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2025-03-16 19:04:48,156 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:48,156 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354699212] [2025-03-16 19:04:48,156 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1354699212] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:48,156 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:48,156 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-16 19:04:48,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [457245125] [2025-03-16 19:04:48,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:48,157 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-16 19:04:48,157 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:48,157 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-16 19:04:48,157 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:04:48,157 INFO L87 Difference]: Start difference. First operand 776 states and 1079 transitions. Second operand has 7 states, 7 states have (on average 8.428571428571429) internal successors, (59), 6 states have internal predecessors, (59), 3 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 4 states have call predecessors, (7), 3 states have call successors, (7) [2025-03-16 19:04:48,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:48,401 INFO L93 Difference]: Finished difference Result 2003 states and 2773 transitions. [2025-03-16 19:04:48,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-16 19:04:48,401 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 8.428571428571429) internal successors, (59), 6 states have internal predecessors, (59), 3 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 4 states have call predecessors, (7), 3 states have call successors, (7) Word has length 80 [2025-03-16 19:04:48,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:48,408 INFO L225 Difference]: With dead ends: 2003 [2025-03-16 19:04:48,409 INFO L226 Difference]: Without dead ends: 1334 [2025-03-16 19:04:48,410 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2025-03-16 19:04:48,411 INFO L435 NwaCegarLoop]: 254 mSDtfsCounter, 194 mSDsluCounter, 1175 mSDsCounter, 0 mSdLazyCounter, 101 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 198 SdHoareTripleChecker+Valid, 1429 SdHoareTripleChecker+Invalid, 102 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 101 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:48,411 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [198 Valid, 1429 Invalid, 102 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 101 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:48,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1334 states. [2025-03-16 19:04:48,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1334 to 1052. [2025-03-16 19:04:48,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1052 states, 797 states have (on average 1.3864491844416562) internal successors, (1105), 802 states have internal predecessors, (1105), 172 states have call successors, (172), 82 states have call predecessors, (172), 82 states have return successors, (172), 167 states have call predecessors, (172), 172 states have call successors, (172) [2025-03-16 19:04:48,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1052 states to 1052 states and 1449 transitions. [2025-03-16 19:04:48,470 INFO L78 Accepts]: Start accepts. Automaton has 1052 states and 1449 transitions. Word has length 80 [2025-03-16 19:04:48,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:48,470 INFO L471 AbstractCegarLoop]: Abstraction has 1052 states and 1449 transitions. [2025-03-16 19:04:48,470 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 8.428571428571429) internal successors, (59), 6 states have internal predecessors, (59), 3 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 4 states have call predecessors, (7), 3 states have call successors, (7) [2025-03-16 19:04:48,470 INFO L276 IsEmpty]: Start isEmpty. Operand 1052 states and 1449 transitions. [2025-03-16 19:04:48,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2025-03-16 19:04:48,471 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:48,471 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:48,472 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2025-03-16 19:04:48,472 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:48,473 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:48,473 INFO L85 PathProgramCache]: Analyzing trace with hash -1008013623, now seen corresponding path program 1 times [2025-03-16 19:04:48,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:48,473 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412240807] [2025-03-16 19:04:48,473 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:48,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:48,481 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 84 statements into 1 equivalence classes. [2025-03-16 19:04:48,493 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 84 of 84 statements. [2025-03-16 19:04:48,493 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:48,494 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:48,590 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2025-03-16 19:04:48,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:48,590 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412240807] [2025-03-16 19:04:48,590 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412240807] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:48,590 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:48,590 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:48,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070837622] [2025-03-16 19:04:48,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:48,591 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:48,591 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:48,591 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:48,591 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:48,591 INFO L87 Difference]: Start difference. First operand 1052 states and 1449 transitions. Second operand has 4 states, 4 states have (on average 15.75) internal successors, (63), 3 states have internal predecessors, (63), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-16 19:04:48,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:48,674 INFO L93 Difference]: Finished difference Result 1961 states and 2722 transitions. [2025-03-16 19:04:48,674 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:48,675 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.75) internal successors, (63), 3 states have internal predecessors, (63), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) Word has length 84 [2025-03-16 19:04:48,675 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:48,681 INFO L225 Difference]: With dead ends: 1961 [2025-03-16 19:04:48,681 INFO L226 Difference]: Without dead ends: 1076 [2025-03-16 19:04:48,684 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:48,684 INFO L435 NwaCegarLoop]: 252 mSDtfsCounter, 3 mSDsluCounter, 490 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 742 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:48,685 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 742 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:48,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1076 states. [2025-03-16 19:04:48,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1076 to 1076. [2025-03-16 19:04:48,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1076 states, 815 states have (on average 1.377914110429448) internal successors, (1123), 820 states have internal predecessors, (1123), 172 states have call successors, (172), 88 states have call predecessors, (172), 88 states have return successors, (172), 167 states have call predecessors, (172), 172 states have call successors, (172) [2025-03-16 19:04:48,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1076 states to 1076 states and 1467 transitions. [2025-03-16 19:04:48,762 INFO L78 Accepts]: Start accepts. Automaton has 1076 states and 1467 transitions. Word has length 84 [2025-03-16 19:04:48,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:48,762 INFO L471 AbstractCegarLoop]: Abstraction has 1076 states and 1467 transitions. [2025-03-16 19:04:48,762 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.75) internal successors, (63), 3 states have internal predecessors, (63), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-16 19:04:48,762 INFO L276 IsEmpty]: Start isEmpty. Operand 1076 states and 1467 transitions. [2025-03-16 19:04:48,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2025-03-16 19:04:48,763 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:48,763 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:48,763 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2025-03-16 19:04:48,763 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:48,764 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:48,764 INFO L85 PathProgramCache]: Analyzing trace with hash -1432969679, now seen corresponding path program 1 times [2025-03-16 19:04:48,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:48,764 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1377735201] [2025-03-16 19:04:48,764 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:48,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:48,780 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 83 statements into 1 equivalence classes. [2025-03-16 19:04:48,798 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 83 of 83 statements. [2025-03-16 19:04:48,798 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:48,798 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:49,034 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2025-03-16 19:04:49,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:49,035 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1377735201] [2025-03-16 19:04:49,035 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1377735201] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:04:49,035 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [790614557] [2025-03-16 19:04:49,035 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:49,036 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:04:49,036 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:04:49,038 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:04:49,050 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2025-03-16 19:04:49,122 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 83 statements into 1 equivalence classes. [2025-03-16 19:04:49,166 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 83 of 83 statements. [2025-03-16 19:04:49,167 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:49,167 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:49,169 INFO L256 TraceCheckSpWp]: Trace formula consists of 420 conjuncts, 14 conjuncts are in the unsatisfiable core [2025-03-16 19:04:49,173 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:04:49,268 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2025-03-16 19:04:49,268 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-03-16 19:04:49,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [790614557] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:49,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-03-16 19:04:49,268 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [10] total 15 [2025-03-16 19:04:49,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1697891170] [2025-03-16 19:04:49,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:49,268 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2025-03-16 19:04:49,268 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:49,269 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-16 19:04:49,269 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=180, Unknown=0, NotChecked=0, Total=210 [2025-03-16 19:04:49,269 INFO L87 Difference]: Start difference. First operand 1076 states and 1467 transitions. Second operand has 8 states, 7 states have (on average 8.428571428571429) internal successors, (59), 7 states have internal predecessors, (59), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-16 19:04:49,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:49,442 INFO L93 Difference]: Finished difference Result 2309 states and 3273 transitions. [2025-03-16 19:04:49,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-16 19:04:49,442 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 8.428571428571429) internal successors, (59), 7 states have internal predecessors, (59), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) Word has length 83 [2025-03-16 19:04:49,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:49,450 INFO L225 Difference]: With dead ends: 2309 [2025-03-16 19:04:49,450 INFO L226 Difference]: Without dead ends: 1488 [2025-03-16 19:04:49,452 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 80 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=261, Unknown=0, NotChecked=0, Total=306 [2025-03-16 19:04:49,453 INFO L435 NwaCegarLoop]: 425 mSDtfsCounter, 133 mSDsluCounter, 2356 mSDsCounter, 0 mSdLazyCounter, 124 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 159 SdHoareTripleChecker+Valid, 2781 SdHoareTripleChecker+Invalid, 126 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 124 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:49,453 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [159 Valid, 2781 Invalid, 126 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 124 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:49,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states. [2025-03-16 19:04:49,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1084. [2025-03-16 19:04:49,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1084 states, 819 states have (on average 1.3687423687423688) internal successors, (1121), 826 states have internal predecessors, (1121), 174 states have call successors, (174), 90 states have call predecessors, (174), 90 states have return successors, (174), 167 states have call predecessors, (174), 174 states have call successors, (174) [2025-03-16 19:04:49,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1084 states to 1084 states and 1469 transitions. [2025-03-16 19:04:49,529 INFO L78 Accepts]: Start accepts. Automaton has 1084 states and 1469 transitions. Word has length 83 [2025-03-16 19:04:49,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:49,530 INFO L471 AbstractCegarLoop]: Abstraction has 1084 states and 1469 transitions. [2025-03-16 19:04:49,530 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 8.428571428571429) internal successors, (59), 7 states have internal predecessors, (59), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-16 19:04:49,530 INFO L276 IsEmpty]: Start isEmpty. Operand 1084 states and 1469 transitions. [2025-03-16 19:04:49,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2025-03-16 19:04:49,531 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:49,531 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:49,538 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2025-03-16 19:04:49,732 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable15 [2025-03-16 19:04:49,733 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:49,733 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:49,733 INFO L85 PathProgramCache]: Analyzing trace with hash -918282914, now seen corresponding path program 1 times [2025-03-16 19:04:49,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:49,733 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862195346] [2025-03-16 19:04:49,733 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:49,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:49,743 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 86 statements into 1 equivalence classes. [2025-03-16 19:04:49,757 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 86 of 86 statements. [2025-03-16 19:04:49,757 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:49,757 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:49,842 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2025-03-16 19:04:49,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:49,842 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862195346] [2025-03-16 19:04:49,842 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [862195346] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:49,842 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:49,842 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-16 19:04:49,842 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038036320] [2025-03-16 19:04:49,842 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:49,842 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-16 19:04:49,842 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:49,843 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-16 19:04:49,843 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:04:49,843 INFO L87 Difference]: Start difference. First operand 1084 states and 1469 transitions. Second operand has 7 states, 7 states have (on average 8.857142857142858) internal successors, (62), 6 states have internal predecessors, (62), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) [2025-03-16 19:04:50,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:50,005 INFO L93 Difference]: Finished difference Result 1956 states and 2662 transitions. [2025-03-16 19:04:50,005 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-16 19:04:50,005 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 8.857142857142858) internal successors, (62), 6 states have internal predecessors, (62), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) Word has length 86 [2025-03-16 19:04:50,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:50,011 INFO L225 Difference]: With dead ends: 1956 [2025-03-16 19:04:50,012 INFO L226 Difference]: Without dead ends: 1121 [2025-03-16 19:04:50,014 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-16 19:04:50,014 INFO L435 NwaCegarLoop]: 252 mSDtfsCounter, 247 mSDsluCounter, 1196 mSDsCounter, 0 mSdLazyCounter, 70 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 248 SdHoareTripleChecker+Valid, 1448 SdHoareTripleChecker+Invalid, 85 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 70 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:50,014 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [248 Valid, 1448 Invalid, 85 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 70 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:50,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1121 states. [2025-03-16 19:04:50,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1121 to 1079. [2025-03-16 19:04:50,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1079 states, 825 states have (on average 1.3648484848484848) internal successors, (1126), 837 states have internal predecessors, (1126), 162 states have call successors, (162), 91 states have call predecessors, (162), 91 states have return successors, (162), 150 states have call predecessors, (162), 162 states have call successors, (162) [2025-03-16 19:04:50,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1079 states to 1079 states and 1450 transitions. [2025-03-16 19:04:50,075 INFO L78 Accepts]: Start accepts. Automaton has 1079 states and 1450 transitions. Word has length 86 [2025-03-16 19:04:50,075 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:50,075 INFO L471 AbstractCegarLoop]: Abstraction has 1079 states and 1450 transitions. [2025-03-16 19:04:50,076 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 8.857142857142858) internal successors, (62), 6 states have internal predecessors, (62), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) [2025-03-16 19:04:50,076 INFO L276 IsEmpty]: Start isEmpty. Operand 1079 states and 1450 transitions. [2025-03-16 19:04:50,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2025-03-16 19:04:50,077 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:50,077 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:50,077 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2025-03-16 19:04:50,077 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:50,077 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:50,079 INFO L85 PathProgramCache]: Analyzing trace with hash 1554635343, now seen corresponding path program 1 times [2025-03-16 19:04:50,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:50,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [260993222] [2025-03-16 19:04:50,079 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:50,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:50,089 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 88 statements into 1 equivalence classes. [2025-03-16 19:04:50,128 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 88 of 88 statements. [2025-03-16 19:04:50,128 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:50,129 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:50,455 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2025-03-16 19:04:50,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:50,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [260993222] [2025-03-16 19:04:50,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [260993222] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:50,455 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:50,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-16 19:04:50,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1564964569] [2025-03-16 19:04:50,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:50,455 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-16 19:04:50,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:50,456 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-16 19:04:50,456 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:04:50,456 INFO L87 Difference]: Start difference. First operand 1079 states and 1450 transitions. Second operand has 7 states, 7 states have (on average 8.714285714285714) internal successors, (61), 6 states have internal predecessors, (61), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-16 19:04:50,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:50,633 INFO L93 Difference]: Finished difference Result 1927 states and 2599 transitions. [2025-03-16 19:04:50,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-16 19:04:50,634 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 8.714285714285714) internal successors, (61), 6 states have internal predecessors, (61), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) Word has length 88 [2025-03-16 19:04:50,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:50,639 INFO L225 Difference]: With dead ends: 1927 [2025-03-16 19:04:50,639 INFO L226 Difference]: Without dead ends: 1077 [2025-03-16 19:04:50,641 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2025-03-16 19:04:50,641 INFO L435 NwaCegarLoop]: 278 mSDtfsCounter, 147 mSDsluCounter, 1272 mSDsCounter, 0 mSdLazyCounter, 77 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 149 SdHoareTripleChecker+Valid, 1550 SdHoareTripleChecker+Invalid, 77 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 77 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:50,641 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [149 Valid, 1550 Invalid, 77 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 77 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:50,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1077 states. [2025-03-16 19:04:50,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1077 to 973. [2025-03-16 19:04:50,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 973 states, 746 states have (on average 1.3672922252010724) internal successors, (1020), 756 states have internal predecessors, (1020), 145 states have call successors, (145), 81 states have call predecessors, (145), 81 states have return successors, (145), 135 states have call predecessors, (145), 145 states have call successors, (145) [2025-03-16 19:04:50,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973 states to 973 states and 1310 transitions. [2025-03-16 19:04:50,692 INFO L78 Accepts]: Start accepts. Automaton has 973 states and 1310 transitions. Word has length 88 [2025-03-16 19:04:50,692 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:50,692 INFO L471 AbstractCegarLoop]: Abstraction has 973 states and 1310 transitions. [2025-03-16 19:04:50,693 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 8.714285714285714) internal successors, (61), 6 states have internal predecessors, (61), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-16 19:04:50,693 INFO L276 IsEmpty]: Start isEmpty. Operand 973 states and 1310 transitions. [2025-03-16 19:04:50,693 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2025-03-16 19:04:50,693 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:50,694 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:50,694 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2025-03-16 19:04:50,694 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:50,694 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:50,694 INFO L85 PathProgramCache]: Analyzing trace with hash 476401327, now seen corresponding path program 1 times [2025-03-16 19:04:50,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:50,694 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552332713] [2025-03-16 19:04:50,694 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:50,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:50,703 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-16 19:04:50,740 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-16 19:04:50,740 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:50,740 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:51,053 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2025-03-16 19:04:51,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:51,054 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1552332713] [2025-03-16 19:04:51,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1552332713] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:51,054 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:51,054 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2025-03-16 19:04:51,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647477192] [2025-03-16 19:04:51,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:51,054 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2025-03-16 19:04:51,055 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:51,055 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-16 19:04:51,055 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2025-03-16 19:04:51,055 INFO L87 Difference]: Start difference. First operand 973 states and 1310 transitions. Second operand has 8 states, 8 states have (on average 8.25) internal successors, (66), 7 states have internal predecessors, (66), 4 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-16 19:04:51,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:51,465 INFO L93 Difference]: Finished difference Result 1875 states and 2519 transitions. [2025-03-16 19:04:51,465 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-16 19:04:51,466 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 8.25) internal successors, (66), 7 states have internal predecessors, (66), 4 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) Word has length 89 [2025-03-16 19:04:51,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:51,474 INFO L225 Difference]: With dead ends: 1875 [2025-03-16 19:04:51,474 INFO L226 Difference]: Without dead ends: 1061 [2025-03-16 19:04:51,476 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2025-03-16 19:04:51,476 INFO L435 NwaCegarLoop]: 307 mSDtfsCounter, 662 mSDsluCounter, 1098 mSDsCounter, 0 mSdLazyCounter, 183 mSolverCounterSat, 109 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 668 SdHoareTripleChecker+Valid, 1405 SdHoareTripleChecker+Invalid, 292 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 109 IncrementalHoareTripleChecker+Valid, 183 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:51,477 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [668 Valid, 1405 Invalid, 292 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [109 Valid, 183 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2025-03-16 19:04:51,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1061 states. [2025-03-16 19:04:51,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1061 to 1011. [2025-03-16 19:04:51,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1011 states, 769 states have (on average 1.3446033810143043) internal successors, (1034), 780 states have internal predecessors, (1034), 154 states have call successors, (154), 87 states have call predecessors, (154), 87 states have return successors, (154), 143 states have call predecessors, (154), 154 states have call successors, (154) [2025-03-16 19:04:51,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1011 states to 1011 states and 1342 transitions. [2025-03-16 19:04:51,548 INFO L78 Accepts]: Start accepts. Automaton has 1011 states and 1342 transitions. Word has length 89 [2025-03-16 19:04:51,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:51,548 INFO L471 AbstractCegarLoop]: Abstraction has 1011 states and 1342 transitions. [2025-03-16 19:04:51,548 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 8.25) internal successors, (66), 7 states have internal predecessors, (66), 4 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-16 19:04:51,548 INFO L276 IsEmpty]: Start isEmpty. Operand 1011 states and 1342 transitions. [2025-03-16 19:04:51,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2025-03-16 19:04:51,549 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:51,549 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:51,550 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2025-03-16 19:04:51,550 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:51,550 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:51,550 INFO L85 PathProgramCache]: Analyzing trace with hash -1101957363, now seen corresponding path program 1 times [2025-03-16 19:04:51,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:51,550 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [952167757] [2025-03-16 19:04:51,550 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:51,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:51,560 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 91 statements into 1 equivalence classes. [2025-03-16 19:04:51,587 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 91 of 91 statements. [2025-03-16 19:04:51,588 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:51,588 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:51,954 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2025-03-16 19:04:51,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:51,955 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [952167757] [2025-03-16 19:04:51,955 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [952167757] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:51,955 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:51,955 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2025-03-16 19:04:51,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380389922] [2025-03-16 19:04:51,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:51,956 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2025-03-16 19:04:51,956 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:51,957 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-16 19:04:51,957 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2025-03-16 19:04:51,957 INFO L87 Difference]: Start difference. First operand 1011 states and 1342 transitions. Second operand has 8 states, 8 states have (on average 8.5) internal successors, (68), 7 states have internal predecessors, (68), 4 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 5 states have call predecessors, (8), 4 states have call successors, (8) [2025-03-16 19:04:52,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:52,327 INFO L93 Difference]: Finished difference Result 1957 states and 2582 transitions. [2025-03-16 19:04:52,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-16 19:04:52,328 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 8.5) internal successors, (68), 7 states have internal predecessors, (68), 4 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 5 states have call predecessors, (8), 4 states have call successors, (8) Word has length 91 [2025-03-16 19:04:52,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:52,334 INFO L225 Difference]: With dead ends: 1957 [2025-03-16 19:04:52,334 INFO L226 Difference]: Without dead ends: 1118 [2025-03-16 19:04:52,336 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2025-03-16 19:04:52,337 INFO L435 NwaCegarLoop]: 269 mSDtfsCounter, 409 mSDsluCounter, 1124 mSDsCounter, 0 mSdLazyCounter, 249 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 415 SdHoareTripleChecker+Valid, 1393 SdHoareTripleChecker+Invalid, 250 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 249 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:52,337 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [415 Valid, 1393 Invalid, 250 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 249 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-03-16 19:04:52,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1118 states. [2025-03-16 19:04:52,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1118 to 1033. [2025-03-16 19:04:52,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1033 states, 783 states have (on average 1.3282247765006385) internal successors, (1040), 795 states have internal predecessors, (1040), 157 states have call successors, (157), 92 states have call predecessors, (157), 92 states have return successors, (157), 145 states have call predecessors, (157), 157 states have call successors, (157) [2025-03-16 19:04:52,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1033 states to 1033 states and 1354 transitions. [2025-03-16 19:04:52,431 INFO L78 Accepts]: Start accepts. Automaton has 1033 states and 1354 transitions. Word has length 91 [2025-03-16 19:04:52,431 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:52,431 INFO L471 AbstractCegarLoop]: Abstraction has 1033 states and 1354 transitions. [2025-03-16 19:04:52,431 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 8.5) internal successors, (68), 7 states have internal predecessors, (68), 4 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 5 states have call predecessors, (8), 4 states have call successors, (8) [2025-03-16 19:04:52,432 INFO L276 IsEmpty]: Start isEmpty. Operand 1033 states and 1354 transitions. [2025-03-16 19:04:52,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2025-03-16 19:04:52,433 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:52,433 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:52,433 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2025-03-16 19:04:52,433 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:52,433 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:52,433 INFO L85 PathProgramCache]: Analyzing trace with hash 1424391039, now seen corresponding path program 1 times [2025-03-16 19:04:52,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:52,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339040384] [2025-03-16 19:04:52,433 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:52,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:52,443 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-03-16 19:04:52,452 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-03-16 19:04:52,452 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:52,452 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:52,500 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-16 19:04:52,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:52,500 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339040384] [2025-03-16 19:04:52,500 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1339040384] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:52,500 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:52,500 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:52,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537198451] [2025-03-16 19:04:52,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:52,501 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:52,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:52,502 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:52,502 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:52,502 INFO L87 Difference]: Start difference. First operand 1033 states and 1354 transitions. Second operand has 4 states, 4 states have (on average 17.0) internal successors, (68), 4 states have internal predecessors, (68), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:52,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:52,677 INFO L93 Difference]: Finished difference Result 2702 states and 3565 transitions. [2025-03-16 19:04:52,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-16 19:04:52,677 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 17.0) internal successors, (68), 4 states have internal predecessors, (68), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 92 [2025-03-16 19:04:52,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:52,686 INFO L225 Difference]: With dead ends: 2702 [2025-03-16 19:04:52,686 INFO L226 Difference]: Without dead ends: 1919 [2025-03-16 19:04:52,688 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:52,689 INFO L435 NwaCegarLoop]: 455 mSDtfsCounter, 196 mSDsluCounter, 680 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 196 SdHoareTripleChecker+Valid, 1135 SdHoareTripleChecker+Invalid, 41 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:52,689 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [196 Valid, 1135 Invalid, 41 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 34 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:52,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1919 states. [2025-03-16 19:04:52,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1919 to 1746. [2025-03-16 19:04:52,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1746 states, 1308 states have (on average 1.3264525993883791) internal successors, (1735), 1328 states have internal predecessors, (1735), 280 states have call successors, (280), 157 states have call predecessors, (280), 157 states have return successors, (280), 260 states have call predecessors, (280), 280 states have call successors, (280) [2025-03-16 19:04:52,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1746 states to 1746 states and 2295 transitions. [2025-03-16 19:04:52,814 INFO L78 Accepts]: Start accepts. Automaton has 1746 states and 2295 transitions. Word has length 92 [2025-03-16 19:04:52,815 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:52,815 INFO L471 AbstractCegarLoop]: Abstraction has 1746 states and 2295 transitions. [2025-03-16 19:04:52,815 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 17.0) internal successors, (68), 4 states have internal predecessors, (68), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:52,815 INFO L276 IsEmpty]: Start isEmpty. Operand 1746 states and 2295 transitions. [2025-03-16 19:04:52,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2025-03-16 19:04:52,816 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:52,816 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:52,816 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2025-03-16 19:04:52,816 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:52,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:52,817 INFO L85 PathProgramCache]: Analyzing trace with hash 1529710524, now seen corresponding path program 1 times [2025-03-16 19:04:52,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:52,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093752284] [2025-03-16 19:04:52,817 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:52,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:52,828 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 94 statements into 1 equivalence classes. [2025-03-16 19:04:52,838 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 94 of 94 statements. [2025-03-16 19:04:52,839 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:52,839 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:52,891 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-16 19:04:52,891 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:52,891 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2093752284] [2025-03-16 19:04:52,891 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2093752284] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:52,891 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:52,891 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:52,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [167868561] [2025-03-16 19:04:52,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:52,892 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:52,892 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:52,892 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:52,893 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:52,893 INFO L87 Difference]: Start difference. First operand 1746 states and 2295 transitions. Second operand has 4 states, 4 states have (on average 17.5) internal successors, (70), 4 states have internal predecessors, (70), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:53,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:53,104 INFO L93 Difference]: Finished difference Result 4060 states and 5358 transitions. [2025-03-16 19:04:53,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-16 19:04:53,104 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 17.5) internal successors, (70), 4 states have internal predecessors, (70), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 94 [2025-03-16 19:04:53,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:53,117 INFO L225 Difference]: With dead ends: 4060 [2025-03-16 19:04:53,117 INFO L226 Difference]: Without dead ends: 2632 [2025-03-16 19:04:53,121 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:53,123 INFO L435 NwaCegarLoop]: 473 mSDtfsCounter, 197 mSDsluCounter, 696 mSDsCounter, 0 mSdLazyCounter, 40 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 197 SdHoareTripleChecker+Valid, 1169 SdHoareTripleChecker+Invalid, 45 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 40 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:53,125 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [197 Valid, 1169 Invalid, 45 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 40 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:53,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2632 states. [2025-03-16 19:04:53,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2632 to 2457. [2025-03-16 19:04:53,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2457 states, 1831 states have (on average 1.3238667394866193) internal successors, (2424), 1859 states have internal predecessors, (2424), 403 states have call successors, (403), 222 states have call predecessors, (403), 222 states have return successors, (403), 375 states have call predecessors, (403), 403 states have call successors, (403) [2025-03-16 19:04:53,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2457 states to 2457 states and 3230 transitions. [2025-03-16 19:04:53,330 INFO L78 Accepts]: Start accepts. Automaton has 2457 states and 3230 transitions. Word has length 94 [2025-03-16 19:04:53,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:53,330 INFO L471 AbstractCegarLoop]: Abstraction has 2457 states and 3230 transitions. [2025-03-16 19:04:53,330 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 17.5) internal successors, (70), 4 states have internal predecessors, (70), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:53,330 INFO L276 IsEmpty]: Start isEmpty. Operand 2457 states and 3230 transitions. [2025-03-16 19:04:53,332 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2025-03-16 19:04:53,333 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:53,333 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:53,333 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2025-03-16 19:04:53,333 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:53,333 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:53,333 INFO L85 PathProgramCache]: Analyzing trace with hash 1911139460, now seen corresponding path program 1 times [2025-03-16 19:04:53,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:53,334 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [346714689] [2025-03-16 19:04:53,334 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:53,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:53,344 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 94 statements into 1 equivalence classes. [2025-03-16 19:04:53,353 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 94 of 94 statements. [2025-03-16 19:04:53,354 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:53,354 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:53,406 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-16 19:04:53,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:53,406 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [346714689] [2025-03-16 19:04:53,407 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [346714689] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:53,407 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:53,407 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:53,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523776789] [2025-03-16 19:04:53,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:53,407 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:53,407 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:53,408 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:53,408 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:53,408 INFO L87 Difference]: Start difference. First operand 2457 states and 3230 transitions. Second operand has 4 states, 4 states have (on average 17.5) internal successors, (70), 4 states have internal predecessors, (70), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:53,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:53,683 INFO L93 Difference]: Finished difference Result 6302 states and 8321 transitions. [2025-03-16 19:04:53,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-16 19:04:53,684 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 17.5) internal successors, (70), 4 states have internal predecessors, (70), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 94 [2025-03-16 19:04:53,684 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:53,702 INFO L225 Difference]: With dead ends: 6302 [2025-03-16 19:04:53,703 INFO L226 Difference]: Without dead ends: 4266 [2025-03-16 19:04:53,709 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:53,709 INFO L435 NwaCegarLoop]: 463 mSDtfsCounter, 202 mSDsluCounter, 694 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 202 SdHoareTripleChecker+Valid, 1157 SdHoareTripleChecker+Invalid, 34 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:53,709 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [202 Valid, 1157 Invalid, 34 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:04:53,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4266 states. [2025-03-16 19:04:53,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4266 to 3957. [2025-03-16 19:04:53,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3957 states, 2920 states have (on average 1.3092465753424658) internal successors, (3823), 2964 states have internal predecessors, (3823), 672 states have call successors, (672), 364 states have call predecessors, (672), 364 states have return successors, (672), 628 states have call predecessors, (672), 672 states have call successors, (672) [2025-03-16 19:04:53,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3957 states to 3957 states and 5167 transitions. [2025-03-16 19:04:53,972 INFO L78 Accepts]: Start accepts. Automaton has 3957 states and 5167 transitions. Word has length 94 [2025-03-16 19:04:53,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:53,972 INFO L471 AbstractCegarLoop]: Abstraction has 3957 states and 5167 transitions. [2025-03-16 19:04:53,976 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 17.5) internal successors, (70), 4 states have internal predecessors, (70), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:53,976 INFO L276 IsEmpty]: Start isEmpty. Operand 3957 states and 5167 transitions. [2025-03-16 19:04:53,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2025-03-16 19:04:53,978 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:53,978 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:53,978 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2025-03-16 19:04:53,978 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:53,979 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:53,979 INFO L85 PathProgramCache]: Analyzing trace with hash 429798629, now seen corresponding path program 1 times [2025-03-16 19:04:53,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:53,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547087241] [2025-03-16 19:04:53,979 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:53,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:53,991 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 95 statements into 1 equivalence classes. [2025-03-16 19:04:53,995 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 95 of 95 statements. [2025-03-16 19:04:53,995 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:53,995 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:54,020 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-16 19:04:54,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:54,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [547087241] [2025-03-16 19:04:54,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [547087241] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:54,021 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:54,021 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-16 19:04:54,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1492310530] [2025-03-16 19:04:54,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:54,021 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-03-16 19:04:54,021 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:54,022 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-16 19:04:54,022 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-16 19:04:54,022 INFO L87 Difference]: Start difference. First operand 3957 states and 5167 transitions. Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:54,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:54,255 INFO L93 Difference]: Finished difference Result 7612 states and 9984 transitions. [2025-03-16 19:04:54,255 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-16 19:04:54,255 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 95 [2025-03-16 19:04:54,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:54,277 INFO L225 Difference]: With dead ends: 7612 [2025-03-16 19:04:54,277 INFO L226 Difference]: Without dead ends: 3990 [2025-03-16 19:04:54,286 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-16 19:04:54,287 INFO L435 NwaCegarLoop]: 255 mSDtfsCounter, 6 mSDsluCounter, 219 mSDsCounter, 0 mSdLazyCounter, 40 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 474 SdHoareTripleChecker+Invalid, 41 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 40 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:54,288 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 474 Invalid, 41 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 40 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:54,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3990 states. [2025-03-16 19:04:54,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3990 to 3963. [2025-03-16 19:04:54,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3963 states, 2926 states have (on average 1.3086124401913874) internal successors, (3829), 2970 states have internal predecessors, (3829), 672 states have call successors, (672), 364 states have call predecessors, (672), 364 states have return successors, (672), 628 states have call predecessors, (672), 672 states have call successors, (672) [2025-03-16 19:04:54,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3963 states to 3963 states and 5173 transitions. [2025-03-16 19:04:54,621 INFO L78 Accepts]: Start accepts. Automaton has 3963 states and 5173 transitions. Word has length 95 [2025-03-16 19:04:54,621 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:54,621 INFO L471 AbstractCegarLoop]: Abstraction has 3963 states and 5173 transitions. [2025-03-16 19:04:54,621 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:54,621 INFO L276 IsEmpty]: Start isEmpty. Operand 3963 states and 5173 transitions. [2025-03-16 19:04:54,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2025-03-16 19:04:54,624 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:54,624 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:54,624 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2025-03-16 19:04:54,624 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:54,625 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:54,625 INFO L85 PathProgramCache]: Analyzing trace with hash -1224402819, now seen corresponding path program 1 times [2025-03-16 19:04:54,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:54,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190606967] [2025-03-16 19:04:54,625 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:54,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:54,638 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 96 statements into 1 equivalence classes. [2025-03-16 19:04:54,650 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 96 of 96 statements. [2025-03-16 19:04:54,651 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:54,651 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:54,741 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-16 19:04:54,741 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:54,741 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190606967] [2025-03-16 19:04:54,741 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190606967] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:54,741 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:54,742 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:54,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97049262] [2025-03-16 19:04:54,742 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:54,742 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:54,742 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:54,743 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:54,743 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:54,743 INFO L87 Difference]: Start difference. First operand 3963 states and 5173 transitions. Second operand has 4 states, 4 states have (on average 18.0) internal successors, (72), 4 states have internal predecessors, (72), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:54,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:54,998 INFO L93 Difference]: Finished difference Result 7577 states and 9911 transitions. [2025-03-16 19:04:54,998 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:54,999 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 18.0) internal successors, (72), 4 states have internal predecessors, (72), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 96 [2025-03-16 19:04:54,999 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:55,027 INFO L225 Difference]: With dead ends: 7577 [2025-03-16 19:04:55,027 INFO L226 Difference]: Without dead ends: 3681 [2025-03-16 19:04:55,038 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:55,039 INFO L435 NwaCegarLoop]: 259 mSDtfsCounter, 79 mSDsluCounter, 467 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 79 SdHoareTripleChecker+Valid, 726 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:55,040 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [79 Valid, 726 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:55,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3681 states. [2025-03-16 19:04:55,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3681 to 3618. [2025-03-16 19:04:55,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3618 states, 2664 states have (on average 1.317942942942943) internal successors, (3511), 2698 states have internal predecessors, (3511), 620 states have call successors, (620), 333 states have call predecessors, (620), 333 states have return successors, (620), 586 states have call predecessors, (620), 620 states have call successors, (620) [2025-03-16 19:04:55,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3618 states to 3618 states and 4751 transitions. [2025-03-16 19:04:55,276 INFO L78 Accepts]: Start accepts. Automaton has 3618 states and 4751 transitions. Word has length 96 [2025-03-16 19:04:55,277 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:55,277 INFO L471 AbstractCegarLoop]: Abstraction has 3618 states and 4751 transitions. [2025-03-16 19:04:55,277 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 18.0) internal successors, (72), 4 states have internal predecessors, (72), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:55,277 INFO L276 IsEmpty]: Start isEmpty. Operand 3618 states and 4751 transitions. [2025-03-16 19:04:55,278 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2025-03-16 19:04:55,278 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:55,278 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:55,278 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24 [2025-03-16 19:04:55,279 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:55,279 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:55,279 INFO L85 PathProgramCache]: Analyzing trace with hash 1520531834, now seen corresponding path program 1 times [2025-03-16 19:04:55,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:55,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1089477556] [2025-03-16 19:04:55,279 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:55,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:55,288 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 97 statements into 1 equivalence classes. [2025-03-16 19:04:55,298 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 97 of 97 statements. [2025-03-16 19:04:55,299 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:55,299 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:55,372 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-16 19:04:55,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:55,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1089477556] [2025-03-16 19:04:55,373 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1089477556] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:04:55,373 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:04:55,373 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-16 19:04:55,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [633331] [2025-03-16 19:04:55,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:04:55,373 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-16 19:04:55,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:55,374 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-16 19:04:55,374 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-16 19:04:55,374 INFO L87 Difference]: Start difference. First operand 3618 states and 4751 transitions. Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 4 states have internal predecessors, (73), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:55,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:55,580 INFO L93 Difference]: Finished difference Result 7051 states and 9277 transitions. [2025-03-16 19:04:55,580 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-16 19:04:55,581 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 18.25) internal successors, (73), 4 states have internal predecessors, (73), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 97 [2025-03-16 19:04:55,581 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:55,596 INFO L225 Difference]: With dead ends: 7051 [2025-03-16 19:04:55,596 INFO L226 Difference]: Without dead ends: 3542 [2025-03-16 19:04:55,603 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-16 19:04:55,604 INFO L435 NwaCegarLoop]: 264 mSDtfsCounter, 61 mSDsluCounter, 472 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 61 SdHoareTripleChecker+Valid, 736 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:55,604 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [61 Valid, 736 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:04:55,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3542 states. [2025-03-16 19:04:55,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3542 to 2730. [2025-03-16 19:04:55,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2730 states, 2010 states have (on average 1.3119402985074626) internal successors, (2637), 2029 states have internal predecessors, (2637), 469 states have call successors, (469), 250 states have call predecessors, (469), 250 states have return successors, (469), 450 states have call predecessors, (469), 469 states have call successors, (469) [2025-03-16 19:04:55,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2730 states to 2730 states and 3575 transitions. [2025-03-16 19:04:55,764 INFO L78 Accepts]: Start accepts. Automaton has 2730 states and 3575 transitions. Word has length 97 [2025-03-16 19:04:55,764 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:55,764 INFO L471 AbstractCegarLoop]: Abstraction has 2730 states and 3575 transitions. [2025-03-16 19:04:55,764 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 18.25) internal successors, (73), 4 states have internal predecessors, (73), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-16 19:04:55,764 INFO L276 IsEmpty]: Start isEmpty. Operand 2730 states and 3575 transitions. [2025-03-16 19:04:55,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2025-03-16 19:04:55,768 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:55,768 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:55,769 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25 [2025-03-16 19:04:55,769 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:55,770 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:55,770 INFO L85 PathProgramCache]: Analyzing trace with hash 1736185426, now seen corresponding path program 1 times [2025-03-16 19:04:55,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:55,770 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797640460] [2025-03-16 19:04:55,771 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:55,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:55,784 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 140 statements into 1 equivalence classes. [2025-03-16 19:04:55,820 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 140 of 140 statements. [2025-03-16 19:04:55,821 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:55,821 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:56,287 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 7 proven. 15 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-16 19:04:56,287 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:56,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797640460] [2025-03-16 19:04:56,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1797640460] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:04:56,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1517103368] [2025-03-16 19:04:56,287 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:56,288 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:04:56,288 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:04:56,290 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:04:56,291 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2025-03-16 19:04:56,383 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 140 statements into 1 equivalence classes. [2025-03-16 19:04:56,452 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 140 of 140 statements. [2025-03-16 19:04:56,452 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:56,452 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:56,455 INFO L256 TraceCheckSpWp]: Trace formula consists of 648 conjuncts, 23 conjuncts are in the unsatisfiable core [2025-03-16 19:04:56,460 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:04:56,670 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 27 proven. 42 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-16 19:04:56,670 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:04:56,954 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 7 proven. 15 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-16 19:04:56,955 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1517103368] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-16 19:04:56,955 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-16 19:04:56,955 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 11, 8] total 23 [2025-03-16 19:04:56,955 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1895635216] [2025-03-16 19:04:56,955 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-16 19:04:56,956 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2025-03-16 19:04:56,956 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:04:56,957 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2025-03-16 19:04:56,957 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=424, Unknown=0, NotChecked=0, Total=506 [2025-03-16 19:04:56,957 INFO L87 Difference]: Start difference. First operand 2730 states and 3575 transitions. Second operand has 23 states, 23 states have (on average 8.826086956521738) internal successors, (203), 20 states have internal predecessors, (203), 9 states have call successors, (40), 4 states have call predecessors, (40), 8 states have return successors, (39), 12 states have call predecessors, (39), 9 states have call successors, (39) [2025-03-16 19:04:58,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:04:58,563 INFO L93 Difference]: Finished difference Result 9025 states and 11833 transitions. [2025-03-16 19:04:58,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2025-03-16 19:04:58,564 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 8.826086956521738) internal successors, (203), 20 states have internal predecessors, (203), 9 states have call successors, (40), 4 states have call predecessors, (40), 8 states have return successors, (39), 12 states have call predecessors, (39), 9 states have call successors, (39) Word has length 140 [2025-03-16 19:04:58,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:04:58,590 INFO L225 Difference]: With dead ends: 9025 [2025-03-16 19:04:58,590 INFO L226 Difference]: Without dead ends: 6557 [2025-03-16 19:04:58,599 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 310 GetRequests, 270 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 366 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=320, Invalid=1402, Unknown=0, NotChecked=0, Total=1722 [2025-03-16 19:04:58,599 INFO L435 NwaCegarLoop]: 362 mSDtfsCounter, 1224 mSDsluCounter, 3843 mSDsCounter, 0 mSdLazyCounter, 1013 mSolverCounterSat, 322 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1237 SdHoareTripleChecker+Valid, 4205 SdHoareTripleChecker+Invalid, 1335 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 322 IncrementalHoareTripleChecker+Valid, 1013 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2025-03-16 19:04:58,600 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1237 Valid, 4205 Invalid, 1335 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [322 Valid, 1013 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2025-03-16 19:04:58,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6557 states. [2025-03-16 19:04:59,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6557 to 5782. [2025-03-16 19:04:59,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5782 states, 4232 states have (on average 1.3107277882797732) internal successors, (5547), 4273 states have internal predecessors, (5547), 1008 states have call successors, (1008), 541 states have call predecessors, (1008), 541 states have return successors, (1008), 967 states have call predecessors, (1008), 1008 states have call successors, (1008) [2025-03-16 19:04:59,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5782 states to 5782 states and 7563 transitions. [2025-03-16 19:04:59,108 INFO L78 Accepts]: Start accepts. Automaton has 5782 states and 7563 transitions. Word has length 140 [2025-03-16 19:04:59,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:04:59,108 INFO L471 AbstractCegarLoop]: Abstraction has 5782 states and 7563 transitions. [2025-03-16 19:04:59,108 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 8.826086956521738) internal successors, (203), 20 states have internal predecessors, (203), 9 states have call successors, (40), 4 states have call predecessors, (40), 8 states have return successors, (39), 12 states have call predecessors, (39), 9 states have call successors, (39) [2025-03-16 19:04:59,109 INFO L276 IsEmpty]: Start isEmpty. Operand 5782 states and 7563 transitions. [2025-03-16 19:04:59,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2025-03-16 19:04:59,115 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:04:59,115 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:04:59,122 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2025-03-16 19:04:59,315 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable26 [2025-03-16 19:04:59,316 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:04:59,317 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:04:59,317 INFO L85 PathProgramCache]: Analyzing trace with hash 599235892, now seen corresponding path program 1 times [2025-03-16 19:04:59,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:04:59,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558254670] [2025-03-16 19:04:59,317 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:59,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:04:59,328 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 142 statements into 1 equivalence classes. [2025-03-16 19:04:59,355 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 142 of 142 statements. [2025-03-16 19:04:59,355 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:59,355 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:59,591 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 14 proven. 8 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-16 19:04:59,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:04:59,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558254670] [2025-03-16 19:04:59,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [558254670] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:04:59,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [244477570] [2025-03-16 19:04:59,592 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:04:59,592 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:04:59,592 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:04:59,594 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:04:59,596 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2025-03-16 19:04:59,679 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 142 statements into 1 equivalence classes. [2025-03-16 19:04:59,737 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 142 of 142 statements. [2025-03-16 19:04:59,737 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:04:59,737 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:04:59,740 INFO L256 TraceCheckSpWp]: Trace formula consists of 666 conjuncts, 32 conjuncts are in the unsatisfiable core [2025-03-16 19:04:59,748 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:00,001 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 37 proven. 37 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-16 19:05:00,002 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:05:00,073 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2025-03-16 19:05:00,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [244477570] provided 1 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:00,075 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2025-03-16 19:05:00,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7, 15] total 21 [2025-03-16 19:05:00,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [80653297] [2025-03-16 19:05:00,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:05:00,075 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-03-16 19:05:00,075 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:00,075 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-16 19:05:00,076 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=373, Unknown=0, NotChecked=0, Total=420 [2025-03-16 19:05:00,076 INFO L87 Difference]: Start difference. First operand 5782 states and 7563 transitions. Second operand has 5 states, 4 states have (on average 20.75) internal successors, (83), 5 states have internal predecessors, (83), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 2 states have call predecessors, (13), 3 states have call successors, (13) [2025-03-16 19:05:00,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:00,300 INFO L93 Difference]: Finished difference Result 10044 states and 13188 transitions. [2025-03-16 19:05:00,301 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-16 19:05:00,301 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 20.75) internal successors, (83), 5 states have internal predecessors, (83), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 2 states have call predecessors, (13), 3 states have call successors, (13) Word has length 142 [2025-03-16 19:05:00,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:00,322 INFO L225 Difference]: With dead ends: 10044 [2025-03-16 19:05:00,322 INFO L226 Difference]: Without dead ends: 4411 [2025-03-16 19:05:00,333 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 289 GetRequests, 270 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=373, Unknown=0, NotChecked=0, Total=420 [2025-03-16 19:05:00,335 INFO L435 NwaCegarLoop]: 251 mSDtfsCounter, 0 mSDsluCounter, 740 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 991 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:00,335 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 991 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-16 19:05:00,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4411 states. [2025-03-16 19:05:00,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4411 to 4372. [2025-03-16 19:05:00,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4372 states, 3216 states have (on average 1.3121890547263682) internal successors, (4220), 3244 states have internal predecessors, (4220), 751 states have call successors, (751), 404 states have call predecessors, (751), 404 states have return successors, (751), 723 states have call predecessors, (751), 751 states have call successors, (751) [2025-03-16 19:05:00,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4372 states to 4372 states and 5722 transitions. [2025-03-16 19:05:00,589 INFO L78 Accepts]: Start accepts. Automaton has 4372 states and 5722 transitions. Word has length 142 [2025-03-16 19:05:00,589 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:00,589 INFO L471 AbstractCegarLoop]: Abstraction has 4372 states and 5722 transitions. [2025-03-16 19:05:00,589 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 20.75) internal successors, (83), 5 states have internal predecessors, (83), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 2 states have call predecessors, (13), 3 states have call successors, (13) [2025-03-16 19:05:00,589 INFO L276 IsEmpty]: Start isEmpty. Operand 4372 states and 5722 transitions. [2025-03-16 19:05:00,595 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 144 [2025-03-16 19:05:00,596 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:00,596 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:00,603 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2025-03-16 19:05:00,800 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable27,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:00,800 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:00,801 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:00,801 INFO L85 PathProgramCache]: Analyzing trace with hash 621294121, now seen corresponding path program 1 times [2025-03-16 19:05:00,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:00,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425965095] [2025-03-16 19:05:00,801 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:00,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:00,812 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 143 statements into 1 equivalence classes. [2025-03-16 19:05:00,861 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 143 of 143 statements. [2025-03-16 19:05:00,861 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:00,861 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:01,042 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 13 proven. 8 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-16 19:05:01,042 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:01,042 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425965095] [2025-03-16 19:05:01,042 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425965095] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:01,043 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1232947688] [2025-03-16 19:05:01,043 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:01,043 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:01,043 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:05:01,045 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:05:01,046 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2025-03-16 19:05:01,128 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 143 statements into 1 equivalence classes. [2025-03-16 19:05:01,188 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 143 of 143 statements. [2025-03-16 19:05:01,188 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:01,188 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:01,192 INFO L256 TraceCheckSpWp]: Trace formula consists of 683 conjuncts, 63 conjuncts are in the unsatisfiable core [2025-03-16 19:05:01,197 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:01,767 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 58 proven. 10 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-16 19:05:01,767 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:05:02,510 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 4 proven. 17 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-16 19:05:02,510 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1232947688] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-16 19:05:02,510 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-16 19:05:02,510 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 17] total 32 [2025-03-16 19:05:02,510 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707381328] [2025-03-16 19:05:02,511 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-16 19:05:02,511 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2025-03-16 19:05:02,511 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:02,511 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2025-03-16 19:05:02,512 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=163, Invalid=829, Unknown=0, NotChecked=0, Total=992 [2025-03-16 19:05:02,512 INFO L87 Difference]: Start difference. First operand 4372 states and 5722 transitions. Second operand has 32 states, 32 states have (on average 7.09375) internal successors, (227), 31 states have internal predecessors, (227), 11 states have call successors, (42), 5 states have call predecessors, (42), 7 states have return successors, (41), 12 states have call predecessors, (41), 11 states have call successors, (41) [2025-03-16 19:05:06,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:06,243 INFO L93 Difference]: Finished difference Result 10797 states and 14174 transitions. [2025-03-16 19:05:06,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2025-03-16 19:05:06,243 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 32 states have (on average 7.09375) internal successors, (227), 31 states have internal predecessors, (227), 11 states have call successors, (42), 5 states have call predecessors, (42), 7 states have return successors, (41), 12 states have call predecessors, (41), 11 states have call successors, (41) Word has length 143 [2025-03-16 19:05:06,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:06,270 INFO L225 Difference]: With dead ends: 10797 [2025-03-16 19:05:06,271 INFO L226 Difference]: Without dead ends: 6666 [2025-03-16 19:05:06,282 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 354 GetRequests, 274 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2002 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1314, Invalid=5328, Unknown=0, NotChecked=0, Total=6642 [2025-03-16 19:05:06,285 INFO L435 NwaCegarLoop]: 607 mSDtfsCounter, 1986 mSDsluCounter, 8044 mSDsCounter, 0 mSdLazyCounter, 3889 mSolverCounterSat, 664 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1986 SdHoareTripleChecker+Valid, 8651 SdHoareTripleChecker+Invalid, 4553 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 664 IncrementalHoareTripleChecker+Valid, 3889 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.3s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:06,285 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1986 Valid, 8651 Invalid, 4553 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [664 Valid, 3889 Invalid, 0 Unknown, 0 Unchecked, 2.3s Time] [2025-03-16 19:05:06,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6666 states. [2025-03-16 19:05:06,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6666 to 5434. [2025-03-16 19:05:06,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5434 states, 4005 states have (on average 1.3061173533083645) internal successors, (5231), 4039 states have internal predecessors, (5231), 921 states have call successors, (921), 507 states have call predecessors, (921), 507 states have return successors, (921), 887 states have call predecessors, (921), 921 states have call successors, (921) [2025-03-16 19:05:06,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5434 states to 5434 states and 7073 transitions. [2025-03-16 19:05:06,680 INFO L78 Accepts]: Start accepts. Automaton has 5434 states and 7073 transitions. Word has length 143 [2025-03-16 19:05:06,680 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:06,681 INFO L471 AbstractCegarLoop]: Abstraction has 5434 states and 7073 transitions. [2025-03-16 19:05:06,681 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 32 states have (on average 7.09375) internal successors, (227), 31 states have internal predecessors, (227), 11 states have call successors, (42), 5 states have call predecessors, (42), 7 states have return successors, (41), 12 states have call predecessors, (41), 11 states have call successors, (41) [2025-03-16 19:05:06,681 INFO L276 IsEmpty]: Start isEmpty. Operand 5434 states and 7073 transitions. [2025-03-16 19:05:06,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2025-03-16 19:05:06,689 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:06,689 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:06,696 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2025-03-16 19:05:06,889 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable28 [2025-03-16 19:05:06,890 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:06,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:06,890 INFO L85 PathProgramCache]: Analyzing trace with hash 231007453, now seen corresponding path program 1 times [2025-03-16 19:05:06,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:06,891 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286157738] [2025-03-16 19:05:06,891 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:06,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:06,901 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 145 statements into 1 equivalence classes. [2025-03-16 19:05:06,912 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 145 of 145 statements. [2025-03-16 19:05:06,912 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:06,912 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:06,997 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2025-03-16 19:05:06,997 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:06,997 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286157738] [2025-03-16 19:05:06,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [286157738] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:05:06,997 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:05:06,997 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-16 19:05:06,997 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1106961383] [2025-03-16 19:05:06,997 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:05:06,998 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-16 19:05:06,998 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:06,998 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-16 19:05:06,999 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:05:06,999 INFO L87 Difference]: Start difference. First operand 5434 states and 7073 transitions. Second operand has 7 states, 7 states have (on average 11.857142857142858) internal successors, (83), 6 states have internal predecessors, (83), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 3 states have call predecessors, (13), 2 states have call successors, (13) [2025-03-16 19:05:07,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:07,750 INFO L93 Difference]: Finished difference Result 15554 states and 20309 transitions. [2025-03-16 19:05:07,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-16 19:05:07,752 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 11.857142857142858) internal successors, (83), 6 states have internal predecessors, (83), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 3 states have call predecessors, (13), 2 states have call successors, (13) Word has length 145 [2025-03-16 19:05:07,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:07,796 INFO L225 Difference]: With dead ends: 15554 [2025-03-16 19:05:07,796 INFO L226 Difference]: Without dead ends: 10717 [2025-03-16 19:05:07,810 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-16 19:05:07,811 INFO L435 NwaCegarLoop]: 472 mSDtfsCounter, 219 mSDsluCounter, 2035 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 224 SdHoareTripleChecker+Valid, 2507 SdHoareTripleChecker+Invalid, 127 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:07,811 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [224 Valid, 2507 Invalid, 127 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:05:07,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10717 states. [2025-03-16 19:05:08,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10717 to 8060. [2025-03-16 19:05:08,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8060 states, 5889 states have (on average 1.3017490236033282) internal successors, (7666), 5942 states have internal predecessors, (7666), 1416 states have call successors, (1416), 754 states have call predecessors, (1416), 754 states have return successors, (1416), 1363 states have call predecessors, (1416), 1416 states have call successors, (1416) [2025-03-16 19:05:08,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8060 states to 8060 states and 10498 transitions. [2025-03-16 19:05:08,406 INFO L78 Accepts]: Start accepts. Automaton has 8060 states and 10498 transitions. Word has length 145 [2025-03-16 19:05:08,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:08,406 INFO L471 AbstractCegarLoop]: Abstraction has 8060 states and 10498 transitions. [2025-03-16 19:05:08,406 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 11.857142857142858) internal successors, (83), 6 states have internal predecessors, (83), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 3 states have call predecessors, (13), 2 states have call successors, (13) [2025-03-16 19:05:08,406 INFO L276 IsEmpty]: Start isEmpty. Operand 8060 states and 10498 transitions. [2025-03-16 19:05:08,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2025-03-16 19:05:08,417 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:08,417 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:08,417 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29 [2025-03-16 19:05:08,417 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:08,418 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:08,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1167759524, now seen corresponding path program 1 times [2025-03-16 19:05:08,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:08,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [231200557] [2025-03-16 19:05:08,418 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:08,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:08,428 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 145 statements into 1 equivalence classes. [2025-03-16 19:05:08,460 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 145 of 145 statements. [2025-03-16 19:05:08,461 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:08,461 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:09,067 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 21 proven. 4 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2025-03-16 19:05:09,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:09,067 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [231200557] [2025-03-16 19:05:09,068 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [231200557] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:09,068 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2123354247] [2025-03-16 19:05:09,068 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:09,068 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:09,068 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:05:09,070 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:05:09,072 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2025-03-16 19:05:09,164 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 145 statements into 1 equivalence classes. [2025-03-16 19:05:09,232 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 145 of 145 statements. [2025-03-16 19:05:09,232 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:09,232 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:09,236 INFO L256 TraceCheckSpWp]: Trace formula consists of 700 conjuncts, 27 conjuncts are in the unsatisfiable core [2025-03-16 19:05:09,239 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:09,520 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 17 proven. 53 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-16 19:05:09,520 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:05:09,744 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 9 proven. 18 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2025-03-16 19:05:09,745 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2123354247] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-16 19:05:09,745 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-16 19:05:09,745 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 11, 9] total 23 [2025-03-16 19:05:09,745 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [668044337] [2025-03-16 19:05:09,745 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-16 19:05:09,745 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2025-03-16 19:05:09,745 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:09,746 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2025-03-16 19:05:09,746 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=440, Unknown=0, NotChecked=0, Total=506 [2025-03-16 19:05:09,746 INFO L87 Difference]: Start difference. First operand 8060 states and 10498 transitions. Second operand has 23 states, 23 states have (on average 10.434782608695652) internal successors, (240), 19 states have internal predecessors, (240), 7 states have call successors, (40), 5 states have call predecessors, (40), 9 states have return successors, (39), 11 states have call predecessors, (39), 7 states have call successors, (39) [2025-03-16 19:05:12,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:12,168 INFO L93 Difference]: Finished difference Result 19271 states and 25074 transitions. [2025-03-16 19:05:12,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2025-03-16 19:05:12,168 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 10.434782608695652) internal successors, (240), 19 states have internal predecessors, (240), 7 states have call successors, (40), 5 states have call predecessors, (40), 9 states have return successors, (39), 11 states have call predecessors, (39), 7 states have call successors, (39) Word has length 145 [2025-03-16 19:05:12,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:12,208 INFO L225 Difference]: With dead ends: 19271 [2025-03-16 19:05:12,208 INFO L226 Difference]: Without dead ends: 11434 [2025-03-16 19:05:12,224 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 352 GetRequests, 292 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 864 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=658, Invalid=3124, Unknown=0, NotChecked=0, Total=3782 [2025-03-16 19:05:12,225 INFO L435 NwaCegarLoop]: 527 mSDtfsCounter, 1467 mSDsluCounter, 5581 mSDsCounter, 0 mSdLazyCounter, 2647 mSolverCounterSat, 542 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1467 SdHoareTripleChecker+Valid, 6108 SdHoareTripleChecker+Invalid, 3189 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 542 IncrementalHoareTripleChecker+Valid, 2647 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:12,225 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1467 Valid, 6108 Invalid, 3189 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [542 Valid, 2647 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2025-03-16 19:05:12,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11434 states. [2025-03-16 19:05:12,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11434 to 5592. [2025-03-16 19:05:12,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5592 states, 4100 states have (on average 1.2992682926829269) internal successors, (5327), 4138 states have internal predecessors, (5327), 970 states have call successors, (970), 521 states have call predecessors, (970), 521 states have return successors, (970), 932 states have call predecessors, (970), 970 states have call successors, (970) [2025-03-16 19:05:12,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5592 states to 5592 states and 7267 transitions. [2025-03-16 19:05:12,720 INFO L78 Accepts]: Start accepts. Automaton has 5592 states and 7267 transitions. Word has length 145 [2025-03-16 19:05:12,720 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:12,720 INFO L471 AbstractCegarLoop]: Abstraction has 5592 states and 7267 transitions. [2025-03-16 19:05:12,720 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 10.434782608695652) internal successors, (240), 19 states have internal predecessors, (240), 7 states have call successors, (40), 5 states have call predecessors, (40), 9 states have return successors, (39), 11 states have call predecessors, (39), 7 states have call successors, (39) [2025-03-16 19:05:12,720 INFO L276 IsEmpty]: Start isEmpty. Operand 5592 states and 7267 transitions. [2025-03-16 19:05:12,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2025-03-16 19:05:12,724 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:12,725 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:12,732 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2025-03-16 19:05:12,929 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:12,929 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:12,929 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:12,929 INFO L85 PathProgramCache]: Analyzing trace with hash -1938377624, now seen corresponding path program 1 times [2025-03-16 19:05:12,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:12,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696669476] [2025-03-16 19:05:12,929 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:12,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:12,941 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 155 statements into 1 equivalence classes. [2025-03-16 19:05:12,957 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 155 of 155 statements. [2025-03-16 19:05:12,958 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:12,958 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:13,135 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 14 proven. 12 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2025-03-16 19:05:13,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:13,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [696669476] [2025-03-16 19:05:13,136 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [696669476] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:13,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [662089783] [2025-03-16 19:05:13,137 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:13,137 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:13,137 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:05:13,139 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:05:13,140 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2025-03-16 19:05:13,226 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 155 statements into 1 equivalence classes. [2025-03-16 19:05:13,283 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 155 of 155 statements. [2025-03-16 19:05:13,283 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:13,283 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:13,289 INFO L256 TraceCheckSpWp]: Trace formula consists of 707 conjuncts, 35 conjuncts are in the unsatisfiable core [2025-03-16 19:05:13,292 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:13,605 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 58 proven. 20 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-16 19:05:13,606 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:05:13,945 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 14 proven. 12 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2025-03-16 19:05:13,946 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [662089783] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-16 19:05:13,946 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-16 19:05:13,946 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 10] total 25 [2025-03-16 19:05:13,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [433343691] [2025-03-16 19:05:13,946 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-16 19:05:13,946 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 25 states [2025-03-16 19:05:13,948 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:13,948 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2025-03-16 19:05:13,948 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=506, Unknown=0, NotChecked=0, Total=600 [2025-03-16 19:05:13,949 INFO L87 Difference]: Start difference. First operand 5592 states and 7267 transitions. Second operand has 25 states, 25 states have (on average 9.6) internal successors, (240), 25 states have internal predecessors, (240), 9 states have call successors, (41), 5 states have call predecessors, (41), 6 states have return successors, (40), 9 states have call predecessors, (40), 9 states have call successors, (40) [2025-03-16 19:05:18,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:18,199 INFO L93 Difference]: Finished difference Result 15227 states and 19904 transitions. [2025-03-16 19:05:18,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2025-03-16 19:05:18,200 INFO L78 Accepts]: Start accepts. Automaton has has 25 states, 25 states have (on average 9.6) internal successors, (240), 25 states have internal predecessors, (240), 9 states have call successors, (41), 5 states have call predecessors, (41), 6 states have return successors, (40), 9 states have call predecessors, (40), 9 states have call successors, (40) Word has length 155 [2025-03-16 19:05:18,200 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:18,230 INFO L225 Difference]: With dead ends: 15227 [2025-03-16 19:05:18,230 INFO L226 Difference]: Without dead ends: 9888 [2025-03-16 19:05:18,242 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 438 GetRequests, 317 SyntacticMatches, 0 SemanticMatches, 121 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5331 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=2033, Invalid=12973, Unknown=0, NotChecked=0, Total=15006 [2025-03-16 19:05:18,243 INFO L435 NwaCegarLoop]: 298 mSDtfsCounter, 2421 mSDsluCounter, 3527 mSDsCounter, 0 mSdLazyCounter, 2573 mSolverCounterSat, 789 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2421 SdHoareTripleChecker+Valid, 3825 SdHoareTripleChecker+Invalid, 3362 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 789 IncrementalHoareTripleChecker+Valid, 2573 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:18,243 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2421 Valid, 3825 Invalid, 3362 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [789 Valid, 2573 Invalid, 0 Unknown, 0 Unchecked, 1.5s Time] [2025-03-16 19:05:18,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9888 states. [2025-03-16 19:05:19,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9888 to 8867. [2025-03-16 19:05:19,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8867 states, 6551 states have (on average 1.2993436116623416) internal successors, (8512), 6608 states have internal predecessors, (8512), 1494 states have call successors, (1494), 821 states have call predecessors, (1494), 821 states have return successors, (1494), 1437 states have call predecessors, (1494), 1494 states have call successors, (1494) [2025-03-16 19:05:19,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8867 states to 8867 states and 11500 transitions. [2025-03-16 19:05:19,228 INFO L78 Accepts]: Start accepts. Automaton has 8867 states and 11500 transitions. Word has length 155 [2025-03-16 19:05:19,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:19,228 INFO L471 AbstractCegarLoop]: Abstraction has 8867 states and 11500 transitions. [2025-03-16 19:05:19,229 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 25 states, 25 states have (on average 9.6) internal successors, (240), 25 states have internal predecessors, (240), 9 states have call successors, (41), 5 states have call predecessors, (41), 6 states have return successors, (40), 9 states have call predecessors, (40), 9 states have call successors, (40) [2025-03-16 19:05:19,229 INFO L276 IsEmpty]: Start isEmpty. Operand 8867 states and 11500 transitions. [2025-03-16 19:05:19,234 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2025-03-16 19:05:19,235 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:19,235 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:19,242 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2025-03-16 19:05:19,435 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:19,436 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:19,436 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:19,437 INFO L85 PathProgramCache]: Analyzing trace with hash 1259474572, now seen corresponding path program 1 times [2025-03-16 19:05:19,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:19,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1763887525] [2025-03-16 19:05:19,437 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:19,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:19,452 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 155 statements into 1 equivalence classes. [2025-03-16 19:05:19,487 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 155 of 155 statements. [2025-03-16 19:05:19,488 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:19,488 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:20,170 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 22 proven. 5 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2025-03-16 19:05:20,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:20,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1763887525] [2025-03-16 19:05:20,173 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1763887525] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:20,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [102591861] [2025-03-16 19:05:20,173 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:20,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:20,173 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:05:20,175 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:05:20,176 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2025-03-16 19:05:20,266 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 155 statements into 1 equivalence classes. [2025-03-16 19:05:20,328 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 155 of 155 statements. [2025-03-16 19:05:20,328 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:20,328 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:20,330 INFO L256 TraceCheckSpWp]: Trace formula consists of 705 conjuncts, 11 conjuncts are in the unsatisfiable core [2025-03-16 19:05:20,333 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:20,399 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 45 proven. 4 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2025-03-16 19:05:20,399 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:05:20,469 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 22 proven. 2 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2025-03-16 19:05:20,470 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [102591861] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-16 19:05:20,470 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-16 19:05:20,470 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 7, 7] total 15 [2025-03-16 19:05:20,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1086224807] [2025-03-16 19:05:20,470 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-16 19:05:20,470 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2025-03-16 19:05:20,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:20,471 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2025-03-16 19:05:20,471 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=180, Unknown=0, NotChecked=0, Total=210 [2025-03-16 19:05:20,471 INFO L87 Difference]: Start difference. First operand 8867 states and 11500 transitions. Second operand has 15 states, 15 states have (on average 11.866666666666667) internal successors, (178), 14 states have internal predecessors, (178), 6 states have call successors, (37), 4 states have call predecessors, (37), 6 states have return successors, (37), 7 states have call predecessors, (37), 6 states have call successors, (37) [2025-03-16 19:05:22,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:22,116 INFO L93 Difference]: Finished difference Result 18112 states and 23477 transitions. [2025-03-16 19:05:22,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2025-03-16 19:05:22,117 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 11.866666666666667) internal successors, (178), 14 states have internal predecessors, (178), 6 states have call successors, (37), 4 states have call predecessors, (37), 6 states have return successors, (37), 7 states have call predecessors, (37), 6 states have call successors, (37) Word has length 155 [2025-03-16 19:05:22,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:22,149 INFO L225 Difference]: With dead ends: 18112 [2025-03-16 19:05:22,149 INFO L226 Difference]: Without dead ends: 9413 [2025-03-16 19:05:22,161 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 354 GetRequests, 316 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 318 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=249, Invalid=1311, Unknown=0, NotChecked=0, Total=1560 [2025-03-16 19:05:22,162 INFO L435 NwaCegarLoop]: 339 mSDtfsCounter, 1088 mSDsluCounter, 2739 mSDsCounter, 0 mSdLazyCounter, 809 mSolverCounterSat, 398 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1088 SdHoareTripleChecker+Valid, 3078 SdHoareTripleChecker+Invalid, 1207 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 398 IncrementalHoareTripleChecker+Valid, 809 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:22,162 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1088 Valid, 3078 Invalid, 1207 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [398 Valid, 809 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2025-03-16 19:05:22,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9413 states. [2025-03-16 19:05:23,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9413 to 9241. [2025-03-16 19:05:23,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9241 states, 6832 states have (on average 1.2985948477751756) internal successors, (8872), 6892 states have internal predecessors, (8872), 1551 states have call successors, (1551), 857 states have call predecessors, (1551), 857 states have return successors, (1551), 1491 states have call predecessors, (1551), 1551 states have call successors, (1551) [2025-03-16 19:05:23,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9241 states to 9241 states and 11974 transitions. [2025-03-16 19:05:23,536 INFO L78 Accepts]: Start accepts. Automaton has 9241 states and 11974 transitions. Word has length 155 [2025-03-16 19:05:23,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:23,537 INFO L471 AbstractCegarLoop]: Abstraction has 9241 states and 11974 transitions. [2025-03-16 19:05:23,537 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 11.866666666666667) internal successors, (178), 14 states have internal predecessors, (178), 6 states have call successors, (37), 4 states have call predecessors, (37), 6 states have return successors, (37), 7 states have call predecessors, (37), 6 states have call successors, (37) [2025-03-16 19:05:23,537 INFO L276 IsEmpty]: Start isEmpty. Operand 9241 states and 11974 transitions. [2025-03-16 19:05:23,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2025-03-16 19:05:23,543 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:23,543 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:23,551 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2025-03-16 19:05:23,743 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable32,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:23,744 INFO L396 AbstractCegarLoop]: === Iteration 34 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:23,747 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:23,747 INFO L85 PathProgramCache]: Analyzing trace with hash -486890776, now seen corresponding path program 1 times [2025-03-16 19:05:23,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:23,748 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [496407277] [2025-03-16 19:05:23,748 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:23,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:23,759 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 164 statements into 1 equivalence classes. [2025-03-16 19:05:23,801 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 164 of 164 statements. [2025-03-16 19:05:23,802 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:23,802 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:24,243 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 22 proven. 8 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2025-03-16 19:05:24,243 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:24,244 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [496407277] [2025-03-16 19:05:24,244 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [496407277] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:24,244 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2076575352] [2025-03-16 19:05:24,244 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:24,244 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:24,244 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:05:24,246 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:05:24,283 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2025-03-16 19:05:24,374 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 164 statements into 1 equivalence classes. [2025-03-16 19:05:24,427 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 164 of 164 statements. [2025-03-16 19:05:24,427 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:24,427 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:24,431 INFO L256 TraceCheckSpWp]: Trace formula consists of 724 conjuncts, 29 conjuncts are in the unsatisfiable core [2025-03-16 19:05:24,434 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:24,792 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 62 proven. 23 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2025-03-16 19:05:24,793 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:05:25,001 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 13 proven. 11 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2025-03-16 19:05:25,001 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2076575352] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-16 19:05:25,001 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-16 19:05:25,001 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 21 [2025-03-16 19:05:25,001 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779150299] [2025-03-16 19:05:25,001 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-16 19:05:25,002 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 21 states [2025-03-16 19:05:25,002 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:25,002 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2025-03-16 19:05:25,002 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=351, Unknown=0, NotChecked=0, Total=420 [2025-03-16 19:05:25,003 INFO L87 Difference]: Start difference. First operand 9241 states and 11974 transitions. Second operand has 21 states, 20 states have (on average 12.6) internal successors, (252), 19 states have internal predecessors, (252), 10 states have call successors, (43), 6 states have call predecessors, (43), 7 states have return successors, (42), 11 states have call predecessors, (42), 10 states have call successors, (42) [2025-03-16 19:05:27,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:27,886 INFO L93 Difference]: Finished difference Result 22118 states and 28626 transitions. [2025-03-16 19:05:27,886 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2025-03-16 19:05:27,886 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 20 states have (on average 12.6) internal successors, (252), 19 states have internal predecessors, (252), 10 states have call successors, (43), 6 states have call predecessors, (43), 7 states have return successors, (42), 11 states have call predecessors, (42), 10 states have call successors, (42) Word has length 164 [2025-03-16 19:05:27,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:27,926 INFO L225 Difference]: With dead ends: 22118 [2025-03-16 19:05:27,926 INFO L226 Difference]: Without dead ends: 12878 [2025-03-16 19:05:27,941 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 383 GetRequests, 330 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 714 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=655, Invalid=2315, Unknown=0, NotChecked=0, Total=2970 [2025-03-16 19:05:27,942 INFO L435 NwaCegarLoop]: 546 mSDtfsCounter, 1174 mSDsluCounter, 3915 mSDsCounter, 0 mSdLazyCounter, 1979 mSolverCounterSat, 385 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1174 SdHoareTripleChecker+Valid, 4461 SdHoareTripleChecker+Invalid, 2364 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 385 IncrementalHoareTripleChecker+Valid, 1979 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:27,942 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1174 Valid, 4461 Invalid, 2364 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [385 Valid, 1979 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2025-03-16 19:05:27,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12878 states. [2025-03-16 19:05:29,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12878 to 11657. [2025-03-16 19:05:29,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11657 states, 8567 states have (on average 1.2888992646200537) internal successors, (11042), 8648 states have internal predecessors, (11042), 1996 states have call successors, (1996), 1093 states have call predecessors, (1996), 1093 states have return successors, (1996), 1915 states have call predecessors, (1996), 1996 states have call successors, (1996) [2025-03-16 19:05:29,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11657 states to 11657 states and 15034 transitions. [2025-03-16 19:05:29,863 INFO L78 Accepts]: Start accepts. Automaton has 11657 states and 15034 transitions. Word has length 164 [2025-03-16 19:05:29,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:29,863 INFO L471 AbstractCegarLoop]: Abstraction has 11657 states and 15034 transitions. [2025-03-16 19:05:29,863 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 21 states, 20 states have (on average 12.6) internal successors, (252), 19 states have internal predecessors, (252), 10 states have call successors, (43), 6 states have call predecessors, (43), 7 states have return successors, (42), 11 states have call predecessors, (42), 10 states have call successors, (42) [2025-03-16 19:05:29,863 INFO L276 IsEmpty]: Start isEmpty. Operand 11657 states and 15034 transitions. [2025-03-16 19:05:29,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2025-03-16 19:05:29,868 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:29,868 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:29,874 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2025-03-16 19:05:30,068 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable33 [2025-03-16 19:05:30,068 INFO L396 AbstractCegarLoop]: === Iteration 35 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:30,069 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:30,069 INFO L85 PathProgramCache]: Analyzing trace with hash 1966519046, now seen corresponding path program 1 times [2025-03-16 19:05:30,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:30,069 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209598944] [2025-03-16 19:05:30,069 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:30,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:30,079 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 173 statements into 1 equivalence classes. [2025-03-16 19:05:30,088 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 173 of 173 statements. [2025-03-16 19:05:30,088 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:30,088 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:30,170 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 120 trivial. 0 not checked. [2025-03-16 19:05:30,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:30,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209598944] [2025-03-16 19:05:30,170 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209598944] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:05:30,170 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:05:30,170 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-16 19:05:30,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694127761] [2025-03-16 19:05:30,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:05:30,171 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-16 19:05:30,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:30,171 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-16 19:05:30,171 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:05:30,171 INFO L87 Difference]: Start difference. First operand 11657 states and 15034 transitions. Second operand has 7 states, 7 states have (on average 12.857142857142858) internal successors, (90), 6 states have internal predecessors, (90), 3 states have call successors, (18), 2 states have call predecessors, (18), 2 states have return successors, (17), 3 states have call predecessors, (17), 2 states have call successors, (17) [2025-03-16 19:05:31,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:31,945 INFO L93 Difference]: Finished difference Result 25624 states and 33050 transitions. [2025-03-16 19:05:31,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-16 19:05:31,946 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 12.857142857142858) internal successors, (90), 6 states have internal predecessors, (90), 3 states have call successors, (18), 2 states have call predecessors, (18), 2 states have return successors, (17), 3 states have call predecessors, (17), 2 states have call successors, (17) Word has length 173 [2025-03-16 19:05:31,946 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:31,990 INFO L225 Difference]: With dead ends: 25624 [2025-03-16 19:05:31,990 INFO L226 Difference]: Without dead ends: 14691 [2025-03-16 19:05:32,007 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-16 19:05:32,007 INFO L435 NwaCegarLoop]: 462 mSDtfsCounter, 198 mSDsluCounter, 1996 mSDsCounter, 0 mSdLazyCounter, 123 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 202 SdHoareTripleChecker+Valid, 2458 SdHoareTripleChecker+Invalid, 124 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 123 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:32,008 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [202 Valid, 2458 Invalid, 124 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 123 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-16 19:05:32,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14691 states. [2025-03-16 19:05:34,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14691 to 13443. [2025-03-16 19:05:34,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13443 states, 9855 states have (on average 1.2843226788432267) internal successors, (12657), 9952 states have internal predecessors, (12657), 2318 states have call successors, (2318), 1269 states have call predecessors, (2318), 1269 states have return successors, (2318), 2221 states have call predecessors, (2318), 2318 states have call successors, (2318) [2025-03-16 19:05:34,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13443 states to 13443 states and 17293 transitions. [2025-03-16 19:05:34,221 INFO L78 Accepts]: Start accepts. Automaton has 13443 states and 17293 transitions. Word has length 173 [2025-03-16 19:05:34,222 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:34,222 INFO L471 AbstractCegarLoop]: Abstraction has 13443 states and 17293 transitions. [2025-03-16 19:05:34,222 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 12.857142857142858) internal successors, (90), 6 states have internal predecessors, (90), 3 states have call successors, (18), 2 states have call predecessors, (18), 2 states have return successors, (17), 3 states have call predecessors, (17), 2 states have call successors, (17) [2025-03-16 19:05:34,222 INFO L276 IsEmpty]: Start isEmpty. Operand 13443 states and 17293 transitions. [2025-03-16 19:05:34,227 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2025-03-16 19:05:34,227 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:34,227 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:34,227 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable34 [2025-03-16 19:05:34,227 INFO L396 AbstractCegarLoop]: === Iteration 36 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:34,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:34,228 INFO L85 PathProgramCache]: Analyzing trace with hash 908645815, now seen corresponding path program 1 times [2025-03-16 19:05:34,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:34,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41978670] [2025-03-16 19:05:34,228 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:34,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:34,243 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 174 statements into 1 equivalence classes. [2025-03-16 19:05:34,263 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 174 of 174 statements. [2025-03-16 19:05:34,263 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:34,263 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:34,722 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 35 proven. 13 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2025-03-16 19:05:34,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:34,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [41978670] [2025-03-16 19:05:34,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [41978670] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:34,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [817606425] [2025-03-16 19:05:34,723 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:34,723 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:34,723 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:05:34,725 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:05:34,726 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2025-03-16 19:05:34,815 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 174 statements into 1 equivalence classes. [2025-03-16 19:05:34,868 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 174 of 174 statements. [2025-03-16 19:05:34,868 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:34,868 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:34,870 INFO L256 TraceCheckSpWp]: Trace formula consists of 755 conjuncts, 20 conjuncts are in the unsatisfiable core [2025-03-16 19:05:34,872 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:34,974 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 84 proven. 0 refuted. 0 times theorem prover too weak. 62 trivial. 0 not checked. [2025-03-16 19:05:34,974 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-03-16 19:05:34,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [817606425] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:05:34,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-03-16 19:05:34,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [10] total 17 [2025-03-16 19:05:34,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420310131] [2025-03-16 19:05:34,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:05:34,974 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2025-03-16 19:05:34,974 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:34,975 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-16 19:05:34,975 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2025-03-16 19:05:34,975 INFO L87 Difference]: Start difference. First operand 13443 states and 17293 transitions. Second operand has 9 states, 9 states have (on average 12.0) internal successors, (108), 8 states have internal predecessors, (108), 3 states have call successors, (15), 3 states have call predecessors, (15), 5 states have return successors, (15), 4 states have call predecessors, (15), 3 states have call successors, (15) [2025-03-16 19:05:36,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:36,839 INFO L93 Difference]: Finished difference Result 26730 states and 34402 transitions. [2025-03-16 19:05:36,839 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-16 19:05:36,839 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 12.0) internal successors, (108), 8 states have internal predecessors, (108), 3 states have call successors, (15), 3 states have call predecessors, (15), 5 states have return successors, (15), 4 states have call predecessors, (15), 3 states have call successors, (15) Word has length 174 [2025-03-16 19:05:36,839 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:36,885 INFO L225 Difference]: With dead ends: 26730 [2025-03-16 19:05:36,886 INFO L226 Difference]: Without dead ends: 13603 [2025-03-16 19:05:36,907 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 192 GetRequests, 170 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=83, Invalid=469, Unknown=0, NotChecked=0, Total=552 [2025-03-16 19:05:36,908 INFO L435 NwaCegarLoop]: 345 mSDtfsCounter, 431 mSDsluCounter, 1329 mSDsCounter, 0 mSdLazyCounter, 336 mSolverCounterSat, 86 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 431 SdHoareTripleChecker+Valid, 1674 SdHoareTripleChecker+Invalid, 422 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 86 IncrementalHoareTripleChecker+Valid, 336 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:36,908 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [431 Valid, 1674 Invalid, 422 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [86 Valid, 336 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-03-16 19:05:36,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13603 states. [2025-03-16 19:05:38,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13603 to 13443. [2025-03-16 19:05:38,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13443 states, 9855 states have (on average 1.2789446981227803) internal successors, (12604), 9952 states have internal predecessors, (12604), 2318 states have call successors, (2318), 1269 states have call predecessors, (2318), 1269 states have return successors, (2318), 2221 states have call predecessors, (2318), 2318 states have call successors, (2318) [2025-03-16 19:05:38,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13443 states to 13443 states and 17240 transitions. [2025-03-16 19:05:38,654 INFO L78 Accepts]: Start accepts. Automaton has 13443 states and 17240 transitions. Word has length 174 [2025-03-16 19:05:38,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:38,655 INFO L471 AbstractCegarLoop]: Abstraction has 13443 states and 17240 transitions. [2025-03-16 19:05:38,655 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 12.0) internal successors, (108), 8 states have internal predecessors, (108), 3 states have call successors, (15), 3 states have call predecessors, (15), 5 states have return successors, (15), 4 states have call predecessors, (15), 3 states have call successors, (15) [2025-03-16 19:05:38,655 INFO L276 IsEmpty]: Start isEmpty. Operand 13443 states and 17240 transitions. [2025-03-16 19:05:38,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2025-03-16 19:05:38,661 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:38,661 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:38,668 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2025-03-16 19:05:38,861 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable35 [2025-03-16 19:05:38,862 INFO L396 AbstractCegarLoop]: === Iteration 37 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:38,862 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:38,862 INFO L85 PathProgramCache]: Analyzing trace with hash 478682513, now seen corresponding path program 1 times [2025-03-16 19:05:38,862 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:38,862 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857161520] [2025-03-16 19:05:38,862 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:38,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:38,872 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 180 statements into 1 equivalence classes. [2025-03-16 19:05:38,887 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 180 of 180 statements. [2025-03-16 19:05:38,887 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:38,887 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:39,186 INFO L134 CoverageAnalysis]: Checked inductivity of 125 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 99 trivial. 0 not checked. [2025-03-16 19:05:39,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:39,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [857161520] [2025-03-16 19:05:39,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [857161520] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-16 19:05:39,186 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-16 19:05:39,186 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-16 19:05:39,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796121653] [2025-03-16 19:05:39,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-16 19:05:39,187 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-16 19:05:39,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:39,187 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-16 19:05:39,187 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-16 19:05:39,187 INFO L87 Difference]: Start difference. First operand 13443 states and 17240 transitions. Second operand has 7 states, 7 states have (on average 15.0) internal successors, (105), 6 states have internal predecessors, (105), 3 states have call successors, (19), 2 states have call predecessors, (19), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18) [2025-03-16 19:05:41,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:41,455 INFO L93 Difference]: Finished difference Result 27392 states and 35168 transitions. [2025-03-16 19:05:41,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-16 19:05:41,456 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 15.0) internal successors, (105), 6 states have internal predecessors, (105), 3 states have call successors, (19), 2 states have call predecessors, (19), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18) Word has length 180 [2025-03-16 19:05:41,456 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:41,503 INFO L225 Difference]: With dead ends: 27392 [2025-03-16 19:05:41,503 INFO L226 Difference]: Without dead ends: 14673 [2025-03-16 19:05:41,524 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2025-03-16 19:05:41,524 INFO L435 NwaCegarLoop]: 348 mSDtfsCounter, 430 mSDsluCounter, 1157 mSDsCounter, 0 mSdLazyCounter, 205 mSolverCounterSat, 85 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 433 SdHoareTripleChecker+Valid, 1505 SdHoareTripleChecker+Invalid, 290 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 85 IncrementalHoareTripleChecker+Valid, 205 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:41,524 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [433 Valid, 1505 Invalid, 290 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [85 Valid, 205 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-03-16 19:05:41,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14673 states. [2025-03-16 19:05:43,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14673 to 14109. [2025-03-16 19:05:43,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14109 states, 10329 states have (on average 1.2782457159453964) internal successors, (13203), 10432 states have internal predecessors, (13203), 2444 states have call successors, (2444), 1335 states have call predecessors, (2444), 1335 states have return successors, (2444), 2341 states have call predecessors, (2444), 2444 states have call successors, (2444) [2025-03-16 19:05:43,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14109 states to 14109 states and 18091 transitions. [2025-03-16 19:05:43,282 INFO L78 Accepts]: Start accepts. Automaton has 14109 states and 18091 transitions. Word has length 180 [2025-03-16 19:05:43,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:43,282 INFO L471 AbstractCegarLoop]: Abstraction has 14109 states and 18091 transitions. [2025-03-16 19:05:43,282 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 15.0) internal successors, (105), 6 states have internal predecessors, (105), 3 states have call successors, (19), 2 states have call predecessors, (19), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18) [2025-03-16 19:05:43,282 INFO L276 IsEmpty]: Start isEmpty. Operand 14109 states and 18091 transitions. [2025-03-16 19:05:43,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2025-03-16 19:05:43,288 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:43,288 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:43,288 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable36 [2025-03-16 19:05:43,288 INFO L396 AbstractCegarLoop]: === Iteration 38 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:43,289 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:43,289 INFO L85 PathProgramCache]: Analyzing trace with hash 220006930, now seen corresponding path program 1 times [2025-03-16 19:05:43,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:43,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215981757] [2025-03-16 19:05:43,289 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:43,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:43,299 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 180 statements into 1 equivalence classes. [2025-03-16 19:05:43,314 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 180 of 180 statements. [2025-03-16 19:05:43,315 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:43,315 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:43,779 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 19 proven. 22 refuted. 0 times theorem prover too weak. 106 trivial. 0 not checked. [2025-03-16 19:05:43,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-16 19:05:43,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215981757] [2025-03-16 19:05:43,780 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215981757] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-16 19:05:43,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1985796700] [2025-03-16 19:05:43,780 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:43,780 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-16 19:05:43,780 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-16 19:05:43,781 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-16 19:05:43,782 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2025-03-16 19:05:43,876 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 180 statements into 1 equivalence classes. [2025-03-16 19:05:43,931 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 180 of 180 statements. [2025-03-16 19:05:43,931 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:43,931 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-16 19:05:43,934 INFO L256 TraceCheckSpWp]: Trace formula consists of 762 conjuncts, 22 conjuncts are in the unsatisfiable core [2025-03-16 19:05:43,936 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-16 19:05:44,084 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 60 proven. 56 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2025-03-16 19:05:44,084 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-16 19:05:44,277 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 19 proven. 22 refuted. 0 times theorem prover too weak. 106 trivial. 0 not checked. [2025-03-16 19:05:44,277 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1985796700] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-16 19:05:44,277 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-16 19:05:44,277 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 8] total 24 [2025-03-16 19:05:44,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [138944095] [2025-03-16 19:05:44,277 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-16 19:05:44,278 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 24 states [2025-03-16 19:05:44,278 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-16 19:05:44,278 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2025-03-16 19:05:44,278 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=459, Unknown=0, NotChecked=0, Total=552 [2025-03-16 19:05:44,279 INFO L87 Difference]: Start difference. First operand 14109 states and 18091 transitions. Second operand has 24 states, 24 states have (on average 10.916666666666666) internal successors, (262), 21 states have internal predecessors, (262), 10 states have call successors, (50), 4 states have call predecessors, (50), 8 states have return successors, (49), 13 states have call predecessors, (49), 10 states have call successors, (49) [2025-03-16 19:05:46,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-16 19:05:46,643 INFO L93 Difference]: Finished difference Result 27124 states and 34796 transitions. [2025-03-16 19:05:46,643 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2025-03-16 19:05:46,643 INFO L78 Accepts]: Start accepts. Automaton has has 24 states, 24 states have (on average 10.916666666666666) internal successors, (262), 21 states have internal predecessors, (262), 10 states have call successors, (50), 4 states have call predecessors, (50), 8 states have return successors, (49), 13 states have call predecessors, (49), 10 states have call successors, (49) Word has length 180 [2025-03-16 19:05:46,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-16 19:05:46,686 INFO L225 Difference]: With dead ends: 27124 [2025-03-16 19:05:46,687 INFO L226 Difference]: Without dead ends: 13739 [2025-03-16 19:05:46,703 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 393 GetRequests, 352 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 362 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=345, Invalid=1461, Unknown=0, NotChecked=0, Total=1806 [2025-03-16 19:05:46,703 INFO L435 NwaCegarLoop]: 527 mSDtfsCounter, 938 mSDsluCounter, 4411 mSDsCounter, 0 mSdLazyCounter, 1133 mSolverCounterSat, 214 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 951 SdHoareTripleChecker+Valid, 4938 SdHoareTripleChecker+Invalid, 1347 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 214 IncrementalHoareTripleChecker+Valid, 1133 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2025-03-16 19:05:46,703 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [951 Valid, 4938 Invalid, 1347 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [214 Valid, 1133 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2025-03-16 19:05:46,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13739 states. [2025-03-16 19:05:48,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13739 to 13341. [2025-03-16 19:05:48,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13341 states, 9777 states have (on average 1.274112713511302) internal successors, (12457), 9872 states have internal predecessors, (12457), 2308 states have call successors, (2308), 1255 states have call predecessors, (2308), 1255 states have return successors, (2308), 2213 states have call predecessors, (2308), 2308 states have call successors, (2308) [2025-03-16 19:05:48,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13341 states to 13341 states and 17073 transitions. [2025-03-16 19:05:48,364 INFO L78 Accepts]: Start accepts. Automaton has 13341 states and 17073 transitions. Word has length 180 [2025-03-16 19:05:48,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-16 19:05:48,364 INFO L471 AbstractCegarLoop]: Abstraction has 13341 states and 17073 transitions. [2025-03-16 19:05:48,364 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 24 states, 24 states have (on average 10.916666666666666) internal successors, (262), 21 states have internal predecessors, (262), 10 states have call successors, (50), 4 states have call predecessors, (50), 8 states have return successors, (49), 13 states have call predecessors, (49), 10 states have call successors, (49) [2025-03-16 19:05:48,364 INFO L276 IsEmpty]: Start isEmpty. Operand 13341 states and 17073 transitions. [2025-03-16 19:05:48,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2025-03-16 19:05:48,370 INFO L210 NwaCegarLoop]: Found error trace [2025-03-16 19:05:48,370 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:48,377 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2025-03-16 19:05:48,571 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable37 [2025-03-16 19:05:48,571 INFO L396 AbstractCegarLoop]: === Iteration 39 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-16 19:05:48,571 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-16 19:05:48,571 INFO L85 PathProgramCache]: Analyzing trace with hash -824868802, now seen corresponding path program 1 times [2025-03-16 19:05:48,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-16 19:05:48,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613021262] [2025-03-16 19:05:48,572 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-16 19:05:48,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-16 19:05:48,582 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 181 statements into 1 equivalence classes. [2025-03-16 19:05:48,618 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 181 of 181 statements. [2025-03-16 19:05:48,618 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:48,618 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-16 19:05:48,618 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-16 19:05:48,627 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 181 statements into 1 equivalence classes. [2025-03-16 19:05:48,676 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 181 of 181 statements. [2025-03-16 19:05:48,676 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-16 19:05:48,676 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-16 19:05:48,739 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-16 19:05:48,740 INFO L340 BasicCegarLoop]: Counterexample is feasible [2025-03-16 19:05:48,740 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location assertErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2025-03-16 19:05:48,742 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable38 [2025-03-16 19:05:48,744 INFO L422 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-16 19:05:48,878 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2025-03-16 19:05:48,881 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 16.03 07:05:48 BoogieIcfgContainer [2025-03-16 19:05:48,882 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2025-03-16 19:05:48,882 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-16 19:05:48,882 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-16 19:05:48,882 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-16 19:05:48,883 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 16.03 07:04:44" (3/4) ... [2025-03-16 19:05:48,883 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2025-03-16 19:05:49,035 INFO L127 tionWitnessGenerator]: Generated YAML witness of length 154. [2025-03-16 19:05:49,112 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-16 19:05:49,113 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.yml [2025-03-16 19:05:49,113 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-16 19:05:49,115 INFO L158 Benchmark]: Toolchain (without parser) took 65932.03ms. Allocated memory was 142.6MB in the beginning and 3.8GB in the end (delta: 3.7GB). Free memory was 112.0MB in the beginning and 2.6GB in the end (delta: -2.5GB). Peak memory consumption was 1.2GB. Max. memory is 16.1GB. [2025-03-16 19:05:49,115 INFO L158 Benchmark]: CDTParser took 0.16ms. Allocated memory is still 226.5MB. Free memory is still 148.3MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-16 19:05:49,115 INFO L158 Benchmark]: CACSL2BoogieTranslator took 334.18ms. Allocated memory is still 142.6MB. Free memory was 111.4MB in the beginning and 93.4MB in the end (delta: 18.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-16 19:05:49,116 INFO L158 Benchmark]: Boogie Procedure Inliner took 56.54ms. Allocated memory is still 142.6MB. Free memory was 93.4MB in the beginning and 90.2MB in the end (delta: 3.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-16 19:05:49,116 INFO L158 Benchmark]: Boogie Preprocessor took 72.35ms. Allocated memory is still 142.6MB. Free memory was 90.2MB in the beginning and 86.7MB in the end (delta: 3.5MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-16 19:05:49,116 INFO L158 Benchmark]: IcfgBuilder took 628.04ms. Allocated memory is still 142.6MB. Free memory was 86.7MB in the beginning and 45.4MB in the end (delta: 41.3MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2025-03-16 19:05:49,116 INFO L158 Benchmark]: TraceAbstraction took 64604.54ms. Allocated memory was 142.6MB in the beginning and 3.8GB in the end (delta: 3.7GB). Free memory was 44.8MB in the beginning and 2.6GB in the end (delta: -2.6GB). Peak memory consumption was 1.1GB. Max. memory is 16.1GB. [2025-03-16 19:05:49,116 INFO L158 Benchmark]: Witness Printer took 230.77ms. Allocated memory is still 3.8GB. Free memory was 2.6GB in the beginning and 2.6GB in the end (delta: 46.1MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2025-03-16 19:05:49,116 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16ms. Allocated memory is still 226.5MB. Free memory is still 148.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 334.18ms. Allocated memory is still 142.6MB. Free memory was 111.4MB in the beginning and 93.4MB in the end (delta: 18.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 56.54ms. Allocated memory is still 142.6MB. Free memory was 93.4MB in the beginning and 90.2MB in the end (delta: 3.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 72.35ms. Allocated memory is still 142.6MB. Free memory was 90.2MB in the beginning and 86.7MB in the end (delta: 3.5MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 628.04ms. Allocated memory is still 142.6MB. Free memory was 86.7MB in the beginning and 45.4MB in the end (delta: 41.3MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * TraceAbstraction took 64604.54ms. Allocated memory was 142.6MB in the beginning and 3.8GB in the end (delta: 3.7GB). Free memory was 44.8MB in the beginning and 2.6GB in the end (delta: -2.6GB). Peak memory consumption was 1.1GB. Max. memory is 16.1GB. * Witness Printer took 230.77ms. Allocated memory is still 3.8GB. Free memory was 2.6GB in the beginning and 2.6GB in the end (delta: 46.1MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 618]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L24] msg_t nomsg = (msg_t )-1; [L25] port_t cs1 ; [L26] int8_t cs1_old ; [L27] int8_t cs1_new ; [L28] port_t cs2 ; [L29] int8_t cs2_old ; [L30] int8_t cs2_new ; [L31] port_t s1s2 ; [L32] int8_t s1s2_old ; [L33] int8_t s1s2_new ; [L34] port_t s1s1 ; [L35] int8_t s1s1_old ; [L36] int8_t s1s1_new ; [L37] port_t s2s1 ; [L38] int8_t s2s1_old ; [L39] int8_t s2s1_new ; [L40] port_t s2s2 ; [L41] int8_t s2s2_old ; [L42] int8_t s2s2_new ; [L43] port_t s1p ; [L44] int8_t s1p_old ; [L45] int8_t s1p_new ; [L46] port_t s2p ; [L47] int8_t s2p_old ; [L48] int8_t s2p_new ; [L51] _Bool side1Failed ; [L52] _Bool side2Failed ; [L53] msg_t side1_written ; [L54] msg_t side2_written ; [L60] static _Bool side1Failed_History_0 ; [L61] static _Bool side1Failed_History_1 ; [L62] static _Bool side1Failed_History_2 ; [L63] static _Bool side2Failed_History_0 ; [L64] static _Bool side2Failed_History_1 ; [L65] static _Bool side2Failed_History_2 ; [L66] static int8_t active_side_History_0 ; [L67] static int8_t active_side_History_1 ; [L68] static int8_t active_side_History_2 ; [L69] static msg_t manual_selection_History_0 ; [L70] static msg_t manual_selection_History_1 ; [L71] static msg_t manual_selection_History_2 ; [L542] int c1 ; [L543] int i2 ; [L546] c1 = 0 [L547] side1Failed = __VERIFIER_nondet_bool() [L548] side2Failed = __VERIFIER_nondet_bool() [L549] side1_written = __VERIFIER_nondet_char() [L550] side2_written = __VERIFIER_nondet_char() [L551] side1Failed_History_0 = __VERIFIER_nondet_bool() [L552] side1Failed_History_1 = __VERIFIER_nondet_bool() [L553] side1Failed_History_2 = __VERIFIER_nondet_bool() [L554] side2Failed_History_0 = __VERIFIER_nondet_bool() [L555] side2Failed_History_1 = __VERIFIER_nondet_bool() [L556] side2Failed_History_2 = __VERIFIER_nondet_bool() [L557] active_side_History_0 = __VERIFIER_nondet_char() [L558] active_side_History_1 = __VERIFIER_nondet_char() [L559] active_side_History_2 = __VERIFIER_nondet_char() [L560] manual_selection_History_0 = __VERIFIER_nondet_char() [L561] manual_selection_History_1 = __VERIFIER_nondet_char() [L562] manual_selection_History_2 = __VERIFIER_nondet_char() [L563] CALL, EXPR init() [L197] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L200] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L203] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L206] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L209] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L212] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L215] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L218] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L221] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L224] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L227] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L230] COND FALSE !((int )manual_selection_History_2 != 0) [L233] return (1); VAL [\result=1, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L563] RET, EXPR init() [L563] i2 = init() [L564] CALL assume_abort_if_not(i2) VAL [\old(cond)=1, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L58] COND FALSE !(!cond) VAL [\old(cond)=1, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L564] RET assume_abort_if_not(i2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, i2=1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L565] cs1_old = nomsg [L566] cs1_new = nomsg [L567] cs2_old = nomsg [L568] cs2_new = nomsg [L569] s1s2_old = nomsg [L570] s1s2_new = nomsg [L571] s1s1_old = nomsg [L572] s1s1_new = nomsg [L573] s2s1_old = nomsg [L574] s2s1_new = nomsg [L575] s2s2_old = nomsg [L576] s2s2_new = nomsg [L577] s1p_old = nomsg [L578] s1p_new = nomsg [L579] s2p_old = nomsg [L580] s2p_new = nomsg [L581] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, i2=1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L582] COND TRUE 1 [L584] CALL Console_task_each_pals_period() [L251] msg_t manual_selection ; [L252] char tmp ; [L255] tmp = __VERIFIER_nondet_char() [L256] manual_selection = tmp [L257] CALL write_manual_selection_history(manual_selection) [L167] manual_selection_History_2 = manual_selection_History_1 [L168] manual_selection_History_1 = manual_selection_History_0 [L169] manual_selection_History_0 = val [L257] RET write_manual_selection_history(manual_selection) [L258] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L259] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L260] manual_selection = (msg_t )0 [L584] RET Console_task_each_pals_period() [L585] CALL Side1_activestandby_task_each_pals_period() [L266] int8_t side1 ; [L267] int8_t side2 ; [L268] msg_t manual_selection ; [L269] int8_t next_state ; [L272] side1 = nomsg [L273] side2 = nomsg [L274] manual_selection = (msg_t )0 [L275] side1Failed = __VERIFIER_nondet_bool() [L276] CALL write_side1_failed_history(side1Failed) [L77] side1Failed_History_2 = side1Failed_History_1 [L78] side1Failed_History_1 = side1Failed_History_0 [L79] side1Failed_History_0 = val [L276] RET write_side1_failed_history(side1Failed) [L277] COND TRUE \read(side1Failed) [L278] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L279] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L280] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L281] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L585] RET Side1_activestandby_task_each_pals_period() [L586] CALL Side2_activestandby_task_each_pals_period() [L323] int8_t side1 ; [L324] int8_t side2 ; [L325] msg_t manual_selection ; [L326] int8_t next_state ; [L329] side1 = nomsg [L330] side2 = nomsg [L331] manual_selection = (msg_t )0 [L332] side2Failed = __VERIFIER_nondet_bool() [L333] CALL write_side2_failed_history(side2Failed) [L107] side2Failed_History_2 = side2Failed_History_1 [L108] side2Failed_History_1 = side2Failed_History_0 [L109] side2Failed_History_0 = val [L333] RET write_side2_failed_history(side2Failed) [L334] COND FALSE !(\read(side2Failed)) [L341] side1 = s1s2_old [L342] s1s2_old = nomsg [L343] side2 = s2s2_old [L344] s2s2_old = nomsg [L345] manual_selection = cs2_old [L346] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L347] COND TRUE (int )side1 == (int )side2 [L348] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, next_state=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L371] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L372] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L373] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L374] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L586] RET Side2_activestandby_task_each_pals_period() [L587] CALL Pendulum_prism_task_each_pals_period() [L380] int8_t active_side ; [L381] int8_t tmp ; [L382] int8_t side1 ; [L383] int8_t side2 ; VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [\old(index)=0, \result=-2, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] RET, EXPR read_active_side_history((unsigned char)0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] tmp = read_active_side_history((unsigned char)0) [L387] active_side = tmp [L388] side1 = nomsg [L389] side2 = nomsg [L390] side1 = s1p_old [L391] s1p_old = nomsg [L392] side2 = s2p_old [L393] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L394] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L397] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L400] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L408] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L409] COND FALSE !((int )side2 == 0) [L412] active_side = (int8_t )0 VAL [active_side=0, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L417] CALL write_active_side_history(active_side) [L137] active_side_History_2 = active_side_History_1 [L138] active_side_History_1 = active_side_History_0 [L139] active_side_History_0 = val [L417] RET write_active_side_history(active_side) [L587] RET Pendulum_prism_task_each_pals_period() [L588] cs1_old = cs1_new [L589] cs1_new = nomsg [L590] cs2_old = cs2_new [L591] cs2_new = nomsg [L592] s1s2_old = s1s2_new [L593] s1s2_new = nomsg [L594] s1s1_old = s1s1_new [L595] s1s1_new = nomsg [L596] s2s1_old = s2s1_new [L597] s2s1_new = nomsg [L598] s2s2_old = s2s2_new [L599] s2s2_new = nomsg [L600] s1p_old = s1p_new [L601] s1p_new = nomsg [L602] s2p_old = s2p_new [L603] s2p_new = nomsg [L604] CALL, EXPR check() [L423] int tmp ; [L424] msg_t tmp___0 ; [L425] _Bool tmp___1 ; [L426] _Bool tmp___2 ; [L427] _Bool tmp___3 ; [L428] _Bool tmp___4 ; [L429] int8_t tmp___5 ; [L430] _Bool tmp___6 ; [L431] _Bool tmp___7 ; [L432] _Bool tmp___8 ; [L433] int8_t tmp___9 ; [L434] _Bool tmp___10 ; [L435] _Bool tmp___11 ; [L436] _Bool tmp___12 ; [L437] msg_t tmp___13 ; [L438] _Bool tmp___14 ; [L439] _Bool tmp___15 ; [L440] _Bool tmp___16 ; [L441] _Bool tmp___17 ; [L442] int8_t tmp___18 ; [L443] int8_t tmp___19 ; [L444] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L447] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L450] COND TRUE ! side2Failed [L451] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L455] CALL assume_abort_if_not((_Bool )tmp) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L58] COND FALSE !(!cond) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L455] RET assume_abort_if_not((_Bool )tmp) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L456] CALL, EXPR read_manual_selection_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L178] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L181] COND TRUE (int )index == 1 [L182] return (manual_selection_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L456] RET, EXPR read_manual_selection_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L456] tmp___0 = read_manual_selection_history((unsigned char)1) [L457] COND TRUE ! tmp___0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L458] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L458] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L458] tmp___1 = read_side1_failed_history((unsigned char)1) [L459] COND TRUE ! tmp___1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L460] CALL, EXPR read_side1_failed_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND TRUE (int )index == 0 [L89] return (side1Failed_History_0); VAL [\old(index)=0, \result=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L460] RET, EXPR read_side1_failed_history((unsigned char)0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L460] tmp___2 = read_side1_failed_history((unsigned char)0) [L461] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L486] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L486] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L486] tmp___7 = read_side1_failed_history((unsigned char)1) [L487] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L502] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L502] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L502] tmp___11 = read_side1_failed_history((unsigned char)1) [L503] COND TRUE ! tmp___11 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L504] CALL, EXPR read_side2_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L118] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L121] COND TRUE (int )index == 1 [L122] return (side2Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L504] RET, EXPR read_side2_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L504] tmp___12 = read_side2_failed_history((unsigned char)1) [L505] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L518] CALL, EXPR read_active_side_history((unsigned char)2) VAL [\old(index)=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L148] COND FALSE !((int )index == 0) VAL [\old(index)=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=2, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L151] COND FALSE !((int )index == 1) VAL [\old(index)=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=2, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L154] COND TRUE (int )index == 2 [L155] return (active_side_History_2); VAL [\old(index)=2, \result=-2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L518] RET, EXPR read_active_side_history((unsigned char)2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L518] tmp___20 = read_active_side_history((unsigned char)2) [L519] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L537] return (1); VAL [\result=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L604] RET, EXPR check() [L604] c1 = check() [L605] CALL assert(c1) VAL [\old(arg)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L616] COND FALSE !(! arg) VAL [\old(arg)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L605] RET assert(c1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, c1=1, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, i2=1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L582] COND TRUE 1 [L584] CALL Console_task_each_pals_period() [L251] msg_t manual_selection ; [L252] char tmp ; [L255] tmp = __VERIFIER_nondet_char() [L256] manual_selection = tmp [L257] CALL write_manual_selection_history(manual_selection) [L167] manual_selection_History_2 = manual_selection_History_1 [L168] manual_selection_History_1 = manual_selection_History_0 [L169] manual_selection_History_0 = val [L257] RET write_manual_selection_history(manual_selection) [L258] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L259] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L260] manual_selection = (msg_t )0 [L584] RET Console_task_each_pals_period() [L585] CALL Side1_activestandby_task_each_pals_period() [L266] int8_t side1 ; [L267] int8_t side2 ; [L268] msg_t manual_selection ; [L269] int8_t next_state ; [L272] side1 = nomsg [L273] side2 = nomsg [L274] manual_selection = (msg_t )0 [L275] side1Failed = __VERIFIER_nondet_bool() [L276] CALL write_side1_failed_history(side1Failed) [L77] side1Failed_History_2 = side1Failed_History_1 [L78] side1Failed_History_1 = side1Failed_History_0 [L79] side1Failed_History_0 = val [L276] RET write_side1_failed_history(side1Failed) [L277] COND TRUE \read(side1Failed) [L278] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L279] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L280] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L281] side1_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L585] RET Side1_activestandby_task_each_pals_period() [L586] CALL Side2_activestandby_task_each_pals_period() [L323] int8_t side1 ; [L324] int8_t side2 ; [L325] msg_t manual_selection ; [L326] int8_t next_state ; [L329] side1 = nomsg [L330] side2 = nomsg [L331] manual_selection = (msg_t )0 [L332] side2Failed = __VERIFIER_nondet_bool() [L333] CALL write_side2_failed_history(side2Failed) [L107] side2Failed_History_2 = side2Failed_History_1 [L108] side2Failed_History_1 = side2Failed_History_0 [L109] side2Failed_History_0 = val [L333] RET write_side2_failed_history(side2Failed) [L334] COND FALSE !(\read(side2Failed)) [L341] side1 = s1s2_old [L342] s1s2_old = nomsg [L343] side2 = s2s2_old [L344] s2s2_old = nomsg [L345] manual_selection = cs2_old [L346] cs2_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection=127, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L347] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection=127, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L350] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection=127, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L351] COND TRUE (int )side2 != (int )nomsg [L352] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection=127, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, next_state=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L371] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L372] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L373] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L374] side2_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection=127, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L586] RET Side2_activestandby_task_each_pals_period() [L587] CALL Pendulum_prism_task_each_pals_period() [L380] int8_t active_side ; [L381] int8_t tmp ; [L382] int8_t side1 ; [L383] int8_t side2 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [\old(index)=0, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] RET, EXPR read_active_side_history((unsigned char)0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] tmp = read_active_side_history((unsigned char)0) [L387] active_side = tmp [L388] side1 = nomsg [L389] side2 = nomsg [L390] side1 = s1p_old [L391] s1p_old = nomsg [L392] side2 = s2p_old [L393] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L394] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L397] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L400] COND FALSE !((int )side1 == 0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L408] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L409] COND TRUE (int )side2 == 0 [L410] active_side = (int8_t )2 VAL [active_side=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L417] CALL write_active_side_history(active_side) [L137] active_side_History_2 = active_side_History_1 [L138] active_side_History_1 = active_side_History_0 [L139] active_side_History_0 = val [L417] RET write_active_side_history(active_side) [L587] RET Pendulum_prism_task_each_pals_period() [L588] cs1_old = cs1_new [L589] cs1_new = nomsg [L590] cs2_old = cs2_new [L591] cs2_new = nomsg [L592] s1s2_old = s1s2_new [L593] s1s2_new = nomsg [L594] s1s1_old = s1s1_new [L595] s1s1_new = nomsg [L596] s2s1_old = s2s1_new [L597] s2s1_new = nomsg [L598] s2s2_old = s2s2_new [L599] s2s2_new = nomsg [L600] s1p_old = s1p_new [L601] s1p_new = nomsg [L602] s2p_old = s2p_new [L603] s2p_new = nomsg [L604] CALL, EXPR check() [L423] int tmp ; [L424] msg_t tmp___0 ; [L425] _Bool tmp___1 ; [L426] _Bool tmp___2 ; [L427] _Bool tmp___3 ; [L428] _Bool tmp___4 ; [L429] int8_t tmp___5 ; [L430] _Bool tmp___6 ; [L431] _Bool tmp___7 ; [L432] _Bool tmp___8 ; [L433] int8_t tmp___9 ; [L434] _Bool tmp___10 ; [L435] _Bool tmp___11 ; [L436] _Bool tmp___12 ; [L437] msg_t tmp___13 ; [L438] _Bool tmp___14 ; [L439] _Bool tmp___15 ; [L440] _Bool tmp___16 ; [L441] _Bool tmp___17 ; [L442] int8_t tmp___18 ; [L443] int8_t tmp___19 ; [L444] int8_t tmp___20 ; VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L447] COND FALSE !(! side1Failed) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L450] COND TRUE ! side2Failed [L451] tmp = 1 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L455] CALL assume_abort_if_not((_Bool )tmp) VAL [\old(cond)=1, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L58] COND FALSE !(!cond) VAL [\old(cond)=1, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L455] RET assume_abort_if_not((_Bool )tmp) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L456] CALL, EXPR read_manual_selection_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L178] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L181] COND TRUE (int )index == 1 [L182] return (manual_selection_History_1); VAL [\old(index)=1, \result=127, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L456] RET, EXPR read_manual_selection_history((unsigned char)1) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L456] tmp___0 = read_manual_selection_history((unsigned char)1) [L457] COND FALSE !(! tmp___0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L486] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=1, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L486] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L486] tmp___7 = read_side1_failed_history((unsigned char)1) [L487] COND TRUE \read(tmp___7) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L488] CALL, EXPR read_side2_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L118] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L121] COND TRUE (int )index == 1 [L122] return (side2Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L488] RET, EXPR read_side2_failed_history((unsigned char)1) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L488] tmp___8 = read_side2_failed_history((unsigned char)1) [L489] COND TRUE ! tmp___8 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L490] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [\old(index)=0, \result=2, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L490] RET, EXPR read_active_side_history((unsigned char)0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L490] tmp___5 = read_active_side_history((unsigned char)0) [L491] COND FALSE !(! ((int )tmp___5 == 2)) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L494] CALL, EXPR read_side2_failed_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L118] COND TRUE (int )index == 0 [L119] return (side2Failed_History_0); VAL [\old(index)=0, \result=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L494] RET, EXPR read_side2_failed_history((unsigned char)0) VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L494] tmp___6 = read_side2_failed_history((unsigned char)0) [L495] COND TRUE ! tmp___6 VAL [active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L496] COND TRUE ! ((int )side2_written == 1) [L497] return (0); VAL [\result=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L604] RET, EXPR check() [L604] c1 = check() [L605] CALL assert(c1) VAL [\old(arg)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L616] COND TRUE ! arg VAL [\old(arg)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L618] reach_error() VAL [\old(arg)=0, active_side_History_0=2, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 8 procedures, 171 locations, 301 edges, 1 error locations. Started 1 CEGAR loops. OverallTime: 64.4s, OverallIterations: 39, TraceHistogramMax: 6, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.1s, AutomataDifference: 30.7s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 15399 SdHoareTripleChecker+Valid, 9.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 15315 mSDsluCounter, 69520 SdHoareTripleChecker+Invalid, 8.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 57000 mSDsCounter, 3697 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 16315 IncrementalHoareTripleChecker+Invalid, 20012 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 3697 mSolverCounterUnsat, 12520 mSDtfsCounter, 16315 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 3371 GetRequests, 2752 SyntacticMatches, 0 SemanticMatches, 619 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10133 ImplicationChecksByTransitivity, 6.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=14109occurred in iteration=37, InterpolantAutomatonStates: 484, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 15.9s AutomataMinimizationTime, 38 MinimizatonAttempts, 17876 StatesRemovedByMinimization, 28 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.4s SsaConstructionTime, 1.5s SatisfiabilityAnalysisTime, 12.2s InterpolantComputationTime, 5384 NumberOfCodeBlocks, 5384 NumberOfCodeBlocksAsserted, 49 NumberOfCheckSat, 6371 ConstructedInterpolants, 0 QuantifiedInterpolants, 19152 SizeOfPredicates, 44 NumberOfNonLiveVariables, 6770 ConjunctsInSsa, 276 ConjunctsInUnsatCore, 56 InterpolantComputations, 31 PerfectInterpolantSequences, 2625/3065 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2025-03-16 19:05:49,137 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE