Tool ULTIMATE Automizer 0.1.24-0ed9222f
Limits timelimit: 900 s, memlimit: 8000 MB, CPU core limit: 2
Host struebli
OS Linux-4.20.1-gentoo-x86_64-AMD_EPYC_7351P_16-Core_Processor-with-gentoo-2.6
System CPU: AMD EPYC 7351P 16-Core Processor, cores: 32, frequency: 2400 MHz, Turbo Boost: enabled; RAM: 135156 MB
Date of execution 2019-01-11 17:27:34 CET
Run set sv-comp19_prop-reachsafety.ReachSafety-BitVectors
Options --full-output
../../../../../svcomp/c/ status cputime (s) walltime (s) memUsage
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 105    71.6  742154240
bitvector/sum02_false-unreach-call_true-no-overflow.i 17.9  14.9  250355712
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 901    846    812601344
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 901    846    896872448
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 901    878    4728184832
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 900    894    641855488
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 900    889    2127253504
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 14.2  8.79 459210752
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 162    147    667242496
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 16.5  12.9  272719872
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 21.0  17.5  280780800
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 34.2  29.5  358846464
bitvector/jain_5_true-unreach-call_true-no-overflow.i 900    880    700936192
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 21.1  17.0  286044160
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 46.1  41.2  351801344
bitvector/modulus_true-unreach-call_true-no-overflow.i 19.2  14.0  362541056
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 41.8  26.7  589234176
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 901    861    1503191040
bitvector/parity_true-unreach-call_true-no-overflow.i 900    888    1053532160
bitvector/sum02_true-unreach-call_true-no-overflow.i 900    895    495931392
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 40.9  23.2  542396416
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 51.7  28.6  628756480
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 41.7  23.9  603582464
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 74.0  43.0  931979264
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 77.4  43.8  1006444544
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 46.3  25.5  847618048
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 901    837    6386565120
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 95.3  54.3  1278291968
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 74.2  43.9  1599385600
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 80.0  46.8  1588035584
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 69.3  39.2  1033101312
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 66.9  38.3  1028902912
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 473    438    838344704
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 26.3  15.6  573747200
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 901    831    780050432
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 900    866    1243959296
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 26.3  15.8  583794688
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 13.2  8.17 237969408
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 7.05 4.38 228847616
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 13.8  8.45 231522304
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 400    354    862203904
bitvector-regression/signextension2_false-unreach-call_true-termination.c 6.89 4.19 230670336
bitvector-regression/signextension_false-unreach-call_true-termination.c 6.49 4.07 231510016
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 7.93 4.75 246550528
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 14.2  8.72 241299456
bitvector-regression/signextension2_true-unreach-call_true-termination.c 7.77 4.72 248430592
bitvector-regression/signextension_true-unreach-call_true-termination.c 8.78 5.30 248250368
bitvector-loops/diamond_false-unreach-call2.i 14.5  9.40 362598400
bitvector-loops/overflow_false-unreach-call1.i 900    882    682418176
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 299    283    640884736
../../../../../svcomp/c/ status cputime (s) walltime (s) memUsage
total 50 14200 13300 43769401344
    correct results 36 2530 1970 21465694208
        correct true 24 1520 1140 15922597888
        correct false 12 1000 824 5543096320
    incorrect results 0
        incorrect true 0
        incorrect false 0
score (50 tasks, max score: 86) 60
Run set sv-comp19_prop-reachsafety.ReachSafety-BitVectors