java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-memsafety/cstrcspn-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-acfac67 [2018-01-28 23:21:51,796 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-28 23:21:51,820 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-28 23:21:51,832 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-28 23:21:51,832 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-28 23:21:51,833 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-28 23:21:51,835 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-28 23:21:51,836 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-28 23:21:51,838 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-28 23:21:51,839 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-28 23:21:51,840 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-28 23:21:51,840 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-28 23:21:51,841 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-28 23:21:51,843 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-28 23:21:51,844 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-28 23:21:51,846 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-28 23:21:51,848 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-28 23:21:51,850 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-28 23:21:51,851 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-28 23:21:51,852 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-28 23:21:51,855 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-28 23:21:51,855 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-28 23:21:51,855 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-28 23:21:51,856 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-28 23:21:51,857 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-28 23:21:51,858 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-28 23:21:51,858 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-28 23:21:51,859 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-28 23:21:51,859 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-28 23:21:51,859 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-28 23:21:51,860 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-28 23:21:51,860 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-28 23:21:51,870 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-28 23:21:51,870 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-28 23:21:51,871 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-28 23:21:51,871 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-28 23:21:51,871 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-28 23:21:51,872 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-28 23:21:51,872 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-28 23:21:51,873 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-28 23:21:51,873 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-28 23:21:51,873 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-28 23:21:51,873 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-28 23:21:51,873 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-28 23:21:51,874 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-28 23:21:51,874 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-28 23:21:51,874 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-28 23:21:51,874 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-28 23:21:51,874 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-28 23:21:51,875 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-28 23:21:51,875 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-28 23:21:51,875 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-28 23:21:51,875 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-28 23:21:51,875 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-28 23:21:51,876 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-28 23:21:51,876 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-28 23:21:51,876 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-28 23:21:51,876 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-28 23:21:51,876 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-28 23:21:51,877 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-28 23:21:51,877 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-28 23:21:51,877 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-28 23:21:51,877 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-28 23:21:51,877 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-28 23:21:51,878 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-28 23:21:51,878 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-28 23:21:51,914 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-28 23:21:51,927 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-28 23:21:51,931 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-28 23:21:51,933 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-28 23:21:51,933 INFO L276 PluginConnector]: CDTParser initialized [2018-01-28 23:21:51,934 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/cstrcspn-alloca_true-valid-memsafety_true-termination.i [2018-01-28 23:21:52,103 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-28 23:21:52,108 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-01-28 23:21:52,109 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-28 23:21:52,109 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-28 23:21:52,115 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-28 23:21:52,116 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.01 11:21:52" (1/1) ... [2018-01-28 23:21:52,118 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@ba793f1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:21:52, skipping insertion in model container [2018-01-28 23:21:52,118 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.01 11:21:52" (1/1) ... [2018-01-28 23:21:52,136 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-28 23:21:52,175 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-28 23:21:52,284 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-28 23:21:52,300 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-28 23:21:52,307 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:21:52 WrapperNode [2018-01-28 23:21:52,307 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-28 23:21:52,308 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-28 23:21:52,308 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-28 23:21:52,308 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-28 23:21:52,319 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:21:52" (1/1) ... [2018-01-28 23:21:52,319 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:21:52" (1/1) ... [2018-01-28 23:21:52,329 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:21:52" (1/1) ... [2018-01-28 23:21:52,330 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:21:52" (1/1) ... [2018-01-28 23:21:52,334 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:21:52" (1/1) ... [2018-01-28 23:21:52,337 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:21:52" (1/1) ... [2018-01-28 23:21:52,338 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:21:52" (1/1) ... [2018-01-28 23:21:52,339 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-28 23:21:52,340 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-28 23:21:52,340 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-28 23:21:52,340 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-28 23:21:52,341 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:21:52" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-28 23:21:52,384 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-28 23:21:52,384 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-28 23:21:52,384 INFO L136 BoogieDeclarations]: Found implementation of procedure cstrcspn [2018-01-28 23:21:52,384 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-28 23:21:52,385 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-28 23:21:52,385 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-28 23:21:52,385 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-28 23:21:52,385 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-28 23:21:52,385 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-28 23:21:52,385 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-28 23:21:52,386 INFO L128 BoogieDeclarations]: Found specification of procedure cstrcspn [2018-01-28 23:21:52,386 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-28 23:21:52,386 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-28 23:21:52,386 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-28 23:21:52,673 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-28 23:21:52,674 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.01 11:21:52 BoogieIcfgContainer [2018-01-28 23:21:52,674 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-28 23:21:52,674 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-01-28 23:21:52,674 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-01-28 23:21:52,675 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-01-28 23:21:52,678 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.01 11:21:52" (1/1) ... [2018-01-28 23:21:52,684 INFO L103 apSepIcfgTransformer]: HeapSepIcfgTransformer: Starting heap partitioning [2018-01-28 23:21:52,684 INFO L104 apSepIcfgTransformer]: To be partitioned heap arrays found [#memory_int] [2018-01-28 23:21:52,685 INFO L150 apSepIcfgTransformer]: starting freeze-var-style preprocessing [2018-01-28 23:21:52,746 INFO L218 apSepIcfgTransformer]: finished preprocessing for the equality analysis [2018-01-28 23:21:52,808 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-28 23:22:30,885 INFO L311 AbstractInterpreter]: Visited 101 different actions 1242 times. Merged at 67 different actions 747 times. Widened at 1 different actions 4 times. Found 100 fixpoints after 12 different actions. Largest state had 43 variables. [2018-01-28 23:22:30,887 INFO L226 apSepIcfgTransformer]: finished equality analysis [2018-01-28 23:22:30,900 INFO L244 HeapSepPreAnalysis]: Number of read from array group [#memory_int] : 7 [2018-01-28 23:22:30,901 INFO L238 apSepIcfgTransformer]: Finished pre analysis before partitioning [2018-01-28 23:22:30,901 INFO L239 apSepIcfgTransformer]: array groups: Set: [#memory_int] [2018-01-28 23:22:30,901 INFO L241 apSepIcfgTransformer]: select infos: Set: ((select (select |v_#memory_int_2| v_cstrcspn_~sc1~2.base_6) v_cstrcspn_~sc1~2.offset_5), at (SUMMARY for call #t~mem2 := read~int(~sc1~2.base, ~sc1~2.offset, 1); srcloc: L547)) ((select (select |v_#memory_int_5| v_cstrcspn_~s~2.base_11) v_cstrcspn_~s~2.offset_9), at (SUMMARY for call #t~mem7 := read~int(~s~2.base, ~s~2.offset, 1); srcloc: L548''''''''''''''')) ((select |v_#memory_int_11| v_main_~nondetString2~4.base_2), at (SUMMARY for call write~int(0, ~nondetString2~4.base, ~nondetString2~4.offset + (~length2~4 - 1) * 1, 1); srcloc: L566')) ((select |v_#memory_int_9| v_main_~nondetString1~4.base_2), at (SUMMARY for call write~int(0, ~nondetString1~4.base, ~nondetString1~4.offset + (~length1~4 - 1) * 1, 1); srcloc: L566)) ((select (select |v_#memory_int_1| v_cstrcspn_~sc1~2.base_3) v_cstrcspn_~sc1~2.offset_3), at (SUMMARY for call #t~mem1 := read~int(~sc1~2.base, ~sc1~2.offset, 1); srcloc: L545')) ((select (select |v_#memory_int_4| v_cstrcspn_~s~2.base_6) v_cstrcspn_~s~2.offset_5), at (SUMMARY for call #t~mem4 := read~int(~s~2.base, ~s~2.offset, 1); srcloc: L548''')) ((select (select |v_#memory_int_3| v_cstrcspn_~s~2.base_3) v_cstrcspn_~s~2.offset_3), at (SUMMARY for call #t~mem3 := read~int(~s~2.base, ~s~2.offset, 1); srcloc: L548)) [2018-01-28 23:22:30,923 INFO L544 PartitionManager]: partitioning result: [2018-01-28 23:22:30,924 INFO L549 PartitionManager]: location blocks for array group [#memory_int] [2018-01-28 23:22:30,924 INFO L558 PartitionManager]: at dimension 0 [2018-01-28 23:22:30,924 INFO L559 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 1 [2018-01-28 23:22:30,924 INFO L560 PartitionManager]: # location blocks :1 [2018-01-28 23:22:30,924 INFO L558 PartitionManager]: at dimension 1 [2018-01-28 23:22:30,924 INFO L559 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 1 [2018-01-28 23:22:30,924 INFO L560 PartitionManager]: # location blocks :1 [2018-01-28 23:22:30,925 INFO L86 ransitionTransformer]: executing heap partitioning transformation [2018-01-28 23:22:30,939 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 28.01 11:22:30 BasicIcfg [2018-01-28 23:22:30,940 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-01-28 23:22:30,940 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-28 23:22:30,940 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-28 23:22:30,999 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-28 23:22:30,999 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.01 11:21:52" (1/4) ... [2018-01-28 23:22:31,000 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@25764dcb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.01 11:22:31, skipping insertion in model container [2018-01-28 23:22:31,000 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.01 11:21:52" (2/4) ... [2018-01-28 23:22:31,000 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@25764dcb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.01 11:22:31, skipping insertion in model container [2018-01-28 23:22:31,001 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.01 11:21:52" (3/4) ... [2018-01-28 23:22:31,001 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@25764dcb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.01 11:22:31, skipping insertion in model container [2018-01-28 23:22:31,001 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 28.01 11:22:30" (4/4) ... [2018-01-28 23:22:31,003 INFO L107 eAbstractionObserver]: Analyzing ICFG HeapSeparatedIcfg [2018-01-28 23:22:31,012 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-28 23:22:31,020 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 15 error locations. [2018-01-28 23:22:31,051 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-28 23:22:31,051 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-28 23:22:31,051 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-28 23:22:31,051 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-28 23:22:31,052 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-28 23:22:31,052 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-28 23:22:31,052 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-28 23:22:31,052 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-28 23:22:31,052 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-28 23:22:31,063 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states. [2018-01-28 23:22:31,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-01-28 23:22:31,068 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 23:22:31,069 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 23:22:31,069 INFO L371 AbstractCegarLoop]: === Iteration 1 === [cstrcspnErr0RequiresViolation, cstrcspnErr9RequiresViolation, cstrcspnErr7RequiresViolation, cstrcspnErr4RequiresViolation, cstrcspnErr6RequiresViolation, cstrcspnErr5RequiresViolation, cstrcspnErr1RequiresViolation, cstrcspnErr3RequiresViolation, cstrcspnErr2RequiresViolation, cstrcspnErr8RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-01-28 23:22:31,072 INFO L82 PathProgramCache]: Analyzing trace with hash -1050940434, now seen corresponding path program 1 times [2018-01-28 23:22:31,073 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 23:22:31,074 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 23:22:31,113 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:31,114 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 23:22:31,114 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:31,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 23:22:31,175 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 23:22:31,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 23:22:31,300 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 23:22:31,300 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-28 23:22:31,302 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-28 23:22:31,315 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-28 23:22:31,316 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-28 23:22:31,318 INFO L87 Difference]: Start difference. First operand 91 states. Second operand 4 states. [2018-01-28 23:22:31,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 23:22:31,443 INFO L93 Difference]: Finished difference Result 149 states and 164 transitions. [2018-01-28 23:22:31,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-28 23:22:31,445 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2018-01-28 23:22:31,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 23:22:31,457 INFO L225 Difference]: With dead ends: 149 [2018-01-28 23:22:31,457 INFO L226 Difference]: Without dead ends: 87 [2018-01-28 23:22:31,461 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-28 23:22:31,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-01-28 23:22:31,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2018-01-28 23:22:31,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-01-28 23:22:31,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 94 transitions. [2018-01-28 23:22:31,502 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 94 transitions. Word has length 15 [2018-01-28 23:22:31,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 23:22:31,502 INFO L432 AbstractCegarLoop]: Abstraction has 87 states and 94 transitions. [2018-01-28 23:22:31,503 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-28 23:22:31,503 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 94 transitions. [2018-01-28 23:22:31,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-01-28 23:22:31,503 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 23:22:31,503 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 23:22:31,503 INFO L371 AbstractCegarLoop]: === Iteration 2 === [cstrcspnErr0RequiresViolation, cstrcspnErr9RequiresViolation, cstrcspnErr7RequiresViolation, cstrcspnErr4RequiresViolation, cstrcspnErr6RequiresViolation, cstrcspnErr5RequiresViolation, cstrcspnErr1RequiresViolation, cstrcspnErr3RequiresViolation, cstrcspnErr2RequiresViolation, cstrcspnErr8RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-01-28 23:22:31,504 INFO L82 PathProgramCache]: Analyzing trace with hash -1050940432, now seen corresponding path program 1 times [2018-01-28 23:22:31,504 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 23:22:31,504 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 23:22:31,505 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:31,505 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 23:22:31,505 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:31,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 23:22:31,518 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 23:22:31,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 23:22:31,657 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 23:22:31,657 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-28 23:22:31,659 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-28 23:22:31,659 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-28 23:22:31,659 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-28 23:22:31,659 INFO L87 Difference]: Start difference. First operand 87 states and 94 transitions. Second operand 6 states. [2018-01-28 23:22:31,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 23:22:31,748 INFO L93 Difference]: Finished difference Result 87 states and 94 transitions. [2018-01-28 23:22:31,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-28 23:22:31,749 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 15 [2018-01-28 23:22:31,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 23:22:31,750 INFO L225 Difference]: With dead ends: 87 [2018-01-28 23:22:31,751 INFO L226 Difference]: Without dead ends: 86 [2018-01-28 23:22:31,752 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-01-28 23:22:31,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states. [2018-01-28 23:22:31,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 86. [2018-01-28 23:22:31,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-01-28 23:22:31,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 93 transitions. [2018-01-28 23:22:31,760 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 93 transitions. Word has length 15 [2018-01-28 23:22:31,760 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 23:22:31,760 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 93 transitions. [2018-01-28 23:22:31,761 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-28 23:22:31,761 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 93 transitions. [2018-01-28 23:22:31,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-01-28 23:22:31,761 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 23:22:31,762 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 23:22:31,762 INFO L371 AbstractCegarLoop]: === Iteration 3 === [cstrcspnErr0RequiresViolation, cstrcspnErr9RequiresViolation, cstrcspnErr7RequiresViolation, cstrcspnErr4RequiresViolation, cstrcspnErr6RequiresViolation, cstrcspnErr5RequiresViolation, cstrcspnErr1RequiresViolation, cstrcspnErr3RequiresViolation, cstrcspnErr2RequiresViolation, cstrcspnErr8RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-01-28 23:22:31,762 INFO L82 PathProgramCache]: Analyzing trace with hash 1780585313, now seen corresponding path program 1 times [2018-01-28 23:22:31,762 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 23:22:31,762 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 23:22:31,763 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:31,764 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 23:22:31,764 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:31,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 23:22:31,775 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 23:22:31,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 23:22:31,818 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 23:22:31,818 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-28 23:22:31,818 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-28 23:22:31,818 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-28 23:22:31,819 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-28 23:22:31,819 INFO L87 Difference]: Start difference. First operand 86 states and 93 transitions. Second operand 4 states. [2018-01-28 23:22:31,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 23:22:31,910 INFO L93 Difference]: Finished difference Result 86 states and 93 transitions. [2018-01-28 23:22:31,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-28 23:22:31,911 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-01-28 23:22:31,912 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 23:22:31,913 INFO L225 Difference]: With dead ends: 86 [2018-01-28 23:22:31,913 INFO L226 Difference]: Without dead ends: 85 [2018-01-28 23:22:31,913 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-28 23:22:31,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-01-28 23:22:31,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-01-28 23:22:31,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-01-28 23:22:31,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 92 transitions. [2018-01-28 23:22:31,921 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 92 transitions. Word has length 16 [2018-01-28 23:22:31,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 23:22:31,921 INFO L432 AbstractCegarLoop]: Abstraction has 85 states and 92 transitions. [2018-01-28 23:22:31,922 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-28 23:22:31,922 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 92 transitions. [2018-01-28 23:22:31,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-01-28 23:22:31,922 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 23:22:31,922 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 23:22:31,923 INFO L371 AbstractCegarLoop]: === Iteration 4 === [cstrcspnErr0RequiresViolation, cstrcspnErr9RequiresViolation, cstrcspnErr7RequiresViolation, cstrcspnErr4RequiresViolation, cstrcspnErr6RequiresViolation, cstrcspnErr5RequiresViolation, cstrcspnErr1RequiresViolation, cstrcspnErr3RequiresViolation, cstrcspnErr2RequiresViolation, cstrcspnErr8RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-01-28 23:22:31,923 INFO L82 PathProgramCache]: Analyzing trace with hash 1780585315, now seen corresponding path program 1 times [2018-01-28 23:22:31,923 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 23:22:31,923 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 23:22:31,924 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:31,924 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 23:22:31,924 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:31,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 23:22:31,935 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 23:22:32,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 23:22:32,011 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 23:22:32,012 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-28 23:22:32,012 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-28 23:22:32,012 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-28 23:22:32,012 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-28 23:22:32,012 INFO L87 Difference]: Start difference. First operand 85 states and 92 transitions. Second operand 5 states. [2018-01-28 23:22:32,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 23:22:32,043 INFO L93 Difference]: Finished difference Result 85 states and 92 transitions. [2018-01-28 23:22:32,043 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-28 23:22:32,043 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-01-28 23:22:32,043 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 23:22:32,044 INFO L225 Difference]: With dead ends: 85 [2018-01-28 23:22:32,044 INFO L226 Difference]: Without dead ends: 84 [2018-01-28 23:22:32,044 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2018-01-28 23:22:32,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-01-28 23:22:32,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 84. [2018-01-28 23:22:32,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-01-28 23:22:32,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 91 transitions. [2018-01-28 23:22:32,050 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 91 transitions. Word has length 16 [2018-01-28 23:22:32,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 23:22:32,050 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 91 transitions. [2018-01-28 23:22:32,050 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-28 23:22:32,050 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 91 transitions. [2018-01-28 23:22:32,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-28 23:22:32,051 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 23:22:32,051 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 23:22:32,052 INFO L371 AbstractCegarLoop]: === Iteration 5 === [cstrcspnErr0RequiresViolation, cstrcspnErr9RequiresViolation, cstrcspnErr7RequiresViolation, cstrcspnErr4RequiresViolation, cstrcspnErr6RequiresViolation, cstrcspnErr5RequiresViolation, cstrcspnErr1RequiresViolation, cstrcspnErr3RequiresViolation, cstrcspnErr2RequiresViolation, cstrcspnErr8RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-01-28 23:22:32,052 INFO L82 PathProgramCache]: Analyzing trace with hash 1247887850, now seen corresponding path program 1 times [2018-01-28 23:22:32,052 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 23:22:32,052 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 23:22:32,053 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:32,053 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 23:22:32,053 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:32,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 23:22:32,065 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 23:22:32,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 23:22:32,096 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 23:22:32,096 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-28 23:22:32,096 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-28 23:22:32,096 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-28 23:22:32,096 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-28 23:22:32,096 INFO L87 Difference]: Start difference. First operand 84 states and 91 transitions. Second operand 6 states. [2018-01-28 23:22:32,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 23:22:32,222 INFO L93 Difference]: Finished difference Result 88 states and 95 transitions. [2018-01-28 23:22:32,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-28 23:22:32,223 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-01-28 23:22:32,223 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 23:22:32,224 INFO L225 Difference]: With dead ends: 88 [2018-01-28 23:22:32,224 INFO L226 Difference]: Without dead ends: 86 [2018-01-28 23:22:32,225 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-01-28 23:22:32,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states. [2018-01-28 23:22:32,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 85. [2018-01-28 23:22:32,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-01-28 23:22:32,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 93 transitions. [2018-01-28 23:22:32,230 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 93 transitions. Word has length 25 [2018-01-28 23:22:32,230 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 23:22:32,230 INFO L432 AbstractCegarLoop]: Abstraction has 85 states and 93 transitions. [2018-01-28 23:22:32,231 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-28 23:22:32,231 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 93 transitions. [2018-01-28 23:22:32,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-28 23:22:32,231 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 23:22:32,231 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 23:22:32,231 INFO L371 AbstractCegarLoop]: === Iteration 6 === [cstrcspnErr0RequiresViolation, cstrcspnErr9RequiresViolation, cstrcspnErr7RequiresViolation, cstrcspnErr4RequiresViolation, cstrcspnErr6RequiresViolation, cstrcspnErr5RequiresViolation, cstrcspnErr1RequiresViolation, cstrcspnErr3RequiresViolation, cstrcspnErr2RequiresViolation, cstrcspnErr8RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-01-28 23:22:32,232 INFO L82 PathProgramCache]: Analyzing trace with hash 1247887852, now seen corresponding path program 1 times [2018-01-28 23:22:32,232 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 23:22:32,232 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 23:22:32,232 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:32,233 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 23:22:32,233 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:32,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 23:22:32,245 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 23:22:32,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 23:22:32,411 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 23:22:32,411 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-01-28 23:22:32,411 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-28 23:22:32,411 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-28 23:22:32,411 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-01-28 23:22:32,412 INFO L87 Difference]: Start difference. First operand 85 states and 93 transitions. Second operand 9 states. [2018-01-28 23:22:32,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 23:22:32,596 INFO L93 Difference]: Finished difference Result 126 states and 137 transitions. [2018-01-28 23:22:32,597 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-28 23:22:32,597 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 25 [2018-01-28 23:22:32,597 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 23:22:32,600 INFO L225 Difference]: With dead ends: 126 [2018-01-28 23:22:32,600 INFO L226 Difference]: Without dead ends: 124 [2018-01-28 23:22:32,601 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-01-28 23:22:32,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-01-28 23:22:32,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 89. [2018-01-28 23:22:32,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-01-28 23:22:32,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 97 transitions. [2018-01-28 23:22:32,611 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 97 transitions. Word has length 25 [2018-01-28 23:22:32,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 23:22:32,611 INFO L432 AbstractCegarLoop]: Abstraction has 89 states and 97 transitions. [2018-01-28 23:22:32,611 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-28 23:22:32,611 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 97 transitions. [2018-01-28 23:22:32,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-28 23:22:32,612 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 23:22:32,613 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 23:22:32,613 INFO L371 AbstractCegarLoop]: === Iteration 7 === [cstrcspnErr0RequiresViolation, cstrcspnErr9RequiresViolation, cstrcspnErr7RequiresViolation, cstrcspnErr4RequiresViolation, cstrcspnErr6RequiresViolation, cstrcspnErr5RequiresViolation, cstrcspnErr1RequiresViolation, cstrcspnErr3RequiresViolation, cstrcspnErr2RequiresViolation, cstrcspnErr8RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-01-28 23:22:32,613 INFO L82 PathProgramCache]: Analyzing trace with hash -456998170, now seen corresponding path program 1 times [2018-01-28 23:22:32,613 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 23:22:32,613 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 23:22:32,614 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:32,614 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 23:22:32,614 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:32,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 23:22:32,627 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 23:22:32,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 23:22:32,735 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 23:22:32,735 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-28 23:22:32,735 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-28 23:22:32,735 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-28 23:22:32,735 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-28 23:22:32,736 INFO L87 Difference]: Start difference. First operand 89 states and 97 transitions. Second operand 6 states. [2018-01-28 23:22:32,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 23:22:32,890 INFO L93 Difference]: Finished difference Result 89 states and 97 transitions. [2018-01-28 23:22:32,891 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-28 23:22:32,891 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-01-28 23:22:32,891 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 23:22:32,892 INFO L225 Difference]: With dead ends: 89 [2018-01-28 23:22:32,892 INFO L226 Difference]: Without dead ends: 74 [2018-01-28 23:22:32,892 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-28 23:22:32,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-01-28 23:22:32,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 74. [2018-01-28 23:22:32,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-28 23:22:32,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 79 transitions. [2018-01-28 23:22:32,900 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 79 transitions. Word has length 25 [2018-01-28 23:22:32,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 23:22:32,900 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 79 transitions. [2018-01-28 23:22:32,900 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-28 23:22:32,900 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 79 transitions. [2018-01-28 23:22:32,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-01-28 23:22:32,901 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 23:22:32,901 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 23:22:32,902 INFO L371 AbstractCegarLoop]: === Iteration 8 === [cstrcspnErr0RequiresViolation, cstrcspnErr9RequiresViolation, cstrcspnErr7RequiresViolation, cstrcspnErr4RequiresViolation, cstrcspnErr6RequiresViolation, cstrcspnErr5RequiresViolation, cstrcspnErr1RequiresViolation, cstrcspnErr3RequiresViolation, cstrcspnErr2RequiresViolation, cstrcspnErr8RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-01-28 23:22:32,902 INFO L82 PathProgramCache]: Analyzing trace with hash 392251896, now seen corresponding path program 1 times [2018-01-28 23:22:32,902 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 23:22:32,902 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 23:22:32,903 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:32,903 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 23:22:32,903 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:32,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 23:22:32,915 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 23:22:32,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 23:22:32,974 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 23:22:32,974 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-28 23:22:32,974 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-28 23:22:32,975 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-28 23:22:32,975 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-28 23:22:32,975 INFO L87 Difference]: Start difference. First operand 74 states and 79 transitions. Second operand 6 states. [2018-01-28 23:22:33,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 23:22:33,062 INFO L93 Difference]: Finished difference Result 78 states and 83 transitions. [2018-01-28 23:22:33,062 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-28 23:22:33,062 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 33 [2018-01-28 23:22:33,062 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 23:22:33,063 INFO L225 Difference]: With dead ends: 78 [2018-01-28 23:22:33,063 INFO L226 Difference]: Without dead ends: 75 [2018-01-28 23:22:33,064 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-01-28 23:22:33,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-01-28 23:22:33,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 74. [2018-01-28 23:22:33,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-28 23:22:33,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 80 transitions. [2018-01-28 23:22:33,071 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 80 transitions. Word has length 33 [2018-01-28 23:22:33,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 23:22:33,071 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 80 transitions. [2018-01-28 23:22:33,071 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-28 23:22:33,071 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 80 transitions. [2018-01-28 23:22:33,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-01-28 23:22:33,072 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 23:22:33,072 INFO L330 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 23:22:33,072 INFO L371 AbstractCegarLoop]: === Iteration 9 === [cstrcspnErr0RequiresViolation, cstrcspnErr9RequiresViolation, cstrcspnErr7RequiresViolation, cstrcspnErr4RequiresViolation, cstrcspnErr6RequiresViolation, cstrcspnErr5RequiresViolation, cstrcspnErr1RequiresViolation, cstrcspnErr3RequiresViolation, cstrcspnErr2RequiresViolation, cstrcspnErr8RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-01-28 23:22:33,073 INFO L82 PathProgramCache]: Analyzing trace with hash 392251898, now seen corresponding path program 1 times [2018-01-28 23:22:33,073 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 23:22:33,073 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 23:22:33,074 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:33,074 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 23:22:33,074 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:33,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 23:22:33,085 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 23:22:33,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 23:22:33,179 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 23:22:33,179 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-01-28 23:22:33,179 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-28 23:22:33,180 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-28 23:22:33,180 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-01-28 23:22:33,180 INFO L87 Difference]: Start difference. First operand 74 states and 80 transitions. Second operand 9 states. [2018-01-28 23:22:33,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 23:22:33,263 INFO L93 Difference]: Finished difference Result 103 states and 110 transitions. [2018-01-28 23:22:33,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-28 23:22:33,264 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 33 [2018-01-28 23:22:33,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 23:22:33,264 INFO L225 Difference]: With dead ends: 103 [2018-01-28 23:22:33,264 INFO L226 Difference]: Without dead ends: 100 [2018-01-28 23:22:33,265 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2018-01-28 23:22:33,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-01-28 23:22:33,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 83. [2018-01-28 23:22:33,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2018-01-28 23:22:33,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 90 transitions. [2018-01-28 23:22:33,270 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 90 transitions. Word has length 33 [2018-01-28 23:22:33,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 23:22:33,270 INFO L432 AbstractCegarLoop]: Abstraction has 83 states and 90 transitions. [2018-01-28 23:22:33,270 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-28 23:22:33,270 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 90 transitions. [2018-01-28 23:22:33,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-28 23:22:33,271 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 23:22:33,271 INFO L330 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 23:22:33,271 INFO L371 AbstractCegarLoop]: === Iteration 10 === [cstrcspnErr0RequiresViolation, cstrcspnErr9RequiresViolation, cstrcspnErr7RequiresViolation, cstrcspnErr4RequiresViolation, cstrcspnErr6RequiresViolation, cstrcspnErr5RequiresViolation, cstrcspnErr1RequiresViolation, cstrcspnErr3RequiresViolation, cstrcspnErr2RequiresViolation, cstrcspnErr8RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-01-28 23:22:33,272 INFO L82 PathProgramCache]: Analyzing trace with hash -378168851, now seen corresponding path program 1 times [2018-01-28 23:22:33,272 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 23:22:33,272 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 23:22:33,272 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:33,272 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 23:22:33,272 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:33,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 23:22:33,281 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 23:22:33,301 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-28 23:22:33,301 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 23:22:33,301 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-28 23:22:33,301 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-28 23:22:33,302 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-28 23:22:33,302 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-28 23:22:33,302 INFO L87 Difference]: Start difference. First operand 83 states and 90 transitions. Second operand 3 states. [2018-01-28 23:22:33,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 23:22:33,316 INFO L93 Difference]: Finished difference Result 133 states and 146 transitions. [2018-01-28 23:22:33,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-28 23:22:33,317 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 44 [2018-01-28 23:22:33,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 23:22:33,318 INFO L225 Difference]: With dead ends: 133 [2018-01-28 23:22:33,318 INFO L226 Difference]: Without dead ends: 85 [2018-01-28 23:22:33,319 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-28 23:22:33,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-01-28 23:22:33,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-01-28 23:22:33,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-01-28 23:22:33,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 92 transitions. [2018-01-28 23:22:33,326 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 92 transitions. Word has length 44 [2018-01-28 23:22:33,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 23:22:33,327 INFO L432 AbstractCegarLoop]: Abstraction has 85 states and 92 transitions. [2018-01-28 23:22:33,327 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-28 23:22:33,327 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 92 transitions. [2018-01-28 23:22:33,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-01-28 23:22:33,328 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 23:22:33,329 INFO L330 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 23:22:33,329 INFO L371 AbstractCegarLoop]: === Iteration 11 === [cstrcspnErr0RequiresViolation, cstrcspnErr9RequiresViolation, cstrcspnErr7RequiresViolation, cstrcspnErr4RequiresViolation, cstrcspnErr6RequiresViolation, cstrcspnErr5RequiresViolation, cstrcspnErr1RequiresViolation, cstrcspnErr3RequiresViolation, cstrcspnErr2RequiresViolation, cstrcspnErr8RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-01-28 23:22:33,329 INFO L82 PathProgramCache]: Analyzing trace with hash 164873217, now seen corresponding path program 1 times [2018-01-28 23:22:33,329 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 23:22:33,329 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 23:22:33,330 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:33,331 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 23:22:33,331 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:33,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-28 23:22:33,346 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-28 23:22:33,406 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-28 23:22:33,407 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-28 23:22:33,407 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-28 23:22:33,407 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-28 23:22:33,407 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-28 23:22:33,407 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-28 23:22:33,408 INFO L87 Difference]: Start difference. First operand 85 states and 92 transitions. Second operand 7 states. [2018-01-28 23:22:33,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-28 23:22:33,487 INFO L93 Difference]: Finished difference Result 85 states and 92 transitions. [2018-01-28 23:22:33,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-28 23:22:33,488 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 46 [2018-01-28 23:22:33,488 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-28 23:22:33,489 INFO L225 Difference]: With dead ends: 85 [2018-01-28 23:22:33,489 INFO L226 Difference]: Without dead ends: 84 [2018-01-28 23:22:33,489 INFO L533 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2018-01-28 23:22:33,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-01-28 23:22:33,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 84. [2018-01-28 23:22:33,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-01-28 23:22:33,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 91 transitions. [2018-01-28 23:22:33,497 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 91 transitions. Word has length 46 [2018-01-28 23:22:33,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-28 23:22:33,497 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 91 transitions. [2018-01-28 23:22:33,497 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-28 23:22:33,497 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 91 transitions. [2018-01-28 23:22:33,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-01-28 23:22:33,499 INFO L322 BasicCegarLoop]: Found error trace [2018-01-28 23:22:33,499 INFO L330 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-28 23:22:33,499 INFO L371 AbstractCegarLoop]: === Iteration 12 === [cstrcspnErr0RequiresViolation, cstrcspnErr9RequiresViolation, cstrcspnErr7RequiresViolation, cstrcspnErr4RequiresViolation, cstrcspnErr6RequiresViolation, cstrcspnErr5RequiresViolation, cstrcspnErr1RequiresViolation, cstrcspnErr3RequiresViolation, cstrcspnErr2RequiresViolation, cstrcspnErr8RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-01-28 23:22:33,500 INFO L82 PathProgramCache]: Analyzing trace with hash 164873219, now seen corresponding path program 1 times [2018-01-28 23:22:33,500 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-28 23:22:33,500 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-28 23:22:33,501 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:33,501 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-28 23:22:33,501 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-28 23:22:33,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-01-28 23:22:33,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-01-28 23:22:33,555 INFO L389 BasicCegarLoop]: Counterexample might be feasible [2018-01-28 23:22:33,558 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] ULTIMATE.startENTRY-->L1: Formula: true InVars {} OutVars{#NULL.offset=|v_#NULL.offset_2|, #NULL.base=|v_#NULL.base_2|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[#valid, #NULL.offset, #NULL.base] [2018-01-28 23:22:33,558 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-28 23:22:33,559 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] mainENTRY-->L556: Formula: (and (<= 0 (+ |v_main_#t~nondet8_1| 2147483648)) (<= |v_main_#t~nondet8_1| 2147483647)) InVars {main_#t~nondet8=|v_main_#t~nondet8_1|} OutVars{main_#t~nondet8=|v_main_#t~nondet8_1|} AuxVars[] AssignedVars[] [2018-01-28 23:22:33,559 INFO L84 mationBacktranslator]: Skipped ATE [421] [421] L556-->L556': Formula: (= v_main_~length1~4_1 |v_main_#t~nondet8_2|) InVars {main_#t~nondet8=|v_main_#t~nondet8_2|} OutVars{main_#t~nondet8=|v_main_#t~nondet8_2|, main_~length1~4=v_main_~length1~4_1} AuxVars[] AssignedVars[main_~length1~4] [2018-01-28 23:22:33,559 INFO L84 mationBacktranslator]: Skipped ATE [425] [425] L556'-->L557: Formula: true InVars {} OutVars{main_#t~nondet8=|v_main_#t~nondet8_3|} AuxVars[] AssignedVars[main_#t~nondet8] [2018-01-28 23:22:33,559 INFO L84 mationBacktranslator]: Skipped ATE [427] [427] L557-->L557': Formula: (and (<= |v_main_#t~nondet9_1| 2147483647) (<= 0 (+ |v_main_#t~nondet9_1| 2147483648))) InVars {main_#t~nondet9=|v_main_#t~nondet9_1|} OutVars{main_#t~nondet9=|v_main_#t~nondet9_1|} AuxVars[] AssignedVars[] [2018-01-28 23:22:33,559 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L557'-->L557'': Formula: (= v_main_~length2~4_1 |v_main_#t~nondet9_2|) InVars {main_#t~nondet9=|v_main_#t~nondet9_2|} OutVars{main_#t~nondet9=|v_main_#t~nondet9_2|, main_~length2~4=v_main_~length2~4_1} AuxVars[] AssignedVars[main_~length2~4] [2018-01-28 23:22:33,559 INFO L84 mationBacktranslator]: Skipped ATE [431] [431] L557''-->L558: Formula: true InVars {} OutVars{main_#t~nondet9=|v_main_#t~nondet9_3|} AuxVars[] AssignedVars[main_#t~nondet9] [2018-01-28 23:22:33,559 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L558-->L558'': Formula: (not (< v_main_~length1~4_4 1)) InVars {main_~length1~4=v_main_~length1~4_4} OutVars{main_~length1~4=v_main_~length1~4_4} AuxVars[] AssignedVars[] [2018-01-28 23:22:33,560 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L558''-->L561': Formula: (not (< v_main_~length2~4_4 1)) InVars {main_~length2~4=v_main_~length2~4_4} OutVars{main_~length2~4=v_main_~length2~4_4} AuxVars[] AssignedVars[] [2018-01-28 23:22:33,560 INFO L84 mationBacktranslator]: Skipped ATE [445] [445] L561'-->L564: Formula: (and (= |v_#length_13| (store |v_#length_14| |v_main_#t~malloc10.base_1| v_main_~length1~4_5)) (= |v_#valid_17| (store |v_#valid_18| |v_main_#t~malloc10.base_1| 1)) (not (= 0 |v_main_#t~malloc10.base_1|)) (= |v_main_#t~malloc10.offset_1| 0) (= (select |v_#valid_18| |v_main_#t~malloc10.base_1|) 0)) InVars {#length=|v_#length_14|, main_~length1~4=v_main_~length1~4_5, #valid=|v_#valid_18|} OutVars{#length=|v_#length_13|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_1|, main_~length1~4=v_main_~length1~4_5, main_#t~malloc10.base=|v_main_#t~malloc10.base_1|, #valid=|v_#valid_17|} AuxVars[] AssignedVars[#valid, #length, main_#t~malloc10.offset, main_#t~malloc10.base] [2018-01-28 23:22:33,560 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L564-->L565: Formula: (and (= v_main_~nondetString1~4.base_1 |v_main_#t~malloc10.base_2|) (= v_main_~nondetString1~4.offset_1 |v_main_#t~malloc10.offset_2|)) InVars {main_#t~malloc10.base=|v_main_#t~malloc10.base_2|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_2|} OutVars{main_#t~malloc10.offset=|v_main_#t~malloc10.offset_2|, main_~nondetString1~4.offset=v_main_~nondetString1~4.offset_1, main_#t~malloc10.base=|v_main_#t~malloc10.base_2|, main_~nondetString1~4.base=v_main_~nondetString1~4.base_1} AuxVars[] AssignedVars[main_~nondetString1~4.base, main_~nondetString1~4.offset] [2018-01-28 23:22:33,560 INFO L84 mationBacktranslator]: Skipped ATE [449] [449] L565-->L565': Formula: (and (= |v_#valid_19| (store |v_#valid_20| |v_main_#t~malloc11.base_1| 1)) (= |v_main_#t~malloc11.offset_1| 0) (not (= |v_main_#t~malloc11.base_1| 0)) (= 0 (select |v_#valid_20| |v_main_#t~malloc11.base_1|)) (= |v_#length_15| (store |v_#length_16| |v_main_#t~malloc11.base_1| v_main_~length2~4_5))) InVars {main_~length2~4=v_main_~length2~4_5, #length=|v_#length_16|, #valid=|v_#valid_20|} OutVars{main_~length2~4=v_main_~length2~4_5, #length=|v_#length_15|, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_1|, main_#t~malloc11.base=|v_main_#t~malloc11.base_1|, #valid=|v_#valid_19|} AuxVars[] AssignedVars[#valid, #length, main_#t~malloc11.offset, main_#t~malloc11.base] [2018-01-28 23:22:33,560 INFO L84 mationBacktranslator]: Skipped ATE [451] [451] L565'-->L566: Formula: (and (= v_main_~nondetString2~4.base_1 |v_main_#t~malloc11.base_2|) (= v_main_~nondetString2~4.offset_1 |v_main_#t~malloc11.offset_2|)) InVars {main_#t~malloc11.base=|v_main_#t~malloc11.base_2|, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_2|} OutVars{main_~nondetString2~4.offset=v_main_~nondetString2~4.offset_1, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_2|, main_#t~malloc11.base=|v_main_#t~malloc11.base_2|, main_~nondetString2~4.base=v_main_~nondetString2~4.base_1} AuxVars[] AssignedVars[main_~nondetString2~4.offset, main_~nondetString2~4.base] [2018-01-28 23:22:33,560 INFO L84 mationBacktranslator]: Skipped ATE [453] [453] L566-->L566': Formula: (let ((.cse0 (+ v_main_~length1~4_6 v_main_~nondetString1~4.offset_2))) (and (= |v_#memory_int_part_locs_0_locs_0_1| |v_#memory_int_part_locs_0_locs_0_2|) (= (select |v_#valid_21| v_main_~nondetString1~4.base_2) 1) (<= 1 .cse0) (<= .cse0 (select |v_#length_17| v_main_~nondetString1~4.base_2)))) InVars {#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_2|, main_~length1~4=v_main_~length1~4_6, main_~nondetString1~4.base=v_main_~nondetString1~4.base_2, #valid=|v_#valid_21|, #length=|v_#length_17|, main_~nondetString1~4.offset=v_main_~nondetString1~4.offset_2} OutVars{#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_1|, main_~length1~4=v_main_~length1~4_6, main_~nondetString1~4.base=v_main_~nondetString1~4.base_2, #valid=|v_#valid_21|, #memory_int=|v_#memory_int_8|, #length=|v_#length_17|, main_~nondetString1~4.offset=v_main_~nondetString1~4.offset_2} AuxVars[] AssignedVars[#memory_int_part_locs_0_locs_0, #memory_int] [2018-01-28 23:22:33,561 INFO L84 mationBacktranslator]: Skipped ATE [459] [459] L566'-->L567: Formula: (let ((.cse0 (+ v_main_~nondetString2~4.offset_2 v_main_~length2~4_6))) (and (<= .cse0 (select |v_#length_19| v_main_~nondetString2~4.base_2)) (= 1 (select |v_#valid_23| v_main_~nondetString2~4.base_2)) (= |v_#memory_int_part_locs_0_locs_0_3| |v_#memory_int_part_locs_0_locs_0_4|) (<= 1 .cse0))) InVars {main_~nondetString2~4.offset=v_main_~nondetString2~4.offset_2, #memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_3|, #valid=|v_#valid_23|, main_~length2~4=v_main_~length2~4_6, #length=|v_#length_19|, main_~nondetString2~4.base=v_main_~nondetString2~4.base_2} OutVars{main_~nondetString2~4.offset=v_main_~nondetString2~4.offset_2, #memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_4|, #valid=|v_#valid_23|, #memory_int=|v_#memory_int_10|, main_~length2~4=v_main_~length2~4_6, #length=|v_#length_19|, main_~nondetString2~4.base=v_main_~nondetString2~4.base_2} AuxVars[] AssignedVars[#memory_int_part_locs_0_locs_0, #memory_int] [2018-01-28 23:22:33,561 INFO L84 mationBacktranslator]: Skipped ATE [467] [467] L567-->cstrcspnENTRY: Formula: (and (= |v_cstrcspn_#in~s2.offsetInParam_1| v_main_~nondetString2~4.offset_5) (= |v_cstrcspn_#in~s1.baseInParam_1| v_main_~nondetString1~4.base_6) (= |v_cstrcspn_#in~s1.offsetInParam_1| v_main_~nondetString1~4.offset_5) (= |v_cstrcspn_#in~s2.baseInParam_1| v_main_~nondetString2~4.base_6)) InVars {main_~nondetString2~4.offset=v_main_~nondetString2~4.offset_5, main_~nondetString1~4.offset=v_main_~nondetString1~4.offset_5, main_~nondetString1~4.base=v_main_~nondetString1~4.base_6, main_~nondetString2~4.base=v_main_~nondetString2~4.base_6} OutVars{cstrcspn_#in~s1.base=|v_cstrcspn_#in~s1.baseInParam_1|, cstrcspn_#in~s2.base=|v_cstrcspn_#in~s2.baseInParam_1|, cstrcspn_#in~s1.offset=|v_cstrcspn_#in~s1.offsetInParam_1|, cstrcspn_#in~s2.offset=|v_cstrcspn_#in~s2.offsetInParam_1|} AuxVars[] AssignedVars[cstrcspn_#in~s1.offset, cstrcspn_#in~s1.base, cstrcspn_#in~s2.base, cstrcspn_#in~s2.offset] [2018-01-28 23:22:33,561 INFO L84 mationBacktranslator]: Skipped ATE [471] [471] cstrcspnENTRY-->L540: Formula: (and (= v_cstrcspn_~s1.offset_1 |v_cstrcspn_#in~s1.offset_1|) (= v_cstrcspn_~s1.base_1 |v_cstrcspn_#in~s1.base_1|)) InVars {cstrcspn_#in~s1.base=|v_cstrcspn_#in~s1.base_1|, cstrcspn_#in~s1.offset=|v_cstrcspn_#in~s1.offset_1|} OutVars{cstrcspn_#in~s1.base=|v_cstrcspn_#in~s1.base_1|, cstrcspn_~s1.offset=v_cstrcspn_~s1.offset_1, cstrcspn_~s1.base=v_cstrcspn_~s1.base_1, cstrcspn_#in~s1.offset=|v_cstrcspn_#in~s1.offset_1|} AuxVars[] AssignedVars[cstrcspn_~s1.base, cstrcspn_~s1.offset] [2018-01-28 23:22:33,561 INFO L84 mationBacktranslator]: Skipped ATE [475] [475] L540-->L542: Formula: (and (= v_cstrcspn_~s2.offset_1 |v_cstrcspn_#in~s2.offset_1|) (= v_cstrcspn_~s2.base_1 |v_cstrcspn_#in~s2.base_1|)) InVars {cstrcspn_#in~s2.base=|v_cstrcspn_#in~s2.base_1|, cstrcspn_#in~s2.offset=|v_cstrcspn_#in~s2.offset_1|} OutVars{cstrcspn_#in~s2.base=|v_cstrcspn_#in~s2.base_1|, cstrcspn_~s2.offset=v_cstrcspn_~s2.offset_1, cstrcspn_~s2.base=v_cstrcspn_~s2.base_1, cstrcspn_#in~s2.offset=|v_cstrcspn_#in~s2.offset_1|} AuxVars[] AssignedVars[cstrcspn_~s2.offset, cstrcspn_~s2.base] [2018-01-28 23:22:33,561 INFO L84 mationBacktranslator]: Skipped ATE [479] [479] L542-->L543: Formula: true InVars {} OutVars{cstrcspn_~sc1~2.offset=v_cstrcspn_~sc1~2.offset_1, cstrcspn_~sc1~2.base=v_cstrcspn_~sc1~2.base_1} AuxVars[] AssignedVars[cstrcspn_~sc1~2.offset, cstrcspn_~sc1~2.base] [2018-01-28 23:22:33,561 INFO L84 mationBacktranslator]: Skipped ATE [483] [483] L543-->L544: Formula: true InVars {} OutVars{cstrcspn_~s~2.offset=v_cstrcspn_~s~2.offset_1, cstrcspn_~s~2.base=v_cstrcspn_~s~2.base_1} AuxVars[] AssignedVars[cstrcspn_~s~2.offset, cstrcspn_~s~2.base] [2018-01-28 23:22:33,562 INFO L84 mationBacktranslator]: Skipped ATE [487] [487] L544-->L545: Formula: true InVars {} OutVars{cstrcspn_~c~2=v_cstrcspn_~c~2_1} AuxVars[] AssignedVars[cstrcspn_~c~2] [2018-01-28 23:22:33,562 INFO L84 mationBacktranslator]: Skipped ATE [491] [491] L545-->L545''''''''': Formula: (and (= v_cstrcspn_~sc1~2.offset_2 v_cstrcspn_~s1.offset_2) (= v_cstrcspn_~sc1~2.base_2 v_cstrcspn_~s1.base_2)) InVars {cstrcspn_~s1.base=v_cstrcspn_~s1.base_2, cstrcspn_~s1.offset=v_cstrcspn_~s1.offset_2} OutVars{cstrcspn_~sc1~2.offset=v_cstrcspn_~sc1~2.offset_2, cstrcspn_~s1.offset=v_cstrcspn_~s1.offset_2, cstrcspn_~s1.base=v_cstrcspn_~s1.base_2, cstrcspn_~sc1~2.base=v_cstrcspn_~sc1~2.base_2} AuxVars[] AssignedVars[cstrcspn_~sc1~2.offset, cstrcspn_~sc1~2.base] [2018-01-28 23:22:33,562 INFO L84 mationBacktranslator]: Skipped ATE [495] [495] L545'''''''''-->L545': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-28 23:22:33,562 INFO L84 mationBacktranslator]: Skipped ATE [503] [503] L545'-->L545'': Formula: (and (<= (+ v_cstrcspn_~sc1~2.offset_3 1) (select |v_#length_1| v_cstrcspn_~sc1~2.base_3)) (<= 0 v_cstrcspn_~sc1~2.offset_3) (= (select (select |v_#memory_int_part_locs_0_locs_0_5| v_cstrcspn_~sc1~2.base_3) v_cstrcspn_~sc1~2.offset_3) |v_cstrcspn_#t~mem1_1|) (= (select |v_#valid_3| v_cstrcspn_~sc1~2.base_3) 1)) InVars {#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_5|, cstrcspn_~sc1~2.offset=v_cstrcspn_~sc1~2.offset_3, #length=|v_#length_1|, cstrcspn_~sc1~2.base=v_cstrcspn_~sc1~2.base_3, #valid=|v_#valid_3|} OutVars{cstrcspn_#t~mem1=|v_cstrcspn_#t~mem1_1|, #memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_5|, #valid=|v_#valid_3|, cstrcspn_~sc1~2.offset=v_cstrcspn_~sc1~2.offset_3, #length=|v_#length_1|, cstrcspn_~sc1~2.base=v_cstrcspn_~sc1~2.base_3} AuxVars[] AssignedVars[cstrcspn_#t~mem1] [2018-01-28 23:22:33,562 INFO L84 mationBacktranslator]: Skipped ATE [513] [513] L545''-->L545''''': Formula: (not (= 0 |v_cstrcspn_#t~mem1_4|)) InVars {cstrcspn_#t~mem1=|v_cstrcspn_#t~mem1_4|} OutVars{cstrcspn_#t~mem1=|v_cstrcspn_#t~mem1_4|} AuxVars[] AssignedVars[] [2018-01-28 23:22:33,562 INFO L84 mationBacktranslator]: Skipped ATE [519] [519] L545'''''-->L546: Formula: true InVars {} OutVars{cstrcspn_#t~mem1=|v_cstrcspn_#t~mem1_5|} AuxVars[] AssignedVars[cstrcspn_#t~mem1] [2018-01-28 23:22:33,563 INFO L84 mationBacktranslator]: Skipped ATE [521] [521] L546-->L547: Formula: (and (= v_cstrcspn_~s~2.offset_2 v_cstrcspn_~s2.offset_2) (= v_cstrcspn_~s~2.base_2 v_cstrcspn_~s2.base_2)) InVars {cstrcspn_~s2.base=v_cstrcspn_~s2.base_2, cstrcspn_~s2.offset=v_cstrcspn_~s2.offset_2} OutVars{cstrcspn_~s~2.base=v_cstrcspn_~s~2.base_2, cstrcspn_~s2.offset=v_cstrcspn_~s2.offset_2, cstrcspn_~s2.base=v_cstrcspn_~s2.base_2, cstrcspn_~s~2.offset=v_cstrcspn_~s~2.offset_2} AuxVars[] AssignedVars[cstrcspn_~s~2.offset, cstrcspn_~s~2.base] [2018-01-28 23:22:33,563 INFO L84 mationBacktranslator]: Skipped ATE [523] [523] L547-->L547': Formula: (and (= 1 (select |v_#valid_5| v_cstrcspn_~sc1~2.base_6)) (<= (+ v_cstrcspn_~sc1~2.offset_5 1) (select |v_#length_3| v_cstrcspn_~sc1~2.base_6)) (<= 0 v_cstrcspn_~sc1~2.offset_5) (= (select (select |v_#memory_int_part_locs_0_locs_0_6| v_cstrcspn_~sc1~2.base_6) v_cstrcspn_~sc1~2.offset_5) |v_cstrcspn_#t~mem2_1|)) InVars {#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_6|, cstrcspn_~sc1~2.offset=v_cstrcspn_~sc1~2.offset_5, #length=|v_#length_3|, cstrcspn_~sc1~2.base=v_cstrcspn_~sc1~2.base_6, #valid=|v_#valid_5|} OutVars{#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_6|, #valid=|v_#valid_5|, cstrcspn_~sc1~2.offset=v_cstrcspn_~sc1~2.offset_5, #length=|v_#length_3|, cstrcspn_~sc1~2.base=v_cstrcspn_~sc1~2.base_6, cstrcspn_#t~mem2=|v_cstrcspn_#t~mem2_1|} AuxVars[] AssignedVars[cstrcspn_#t~mem2] [2018-01-28 23:22:33,563 INFO L84 mationBacktranslator]: Skipped ATE [529] [529] L547'-->L547'': Formula: (= v_cstrcspn_~c~2_2 |v_cstrcspn_#t~mem2_2|) InVars {cstrcspn_#t~mem2=|v_cstrcspn_#t~mem2_2|} OutVars{cstrcspn_~c~2=v_cstrcspn_~c~2_2, cstrcspn_#t~mem2=|v_cstrcspn_#t~mem2_2|} AuxVars[] AssignedVars[cstrcspn_~c~2] [2018-01-28 23:22:33,563 INFO L84 mationBacktranslator]: Skipped ATE [531] [531] L547''-->L548'''''''''''''': Formula: true InVars {} OutVars{cstrcspn_#t~mem2=|v_cstrcspn_#t~mem2_3|} AuxVars[] AssignedVars[cstrcspn_#t~mem2] [2018-01-28 23:22:33,563 INFO L84 mationBacktranslator]: Skipped ATE [533] [533] L548''''''''''''''-->L548: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-28 23:22:33,563 INFO L84 mationBacktranslator]: Skipped ATE [537] [537] L548-->L548': Formula: (and (<= (+ v_cstrcspn_~s~2.offset_3 1) (select |v_#length_5| v_cstrcspn_~s~2.base_3)) (<= 0 v_cstrcspn_~s~2.offset_3) (= 1 (select |v_#valid_7| v_cstrcspn_~s~2.base_3)) (= |v_cstrcspn_#t~mem3_1| (select (select |v_#memory_int_part_locs_0_locs_0_7| v_cstrcspn_~s~2.base_3) v_cstrcspn_~s~2.offset_3))) InVars {#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_7|, cstrcspn_~s~2.base=v_cstrcspn_~s~2.base_3, #length=|v_#length_5|, cstrcspn_~s~2.offset=v_cstrcspn_~s~2.offset_3, #valid=|v_#valid_7|} OutVars{#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_7|, cstrcspn_~s~2.offset=v_cstrcspn_~s~2.offset_3, #valid=|v_#valid_7|, cstrcspn_~s~2.base=v_cstrcspn_~s~2.base_3, #length=|v_#length_5|, cstrcspn_#t~mem3=|v_cstrcspn_#t~mem3_1|} AuxVars[] AssignedVars[cstrcspn_#t~mem3] [2018-01-28 23:22:33,563 INFO L84 mationBacktranslator]: Skipped ATE [549] [549] L548'-->L548'': Formula: (let ((.cse0 (= 0 |v_cstrcspn_#t~mem3_2|))) (or (and |v_cstrcspn_#t~short5_1| (not .cse0)) (and (not |v_cstrcspn_#t~short5_1|) .cse0))) InVars {cstrcspn_#t~mem3=|v_cstrcspn_#t~mem3_2|} OutVars{cstrcspn_#t~short5=|v_cstrcspn_#t~short5_1|, cstrcspn_#t~mem3=|v_cstrcspn_#t~mem3_2|} AuxVars[] AssignedVars[cstrcspn_#t~short5] [2018-01-28 23:22:33,564 INFO L84 mationBacktranslator]: Skipped ATE [555] [555] L548''-->L548''': Formula: |v_cstrcspn_#t~short5_2| InVars {cstrcspn_#t~short5=|v_cstrcspn_#t~short5_2|} OutVars{cstrcspn_#t~short5=|v_cstrcspn_#t~short5_2|} AuxVars[] AssignedVars[] [2018-01-28 23:22:33,564 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L548'''-->L548'''': Formula: (and (= 1 (select |v_#valid_9| v_cstrcspn_~s~2.base_6)) (<= 0 v_cstrcspn_~s~2.offset_5) (= (select (select |v_#memory_int_part_locs_0_locs_0_9| v_cstrcspn_~s~2.base_6) v_cstrcspn_~s~2.offset_5) |v_cstrcspn_#t~mem4_1|) (<= (+ v_cstrcspn_~s~2.offset_5 1) (select |v_#length_7| v_cstrcspn_~s~2.base_6))) InVars {#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_9|, cstrcspn_~s~2.base=v_cstrcspn_~s~2.base_6, #length=|v_#length_7|, cstrcspn_~s~2.offset=v_cstrcspn_~s~2.offset_5, #valid=|v_#valid_9|} OutVars{#memory_int_part_locs_0_locs_0=|v_#memory_int_part_locs_0_locs_0_9|, cstrcspn_~s~2.offset=v_cstrcspn_~s~2.offset_5, #valid=|v_#valid_9|, cstrcspn_~s~2.base=v_cstrcspn_~s~2.base_6, #length=|v_#length_7|, cstrcspn_#t~mem4=|v_cstrcspn_#t~mem4_1|} AuxVars[] AssignedVars[cstrcspn_#t~mem4] [2018-01-28 23:22:33,564 INFO L84 mationBacktranslator]: Skipped ATE [577] [577] L548''''-->L548'''''': Formula: (let ((.cse0 (= (let ((.cse1 (mod v_cstrcspn_~c~2_3 256))) (ite (<= .cse1 127) .cse1 (+ .cse1 (- 256)))) |v_cstrcspn_#t~mem4_2|))) (or (and (not .cse0) |v_cstrcspn_#t~short5_3|) (and (not |v_cstrcspn_#t~short5_3|) .cse0))) InVars {cstrcspn_#t~mem4=|v_cstrcspn_#t~mem4_2|, cstrcspn_~c~2=v_cstrcspn_~c~2_3} OutVars{cstrcspn_#t~short5=|v_cstrcspn_#t~short5_3|, cstrcspn_#t~mem4=|v_cstrcspn_#t~mem4_2|, cstrcspn_~c~2=v_cstrcspn_~c~2_3} AuxVars[] AssignedVars[cstrcspn_#t~short5] [2018-01-28 23:22:33,564 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L548''''''-->L548''''''''''': Formula: |v_cstrcspn_#t~short5_7| InVars {cstrcspn_#t~short5=|v_cstrcspn_#t~short5_7|} OutVars{cstrcspn_#t~short5=|v_cstrcspn_#t~short5_7|} AuxVars[] AssignedVars[] [2018-01-28 23:22:33,564 INFO L84 mationBacktranslator]: Skipped ATE [581] [581] L548'''''''''''-->L548'''''''''''': Formula: true InVars {} OutVars{cstrcspn_#t~mem3=|v_cstrcspn_#t~mem3_4|} AuxVars[] AssignedVars[cstrcspn_#t~mem3] [2018-01-28 23:22:33,564 INFO L84 mationBacktranslator]: Skipped ATE [587] [587] L548''''''''''''-->L548''''''''''''': Formula: true InVars {} OutVars{cstrcspn_#t~mem4=|v_cstrcspn_#t~mem4_4|} AuxVars[] AssignedVars[cstrcspn_#t~mem4] [2018-01-28 23:22:33,564 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L548'''''''''''''-->L549: Formula: true InVars {} OutVars{cstrcspn_#t~short5=|v_cstrcspn_#t~short5_8|} AuxVars[] AssignedVars[cstrcspn_#t~short5] [2018-01-28 23:22:33,564 INFO L84 mationBacktranslator]: Skipped ATE [595] [595] L549-->L549': Formula: (and (= |v_cstrcspn_#t~post6.base_1| v_cstrcspn_~s~2.base_9) (= |v_cstrcspn_#t~post6.offset_1| v_cstrcspn_~s~2.offset_7)) InVars {cstrcspn_~s~2.offset=v_cstrcspn_~s~2.offset_7, cstrcspn_~s~2.base=v_cstrcspn_~s~2.base_9} OutVars{cstrcspn_#t~post6.base=|v_cstrcspn_#t~post6.base_1|, cstrcspn_~s~2.base=v_cstrcspn_~s~2.base_9, cstrcspn_#t~post6.offset=|v_cstrcspn_#t~post6.offset_1|, cstrcspn_~s~2.offset=v_cstrcspn_~s~2.offset_7} AuxVars[] AssignedVars[cstrcspn_#t~post6.base, cstrcspn_#t~post6.offset] [2018-01-28 23:22:33,564 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L549'-->L549'': Formula: (and (= v_cstrcspn_~s~2.offset_8 (+ |v_cstrcspn_#t~post6.offset_2| 1)) (= v_cstrcspn_~s~2.base_10 |v_cstrcspn_#t~post6.base_2|)) InVars {cstrcspn_#t~post6.offset=|v_cstrcspn_#t~post6.offset_2|, cstrcspn_#t~post6.base=|v_cstrcspn_#t~post6.base_2|} OutVars{cstrcspn_#t~post6.base=|v_cstrcspn_#t~post6.base_2|, cstrcspn_~s~2.base=v_cstrcspn_~s~2.base_10, cstrcspn_#t~post6.offset=|v_cstrcspn_#t~post6.offset_2|, cstrcspn_~s~2.offset=v_cstrcspn_~s~2.offset_8} AuxVars[] AssignedVars[cstrcspn_~s~2.offset, cstrcspn_~s~2.base] [2018-01-28 23:22:33,565 INFO L84 mationBacktranslator]: Skipped ATE [599] [599] L549''-->L548'''''''''''''': Formula: true InVars {} OutVars{cstrcspn_#t~post6.offset=|v_cstrcspn_#t~post6.offset_3|, cstrcspn_#t~post6.base=|v_cstrcspn_#t~post6.base_3|} AuxVars[] AssignedVars[cstrcspn_#t~post6.base, cstrcspn_#t~post6.offset] [2018-01-28 23:22:33,565 INFO L84 mationBacktranslator]: Skipped ATE [533] [533] L548''''''''''''''-->L548: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-28 23:22:33,565 INFO L84 mationBacktranslator]: Skipped ATE [541] [541] L548-->cstrcspnErr5RequiresViolation: Formula: (or (not (<= 0 v_cstrcspn_~s~2.offset_4)) (not (<= (+ v_cstrcspn_~s~2.offset_4 1) (select |v_#length_6| v_cstrcspn_~s~2.base_5)))) InVars {#length=|v_#length_6|, cstrcspn_~s~2.base=v_cstrcspn_~s~2.base_5, cstrcspn_~s~2.offset=v_cstrcspn_~s~2.offset_4} OutVars{#length=|v_#length_6|, cstrcspn_~s~2.base=v_cstrcspn_~s~2.base_5, cstrcspn_~s~2.offset=v_cstrcspn_~s~2.offset_4} AuxVars[] AssignedVars[] [2018-01-28 23:22:33,569 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.01 11:22:33 BasicIcfg [2018-01-28 23:22:33,569 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-28 23:22:33,570 INFO L168 Benchmark]: Toolchain (without parser) took 41466.37 ms. Allocated memory was 302.0 MB in the beginning and 2.2 GB in the end (delta: 1.9 GB). Free memory was 258.9 MB in the beginning and 1.9 GB in the end (delta: -1.6 GB). Peak memory consumption was 333.2 MB. Max. memory is 5.3 GB. [2018-01-28 23:22:33,570 INFO L168 Benchmark]: CDTParser took 0.21 ms. Allocated memory is still 302.0 MB. Free memory is still 264.8 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-28 23:22:33,570 INFO L168 Benchmark]: CACSL2BoogieTranslator took 198.87 ms. Allocated memory is still 302.0 MB. Free memory was 258.9 MB in the beginning and 248.9 MB in the end (delta: 10.0 MB). Peak memory consumption was 10.0 MB. Max. memory is 5.3 GB. [2018-01-28 23:22:33,571 INFO L168 Benchmark]: Boogie Preprocessor took 31.42 ms. Allocated memory is still 302.0 MB. Free memory was 248.9 MB in the beginning and 246.9 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-28 23:22:33,571 INFO L168 Benchmark]: RCFGBuilder took 334.37 ms. Allocated memory is still 302.0 MB. Free memory was 246.9 MB in the beginning and 224.0 MB in the end (delta: 23.0 MB). Peak memory consumption was 23.0 MB. Max. memory is 5.3 GB. [2018-01-28 23:22:33,571 INFO L168 Benchmark]: IcfgTransformer took 38265.45 ms. Allocated memory was 302.0 MB in the beginning and 2.2 GB in the end (delta: 1.9 GB). Free memory was 224.0 MB in the beginning and 971.6 MB in the end (delta: -747.6 MB). Peak memory consumption was 1.1 GB. Max. memory is 5.3 GB. [2018-01-28 23:22:33,572 INFO L168 Benchmark]: TraceAbstraction took 2628.87 ms. Allocated memory was 2.2 GB in the beginning and 2.2 GB in the end (delta: 89.7 MB). Free memory was 971.6 MB in the beginning and 1.9 GB in the end (delta: -896.0 MB). There was no memory consumed. Max. memory is 5.3 GB. [2018-01-28 23:22:33,573 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21 ms. Allocated memory is still 302.0 MB. Free memory is still 264.8 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 198.87 ms. Allocated memory is still 302.0 MB. Free memory was 258.9 MB in the beginning and 248.9 MB in the end (delta: 10.0 MB). Peak memory consumption was 10.0 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 31.42 ms. Allocated memory is still 302.0 MB. Free memory was 248.9 MB in the beginning and 246.9 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 334.37 ms. Allocated memory is still 302.0 MB. Free memory was 246.9 MB in the beginning and 224.0 MB in the end (delta: 23.0 MB). Peak memory consumption was 23.0 MB. Max. memory is 5.3 GB. * IcfgTransformer took 38265.45 ms. Allocated memory was 302.0 MB in the beginning and 2.2 GB in the end (delta: 1.9 GB). Free memory was 224.0 MB in the beginning and 971.6 MB in the end (delta: -747.6 MB). Peak memory consumption was 1.1 GB. Max. memory is 5.3 GB. * TraceAbstraction took 2628.87 ms. Allocated memory was 2.2 GB in the beginning and 2.2 GB in the end (delta: 89.7 MB). Free memory was 971.6 MB in the beginning and 1.9 GB in the end (delta: -896.0 MB). There was no memory consumed. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 83 LocStat_MAX_WEQGRAPH_SIZE : 5 LocStat_MAX_SIZEOF_WEQEDGELABEL : 3 LocStat_NO_SUPPORTING_EQUALITIES : 1483 LocStat_NO_SUPPORTING_DISEQUALITIES : 621 LocStat_NO_DISJUNCTIONS : -166 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 110 TransStat_MAX_WEQGRAPH_SIZE : 2 TransStat_MAX_SIZEOF_WEQEDGELABEL : 1 TransStat_NO_SUPPORTING_EQUALITIES : 128 TransStat_NO_SUPPORTING_DISEQUALITIES : 16 TransStat_NO_DISJUNCTIONS : 117 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 2.242806 RENAME_VARIABLES(MILLISECONDS) : 0.189610 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 1.071207 PROJECTAWAY(MILLISECONDS) : 0.021818 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.075158 DISJOIN(MILLISECONDS) : 0.271266 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.210159 ADD_EQUALITY(MILLISECONDS) : 0.030308 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.007475 #CONJOIN_DISJUNCTIVE : 1840 #RENAME_VARIABLES : 4012 #UNFREEZE : 0 #CONJOIN : 2373 #PROJECTAWAY : 2162 #ADD_WEAK_EQUALITY : 11 #DISJOIN : 376 #RENAME_VARIABLES_DISJUNCTIVE : 3863 #ADD_EQUALITY : 130 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 14 * Results from de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: - StatisticsResult: HeapSeparatorStatistics COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_0 : 1 COUNT_BLOCKS_for_[#memory_int]_at_dim_0 : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_1 : 1 COUNT_BLOCKS_for_[#memory_int]_at_dim_1 : 1 COUNT_ARRAY_READS for [#memory_int] : 7 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 1]: pointer dereference may fail pointer dereference may fail We found a FailurePath: - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 91 locations, 15 error locations. UNSAFE Result, 2.5s OverallTime, 12 OverallIterations, 2 TraceHistogramMax, 1.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 810 SDtfs, 985 SDslu, 1404 SDs, 0 SdLazy, 771 SolverSat, 46 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 80 GetRequests, 15 SyntacticMatches, 1 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=91occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 11 MinimizatonAttempts, 54 StatesRemovedByMinimization, 4 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.1s SatisfiabilityAnalysisTime, 0.9s InterpolantComputationTime, 339 NumberOfCodeBlocks, 339 NumberOfCodeBlocksAsserted, 12 NumberOfCheckSat, 282 ConstructedInterpolants, 0 QuantifiedInterpolants, 32152 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 11 InterpolantComputations, 11 PerfectInterpolantSequences, 4/4 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcspn-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-01-28_23-22-33-581.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcspn-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-VPDomainBenchmark-0-2018-01-28_23-22-33-581.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcspn-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-0-2018-01-28_23-22-33-581.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcspn-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-HeapSeparatorBenchmark-0-2018-01-28_23-22-33-581.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcspn-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-28_23-22-33-581.csv Received shutdown request...