java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_1_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 12:29:49,289 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 12:29:49,290 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 12:29:49,305 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 12:29:49,305 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 12:29:49,306 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 12:29:49,307 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 12:29:49,308 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 12:29:49,310 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 12:29:49,311 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 12:29:49,311 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 12:29:49,311 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 12:29:49,312 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 12:29:49,313 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 12:29:49,314 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 12:29:49,317 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 12:29:49,319 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 12:29:49,321 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 12:29:49,323 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 12:29:49,324 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 12:29:49,326 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 12:29:49,327 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 12:29:49,327 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 12:29:49,328 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 12:29:49,329 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 12:29:49,330 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 12:29:49,330 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 12:29:49,331 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 12:29:49,331 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 12:29:49,331 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 12:29:49,332 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 12:29:49,333 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ.epf [2018-01-24 12:29:49,343 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 12:29:49,343 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 12:29:49,344 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 12:29:49,344 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 12:29:49,345 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 12:29:49,345 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 12:29:49,345 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 12:29:49,346 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 12:29:49,346 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 12:29:49,346 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 12:29:49,346 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 12:29:49,346 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 12:29:49,347 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 12:29:49,347 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 12:29:49,347 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 12:29:49,347 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 12:29:49,347 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 12:29:49,348 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 12:29:49,348 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 12:29:49,348 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 12:29:49,348 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 12:29:49,349 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 12:29:49,349 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 12:29:49,349 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 12:29:49,349 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 12:29:49,349 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 12:29:49,350 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 12:29:49,350 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 12:29:49,350 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-24 12:29:49,350 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 12:29:49,350 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 12:29:49,351 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 12:29:49,352 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 12:29:49,352 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 12:29:49,388 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 12:29:49,400 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 12:29:49,404 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 12:29:49,406 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 12:29:49,407 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 12:29:49,407 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_1_true-valid-memsafety_true-termination.i [2018-01-24 12:29:49,614 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 12:29:49,620 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 12:29:49,621 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 12:29:49,621 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 12:29:49,627 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 12:29:49,628 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 12:29:49" (1/1) ... [2018-01-24 12:29:49,632 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5d434187 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:29:49, skipping insertion in model container [2018-01-24 12:29:49,632 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 12:29:49" (1/1) ... [2018-01-24 12:29:49,652 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 12:29:49,705 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 12:29:49,835 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 12:29:49,857 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 12:29:49,869 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:29:49 WrapperNode [2018-01-24 12:29:49,869 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 12:29:49,870 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 12:29:49,870 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 12:29:49,870 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 12:29:49,887 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:29:49" (1/1) ... [2018-01-24 12:29:49,887 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:29:49" (1/1) ... [2018-01-24 12:29:49,902 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:29:49" (1/1) ... [2018-01-24 12:29:49,903 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:29:49" (1/1) ... [2018-01-24 12:29:49,910 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:29:49" (1/1) ... [2018-01-24 12:29:49,914 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:29:49" (1/1) ... [2018-01-24 12:29:49,916 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:29:49" (1/1) ... [2018-01-24 12:29:49,919 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 12:29:49,919 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 12:29:49,919 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 12:29:49,920 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 12:29:49,921 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:29:49" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 12:29:49,978 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 12:29:49,979 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 12:29:49,979 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2018-01-24 12:29:49,979 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-01-24 12:29:49,979 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-01-24 12:29:49,979 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_atomic_sub_return [2018-01-24 12:29:49,979 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_sub [2018-01-24 12:29:49,979 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-01-24 12:29:49,980 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_put [2018-01-24 12:29:49,980 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-01-24 12:29:49,980 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-01-24 12:29:49,980 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_put [2018-01-24 12:29:49,980 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-01-24 12:29:49,980 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-01-24 12:29:49,981 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-01-24 12:29:49,981 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-01-24 12:29:49,981 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 12:29:49,981 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-01-24 12:29:49,981 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-01-24 12:29:49,981 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 12:29:49,981 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 12:29:49,982 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 12:29:49,982 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 12:29:49,982 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 12:29:49,982 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-01-24 12:29:49,982 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-01-24 12:29:49,982 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-01-24 12:29:49,983 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-01-24 12:29:49,983 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 12:29:49,983 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-01-24 12:29:49,983 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-01-24 12:29:49,983 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-01-24 12:29:49,983 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_atomic_sub_return [2018-01-24 12:29:49,984 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_sub [2018-01-24 12:29:49,984 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2018-01-24 12:29:49,984 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-01-24 12:29:49,984 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_put [2018-01-24 12:29:49,984 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-01-24 12:29:49,984 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-01-24 12:29:49,984 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_put [2018-01-24 12:29:49,984 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-01-24 12:29:49,985 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-01-24 12:29:49,985 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-01-24 12:29:49,985 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-01-24 12:29:49,985 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 12:29:49,985 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 12:29:49,985 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 12:29:50,263 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-01-24 12:29:50,388 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 12:29:50,388 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 12:29:50 BoogieIcfgContainer [2018-01-24 12:29:50,389 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 12:29:50,389 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 12:29:50,390 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 12:29:50,391 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 12:29:50,392 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 12:29:49" (1/3) ... [2018-01-24 12:29:50,393 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@a1ea8b1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 12:29:50, skipping insertion in model container [2018-01-24 12:29:50,393 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:29:49" (2/3) ... [2018-01-24 12:29:50,393 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@a1ea8b1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 12:29:50, skipping insertion in model container [2018-01-24 12:29:50,393 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 12:29:50" (3/3) ... [2018-01-24 12:29:50,395 INFO L105 eAbstractionObserver]: Analyzing ICFG memleaks_test22_1_true-valid-memsafety_true-termination.i [2018-01-24 12:29:50,402 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 12:29:50,409 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 19 error locations. [2018-01-24 12:29:50,452 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 12:29:50,452 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 12:29:50,452 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 12:29:50,452 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 12:29:50,452 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 12:29:50,453 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 12:29:50,453 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 12:29:50,453 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 12:29:50,453 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 12:29:50,473 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states. [2018-01-24 12:29:50,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 12:29:50,481 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:50,483 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:50,483 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:50,488 INFO L82 PathProgramCache]: Analyzing trace with hash -401333144, now seen corresponding path program 1 times [2018-01-24 12:29:50,489 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:50,490 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:50,543 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:50,543 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:50,543 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:50,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:50,602 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:50,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:50,752 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:29:50,752 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 12:29:50,754 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 12:29:50,842 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 12:29:50,843 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 12:29:50,935 INFO L87 Difference]: Start difference. First operand 118 states. Second operand 5 states. [2018-01-24 12:29:51,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:29:51,009 INFO L93 Difference]: Finished difference Result 224 states and 237 transitions. [2018-01-24 12:29:51,010 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 12:29:51,012 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 12:29:51,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:29:51,030 INFO L225 Difference]: With dead ends: 224 [2018-01-24 12:29:51,030 INFO L226 Difference]: Without dead ends: 121 [2018-01-24 12:29:51,035 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 12:29:51,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-01-24 12:29:51,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 119. [2018-01-24 12:29:51,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-01-24 12:29:51,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 126 transitions. [2018-01-24 12:29:51,076 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 126 transitions. Word has length 17 [2018-01-24 12:29:51,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:29:51,077 INFO L432 AbstractCegarLoop]: Abstraction has 119 states and 126 transitions. [2018-01-24 12:29:51,077 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 12:29:51,077 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 126 transitions. [2018-01-24 12:29:51,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-24 12:29:51,077 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:51,078 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:51,078 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:51,078 INFO L82 PathProgramCache]: Analyzing trace with hash 1306365930, now seen corresponding path program 1 times [2018-01-24 12:29:51,078 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:51,078 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:51,079 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:51,079 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:51,080 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:51,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:51,106 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:51,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:51,192 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:29:51,192 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 12:29:51,193 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 12:29:51,193 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 12:29:51,193 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 12:29:51,194 INFO L87 Difference]: Start difference. First operand 119 states and 126 transitions. Second operand 6 states. [2018-01-24 12:29:51,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:29:51,376 INFO L93 Difference]: Finished difference Result 121 states and 128 transitions. [2018-01-24 12:29:51,377 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 12:29:51,377 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2018-01-24 12:29:51,377 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:29:51,378 INFO L225 Difference]: With dead ends: 121 [2018-01-24 12:29:51,378 INFO L226 Difference]: Without dead ends: 120 [2018-01-24 12:29:51,379 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 12:29:51,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-01-24 12:29:51,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 118. [2018-01-24 12:29:51,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-24 12:29:51,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 125 transitions. [2018-01-24 12:29:51,388 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 125 transitions. Word has length 19 [2018-01-24 12:29:51,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:29:51,389 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 125 transitions. [2018-01-24 12:29:51,389 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 12:29:51,389 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 125 transitions. [2018-01-24 12:29:51,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-24 12:29:51,389 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:51,389 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:51,390 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:51,390 INFO L82 PathProgramCache]: Analyzing trace with hash 1306365931, now seen corresponding path program 1 times [2018-01-24 12:29:51,390 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:51,390 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:51,391 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:51,392 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:51,392 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:51,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:51,415 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:51,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:51,682 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:29:51,682 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 12:29:51,683 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 12:29:51,683 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 12:29:51,683 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-24 12:29:51,683 INFO L87 Difference]: Start difference. First operand 118 states and 125 transitions. Second operand 7 states. [2018-01-24 12:29:51,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:29:51,897 INFO L93 Difference]: Finished difference Result 120 states and 127 transitions. [2018-01-24 12:29:51,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 12:29:51,897 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-01-24 12:29:51,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:29:51,902 INFO L225 Difference]: With dead ends: 120 [2018-01-24 12:29:51,902 INFO L226 Difference]: Without dead ends: 119 [2018-01-24 12:29:51,902 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-01-24 12:29:51,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-01-24 12:29:51,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 117. [2018-01-24 12:29:51,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-01-24 12:29:51,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 124 transitions. [2018-01-24 12:29:51,917 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 124 transitions. Word has length 19 [2018-01-24 12:29:51,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:29:51,917 INFO L432 AbstractCegarLoop]: Abstraction has 117 states and 124 transitions. [2018-01-24 12:29:51,917 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 12:29:51,917 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 124 transitions. [2018-01-24 12:29:51,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-01-24 12:29:51,919 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:51,919 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:51,919 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:51,919 INFO L82 PathProgramCache]: Analyzing trace with hash -860603530, now seen corresponding path program 1 times [2018-01-24 12:29:51,920 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:51,920 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:51,922 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:51,922 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:51,922 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:51,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:51,947 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:52,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:52,033 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:29:52,033 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-01-24 12:29:52,033 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 12:29:52,034 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 12:29:52,034 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-24 12:29:52,034 INFO L87 Difference]: Start difference. First operand 117 states and 124 transitions. Second operand 7 states. [2018-01-24 12:29:52,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:29:52,091 INFO L93 Difference]: Finished difference Result 183 states and 192 transitions. [2018-01-24 12:29:52,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 12:29:52,091 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 29 [2018-01-24 12:29:52,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:29:52,093 INFO L225 Difference]: With dead ends: 183 [2018-01-24 12:29:52,094 INFO L226 Difference]: Without dead ends: 129 [2018-01-24 12:29:52,095 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-01-24 12:29:52,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2018-01-24 12:29:52,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 125. [2018-01-24 12:29:52,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-01-24 12:29:52,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 132 transitions. [2018-01-24 12:29:52,111 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 132 transitions. Word has length 29 [2018-01-24 12:29:52,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:29:52,111 INFO L432 AbstractCegarLoop]: Abstraction has 125 states and 132 transitions. [2018-01-24 12:29:52,111 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 12:29:52,112 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 132 transitions. [2018-01-24 12:29:52,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 12:29:52,113 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:52,113 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:52,113 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:52,114 INFO L82 PathProgramCache]: Analyzing trace with hash 23284980, now seen corresponding path program 1 times [2018-01-24 12:29:52,114 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:52,114 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:52,115 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:52,116 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:52,116 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:52,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:52,129 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:52,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:52,164 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:29:52,165 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 12:29:52,165 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 12:29:52,165 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 12:29:52,166 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 12:29:52,166 INFO L87 Difference]: Start difference. First operand 125 states and 132 transitions. Second operand 3 states. [2018-01-24 12:29:52,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:29:52,280 INFO L93 Difference]: Finished difference Result 141 states and 148 transitions. [2018-01-24 12:29:52,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 12:29:52,280 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2018-01-24 12:29:52,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:29:52,281 INFO L225 Difference]: With dead ends: 141 [2018-01-24 12:29:52,282 INFO L226 Difference]: Without dead ends: 129 [2018-01-24 12:29:52,282 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 12:29:52,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2018-01-24 12:29:52,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 121. [2018-01-24 12:29:52,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2018-01-24 12:29:52,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 127 transitions. [2018-01-24 12:29:52,296 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 127 transitions. Word has length 27 [2018-01-24 12:29:52,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:29:52,297 INFO L432 AbstractCegarLoop]: Abstraction has 121 states and 127 transitions. [2018-01-24 12:29:52,297 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 12:29:52,297 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 127 transitions. [2018-01-24 12:29:52,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-01-24 12:29:52,298 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:52,298 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:52,298 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:52,298 INFO L82 PathProgramCache]: Analyzing trace with hash -1295663626, now seen corresponding path program 1 times [2018-01-24 12:29:52,299 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:52,299 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:52,300 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:52,300 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:52,300 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:52,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:52,311 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:52,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:52,374 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:29:52,374 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 12:29:52,374 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 12:29:52,374 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 12:29:52,375 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 12:29:52,375 INFO L87 Difference]: Start difference. First operand 121 states and 127 transitions. Second operand 6 states. [2018-01-24 12:29:52,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:29:52,420 INFO L93 Difference]: Finished difference Result 125 states and 130 transitions. [2018-01-24 12:29:52,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 12:29:52,420 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 29 [2018-01-24 12:29:52,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:29:52,422 INFO L225 Difference]: With dead ends: 125 [2018-01-24 12:29:52,422 INFO L226 Difference]: Without dead ends: 113 [2018-01-24 12:29:52,422 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 12:29:52,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-01-24 12:29:52,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-01-24 12:29:52,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-01-24 12:29:52,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 118 transitions. [2018-01-24 12:29:52,433 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 118 transitions. Word has length 29 [2018-01-24 12:29:52,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:29:52,433 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 118 transitions. [2018-01-24 12:29:52,434 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 12:29:52,434 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 118 transitions. [2018-01-24 12:29:52,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-24 12:29:52,435 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:52,435 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:52,435 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:52,435 INFO L82 PathProgramCache]: Analyzing trace with hash 522747174, now seen corresponding path program 1 times [2018-01-24 12:29:52,435 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:52,436 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:52,437 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:52,437 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:52,437 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:52,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:52,455 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:52,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:52,489 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:29:52,489 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 12:29:52,490 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 12:29:52,490 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 12:29:52,490 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 12:29:52,490 INFO L87 Difference]: Start difference. First operand 113 states and 118 transitions. Second operand 4 states. [2018-01-24 12:29:52,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:29:52,523 INFO L93 Difference]: Finished difference Result 205 states and 215 transitions. [2018-01-24 12:29:52,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 12:29:52,524 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2018-01-24 12:29:52,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:29:52,525 INFO L225 Difference]: With dead ends: 205 [2018-01-24 12:29:52,525 INFO L226 Difference]: Without dead ends: 114 [2018-01-24 12:29:52,526 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 12:29:52,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-01-24 12:29:52,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. [2018-01-24 12:29:52,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-01-24 12:29:52,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 119 transitions. [2018-01-24 12:29:52,536 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 119 transitions. Word has length 34 [2018-01-24 12:29:52,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:29:52,536 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 119 transitions. [2018-01-24 12:29:52,537 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 12:29:52,537 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 119 transitions. [2018-01-24 12:29:52,538 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-01-24 12:29:52,538 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:52,538 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:52,538 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:52,538 INFO L82 PathProgramCache]: Analyzing trace with hash -1305776369, now seen corresponding path program 1 times [2018-01-24 12:29:52,538 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:52,539 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:52,540 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:52,540 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:52,540 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:52,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:52,558 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:52,610 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:52,610 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:29:52,610 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:29:52,621 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:52,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:52,678 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:29:52,708 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:52,743 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-24 12:29:52,743 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2018-01-24 12:29:52,744 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 12:29:52,744 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 12:29:52,744 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-01-24 12:29:52,744 INFO L87 Difference]: Start difference. First operand 114 states and 119 transitions. Second operand 6 states. [2018-01-24 12:29:52,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:29:52,807 INFO L93 Difference]: Finished difference Result 206 states and 216 transitions. [2018-01-24 12:29:52,808 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 12:29:52,808 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-01-24 12:29:52,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:29:52,809 INFO L225 Difference]: With dead ends: 206 [2018-01-24 12:29:52,809 INFO L226 Difference]: Without dead ends: 115 [2018-01-24 12:29:52,810 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 12:29:52,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-01-24 12:29:52,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-01-24 12:29:52,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-01-24 12:29:52,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 120 transitions. [2018-01-24 12:29:52,820 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 120 transitions. Word has length 35 [2018-01-24 12:29:52,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:29:52,820 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 120 transitions. [2018-01-24 12:29:52,820 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 12:29:52,820 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 120 transitions. [2018-01-24 12:29:52,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-24 12:29:52,822 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:52,822 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:52,822 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:52,822 INFO L82 PathProgramCache]: Analyzing trace with hash 2139535942, now seen corresponding path program 2 times [2018-01-24 12:29:52,822 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:52,822 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:52,824 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:52,824 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:52,824 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:52,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:52,842 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:52,893 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:52,893 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:29:52,893 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:29:52,902 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:29:52,932 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:29:52,935 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:29:52,939 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:29:52,971 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 12:29:52,973 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:29:53,034 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 12:29:53,034 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:29:53,050 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 12:29:53,051 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 12:29:53,757 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 12:29:53,784 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-24 12:29:53,784 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [14] imperfect sequences [6] total 19 [2018-01-24 12:29:53,784 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 12:29:53,784 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 12:29:53,785 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=291, Unknown=0, NotChecked=0, Total=342 [2018-01-24 12:29:53,785 INFO L87 Difference]: Start difference. First operand 115 states and 120 transitions. Second operand 19 states. [2018-01-24 12:29:56,859 WARN L143 SmtUtils]: Spent 2778ms on a formula simplification that was a NOOP. DAG size: 32 [2018-01-24 12:29:57,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:29:57,498 INFO L93 Difference]: Finished difference Result 206 states and 217 transitions. [2018-01-24 12:29:57,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 12:29:57,498 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 36 [2018-01-24 12:29:57,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:29:57,499 INFO L225 Difference]: With dead ends: 206 [2018-01-24 12:29:57,499 INFO L226 Difference]: Without dead ends: 115 [2018-01-24 12:29:57,500 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 78 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=99, Invalid=603, Unknown=0, NotChecked=0, Total=702 [2018-01-24 12:29:57,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-01-24 12:29:57,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-01-24 12:29:57,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-01-24 12:29:57,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 120 transitions. [2018-01-24 12:29:57,512 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 120 transitions. Word has length 36 [2018-01-24 12:29:57,513 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:29:57,513 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 120 transitions. [2018-01-24 12:29:57,513 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 12:29:57,513 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 120 transitions. [2018-01-24 12:29:57,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 12:29:57,514 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:57,514 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:57,514 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:57,514 INFO L82 PathProgramCache]: Analyzing trace with hash 1570035182, now seen corresponding path program 1 times [2018-01-24 12:29:57,514 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:57,514 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:57,515 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:57,515 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:29:57,515 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:57,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:57,530 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:57,634 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 12:29:57,634 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:29:57,635 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-01-24 12:29:57,635 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 12:29:57,635 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 12:29:57,636 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 12:29:57,636 INFO L87 Difference]: Start difference. First operand 115 states and 120 transitions. Second operand 10 states. [2018-01-24 12:29:57,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:29:57,879 INFO L93 Difference]: Finished difference Result 115 states and 120 transitions. [2018-01-24 12:29:57,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 12:29:57,880 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 37 [2018-01-24 12:29:57,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:29:57,881 INFO L225 Difference]: With dead ends: 115 [2018-01-24 12:29:57,881 INFO L226 Difference]: Without dead ends: 114 [2018-01-24 12:29:57,882 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 12:29:57,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-01-24 12:29:57,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. [2018-01-24 12:29:57,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-01-24 12:29:57,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 119 transitions. [2018-01-24 12:29:57,899 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 119 transitions. Word has length 37 [2018-01-24 12:29:57,899 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:29:57,899 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 119 transitions. [2018-01-24 12:29:57,899 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 12:29:57,899 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 119 transitions. [2018-01-24 12:29:57,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 12:29:57,900 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:57,900 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:57,900 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:57,900 INFO L82 PathProgramCache]: Analyzing trace with hash 258949559, now seen corresponding path program 1 times [2018-01-24 12:29:57,900 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:57,900 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:57,901 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:57,901 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:57,901 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:57,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:57,916 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:58,005 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 12:29:58,005 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:29:58,005 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-01-24 12:29:58,006 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 12:29:58,006 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 12:29:58,006 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 12:29:58,006 INFO L87 Difference]: Start difference. First operand 114 states and 119 transitions. Second operand 10 states. [2018-01-24 12:29:58,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:29:58,291 INFO L93 Difference]: Finished difference Result 114 states and 119 transitions. [2018-01-24 12:29:58,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 12:29:58,291 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-01-24 12:29:58,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:29:58,293 INFO L225 Difference]: With dead ends: 114 [2018-01-24 12:29:58,293 INFO L226 Difference]: Without dead ends: 112 [2018-01-24 12:29:58,293 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 12:29:58,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-01-24 12:29:58,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-01-24 12:29:58,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-01-24 12:29:58,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 117 transitions. [2018-01-24 12:29:58,308 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 117 transitions. Word has length 42 [2018-01-24 12:29:58,309 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:29:58,309 INFO L432 AbstractCegarLoop]: Abstraction has 112 states and 117 transitions. [2018-01-24 12:29:58,309 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 12:29:58,309 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 117 transitions. [2018-01-24 12:29:58,310 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 12:29:58,310 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:58,310 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:58,310 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:58,311 INFO L82 PathProgramCache]: Analyzing trace with hash 258949560, now seen corresponding path program 1 times [2018-01-24 12:29:58,311 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:58,311 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:58,312 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:58,312 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:58,312 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:58,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:58,330 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:58,388 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:58,388 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:29:58,388 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:29:58,395 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:58,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:58,419 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:29:58,429 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:58,449 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-24 12:29:58,449 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2018-01-24 12:29:58,450 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 12:29:58,450 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 12:29:58,450 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-01-24 12:29:58,450 INFO L87 Difference]: Start difference. First operand 112 states and 117 transitions. Second operand 8 states. [2018-01-24 12:29:58,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:29:58,516 INFO L93 Difference]: Finished difference Result 200 states and 210 transitions. [2018-01-24 12:29:58,516 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 12:29:58,516 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 42 [2018-01-24 12:29:58,516 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:29:58,517 INFO L225 Difference]: With dead ends: 200 [2018-01-24 12:29:58,517 INFO L226 Difference]: Without dead ends: 113 [2018-01-24 12:29:58,518 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 42 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-01-24 12:29:58,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-01-24 12:29:58,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-01-24 12:29:58,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-01-24 12:29:58,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 118 transitions. [2018-01-24 12:29:58,529 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 118 transitions. Word has length 42 [2018-01-24 12:29:58,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:29:58,529 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 118 transitions. [2018-01-24 12:29:58,529 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 12:29:58,529 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 118 transitions. [2018-01-24 12:29:58,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-01-24 12:29:58,530 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:29:58,530 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:29:58,531 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:29:58,531 INFO L82 PathProgramCache]: Analyzing trace with hash -549832031, now seen corresponding path program 2 times [2018-01-24 12:29:58,531 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:29:58,531 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:29:58,532 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:58,532 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:29:58,532 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:29:58,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:29:58,548 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:29:58,647 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:29:58,647 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:29:58,647 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:29:58,655 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:29:58,672 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:29:58,675 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:29:58,678 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:29:58,685 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 12:29:58,686 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:29:58,706 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 12:29:58,706 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:29:58,725 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 12:29:58,725 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 12:29:59,195 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 12:29:59,214 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-24 12:29:59,214 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [8] total 22 [2018-01-24 12:29:59,215 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 12:29:59,215 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 12:29:59,215 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=390, Unknown=0, NotChecked=0, Total=462 [2018-01-24 12:29:59,216 INFO L87 Difference]: Start difference. First operand 113 states and 118 transitions. Second operand 22 states. [2018-01-24 12:30:03,204 WARN L143 SmtUtils]: Spent 3649ms on a formula simplification that was a NOOP. DAG size: 32 [2018-01-24 12:30:03,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:03,734 INFO L93 Difference]: Finished difference Result 199 states and 211 transitions. [2018-01-24 12:30:03,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 12:30:03,735 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 43 [2018-01-24 12:30:03,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:03,736 INFO L225 Difference]: With dead ends: 199 [2018-01-24 12:30:03,736 INFO L226 Difference]: Without dead ends: 112 [2018-01-24 12:30:03,737 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 29 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 155 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=147, Invalid=845, Unknown=0, NotChecked=0, Total=992 [2018-01-24 12:30:03,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-01-24 12:30:03,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-01-24 12:30:03,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-01-24 12:30:03,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 117 transitions. [2018-01-24 12:30:03,756 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 117 transitions. Word has length 43 [2018-01-24 12:30:03,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:03,756 INFO L432 AbstractCegarLoop]: Abstraction has 112 states and 117 transitions. [2018-01-24 12:30:03,757 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 12:30:03,757 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 117 transitions. [2018-01-24 12:30:03,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-01-24 12:30:03,758 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:03,758 INFO L322 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:03,758 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:03,758 INFO L82 PathProgramCache]: Analyzing trace with hash -2038388811, now seen corresponding path program 1 times [2018-01-24 12:30:03,759 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:03,759 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:03,760 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:03,760 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:30:03,760 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:03,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:03,775 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:03,863 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 12:30:03,863 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:30:03,863 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-01-24 12:30:03,864 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 12:30:03,864 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 12:30:03,864 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-01-24 12:30:03,864 INFO L87 Difference]: Start difference. First operand 112 states and 117 transitions. Second operand 8 states. [2018-01-24 12:30:03,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:03,951 INFO L93 Difference]: Finished difference Result 175 states and 182 transitions. [2018-01-24 12:30:03,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 12:30:03,953 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 49 [2018-01-24 12:30:03,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:03,955 INFO L225 Difference]: With dead ends: 175 [2018-01-24 12:30:03,955 INFO L226 Difference]: Without dead ends: 112 [2018-01-24 12:30:03,955 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-01-24 12:30:03,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-01-24 12:30:03,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-01-24 12:30:03,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-01-24 12:30:03,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 116 transitions. [2018-01-24 12:30:03,972 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 116 transitions. Word has length 49 [2018-01-24 12:30:03,973 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:03,973 INFO L432 AbstractCegarLoop]: Abstraction has 112 states and 116 transitions. [2018-01-24 12:30:03,973 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 12:30:03,973 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 116 transitions. [2018-01-24 12:30:03,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-01-24 12:30:03,974 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:03,974 INFO L322 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:03,974 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:03,974 INFO L82 PathProgramCache]: Analyzing trace with hash 2077653417, now seen corresponding path program 1 times [2018-01-24 12:30:03,975 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:03,975 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:03,976 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:03,976 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:03,976 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:03,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:03,990 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:04,063 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 12:30:04,063 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:30:04,064 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-01-24 12:30:04,064 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 12:30:04,064 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 12:30:04,064 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 12:30:04,064 INFO L87 Difference]: Start difference. First operand 112 states and 116 transitions. Second operand 10 states. [2018-01-24 12:30:04,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:04,123 INFO L93 Difference]: Finished difference Result 177 states and 183 transitions. [2018-01-24 12:30:04,123 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 12:30:04,123 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 54 [2018-01-24 12:30:04,124 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:04,124 INFO L225 Difference]: With dead ends: 177 [2018-01-24 12:30:04,124 INFO L226 Difference]: Without dead ends: 112 [2018-01-24 12:30:04,125 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 12:30:04,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-01-24 12:30:04,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-01-24 12:30:04,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-01-24 12:30:04,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 115 transitions. [2018-01-24 12:30:04,139 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 115 transitions. Word has length 54 [2018-01-24 12:30:04,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:04,140 INFO L432 AbstractCegarLoop]: Abstraction has 112 states and 115 transitions. [2018-01-24 12:30:04,140 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 12:30:04,140 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 115 transitions. [2018-01-24 12:30:04,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-01-24 12:30:04,141 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:04,141 INFO L322 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:04,141 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:04,141 INFO L82 PathProgramCache]: Analyzing trace with hash -154764032, now seen corresponding path program 1 times [2018-01-24 12:30:04,142 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:04,142 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:04,143 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:04,143 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:04,143 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:04,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:04,164 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:04,451 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 12:30:04,451 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:30:04,451 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2018-01-24 12:30:04,451 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 12:30:04,451 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 12:30:04,452 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=379, Unknown=0, NotChecked=0, Total=420 [2018-01-24 12:30:04,452 INFO L87 Difference]: Start difference. First operand 112 states and 115 transitions. Second operand 21 states. [2018-01-24 12:30:04,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:04,832 INFO L93 Difference]: Finished difference Result 121 states and 124 transitions. [2018-01-24 12:30:04,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 12:30:04,832 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 65 [2018-01-24 12:30:04,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:04,833 INFO L225 Difference]: With dead ends: 121 [2018-01-24 12:30:04,833 INFO L226 Difference]: Without dead ends: 119 [2018-01-24 12:30:04,834 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 57 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=69, Invalid=687, Unknown=0, NotChecked=0, Total=756 [2018-01-24 12:30:04,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-01-24 12:30:04,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 110. [2018-01-24 12:30:04,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-24 12:30:04,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 113 transitions. [2018-01-24 12:30:04,861 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 113 transitions. Word has length 65 [2018-01-24 12:30:04,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:04,861 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 113 transitions. [2018-01-24 12:30:04,861 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 12:30:04,861 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 113 transitions. [2018-01-24 12:30:04,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-01-24 12:30:04,862 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:04,862 INFO L322 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:04,863 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:04,863 INFO L82 PathProgramCache]: Analyzing trace with hash -154764031, now seen corresponding path program 1 times [2018-01-24 12:30:04,863 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:04,863 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:04,864 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:04,864 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:04,864 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:04,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:04,886 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:04,956 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:04,956 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:30:04,956 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:30:04,964 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:05,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:05,005 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:30:05,022 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:05,056 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-24 12:30:05,056 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-01-24 12:30:05,057 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 12:30:05,057 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 12:30:05,057 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-01-24 12:30:05,057 INFO L87 Difference]: Start difference. First operand 110 states and 113 transitions. Second operand 10 states. [2018-01-24 12:30:05,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:05,091 INFO L93 Difference]: Finished difference Result 194 states and 200 transitions. [2018-01-24 12:30:05,092 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 12:30:05,092 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 65 [2018-01-24 12:30:05,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:05,093 INFO L225 Difference]: With dead ends: 194 [2018-01-24 12:30:05,093 INFO L226 Difference]: Without dead ends: 111 [2018-01-24 12:30:05,094 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-01-24 12:30:05,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-01-24 12:30:05,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2018-01-24 12:30:05,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-01-24 12:30:05,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 114 transitions. [2018-01-24 12:30:05,111 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 114 transitions. Word has length 65 [2018-01-24 12:30:05,112 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:05,112 INFO L432 AbstractCegarLoop]: Abstraction has 111 states and 114 transitions. [2018-01-24 12:30:05,112 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 12:30:05,112 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 114 transitions. [2018-01-24 12:30:05,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-01-24 12:30:05,113 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:05,113 INFO L322 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:05,113 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:05,114 INFO L82 PathProgramCache]: Analyzing trace with hash -477131272, now seen corresponding path program 2 times [2018-01-24 12:30:05,114 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:05,114 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:05,115 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:05,115 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:05,115 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:05,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:05,138 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:05,239 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:05,239 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:30:05,240 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:30:05,247 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:30:05,288 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:05,300 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:30:05,306 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:30:05,316 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 12:30:05,316 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:05,356 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 12:30:05,357 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:05,383 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 12:30:05,383 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 12:30:06,272 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 12:30:06,292 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-24 12:30:06,292 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [10] total 29 [2018-01-24 12:30:06,293 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 12:30:06,293 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 12:30:06,293 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=705, Unknown=0, NotChecked=0, Total=812 [2018-01-24 12:30:06,294 INFO L87 Difference]: Start difference. First operand 111 states and 114 transitions. Second operand 29 states. [2018-01-24 12:30:08,460 WARN L143 SmtUtils]: Spent 2019ms on a formula simplification that was a NOOP. DAG size: 31 [2018-01-24 12:30:12,606 WARN L143 SmtUtils]: Spent 4040ms on a formula simplification that was a NOOP. DAG size: 31 [2018-01-24 12:30:13,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:13,526 INFO L93 Difference]: Finished difference Result 193 states and 201 transitions. [2018-01-24 12:30:13,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 12:30:13,526 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 66 [2018-01-24 12:30:13,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:13,527 INFO L225 Difference]: With dead ends: 193 [2018-01-24 12:30:13,527 INFO L226 Difference]: Without dead ends: 110 [2018-01-24 12:30:13,528 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 89 GetRequests, 47 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 369 ImplicationChecksByTransitivity, 7.3s TimeCoverageRelationStatistics Valid=227, Invalid=1579, Unknown=0, NotChecked=0, Total=1806 [2018-01-24 12:30:13,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-01-24 12:30:13,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 110. [2018-01-24 12:30:13,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-24 12:30:13,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 113 transitions. [2018-01-24 12:30:13,540 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 113 transitions. Word has length 66 [2018-01-24 12:30:13,540 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:13,540 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 113 transitions. [2018-01-24 12:30:13,541 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-24 12:30:13,541 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 113 transitions. [2018-01-24 12:30:13,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-01-24 12:30:13,541 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:13,541 INFO L322 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:13,542 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:13,542 INFO L82 PathProgramCache]: Analyzing trace with hash 1613283294, now seen corresponding path program 1 times [2018-01-24 12:30:13,542 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:13,542 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:13,543 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:13,543 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:30:13,543 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:13,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:13,555 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:13,640 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-01-24 12:30:13,640 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:30:13,640 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-01-24 12:30:13,641 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 12:30:13,641 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 12:30:13,641 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-01-24 12:30:13,641 INFO L87 Difference]: Start difference. First operand 110 states and 113 transitions. Second operand 11 states. [2018-01-24 12:30:13,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:13,789 INFO L93 Difference]: Finished difference Result 116 states and 118 transitions. [2018-01-24 12:30:13,789 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 12:30:13,789 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 65 [2018-01-24 12:30:13,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:13,790 INFO L225 Difference]: With dead ends: 116 [2018-01-24 12:30:13,790 INFO L226 Difference]: Without dead ends: 110 [2018-01-24 12:30:13,790 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-01-24 12:30:13,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-01-24 12:30:13,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 110. [2018-01-24 12:30:13,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-24 12:30:13,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 112 transitions. [2018-01-24 12:30:13,805 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 112 transitions. Word has length 65 [2018-01-24 12:30:13,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:13,805 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 112 transitions. [2018-01-24 12:30:13,805 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 12:30:13,805 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 112 transitions. [2018-01-24 12:30:13,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-01-24 12:30:13,806 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:13,806 INFO L322 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:13,806 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:13,806 INFO L82 PathProgramCache]: Analyzing trace with hash -1474253813, now seen corresponding path program 1 times [2018-01-24 12:30:13,806 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:13,807 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:13,808 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:13,808 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:13,808 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:13,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:13,834 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:14,161 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-01-24 12:30:14,161 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:30:14,161 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2018-01-24 12:30:14,162 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 12:30:14,162 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 12:30:14,162 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=507, Unknown=0, NotChecked=0, Total=552 [2018-01-24 12:30:14,162 INFO L87 Difference]: Start difference. First operand 110 states and 112 transitions. Second operand 24 states. [2018-01-24 12:30:14,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:14,624 INFO L93 Difference]: Finished difference Result 115 states and 117 transitions. [2018-01-24 12:30:14,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 12:30:14,624 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 81 [2018-01-24 12:30:14,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:14,625 INFO L225 Difference]: With dead ends: 115 [2018-01-24 12:30:14,625 INFO L226 Difference]: Without dead ends: 113 [2018-01-24 12:30:14,626 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=85, Invalid=1037, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 12:30:14,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-01-24 12:30:14,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 108. [2018-01-24 12:30:14,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-01-24 12:30:14,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 110 transitions. [2018-01-24 12:30:14,638 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 110 transitions. Word has length 81 [2018-01-24 12:30:14,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:14,639 INFO L432 AbstractCegarLoop]: Abstraction has 108 states and 110 transitions. [2018-01-24 12:30:14,639 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 12:30:14,639 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 110 transitions. [2018-01-24 12:30:14,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-01-24 12:30:14,640 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:14,640 INFO L322 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:14,640 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:14,640 INFO L82 PathProgramCache]: Analyzing trace with hash -1474253812, now seen corresponding path program 1 times [2018-01-24 12:30:14,640 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:14,640 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:14,641 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:14,642 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:14,642 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:14,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:14,658 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:14,802 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:14,803 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:30:14,803 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:30:14,809 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:14,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:14,848 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:30:14,863 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:14,897 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-24 12:30:14,897 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2018-01-24 12:30:14,898 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 12:30:14,898 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 12:30:14,898 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=75, Unknown=0, NotChecked=0, Total=132 [2018-01-24 12:30:14,898 INFO L87 Difference]: Start difference. First operand 108 states and 110 transitions. Second operand 12 states. [2018-01-24 12:30:14,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:14,933 INFO L93 Difference]: Finished difference Result 188 states and 192 transitions. [2018-01-24 12:30:14,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 12:30:14,933 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 81 [2018-01-24 12:30:14,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:14,934 INFO L225 Difference]: With dead ends: 188 [2018-01-24 12:30:14,934 INFO L226 Difference]: Without dead ends: 109 [2018-01-24 12:30:14,935 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 81 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=95, Unknown=0, NotChecked=0, Total=156 [2018-01-24 12:30:14,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-01-24 12:30:14,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 109. [2018-01-24 12:30:14,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-01-24 12:30:14,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 111 transitions. [2018-01-24 12:30:14,952 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 111 transitions. Word has length 81 [2018-01-24 12:30:14,952 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:14,952 INFO L432 AbstractCegarLoop]: Abstraction has 109 states and 111 transitions. [2018-01-24 12:30:14,952 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 12:30:14,952 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 111 transitions. [2018-01-24 12:30:14,953 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-01-24 12:30:14,953 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:14,953 INFO L322 BasicCegarLoop]: trace histogram [8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:14,953 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:14,954 INFO L82 PathProgramCache]: Analyzing trace with hash 1420750595, now seen corresponding path program 2 times [2018-01-24 12:30:14,954 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:14,954 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:14,955 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:14,955 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:14,955 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:14,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:14,978 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:15,116 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:15,117 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:30:15,117 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:30:15,123 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:30:15,161 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:15,174 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:30:15,179 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:30:15,193 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 12:30:15,194 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:15,308 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 12:30:15,308 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:15,337 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 12:30:15,337 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 12:30:15,716 WARN L143 SmtUtils]: Spent 202ms on a formula simplification that was a NOOP. DAG size: 21 [2018-01-24 12:30:16,785 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-24 12:30:16,807 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-24 12:30:16,807 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [24] imperfect sequences [12] total 35 [2018-01-24 12:30:16,807 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-01-24 12:30:16,808 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-01-24 12:30:16,808 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=142, Invalid=1048, Unknown=0, NotChecked=0, Total=1190 [2018-01-24 12:30:16,808 INFO L87 Difference]: Start difference. First operand 109 states and 111 transitions. Second operand 35 states. [2018-01-24 12:30:19,366 WARN L143 SmtUtils]: Spent 2027ms on a formula simplification that was a NOOP. DAG size: 35 [2018-01-24 12:30:20,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:20,404 INFO L93 Difference]: Finished difference Result 187 states and 193 transitions. [2018-01-24 12:30:20,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-24 12:30:20,405 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 82 [2018-01-24 12:30:20,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:20,406 INFO L225 Difference]: With dead ends: 187 [2018-01-24 12:30:20,406 INFO L226 Difference]: Without dead ends: 108 [2018-01-24 12:30:20,407 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 57 SyntacticMatches, 3 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 617 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=314, Invalid=2442, Unknown=0, NotChecked=0, Total=2756 [2018-01-24 12:30:20,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2018-01-24 12:30:20,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 108. [2018-01-24 12:30:20,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-01-24 12:30:20,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 110 transitions. [2018-01-24 12:30:20,423 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 110 transitions. Word has length 82 [2018-01-24 12:30:20,423 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:20,424 INFO L432 AbstractCegarLoop]: Abstraction has 108 states and 110 transitions. [2018-01-24 12:30:20,424 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-01-24 12:30:20,424 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 110 transitions. [2018-01-24 12:30:20,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 12:30:20,424 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:20,425 INFO L322 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:20,425 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:20,425 INFO L82 PathProgramCache]: Analyzing trace with hash -1218395795, now seen corresponding path program 1 times [2018-01-24 12:30:20,425 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:20,425 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:20,426 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:20,426 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:30:20,427 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:20,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:20,443 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:20,609 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:20,609 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:30:20,609 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:30:20,620 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:20,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:20,693 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:30:20,723 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:20,755 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-24 12:30:20,755 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2018-01-24 12:30:20,756 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 12:30:20,756 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 12:30:20,756 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=102, Unknown=0, NotChecked=0, Total=182 [2018-01-24 12:30:20,756 INFO L87 Difference]: Start difference. First operand 108 states and 110 transitions. Second operand 14 states. [2018-01-24 12:30:20,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:20,817 INFO L93 Difference]: Finished difference Result 186 states and 190 transitions. [2018-01-24 12:30:20,817 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 12:30:20,817 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 87 [2018-01-24 12:30:20,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:20,818 INFO L225 Difference]: With dead ends: 186 [2018-01-24 12:30:20,819 INFO L226 Difference]: Without dead ends: 109 [2018-01-24 12:30:20,819 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=84, Invalid=126, Unknown=0, NotChecked=0, Total=210 [2018-01-24 12:30:20,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-01-24 12:30:20,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 109. [2018-01-24 12:30:20,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-01-24 12:30:20,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 111 transitions. [2018-01-24 12:30:20,844 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 111 transitions. Word has length 87 [2018-01-24 12:30:20,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:20,844 INFO L432 AbstractCegarLoop]: Abstraction has 109 states and 111 transitions. [2018-01-24 12:30:20,844 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 12:30:20,844 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 111 transitions. [2018-01-24 12:30:20,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-24 12:30:20,845 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:20,845 INFO L322 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:20,845 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:20,845 INFO L82 PathProgramCache]: Analyzing trace with hash -1495748828, now seen corresponding path program 2 times [2018-01-24 12:30:20,846 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:20,846 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:20,846 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:20,847 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:20,847 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:20,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:20,868 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:20,988 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:20,988 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:30:20,988 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:30:20,995 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:30:21,030 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:21,043 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:21,045 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:30:21,048 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:30:21,060 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:21,081 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-24 12:30:21,081 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 15 [2018-01-24 12:30:21,082 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 12:30:21,082 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 12:30:21,082 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=117, Unknown=0, NotChecked=0, Total=210 [2018-01-24 12:30:21,082 INFO L87 Difference]: Start difference. First operand 109 states and 111 transitions. Second operand 15 states. [2018-01-24 12:30:21,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:21,153 INFO L93 Difference]: Finished difference Result 187 states and 191 transitions. [2018-01-24 12:30:21,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 12:30:21,154 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 88 [2018-01-24 12:30:21,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:21,155 INFO L225 Difference]: With dead ends: 187 [2018-01-24 12:30:21,155 INFO L226 Difference]: Without dead ends: 110 [2018-01-24 12:30:21,155 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=97, Invalid=143, Unknown=0, NotChecked=0, Total=240 [2018-01-24 12:30:21,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-01-24 12:30:21,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 110. [2018-01-24 12:30:21,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-24 12:30:21,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 112 transitions. [2018-01-24 12:30:21,182 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 112 transitions. Word has length 88 [2018-01-24 12:30:21,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:21,182 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 112 transitions. [2018-01-24 12:30:21,183 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 12:30:21,183 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 112 transitions. [2018-01-24 12:30:21,183 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-01-24 12:30:21,183 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:21,184 INFO L322 BasicCegarLoop]: trace histogram [11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:21,184 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:21,184 INFO L82 PathProgramCache]: Analyzing trace with hash -1503758259, now seen corresponding path program 3 times [2018-01-24 12:30:21,184 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:21,184 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:21,185 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:21,185 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:30:21,185 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:21,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:21,207 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:21,459 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:21,460 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:30:21,460 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:30:21,468 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:30:21,517 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:30:21,535 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:30:21,594 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:30:21,954 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:30:22,273 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:30:22,603 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:30:22,798 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:30:22,800 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:30:22,805 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:30:22,979 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:23,000 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-24 12:30:23,000 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 20] total 33 [2018-01-24 12:30:23,000 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-24 12:30:23,001 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-24 12:30:23,001 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=770, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 12:30:23,001 INFO L87 Difference]: Start difference. First operand 110 states and 112 transitions. Second operand 33 states. [2018-01-24 12:30:23,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:23,087 INFO L93 Difference]: Finished difference Result 188 states and 192 transitions. [2018-01-24 12:30:23,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 12:30:23,088 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 89 [2018-01-24 12:30:23,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:23,088 INFO L225 Difference]: With dead ends: 188 [2018-01-24 12:30:23,088 INFO L226 Difference]: Without dead ends: 111 [2018-01-24 12:30:23,089 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 72 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 390 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=324, Invalid=936, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 12:30:23,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-01-24 12:30:23,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2018-01-24 12:30:23,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-01-24 12:30:23,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 113 transitions. [2018-01-24 12:30:23,115 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 113 transitions. Word has length 89 [2018-01-24 12:30:23,115 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:23,115 INFO L432 AbstractCegarLoop]: Abstraction has 111 states and 113 transitions. [2018-01-24 12:30:23,115 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-24 12:30:23,115 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 113 transitions. [2018-01-24 12:30:23,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-01-24 12:30:23,116 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:23,116 INFO L322 BasicCegarLoop]: trace histogram [12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:23,116 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:23,117 INFO L82 PathProgramCache]: Analyzing trace with hash -1752050620, now seen corresponding path program 4 times [2018-01-24 12:30:23,117 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:23,117 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:23,118 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:23,118 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:30:23,118 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:23,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:23,139 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:23,319 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:23,319 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:30:23,319 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:30:23,326 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:30:23,382 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:30:23,385 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:30:23,404 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:23,424 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-24 12:30:23,424 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 17 [2018-01-24 12:30:23,424 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 12:30:23,424 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 12:30:23,424 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=150, Unknown=0, NotChecked=0, Total=272 [2018-01-24 12:30:23,425 INFO L87 Difference]: Start difference. First operand 111 states and 113 transitions. Second operand 17 states. [2018-01-24 12:30:23,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:23,471 INFO L93 Difference]: Finished difference Result 189 states and 193 transitions. [2018-01-24 12:30:23,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 12:30:23,471 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 90 [2018-01-24 12:30:23,471 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:23,472 INFO L225 Difference]: With dead ends: 189 [2018-01-24 12:30:23,472 INFO L226 Difference]: Without dead ends: 112 [2018-01-24 12:30:23,473 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=126, Invalid=180, Unknown=0, NotChecked=0, Total=306 [2018-01-24 12:30:23,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-01-24 12:30:23,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-01-24 12:30:23,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-01-24 12:30:23,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 114 transitions. [2018-01-24 12:30:23,491 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 114 transitions. Word has length 90 [2018-01-24 12:30:23,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:23,492 INFO L432 AbstractCegarLoop]: Abstraction has 112 states and 114 transitions. [2018-01-24 12:30:23,492 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 12:30:23,492 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 114 transitions. [2018-01-24 12:30:23,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-01-24 12:30:23,492 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:23,492 INFO L322 BasicCegarLoop]: trace histogram [13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:23,492 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:23,493 INFO L82 PathProgramCache]: Analyzing trace with hash -859179219, now seen corresponding path program 5 times [2018-01-24 12:30:23,493 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:23,493 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:23,493 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:23,493 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:30:23,493 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:23,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:23,513 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:23,735 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:23,735 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:30:23,766 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:30:23,771 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:30:23,785 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:23,787 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:23,791 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:23,805 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:23,818 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:23,860 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:23,891 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:24,138 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:24,143 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:30:24,147 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:30:24,165 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:24,186 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-24 12:30:24,186 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2018-01-24 12:30:24,187 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 12:30:24,187 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 12:30:24,187 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=168, Unknown=0, NotChecked=0, Total=306 [2018-01-24 12:30:24,187 INFO L87 Difference]: Start difference. First operand 112 states and 114 transitions. Second operand 18 states. [2018-01-24 12:30:24,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:24,269 INFO L93 Difference]: Finished difference Result 190 states and 194 transitions. [2018-01-24 12:30:24,270 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 12:30:24,270 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 91 [2018-01-24 12:30:24,270 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:24,271 INFO L225 Difference]: With dead ends: 190 [2018-01-24 12:30:24,271 INFO L226 Difference]: Without dead ends: 113 [2018-01-24 12:30:24,272 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=142, Invalid=200, Unknown=0, NotChecked=0, Total=342 [2018-01-24 12:30:24,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-01-24 12:30:24,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-01-24 12:30:24,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-01-24 12:30:24,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 115 transitions. [2018-01-24 12:30:24,299 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 115 transitions. Word has length 91 [2018-01-24 12:30:24,299 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:24,299 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 115 transitions. [2018-01-24 12:30:24,299 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 12:30:24,299 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 115 transitions. [2018-01-24 12:30:24,300 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 12:30:24,300 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:24,300 INFO L322 BasicCegarLoop]: trace histogram [14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:24,300 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:24,300 INFO L82 PathProgramCache]: Analyzing trace with hash 1050030436, now seen corresponding path program 6 times [2018-01-24 12:30:24,301 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:24,301 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:24,301 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:24,302 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:30:24,302 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:24,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:24,323 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:24,476 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:24,476 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:30:24,476 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:30:24,482 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:30:24,517 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:30:24,528 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:30:24,543 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:30:24,747 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:30:25,257 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:30:26,515 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:30:27,779 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:30:30,082 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:30:30,085 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:30:30,091 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:30:30,102 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:30,124 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-24 12:30:30,124 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2018-01-24 12:30:30,124 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 12:30:30,125 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 12:30:30,125 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=187, Unknown=0, NotChecked=0, Total=342 [2018-01-24 12:30:30,125 INFO L87 Difference]: Start difference. First operand 113 states and 115 transitions. Second operand 19 states. [2018-01-24 12:30:30,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:30,181 INFO L93 Difference]: Finished difference Result 191 states and 195 transitions. [2018-01-24 12:30:30,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 12:30:30,181 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 92 [2018-01-24 12:30:30,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:30,182 INFO L225 Difference]: With dead ends: 191 [2018-01-24 12:30:30,182 INFO L226 Difference]: Without dead ends: 114 [2018-01-24 12:30:30,182 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 92 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=159, Invalid=221, Unknown=0, NotChecked=0, Total=380 [2018-01-24 12:30:30,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-01-24 12:30:30,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. [2018-01-24 12:30:30,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-01-24 12:30:30,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 116 transitions. [2018-01-24 12:30:30,199 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 116 transitions. Word has length 92 [2018-01-24 12:30:30,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:30,199 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 116 transitions. [2018-01-24 12:30:30,199 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 12:30:30,199 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 116 transitions. [2018-01-24 12:30:30,200 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-01-24 12:30:30,200 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:30,201 INFO L322 BasicCegarLoop]: trace histogram [15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:30,201 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:30,201 INFO L82 PathProgramCache]: Analyzing trace with hash 105987597, now seen corresponding path program 7 times [2018-01-24 12:30:30,201 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:30,201 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:30,202 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:30,202 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:30:30,202 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:30,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:30,219 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:30,516 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:30,516 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:30:30,516 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:30:30,524 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:30,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:30,581 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:30:30,615 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:30,636 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-24 12:30:30,636 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 20 [2018-01-24 12:30:30,637 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 12:30:30,638 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 12:30:30,638 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=173, Invalid=207, Unknown=0, NotChecked=0, Total=380 [2018-01-24 12:30:30,638 INFO L87 Difference]: Start difference. First operand 114 states and 116 transitions. Second operand 20 states. [2018-01-24 12:30:30,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:30:30,692 INFO L93 Difference]: Finished difference Result 192 states and 196 transitions. [2018-01-24 12:30:30,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 12:30:30,693 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 93 [2018-01-24 12:30:30,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:30:30,693 INFO L225 Difference]: With dead ends: 192 [2018-01-24 12:30:30,693 INFO L226 Difference]: Without dead ends: 115 [2018-01-24 12:30:30,694 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 93 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=177, Invalid=243, Unknown=0, NotChecked=0, Total=420 [2018-01-24 12:30:30,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-01-24 12:30:30,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-01-24 12:30:30,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-01-24 12:30:30,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 117 transitions. [2018-01-24 12:30:30,712 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 117 transitions. Word has length 93 [2018-01-24 12:30:30,712 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:30:30,712 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 117 transitions. [2018-01-24 12:30:30,712 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 12:30:30,712 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 117 transitions. [2018-01-24 12:30:30,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-01-24 12:30:30,713 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:30:30,713 INFO L322 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:30:30,713 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 12:30:30,713 INFO L82 PathProgramCache]: Analyzing trace with hash 905430660, now seen corresponding path program 8 times [2018-01-24 12:30:30,713 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-24 12:30:30,713 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-24 12:30:30,714 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:30,714 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:30:30,714 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:30:30,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:30:30,795 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:30:34,099 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:30:34,099 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:30:34,099 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:30:34,105 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:30:34,138 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:34,154 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:30:34,159 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:30:34,165 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:30:34,376 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-01-24 12:30:34,377 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-01-24 12:30:34,377 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,379 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,382 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,383 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:20, output treesize:16 [2018-01-24 12:30:34,427 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 20 [2018-01-24 12:30:34,429 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,431 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 27 [2018-01-24 12:30:34,431 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,436 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,441 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,441 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:31, output treesize:27 [2018-01-24 12:30:34,495 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 29 [2018-01-24 12:30:34,498 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,498 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,499 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,499 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 52 [2018-01-24 12:30:34,500 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,506 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,513 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,513 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-01-24 12:30:34,574 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 38 [2018-01-24 12:30:34,580 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,581 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,582 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,583 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,584 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,585 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,586 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 85 [2018-01-24 12:30:34,586 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,599 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,608 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,609 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:53, output treesize:49 [2018-01-24 12:30:34,699 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 47 [2018-01-24 12:30:34,714 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,715 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,716 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,722 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,730 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,731 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,740 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,741 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,742 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,743 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,744 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 126 [2018-01-24 12:30:34,744 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,766 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,777 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,777 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:64, output treesize:60 [2018-01-24 12:30:34,862 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 56 [2018-01-24 12:30:34,868 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,869 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,869 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,870 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,871 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,871 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,872 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,873 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,873 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,874 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,875 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,875 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,876 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,877 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,878 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:34,879 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 175 [2018-01-24 12:30:34,879 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,904 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,915 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:34,915 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:75, output treesize:71 [2018-01-24 12:30:35,003 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 65 [2018-01-24 12:30:35,007 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,008 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,010 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,010 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,011 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,012 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,013 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,014 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,015 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,016 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,017 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,018 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,019 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,020 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,021 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,021 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,023 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,023 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,024 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,025 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,026 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,028 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 21 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 232 [2018-01-24 12:30:35,028 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:35,072 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:35,087 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:35,088 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:86, output treesize:82 [2018-01-24 12:30:35,219 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 74 [2018-01-24 12:30:35,223 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,223 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,224 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,225 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,226 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,226 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,227 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,228 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,228 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,229 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,230 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,231 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,231 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,233 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,234 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,235 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,236 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,236 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,237 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,238 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,238 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,239 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,240 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,241 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,241 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,242 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,243 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,244 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,245 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 28 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 297 [2018-01-24 12:30:35,245 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:35,301 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:35,316 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:35,316 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:97, output treesize:93 [2018-01-24 12:30:35,417 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 102 treesize of output 83 [2018-01-24 12:30:35,421 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,422 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,423 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,424 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,424 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,425 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,426 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,427 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,428 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,429 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,430 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,430 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,431 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,432 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,433 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,433 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,434 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,435 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,436 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,436 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,437 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,441 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,442 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,443 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,444 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,445 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,445 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,446 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,447 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,448 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,449 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,449 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,450 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,451 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,452 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,453 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,455 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 36 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 370 [2018-01-24 12:30:35,456 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:35,548 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:35,565 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:35,565 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:108, output treesize:104 [2018-01-24 12:30:35,669 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 113 treesize of output 92 [2018-01-24 12:30:35,673 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,674 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,674 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,675 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,676 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,677 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,678 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,678 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,679 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,680 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,681 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,682 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,682 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,683 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,684 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,685 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,686 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,687 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,688 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,689 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,689 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,690 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,691 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,692 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,693 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,693 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,694 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,695 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,696 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,697 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,697 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,698 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,699 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,700 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,701 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,702 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,702 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,703 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,704 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,705 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,706 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,707 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,707 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,708 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,709 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,711 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 45 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 451 [2018-01-24 12:30:35,711 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:35,808 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:35,832 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 12:30:35,832 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:124, output treesize:120 [2018-01-24 12:30:35,974 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 124 treesize of output 101 [2018-01-24 12:30:35,980 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,981 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,983 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,984 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,985 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,986 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,987 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,988 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,989 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,991 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,992 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,993 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,994 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,995 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,997 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,998 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:35,999 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,000 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,001 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,002 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,004 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,004 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,006 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,007 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,008 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,009 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,010 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,011 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,012 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,013 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,014 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,015 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,017 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,018 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,019 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,020 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,021 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,022 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,023 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,025 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,026 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,028 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,029 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,030 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,031 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,032 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,033 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,035 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,036 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,037 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,038 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,040 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,041 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,042 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,043 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:36,045 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 55 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 101 treesize of output 540 [2018-01-24 12:30:36,046 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:36,208 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:36,237 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 12:30:36,237 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:135, output treesize:131 [2018-01-24 12:30:41,128 WARN L143 SmtUtils]: Spent 2026ms on a formula simplification that was a NOOP. DAG size: 58 [2018-01-24 12:30:41,137 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 135 treesize of output 110 [2018-01-24 12:30:41,145 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,146 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,148 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,149 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,151 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,152 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,154 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,155 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,157 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,158 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,162 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,164 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,165 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,167 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,168 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,170 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,171 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,172 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,174 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,177 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,179 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,183 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,185 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,187 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,188 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,190 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,191 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,195 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,197 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,198 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,200 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,202 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,203 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,205 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,208 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,209 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,211 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,212 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,213 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,215 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,218 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,219 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,221 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,222 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,223 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,227 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,229 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,232 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,233 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,236 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,238 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,240 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,243 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,245 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,248 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 12:30:41,252 INFO L303 Elim1Store]: Index analysis took 113 ms [2018-01-24 12:30:41,254 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 11 select indices, 11 select index equivalence classes, 55 disjoint index pairs (out of 55 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 110 treesize of output 551 [2018-01-24 12:30:41,255 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 12:30:41,416 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 12:30:41,452 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-01-24 12:30:41,452 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:151, output treesize:147 Received shutdown request... [2018-01-24 12:30:42,917 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-01-24 12:30:42,918 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 12:30:42,921 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 12:30:42,922 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 12:30:42 BoogieIcfgContainer [2018-01-24 12:30:42,922 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 12:30:42,923 INFO L168 Benchmark]: Toolchain (without parser) took 53307.98 ms. Allocated memory was 302.5 MB in the beginning and 782.2 MB in the end (delta: 479.7 MB). Free memory was 261.6 MB in the beginning and 393.3 MB in the end (delta: -131.8 MB). Peak memory consumption was 348.0 MB. Max. memory is 5.3 GB. [2018-01-24 12:30:42,924 INFO L168 Benchmark]: CDTParser took 0.32 ms. Allocated memory is still 302.5 MB. Free memory is still 268.5 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 12:30:42,924 INFO L168 Benchmark]: CACSL2BoogieTranslator took 248.14 ms. Allocated memory is still 302.5 MB. Free memory was 261.6 MB in the beginning and 247.3 MB in the end (delta: 14.2 MB). Peak memory consumption was 14.2 MB. Max. memory is 5.3 GB. [2018-01-24 12:30:42,924 INFO L168 Benchmark]: Boogie Preprocessor took 49.13 ms. Allocated memory is still 302.5 MB. Free memory was 247.3 MB in the beginning and 245.4 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 12:30:42,924 INFO L168 Benchmark]: RCFGBuilder took 469.32 ms. Allocated memory is still 302.5 MB. Free memory was 245.4 MB in the beginning and 214.8 MB in the end (delta: 30.6 MB). Peak memory consumption was 30.6 MB. Max. memory is 5.3 GB. [2018-01-24 12:30:42,925 INFO L168 Benchmark]: TraceAbstraction took 52532.38 ms. Allocated memory was 302.5 MB in the beginning and 782.2 MB in the end (delta: 479.7 MB). Free memory was 214.8 MB in the beginning and 393.3 MB in the end (delta: -178.5 MB). Peak memory consumption was 301.2 MB. Max. memory is 5.3 GB. [2018-01-24 12:30:42,926 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32 ms. Allocated memory is still 302.5 MB. Free memory is still 268.5 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 248.14 ms. Allocated memory is still 302.5 MB. Free memory was 261.6 MB in the beginning and 247.3 MB in the end (delta: 14.2 MB). Peak memory consumption was 14.2 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 49.13 ms. Allocated memory is still 302.5 MB. Free memory was 247.3 MB in the beginning and 245.4 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 469.32 ms. Allocated memory is still 302.5 MB. Free memory was 245.4 MB in the beginning and 214.8 MB in the end (delta: 30.6 MB). Peak memory consumption was 30.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 52532.38 ms. Allocated memory was 302.5 MB in the beginning and 782.2 MB in the end (delta: 479.7 MB). Free memory was 214.8 MB in the beginning and 393.3 MB in the end (delta: -178.5 MB). Peak memory consumption was 301.2 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1294). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1294). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1411). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1411). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1265). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1265). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1267). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1267). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1441]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1441). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 75 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 18 procedures, 118 locations, 19 error locations. TIMEOUT Result, 52.4s OverallTime, 30 OverallIterations, 16 TraceHistogramMax, 22.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 2910 SDtfs, 799 SDslu, 22687 SDs, 0 SdLazy, 6587 SolverSat, 241 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1479 GetRequests, 1023 SyntacticMatches, 5 SemanticMatches, 451 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1980 ImplicationChecksByTransitivity, 22.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=125occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.4s AutomataMinimizationTime, 29 MinimizatonAttempts, 32 StatesRemovedByMinimization, 7 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 8.0s SatisfiabilityAnalysisTime, 8.1s InterpolantComputationTime, 2727 NumberOfCodeBlocks, 2707 NumberOfCodeBlocksAsserted, 66 NumberOfCheckSat, 2683 ConstructedInterpolants, 175 QuantifiedInterpolants, 586303 SizeOfPredicates, 67 NumberOfNonLiveVariables, 5369 ConjunctsInSsa, 395 ConjunctsInUnsatCore, 44 InterpolantComputations, 18 PerfectInterpolantSequences, 183/1473 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test22_1_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_12-30-42-935.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test22_1_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel+AI_EQ.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_12-30-42-935.csv Completed graceful shutdown