java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/memsafety/20051113-1.c_false-valid-memtrack.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 13:01:37,353 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 13:01:37,355 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 13:01:37,370 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 13:01:37,370 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 13:01:37,371 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 13:01:37,372 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 13:01:37,374 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 13:01:37,375 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 13:01:37,376 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 13:01:37,377 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 13:01:37,377 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 13:01:37,378 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 13:01:37,380 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 13:01:37,381 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 13:01:37,383 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 13:01:37,385 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 13:01:37,387 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 13:01:37,388 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 13:01:37,389 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 13:01:37,392 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-01-24 13:01:37,397 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 13:01:37,397 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 13:01:37,397 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf [2018-01-24 13:01:37,406 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 13:01:37,407 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 13:01:37,454 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 13:01:37,454 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 13:01:37,454 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 13:01:37,454 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 13:01:37,454 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 13:01:37,455 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 13:01:37,455 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 13:01:37,455 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 13:01:37,455 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 13:01:37,455 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 13:01:37,456 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 13:01:37,456 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 13:01:37,456 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 13:01:37,456 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 13:01:37,456 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 13:01:37,456 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 13:01:37,456 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 13:01:37,456 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 13:01:37,457 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 13:01:37,457 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 13:01:37,457 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 13:01:37,457 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:01:37,457 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 13:01:37,458 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 13:01:37,458 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 13:01:37,458 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 13:01:37,458 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-01-24 13:01:37,458 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 13:01:37,458 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 13:01:37,458 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 13:01:37,459 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 13:01:37,459 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 13:01:37,490 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 13:01:37,500 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 13:01:37,503 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 13:01:37,504 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 13:01:37,504 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 13:01:37,505 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/memsafety/20051113-1.c_false-valid-memtrack.i [2018-01-24 13:01:37,672 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 13:01:37,677 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 13:01:37,678 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 13:01:37,678 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 13:01:37,683 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 13:01:37,683 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:01:37" (1/1) ... [2018-01-24 13:01:37,686 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@24f959c7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:01:37, skipping insertion in model container [2018-01-24 13:01:37,686 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:01:37" (1/1) ... [2018-01-24 13:01:37,699 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:01:37,738 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:01:37,870 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:01:37,895 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:01:37,905 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:01:37 WrapperNode [2018-01-24 13:01:37,905 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 13:01:37,906 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 13:01:37,906 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 13:01:37,906 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 13:01:37,922 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:01:37" (1/1) ... [2018-01-24 13:01:37,922 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:01:37" (1/1) ... [2018-01-24 13:01:37,931 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:01:37" (1/1) ... [2018-01-24 13:01:37,932 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:01:37" (1/1) ... [2018-01-24 13:01:37,937 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:01:37" (1/1) ... [2018-01-24 13:01:37,941 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:01:37" (1/1) ... [2018-01-24 13:01:37,943 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:01:37" (1/1) ... [2018-01-24 13:01:37,945 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 13:01:37,945 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 13:01:37,946 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 13:01:37,946 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 13:01:37,947 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:01:37" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:01:37,992 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 13:01:37,993 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 13:01:37,993 INFO L136 BoogieDeclarations]: Found implementation of procedure Sum [2018-01-24 13:01:37,993 INFO L136 BoogieDeclarations]: Found implementation of procedure Sum2 [2018-01-24 13:01:37,993 INFO L136 BoogieDeclarations]: Found implementation of procedure dummy_abort [2018-01-24 13:01:37,993 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 13:01:37,993 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 13:01:37,993 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 13:01:37,993 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 13:01:37,993 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 13:01:37,993 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 13:01:37,993 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-01-24 13:01:37,994 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-01-24 13:01:37,994 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-01-24 13:01:37,994 INFO L128 BoogieDeclarations]: Found specification of procedure Sum [2018-01-24 13:01:37,994 INFO L128 BoogieDeclarations]: Found specification of procedure Sum2 [2018-01-24 13:01:37,994 INFO L128 BoogieDeclarations]: Found specification of procedure dummy_abort [2018-01-24 13:01:37,994 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 13:01:37,994 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 13:01:37,994 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 13:01:38,136 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-01-24 13:01:38,290 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 13:01:38,291 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:01:38 BoogieIcfgContainer [2018-01-24 13:01:38,291 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 13:01:38,291 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 13:01:38,291 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 13:01:38,293 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 13:01:38,293 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 01:01:37" (1/3) ... [2018-01-24 13:01:38,294 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@57b9b0d6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:01:38, skipping insertion in model container [2018-01-24 13:01:38,294 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:01:37" (2/3) ... [2018-01-24 13:01:38,294 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@57b9b0d6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:01:38, skipping insertion in model container [2018-01-24 13:01:38,294 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:01:38" (3/3) ... [2018-01-24 13:01:38,296 INFO L105 eAbstractionObserver]: Analyzing ICFG 20051113-1.c_false-valid-memtrack.i [2018-01-24 13:01:38,302 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 13:01:38,308 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 25 error locations. [2018-01-24 13:01:38,351 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 13:01:38,352 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 13:01:38,352 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 13:01:38,352 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 13:01:38,352 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 13:01:38,353 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 13:01:38,353 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 13:01:38,353 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 13:01:38,354 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 13:01:38,377 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states. [2018-01-24 13:01:38,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 13:01:38,381 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:38,382 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:38,382 INFO L371 AbstractCegarLoop]: === Iteration 1 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:38,386 INFO L82 PathProgramCache]: Analyzing trace with hash -1274877597, now seen corresponding path program 1 times [2018-01-24 13:01:38,388 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:38,428 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:38,428 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:38,428 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:38,428 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:38,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:38,474 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:38,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:01:38,548 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:01:38,548 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 13:01:38,548 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:01:38,552 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 13:01:38,568 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 13:01:38,569 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 13:01:38,572 INFO L87 Difference]: Start difference. First operand 80 states. Second operand 4 states. [2018-01-24 13:01:38,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:38,855 INFO L93 Difference]: Finished difference Result 111 states and 123 transitions. [2018-01-24 13:01:38,856 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 13:01:38,857 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 8 [2018-01-24 13:01:38,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:38,868 INFO L225 Difference]: With dead ends: 111 [2018-01-24 13:01:38,869 INFO L226 Difference]: Without dead ends: 69 [2018-01-24 13:01:38,872 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:01:38,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-01-24 13:01:38,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2018-01-24 13:01:38,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-01-24 13:01:38,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 74 transitions. [2018-01-24 13:01:38,916 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 74 transitions. Word has length 8 [2018-01-24 13:01:38,916 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:38,916 INFO L432 AbstractCegarLoop]: Abstraction has 69 states and 74 transitions. [2018-01-24 13:01:38,916 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 13:01:38,916 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 74 transitions. [2018-01-24 13:01:38,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 13:01:38,917 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:38,917 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:38,917 INFO L371 AbstractCegarLoop]: === Iteration 2 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:38,917 INFO L82 PathProgramCache]: Analyzing trace with hash -1274877596, now seen corresponding path program 1 times [2018-01-24 13:01:38,918 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:38,918 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:38,919 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:38,919 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:38,919 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:38,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:38,934 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:38,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:01:38,998 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:01:38,998 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 13:01:38,998 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:01:39,000 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 13:01:39,000 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 13:01:39,000 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 13:01:39,000 INFO L87 Difference]: Start difference. First operand 69 states and 74 transitions. Second operand 4 states. [2018-01-24 13:01:39,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:39,172 INFO L93 Difference]: Finished difference Result 69 states and 74 transitions. [2018-01-24 13:01:39,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 13:01:39,173 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 8 [2018-01-24 13:01:39,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:39,174 INFO L225 Difference]: With dead ends: 69 [2018-01-24 13:01:39,175 INFO L226 Difference]: Without dead ends: 61 [2018-01-24 13:01:39,175 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:01:39,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-01-24 13:01:39,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2018-01-24 13:01:39,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-01-24 13:01:39,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 66 transitions. [2018-01-24 13:01:39,186 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 66 transitions. Word has length 8 [2018-01-24 13:01:39,186 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:39,186 INFO L432 AbstractCegarLoop]: Abstraction has 61 states and 66 transitions. [2018-01-24 13:01:39,186 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 13:01:39,186 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 66 transitions. [2018-01-24 13:01:39,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-24 13:01:39,187 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:39,187 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:39,187 INFO L371 AbstractCegarLoop]: === Iteration 3 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:39,188 INFO L82 PathProgramCache]: Analyzing trace with hash -1852712777, now seen corresponding path program 1 times [2018-01-24 13:01:39,188 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:39,189 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:39,189 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:39,189 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:39,189 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:39,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:39,216 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:39,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:01:39,272 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:01:39,273 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 13:01:39,273 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:01:39,273 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 13:01:39,273 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 13:01:39,274 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:01:39,274 INFO L87 Difference]: Start difference. First operand 61 states and 66 transitions. Second operand 5 states. [2018-01-24 13:01:39,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:39,385 INFO L93 Difference]: Finished difference Result 61 states and 66 transitions. [2018-01-24 13:01:39,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:01:39,386 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2018-01-24 13:01:39,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:39,387 INFO L225 Difference]: With dead ends: 61 [2018-01-24 13:01:39,387 INFO L226 Difference]: Without dead ends: 59 [2018-01-24 13:01:39,388 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:01:39,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-01-24 13:01:39,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2018-01-24 13:01:39,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2018-01-24 13:01:39,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 64 transitions. [2018-01-24 13:01:39,397 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 64 transitions. Word has length 25 [2018-01-24 13:01:39,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:39,397 INFO L432 AbstractCegarLoop]: Abstraction has 59 states and 64 transitions. [2018-01-24 13:01:39,397 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 13:01:39,397 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 64 transitions. [2018-01-24 13:01:39,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-24 13:01:39,398 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:39,398 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:39,399 INFO L371 AbstractCegarLoop]: === Iteration 4 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:39,399 INFO L82 PathProgramCache]: Analyzing trace with hash -1852712776, now seen corresponding path program 1 times [2018-01-24 13:01:39,399 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:39,400 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:39,400 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:39,400 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:39,400 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:39,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:39,424 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:39,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:01:39,532 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:01:39,532 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:01:39,532 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:01:39,533 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:01:39,533 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:01:39,533 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:01:39,533 INFO L87 Difference]: Start difference. First operand 59 states and 64 transitions. Second operand 6 states. [2018-01-24 13:01:39,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:39,659 INFO L93 Difference]: Finished difference Result 59 states and 64 transitions. [2018-01-24 13:01:39,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:01:39,660 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-01-24 13:01:39,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:39,661 INFO L225 Difference]: With dead ends: 59 [2018-01-24 13:01:39,662 INFO L226 Difference]: Without dead ends: 58 [2018-01-24 13:01:39,662 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:01:39,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-01-24 13:01:39,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 58. [2018-01-24 13:01:39,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-01-24 13:01:39,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 63 transitions. [2018-01-24 13:01:39,671 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 63 transitions. Word has length 25 [2018-01-24 13:01:39,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:39,671 INFO L432 AbstractCegarLoop]: Abstraction has 58 states and 63 transitions. [2018-01-24 13:01:39,672 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:01:39,672 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 63 transitions. [2018-01-24 13:01:39,673 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 13:01:39,673 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:39,673 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:39,673 INFO L371 AbstractCegarLoop]: === Iteration 5 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:39,673 INFO L82 PathProgramCache]: Analyzing trace with hash 1954449657, now seen corresponding path program 1 times [2018-01-24 13:01:39,674 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:39,675 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:39,675 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:39,675 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:39,676 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:39,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:39,701 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:40,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:01:40,089 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:01:40,089 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-01-24 13:01:40,089 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:01:40,089 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 13:01:40,090 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 13:01:40,090 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-01-24 13:01:40,090 INFO L87 Difference]: Start difference. First operand 58 states and 63 transitions. Second operand 9 states. [2018-01-24 13:01:40,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:40,358 INFO L93 Difference]: Finished difference Result 93 states and 102 transitions. [2018-01-24 13:01:40,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:01:40,359 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 27 [2018-01-24 13:01:40,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:40,360 INFO L225 Difference]: With dead ends: 93 [2018-01-24 13:01:40,360 INFO L226 Difference]: Without dead ends: 64 [2018-01-24 13:01:40,361 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 1 SyntacticMatches, 6 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:01:40,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-01-24 13:01:40,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 62. [2018-01-24 13:01:40,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-01-24 13:01:40,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 67 transitions. [2018-01-24 13:01:40,371 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 67 transitions. Word has length 27 [2018-01-24 13:01:40,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:40,371 INFO L432 AbstractCegarLoop]: Abstraction has 62 states and 67 transitions. [2018-01-24 13:01:40,371 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 13:01:40,371 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 67 transitions. [2018-01-24 13:01:40,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-01-24 13:01:40,372 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:40,373 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:40,373 INFO L371 AbstractCegarLoop]: === Iteration 6 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:40,373 INFO L82 PathProgramCache]: Analyzing trace with hash 1339860797, now seen corresponding path program 1 times [2018-01-24 13:01:40,373 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:40,374 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:40,374 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:40,374 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:40,374 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:40,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:40,394 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:40,550 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:01:40,550 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:40,550 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:40,557 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:40,557 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:01:40,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:40,594 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:40,644 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 13:01:40,644 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:40,677 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 13:01:40,699 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:01:40,699 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4, 4] imperfect sequences [6] total 11 [2018-01-24 13:01:40,699 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:01:40,699 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 13:01:40,700 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 13:01:40,700 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-01-24 13:01:40,700 INFO L87 Difference]: Start difference. First operand 62 states and 67 transitions. Second operand 4 states. [2018-01-24 13:01:40,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:40,716 INFO L93 Difference]: Finished difference Result 114 states and 124 transitions. [2018-01-24 13:01:40,717 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 13:01:40,717 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 33 [2018-01-24 13:01:40,717 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:40,718 INFO L225 Difference]: With dead ends: 114 [2018-01-24 13:01:40,718 INFO L226 Difference]: Without dead ends: 63 [2018-01-24 13:01:40,719 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 61 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2018-01-24 13:01:40,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-01-24 13:01:40,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2018-01-24 13:01:40,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-01-24 13:01:40,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-01-24 13:01:40,727 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 33 [2018-01-24 13:01:40,727 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:40,727 INFO L432 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-01-24 13:01:40,727 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 13:01:40,727 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-01-24 13:01:40,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-24 13:01:40,728 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:40,728 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:40,729 INFO L371 AbstractCegarLoop]: === Iteration 7 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:40,729 INFO L82 PathProgramCache]: Analyzing trace with hash 1619594826, now seen corresponding path program 1 times [2018-01-24 13:01:40,729 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:40,730 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:40,730 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:40,730 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:40,730 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:40,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:40,751 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:40,937 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-01-24 13:01:40,937 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:40,937 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:40,946 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:40,946 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:01:40,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:40,970 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:40,995 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 13:01:40,996 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:41,047 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 13:01:41,067 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:41,068 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 4 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:01:41,071 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:41,072 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:01:41,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:41,112 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:41,118 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 13:01:41,118 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:41,189 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 13:01:41,190 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:01:41,190 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5, 5, 5] total 13 [2018-01-24 13:01:41,191 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:01:41,191 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:01:41,191 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:01:41,191 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:01:41,191 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 10 states. [2018-01-24 13:01:41,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:41,431 INFO L93 Difference]: Finished difference Result 126 states and 138 transitions. [2018-01-24 13:01:41,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:01:41,431 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 34 [2018-01-24 13:01:41,431 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:41,433 INFO L225 Difference]: With dead ends: 126 [2018-01-24 13:01:41,433 INFO L226 Difference]: Without dead ends: 75 [2018-01-24 13:01:41,434 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 146 GetRequests, 128 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=219, Unknown=0, NotChecked=0, Total=272 [2018-01-24 13:01:41,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-01-24 13:01:41,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 70. [2018-01-24 13:01:41,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-24 13:01:41,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 76 transitions. [2018-01-24 13:01:41,442 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 76 transitions. Word has length 34 [2018-01-24 13:01:41,443 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:41,443 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 76 transitions. [2018-01-24 13:01:41,443 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:01:41,443 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 76 transitions. [2018-01-24 13:01:41,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 13:01:41,444 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:41,444 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:41,444 INFO L371 AbstractCegarLoop]: === Iteration 8 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:41,445 INFO L82 PathProgramCache]: Analyzing trace with hash -341936469, now seen corresponding path program 1 times [2018-01-24 13:01:41,445 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:41,446 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:41,446 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:41,446 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:41,446 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:41,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:41,462 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:41,505 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:01:41,505 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:01:41,505 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 13:01:41,505 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:01:41,506 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 13:01:41,506 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 13:01:41,506 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:01:41,507 INFO L87 Difference]: Start difference. First operand 70 states and 76 transitions. Second operand 5 states. [2018-01-24 13:01:41,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:41,650 INFO L93 Difference]: Finished difference Result 70 states and 76 transitions. [2018-01-24 13:01:41,651 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:01:41,651 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2018-01-24 13:01:41,651 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:41,652 INFO L225 Difference]: With dead ends: 70 [2018-01-24 13:01:41,652 INFO L226 Difference]: Without dead ends: 68 [2018-01-24 13:01:41,653 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:01:41,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-01-24 13:01:41,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 68. [2018-01-24 13:01:41,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68 states. [2018-01-24 13:01:41,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 74 transitions. [2018-01-24 13:01:41,660 INFO L78 Accepts]: Start accepts. Automaton has 68 states and 74 transitions. Word has length 42 [2018-01-24 13:01:41,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:41,661 INFO L432 AbstractCegarLoop]: Abstraction has 68 states and 74 transitions. [2018-01-24 13:01:41,661 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 13:01:41,661 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 74 transitions. [2018-01-24 13:01:41,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 13:01:41,662 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:41,662 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:41,662 INFO L371 AbstractCegarLoop]: === Iteration 9 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:41,663 INFO L82 PathProgramCache]: Analyzing trace with hash -341936468, now seen corresponding path program 1 times [2018-01-24 13:01:41,663 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:41,664 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:41,664 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:41,664 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:41,664 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:41,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:41,681 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:41,776 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:01:41,777 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:01:41,777 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:01:41,777 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:01:41,777 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:01:41,777 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:01:41,777 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:01:41,778 INFO L87 Difference]: Start difference. First operand 68 states and 74 transitions. Second operand 6 states. [2018-01-24 13:01:41,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:41,899 INFO L93 Difference]: Finished difference Result 68 states and 74 transitions. [2018-01-24 13:01:41,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:01:41,900 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 42 [2018-01-24 13:01:41,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:41,901 INFO L225 Difference]: With dead ends: 68 [2018-01-24 13:01:41,901 INFO L226 Difference]: Without dead ends: 67 [2018-01-24 13:01:41,901 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:01:41,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-01-24 13:01:41,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2018-01-24 13:01:41,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-01-24 13:01:41,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 73 transitions. [2018-01-24 13:01:41,910 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 73 transitions. Word has length 42 [2018-01-24 13:01:41,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:41,910 INFO L432 AbstractCegarLoop]: Abstraction has 67 states and 73 transitions. [2018-01-24 13:01:41,910 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:01:41,911 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 73 transitions. [2018-01-24 13:01:41,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 13:01:41,912 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:41,912 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:41,912 INFO L371 AbstractCegarLoop]: === Iteration 10 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:41,912 INFO L82 PathProgramCache]: Analyzing trace with hash -614912991, now seen corresponding path program 2 times [2018-01-24 13:01:41,912 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:41,913 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:41,913 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:41,914 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:41,914 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:41,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:41,930 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:42,095 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:01:42,095 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:42,095 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:42,102 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:01:42,102 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:01:42,116 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:42,129 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:42,130 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:42,132 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:42,218 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 13:01:42,218 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:42,307 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 13:01:42,330 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:42,330 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:01:42,333 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:01:42,333 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:01:42,351 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:42,376 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:42,387 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:42,392 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:42,396 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 13:01:42,396 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:42,421 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 13:01:42,425 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:01:42,425 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6, 6, 6] total 16 [2018-01-24 13:01:42,425 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:01:42,426 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 13:01:42,426 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 13:01:42,426 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=189, Unknown=0, NotChecked=0, Total=240 [2018-01-24 13:01:42,426 INFO L87 Difference]: Start difference. First operand 67 states and 73 transitions. Second operand 12 states. [2018-01-24 13:01:42,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:42,641 INFO L93 Difference]: Finished difference Result 136 states and 150 transitions. [2018-01-24 13:01:42,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 13:01:42,641 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 41 [2018-01-24 13:01:42,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:42,642 INFO L225 Difference]: With dead ends: 136 [2018-01-24 13:01:42,642 INFO L226 Difference]: Without dead ends: 82 [2018-01-24 13:01:42,643 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 176 GetRequests, 154 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=75, Invalid=345, Unknown=0, NotChecked=0, Total=420 [2018-01-24 13:01:42,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-01-24 13:01:42,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 74. [2018-01-24 13:01:42,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-24 13:01:42,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 81 transitions. [2018-01-24 13:01:42,650 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 81 transitions. Word has length 41 [2018-01-24 13:01:42,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:42,650 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 81 transitions. [2018-01-24 13:01:42,650 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 13:01:42,651 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 81 transitions. [2018-01-24 13:01:42,652 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-01-24 13:01:42,652 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:42,652 INFO L322 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:42,652 INFO L371 AbstractCegarLoop]: === Iteration 11 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:42,653 INFO L82 PathProgramCache]: Analyzing trace with hash 1732121728, now seen corresponding path program 1 times [2018-01-24 13:01:42,653 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:42,654 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:42,654 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:01:42,654 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:42,654 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:42,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:42,670 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:42,922 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-01-24 13:01:42,922 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:42,922 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:42,927 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:42,927 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:01:42,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:42,948 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:42,996 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:01:42,996 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:43,093 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:01:43,113 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:43,113 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:01:43,118 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:43,118 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:01:43,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:43,161 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:43,168 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:01:43,168 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:43,204 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:01:43,206 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:01:43,206 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 7, 7, 7, 7] total 22 [2018-01-24 13:01:43,206 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:01:43,206 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 13:01:43,207 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 13:01:43,207 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=378, Unknown=0, NotChecked=0, Total=462 [2018-01-24 13:01:43,207 INFO L87 Difference]: Start difference. First operand 74 states and 81 transitions. Second operand 17 states. [2018-01-24 13:01:43,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:43,471 INFO L93 Difference]: Finished difference Result 144 states and 160 transitions. [2018-01-24 13:01:43,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 13:01:43,471 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 45 [2018-01-24 13:01:43,471 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:43,472 INFO L225 Difference]: With dead ends: 144 [2018-01-24 13:01:43,472 INFO L226 Difference]: Without dead ends: 84 [2018-01-24 13:01:43,473 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 168 SyntacticMatches, 10 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 108 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=116, Invalid=586, Unknown=0, NotChecked=0, Total=702 [2018-01-24 13:01:43,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-01-24 13:01:43,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 79. [2018-01-24 13:01:43,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-01-24 13:01:43,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 87 transitions. [2018-01-24 13:01:43,478 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 87 transitions. Word has length 45 [2018-01-24 13:01:43,478 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:43,478 INFO L432 AbstractCegarLoop]: Abstraction has 79 states and 87 transitions. [2018-01-24 13:01:43,478 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 13:01:43,479 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 87 transitions. [2018-01-24 13:01:43,479 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-01-24 13:01:43,480 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:43,480 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:43,480 INFO L371 AbstractCegarLoop]: === Iteration 12 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:43,480 INFO L82 PathProgramCache]: Analyzing trace with hash -117713403, now seen corresponding path program 3 times [2018-01-24 13:01:43,480 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:43,481 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:43,481 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:43,481 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:43,481 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:43,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:43,497 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:43,849 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 17 proven. 13 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:01:43,849 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:43,849 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:43,854 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:01:43,855 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:01:43,867 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:01:43,877 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:01:43,878 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:43,881 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:43,902 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:01:43,904 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:43,907 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:43,908 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-01-24 13:01:43,981 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 13:01:43,982 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:01:43,982 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:43,984 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,001 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,001 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:20, output treesize:16 [2018-01-24 13:01:44,019 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 13:01:44,021 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,022 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,024 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 13:01:44,025 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,030 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,035 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,035 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:29, output treesize:25 [2018-01-24 13:01:44,080 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 13:01:44,083 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,083 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,084 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,085 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,086 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,086 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,087 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 13:01:44,088 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,106 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,116 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,116 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:38, output treesize:34 [2018-01-24 13:01:44,143 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 13:01:44,146 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,147 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,148 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,149 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,149 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,150 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,151 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,152 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,153 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,154 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,154 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,155 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,156 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 13:01:44,157 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,187 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,195 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,195 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:47, output treesize:43 [2018-01-24 13:01:44,232 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 13:01:44,236 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,237 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,238 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,238 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,239 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,240 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,240 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,241 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,242 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,242 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,243 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,244 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,244 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,245 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,246 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,246 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,247 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 13:01:44,248 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,280 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,289 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,289 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:56, output treesize:52 [2018-01-24 13:01:44,327 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 13:01:44,333 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,334 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,340 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,340 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,341 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,342 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,342 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,343 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,344 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,344 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,361 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,367 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,380 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,383 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,384 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,385 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,386 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,386 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,387 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,388 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,388 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,390 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 13:01:44,391 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,421 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,430 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,431 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:65, output treesize:61 [2018-01-24 13:01:44,463 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 13:01:44,467 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,467 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,468 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,468 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,469 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,470 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,470 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,471 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,471 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,472 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,473 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,473 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,474 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,474 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,475 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,475 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,476 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,476 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,477 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,478 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,478 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,479 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,479 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,480 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,481 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,481 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,482 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,483 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 13:01:44,484 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,524 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,535 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,535 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-01-24 13:01:44,755 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 53 [2018-01-24 13:01:44,762 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,763 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,764 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,765 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,766 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,767 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,767 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,768 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,769 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,769 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,770 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,771 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,771 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,772 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,772 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,773 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,773 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,774 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,775 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,775 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,776 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,776 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,777 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,778 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,778 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,779 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,779 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:44,781 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 7 select indices, 7 select index equivalence classes, 27 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 160 [2018-01-24 13:01:44,781 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,799 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:44,805 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 13:01:44,805 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:90, output treesize:25 [2018-01-24 13:01:44,879 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 10 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 13:01:44,879 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:45,504 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 13:01:45,523 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:45,523 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:01:45,527 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:01:45,527 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:01:45,543 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:01:45,564 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:01:45,587 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:45,592 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:45,595 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:01:45,595 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,598 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,598 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-01-24 13:01:45,722 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 13:01:45,723 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:01:45,723 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,726 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,730 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,730 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:20, output treesize:16 [2018-01-24 13:01:45,771 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 13:01:45,774 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,775 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,776 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 13:01:45,777 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,783 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,790 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,790 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:29, output treesize:25 [2018-01-24 13:01:45,879 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 13:01:45,883 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,884 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,885 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,885 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,886 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,887 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,888 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 13:01:45,889 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,902 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,910 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,910 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:38, output treesize:34 [2018-01-24 13:01:45,957 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 13:01:45,959 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,960 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,960 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,961 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,962 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,962 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,963 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,963 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,964 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,964 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,965 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,966 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:45,966 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 13:01:45,967 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,984 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,990 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:45,990 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:47, output treesize:43 [2018-01-24 13:01:46,040 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 13:01:46,042 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,043 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,043 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,044 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,044 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,045 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,045 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,046 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,046 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,047 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,047 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,048 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,048 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,049 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,050 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,050 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,051 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 13:01:46,051 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:46,072 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:46,080 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:46,080 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:56, output treesize:52 [2018-01-24 13:01:46,133 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 13:01:46,135 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,136 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,137 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,137 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,138 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,138 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,139 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,140 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,140 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,141 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,142 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,142 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,143 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,144 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,144 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,145 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,146 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,146 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,147 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,147 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,148 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,149 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 13:01:46,150 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:46,178 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:46,187 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:46,187 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:65, output treesize:61 [2018-01-24 13:01:46,253 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 13:01:46,256 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,257 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,257 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,258 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,259 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,259 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,260 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,261 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,261 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,262 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,262 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,263 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,263 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,264 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,265 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,265 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,266 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,267 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,267 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,268 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,268 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,269 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,270 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,270 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,271 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,272 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,272 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,273 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 13:01:46,274 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:46,324 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:46,335 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:46,335 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-01-24 13:01:46,619 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 41 [2018-01-24 13:01:46,622 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,622 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,623 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,623 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,624 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,624 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:46,625 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 27 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 43 [2018-01-24 13:01:46,625 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:46,633 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:46,638 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 13:01:46,638 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:78, output treesize:25 [2018-01-24 13:01:46,735 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 10 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 13:01:46,736 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:47,276 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 13:01:47,278 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:01:47,278 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 17, 10, 17, 10] total 54 [2018-01-24 13:01:47,278 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:01:47,279 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 13:01:47,279 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 13:01:47,280 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=2521, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 13:01:47,280 INFO L87 Difference]: Start difference. First operand 79 states and 87 transitions. Second operand 30 states. [2018-01-24 13:01:49,254 WARN L146 SmtUtils]: Spent 440ms on a formula simplification. DAG size of input: 90 DAG size of output 75 [2018-01-24 13:01:49,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:49,374 INFO L93 Difference]: Finished difference Result 113 states and 126 transitions. [2018-01-24 13:01:49,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 13:01:49,375 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 49 [2018-01-24 13:01:49,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:49,376 INFO L225 Difference]: With dead ends: 113 [2018-01-24 13:01:49,376 INFO L226 Difference]: Without dead ends: 77 [2018-01-24 13:01:49,378 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 235 GetRequests, 136 SyntacticMatches, 28 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2186 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=795, Invalid=4461, Unknown=0, NotChecked=0, Total=5256 [2018-01-24 13:01:49,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-01-24 13:01:49,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2018-01-24 13:01:49,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-01-24 13:01:49,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 84 transitions. [2018-01-24 13:01:49,385 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 84 transitions. Word has length 49 [2018-01-24 13:01:49,385 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:49,386 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 84 transitions. [2018-01-24 13:01:49,386 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 13:01:49,386 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 84 transitions. [2018-01-24 13:01:49,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 13:01:49,387 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:49,387 INFO L322 BasicCegarLoop]: trace histogram [4, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:49,387 INFO L371 AbstractCegarLoop]: === Iteration 13 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:49,387 INFO L82 PathProgramCache]: Analyzing trace with hash 2106198684, now seen corresponding path program 1 times [2018-01-24 13:01:49,388 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:49,388 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:49,388 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:01:49,389 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:49,389 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:49,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:49,399 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:49,466 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-01-24 13:01:49,466 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:01:49,466 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:01:49,466 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:01:49,466 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 13:01:49,466 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 13:01:49,467 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:01:49,467 INFO L87 Difference]: Start difference. First operand 77 states and 84 transitions. Second operand 5 states. [2018-01-24 13:01:49,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:49,534 INFO L93 Difference]: Finished difference Result 86 states and 93 transitions. [2018-01-24 13:01:49,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:01:49,535 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2018-01-24 13:01:49,535 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:49,536 INFO L225 Difference]: With dead ends: 86 [2018-01-24 13:01:49,536 INFO L226 Difference]: Without dead ends: 83 [2018-01-24 13:01:49,536 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:01:49,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-01-24 13:01:49,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 82. [2018-01-24 13:01:49,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-24 13:01:49,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 89 transitions. [2018-01-24 13:01:49,542 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 89 transitions. Word has length 52 [2018-01-24 13:01:49,543 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:49,543 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 89 transitions. [2018-01-24 13:01:49,543 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 13:01:49,543 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 89 transitions. [2018-01-24 13:01:49,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 13:01:49,543 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:49,544 INFO L322 BasicCegarLoop]: trace histogram [4, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:49,544 INFO L371 AbstractCegarLoop]: === Iteration 14 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:49,544 INFO L82 PathProgramCache]: Analyzing trace with hash 1604645521, now seen corresponding path program 1 times [2018-01-24 13:01:49,544 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:49,545 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:49,545 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:49,545 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:49,545 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:49,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:49,557 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:50,103 WARN L146 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 29 DAG size of output 21 [2018-01-24 13:01:50,270 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-01-24 13:01:50,270 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:50,270 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:50,279 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:50,280 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:01:50,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:50,310 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:50,396 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 13:01:50,396 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:50,530 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 13:01:50,550 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:50,550 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:01:50,553 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:50,553 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:01:50,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:50,596 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:50,601 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 13:01:50,602 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:50,636 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 13:01:50,638 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:01:50,638 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8, 8, 8] total 25 [2018-01-24 13:01:50,638 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:01:50,638 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 13:01:50,639 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 13:01:50,639 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=490, Unknown=0, NotChecked=0, Total=600 [2018-01-24 13:01:50,639 INFO L87 Difference]: Start difference. First operand 82 states and 89 transitions. Second operand 19 states. [2018-01-24 13:01:50,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:50,998 INFO L93 Difference]: Finished difference Result 151 states and 166 transitions. [2018-01-24 13:01:50,998 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 13:01:50,998 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 52 [2018-01-24 13:01:50,999 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:50,999 INFO L225 Difference]: With dead ends: 151 [2018-01-24 13:01:50,999 INFO L226 Difference]: Without dead ends: 84 [2018-01-24 13:01:51,000 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 194 SyntacticMatches, 8 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 153 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=174, Invalid=882, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 13:01:51,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-01-24 13:01:51,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 81. [2018-01-24 13:01:51,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-01-24 13:01:51,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 88 transitions. [2018-01-24 13:01:51,006 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 88 transitions. Word has length 52 [2018-01-24 13:01:51,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:51,006 INFO L432 AbstractCegarLoop]: Abstraction has 81 states and 88 transitions. [2018-01-24 13:01:51,006 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 13:01:51,007 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 88 transitions. [2018-01-24 13:01:51,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-01-24 13:01:51,007 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:51,008 INFO L322 BasicCegarLoop]: trace histogram [5, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:51,008 INFO L371 AbstractCegarLoop]: === Iteration 15 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:51,008 INFO L82 PathProgramCache]: Analyzing trace with hash -544800124, now seen corresponding path program 1 times [2018-01-24 13:01:51,008 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:51,008 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:51,009 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:51,009 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:51,009 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:51,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:51,021 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:51,200 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-01-24 13:01:51,201 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:51,201 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:51,212 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:51,212 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:01:51,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:51,242 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:51,310 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:01:51,311 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:51,445 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:01:51,465 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:51,465 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:01:51,468 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:51,468 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:01:51,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:51,511 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:51,516 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:01:51,516 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:51,542 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:01:51,544 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:01:51,544 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 23 [2018-01-24 13:01:51,544 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:01:51,544 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 13:01:51,544 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 13:01:51,545 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=124, Invalid=382, Unknown=0, NotChecked=0, Total=506 [2018-01-24 13:01:51,545 INFO L87 Difference]: Start difference. First operand 81 states and 88 transitions. Second operand 16 states. [2018-01-24 13:01:51,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:51,695 INFO L93 Difference]: Finished difference Result 148 states and 162 transitions. [2018-01-24 13:01:51,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 13:01:51,695 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 56 [2018-01-24 13:01:51,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:51,696 INFO L225 Difference]: With dead ends: 148 [2018-01-24 13:01:51,696 INFO L226 Difference]: Without dead ends: 80 [2018-01-24 13:01:51,697 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 242 GetRequests, 208 SyntacticMatches, 10 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=143, Invalid=507, Unknown=0, NotChecked=0, Total=650 [2018-01-24 13:01:51,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-24 13:01:51,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 77. [2018-01-24 13:01:51,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-01-24 13:01:51,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 83 transitions. [2018-01-24 13:01:51,703 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 83 transitions. Word has length 56 [2018-01-24 13:01:51,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:51,703 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 83 transitions. [2018-01-24 13:01:51,703 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 13:01:51,703 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 83 transitions. [2018-01-24 13:01:51,704 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-01-24 13:01:51,704 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:51,704 INFO L322 BasicCegarLoop]: trace histogram [6, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:51,705 INFO L371 AbstractCegarLoop]: === Iteration 16 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:51,705 INFO L82 PathProgramCache]: Analyzing trace with hash -1454707584, now seen corresponding path program 1 times [2018-01-24 13:01:51,705 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:51,706 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:51,706 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:51,706 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:51,706 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:51,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:51,723 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:51,949 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 13:01:51,949 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:51,949 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:51,956 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:51,957 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:01:51,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:51,980 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:52,042 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:01:52,042 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:52,264 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:01:52,297 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:52,297 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:01:52,300 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:52,300 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:01:52,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:52,349 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:52,355 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:01:52,355 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:52,397 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:01:52,398 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:01:52,398 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10, 10, 10, 10] total 25 [2018-01-24 13:01:52,398 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:01:52,399 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 13:01:52,399 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 13:01:52,399 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=440, Unknown=0, NotChecked=0, Total=600 [2018-01-24 13:01:52,400 INFO L87 Difference]: Start difference. First operand 77 states and 83 transitions. Second operand 17 states. [2018-01-24 13:01:52,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:52,608 INFO L93 Difference]: Finished difference Result 150 states and 163 transitions. [2018-01-24 13:01:52,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 13:01:52,608 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 60 [2018-01-24 13:01:52,608 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:52,609 INFO L225 Difference]: With dead ends: 150 [2018-01-24 13:01:52,609 INFO L226 Difference]: Without dead ends: 87 [2018-01-24 13:01:52,609 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 222 SyntacticMatches, 8 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 106 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=191, Invalid=621, Unknown=0, NotChecked=0, Total=812 [2018-01-24 13:01:52,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-01-24 13:01:52,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 84. [2018-01-24 13:01:52,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-01-24 13:01:52,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 90 transitions. [2018-01-24 13:01:52,617 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 90 transitions. Word has length 60 [2018-01-24 13:01:52,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:52,617 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 90 transitions. [2018-01-24 13:01:52,617 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 13:01:52,617 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 90 transitions. [2018-01-24 13:01:52,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-01-24 13:01:52,618 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:52,618 INFO L322 BasicCegarLoop]: trace histogram [7, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:52,618 INFO L371 AbstractCegarLoop]: === Iteration 17 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:52,618 INFO L82 PathProgramCache]: Analyzing trace with hash -374403177, now seen corresponding path program 2 times [2018-01-24 13:01:52,618 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:52,619 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:52,619 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:01:52,619 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:52,619 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:52,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:52,635 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:52,817 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 13:01:52,817 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:52,817 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:52,823 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:01:52,823 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:01:52,841 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:52,854 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:52,856 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:52,857 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:52,942 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 13:01:52,943 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:53,113 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 13:01:53,133 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:53,133 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:01:53,136 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:01:53,136 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:01:53,159 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:53,192 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:53,208 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:53,213 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:53,217 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 13:01:53,217 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:53,263 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 13:01:53,265 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:01:53,265 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 11, 11, 11] total 28 [2018-01-24 13:01:53,265 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:01:53,265 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 13:01:53,266 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 13:01:53,266 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=559, Unknown=0, NotChecked=0, Total=756 [2018-01-24 13:01:53,266 INFO L87 Difference]: Start difference. First operand 84 states and 90 transitions. Second operand 19 states. [2018-01-24 13:01:53,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:53,477 INFO L93 Difference]: Finished difference Result 154 states and 166 transitions. [2018-01-24 13:01:53,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 13:01:53,477 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 67 [2018-01-24 13:01:53,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:53,478 INFO L225 Difference]: With dead ends: 154 [2018-01-24 13:01:53,478 INFO L226 Difference]: Without dead ends: 85 [2018-01-24 13:01:53,479 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 288 GetRequests, 250 SyntacticMatches, 8 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 123 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=229, Invalid=763, Unknown=0, NotChecked=0, Total=992 [2018-01-24 13:01:53,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-01-24 13:01:53,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-01-24 13:01:53,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-01-24 13:01:53,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 90 transitions. [2018-01-24 13:01:53,486 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 90 transitions. Word has length 67 [2018-01-24 13:01:53,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:53,486 INFO L432 AbstractCegarLoop]: Abstraction has 85 states and 90 transitions. [2018-01-24 13:01:53,486 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 13:01:53,486 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 90 transitions. [2018-01-24 13:01:53,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-01-24 13:01:53,486 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:53,487 INFO L322 BasicCegarLoop]: trace histogram [8, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:53,487 INFO L371 AbstractCegarLoop]: === Iteration 18 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:53,487 INFO L82 PathProgramCache]: Analyzing trace with hash -1696068192, now seen corresponding path program 3 times [2018-01-24 13:01:53,487 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:53,487 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:53,487 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:01:53,488 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:53,488 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:53,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:53,503 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:53,779 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-01-24 13:01:53,779 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:53,779 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:53,784 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:01:53,784 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:01:53,798 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:01:53,811 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:01:53,822 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:01:53,824 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:53,826 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:53,844 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 13:01:53,845 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:01:53,845 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:53,846 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:53,848 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:53,849 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:15, output treesize:11 [2018-01-24 13:01:53,861 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 13:01:53,862 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,863 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,863 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 13:01:53,863 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:53,867 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:53,870 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:53,870 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:20 [2018-01-24 13:01:53,885 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 13:01:53,887 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,888 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,888 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,889 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,889 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,890 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,891 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 13:01:53,891 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:53,901 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:53,906 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:53,906 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:33, output treesize:29 [2018-01-24 13:01:53,926 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 13:01:53,932 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,933 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,934 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,935 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,935 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,936 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,937 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,938 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,938 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,939 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,939 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,940 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,941 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 13:01:53,941 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:53,957 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:53,963 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:53,964 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-01-24 13:01:53,985 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 13:01:53,991 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,992 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:53,992 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,003 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,004 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,004 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,005 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,005 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,006 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,006 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,007 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,007 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,008 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,008 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,009 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,010 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,010 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 13:01:54,011 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:54,032 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:54,039 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:54,039 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:51, output treesize:47 [2018-01-24 13:01:54,063 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 13:01:54,066 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,066 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,067 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,067 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,068 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,069 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,069 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,070 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,070 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,071 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,071 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,072 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,073 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,073 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,074 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,074 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,075 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,076 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,076 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,077 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,078 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,078 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 13:01:54,079 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:54,110 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:54,118 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:54,118 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:60, output treesize:56 [2018-01-24 13:01:54,146 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 13:01:54,148 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,149 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,150 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,150 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,151 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,151 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,152 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,153 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,153 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,154 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,154 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,155 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,156 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,156 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,157 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,157 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,158 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,158 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,159 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,159 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,160 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,160 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,161 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,162 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,162 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,163 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,163 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:54,164 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 13:01:54,165 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:54,208 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:54,217 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:54,217 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:69, output treesize:65 [2018-01-24 13:01:54,475 WARN L307 Elim1Store]: Array PQE input equivalent to false [2018-01-24 13:01:54,476 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:54,476 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:54,476 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:121, output treesize:1 [2018-01-24 13:01:54,500 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 13:01:54,500 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:54,695 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 13:01:54,730 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:54,730 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:01:54,735 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:01:54,735 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:01:54,773 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:01:54,819 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:01:54,946 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:01:54,988 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:54,996 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:55,008 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 13:01:55,010 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 13:01:55,010 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,013 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,016 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,016 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:15, output treesize:11 [2018-01-24 13:01:55,020 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 13:01:55,021 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,022 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,022 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 13:01:55,023 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,027 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,030 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,031 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:20 [2018-01-24 13:01:55,033 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 13:01:55,035 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,036 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,036 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,037 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,037 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,038 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,038 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 13:01:55,039 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,048 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,053 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,053 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:33, output treesize:29 [2018-01-24 13:01:55,057 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 13:01:55,059 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,059 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,060 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,060 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,061 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,062 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,062 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,063 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,063 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,064 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,065 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,065 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,066 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 13:01:55,066 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,087 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,093 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,093 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-01-24 13:01:55,097 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 13:01:55,100 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,100 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,101 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,102 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,102 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,103 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,103 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,104 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,105 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,105 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,106 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,106 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,107 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,108 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,108 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,109 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,110 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 13:01:55,110 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,136 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,144 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,144 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:51, output treesize:47 [2018-01-24 13:01:55,147 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 13:01:55,150 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,150 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,151 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,152 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,152 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,153 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,154 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,154 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,155 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,156 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,156 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,157 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,158 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,158 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,159 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,160 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,161 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,161 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,162 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,163 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,163 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,164 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 13:01:55,165 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,200 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,210 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,210 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:60, output treesize:56 [2018-01-24 13:01:55,214 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 13:01:55,217 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,218 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,219 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,219 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,220 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,220 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,221 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,223 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,224 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,225 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,225 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,226 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,226 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,227 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,228 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,228 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,229 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,229 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,230 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,231 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,231 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,232 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,233 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,233 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,234 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,234 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,235 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:01:55,236 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 13:01:55,237 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,282 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,293 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:01:55,293 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:69, output treesize:65 [2018-01-24 13:01:55,627 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 13:01:55,628 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:55,804 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 13:01:55,806 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:01:55,806 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 17, 8, 17, 8] total 42 [2018-01-24 13:01:55,806 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:01:55,806 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 13:01:55,806 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 13:01:55,807 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=213, Invalid=1509, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 13:01:55,807 INFO L87 Difference]: Start difference. First operand 85 states and 90 transitions. Second operand 28 states. [2018-01-24 13:01:56,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:56,769 INFO L93 Difference]: Finished difference Result 130 states and 139 transitions. [2018-01-24 13:01:56,769 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 13:01:56,769 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 74 [2018-01-24 13:01:56,769 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:56,770 INFO L225 Difference]: With dead ends: 130 [2018-01-24 13:01:56,770 INFO L226 Difference]: Without dead ends: 94 [2018-01-24 13:01:56,772 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 248 SyntacticMatches, 28 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1458 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=476, Invalid=3556, Unknown=0, NotChecked=0, Total=4032 [2018-01-24 13:01:56,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-01-24 13:01:56,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 91. [2018-01-24 13:01:56,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-01-24 13:01:56,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 95 transitions. [2018-01-24 13:01:56,781 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 95 transitions. Word has length 74 [2018-01-24 13:01:56,781 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:56,781 INFO L432 AbstractCegarLoop]: Abstraction has 91 states and 95 transitions. [2018-01-24 13:01:56,781 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 13:01:56,781 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 95 transitions. [2018-01-24 13:01:56,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-01-24 13:01:56,782 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:56,782 INFO L322 BasicCegarLoop]: trace histogram [8, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:56,782 INFO L371 AbstractCegarLoop]: === Iteration 19 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:56,783 INFO L82 PathProgramCache]: Analyzing trace with hash 1151371872, now seen corresponding path program 4 times [2018-01-24 13:01:56,783 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:56,783 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:56,783 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:01:56,783 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:56,784 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:56,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:56,802 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:56,976 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:56,976 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:56,976 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:57,000 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:01:57,000 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:01:57,060 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:57,063 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:57,199 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:57,199 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:57,484 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:57,505 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:57,505 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:01:57,508 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:01:57,508 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:01:57,601 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:57,606 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:57,612 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:57,613 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:57,654 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:57,656 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:01:57,656 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 32 [2018-01-24 13:01:57,656 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:01:57,656 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 13:01:57,657 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 13:01:57,657 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=357, Invalid=635, Unknown=0, NotChecked=0, Total=992 [2018-01-24 13:01:57,657 INFO L87 Difference]: Start difference. First operand 91 states and 95 transitions. Second operand 22 states. [2018-01-24 13:01:57,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:57,698 INFO L93 Difference]: Finished difference Result 164 states and 172 transitions. [2018-01-24 13:01:57,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 13:01:57,698 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 86 [2018-01-24 13:01:57,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:57,699 INFO L225 Difference]: With dead ends: 164 [2018-01-24 13:01:57,699 INFO L226 Difference]: Without dead ends: 92 [2018-01-24 13:01:57,700 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 355 GetRequests, 322 SyntacticMatches, 2 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 374 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=380, Invalid=676, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 13:01:57,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2018-01-24 13:01:57,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 92. [2018-01-24 13:01:57,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-01-24 13:01:57,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 96 transitions. [2018-01-24 13:01:57,705 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 96 transitions. Word has length 86 [2018-01-24 13:01:57,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:57,706 INFO L432 AbstractCegarLoop]: Abstraction has 92 states and 96 transitions. [2018-01-24 13:01:57,706 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 13:01:57,706 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 96 transitions. [2018-01-24 13:01:57,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 13:01:57,706 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:57,706 INFO L322 BasicCegarLoop]: trace histogram [9, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:57,707 INFO L371 AbstractCegarLoop]: === Iteration 20 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:57,707 INFO L82 PathProgramCache]: Analyzing trace with hash -1429474957, now seen corresponding path program 5 times [2018-01-24 13:01:57,707 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:57,707 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:57,707 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:01:57,707 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:57,708 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:57,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:57,726 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:57,865 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:57,865 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:57,865 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:57,873 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:01:57,874 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:01:57,881 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:57,887 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:57,891 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:57,898 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:57,908 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:57,924 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:57,928 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:57,930 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:57,999 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:57,999 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:58,257 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:58,277 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:58,278 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:01:58,281 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:01:58,281 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:01:58,292 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:58,295 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:58,309 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:58,337 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:58,435 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:58,904 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:01:58,929 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:58,935 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:58,941 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:58,941 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:58,993 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:58,995 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:01:58,995 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 35 [2018-01-24 13:01:58,995 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:01:58,996 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 13:01:58,996 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 13:01:58,996 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=426, Invalid=764, Unknown=0, NotChecked=0, Total=1190 [2018-01-24 13:01:58,996 INFO L87 Difference]: Start difference. First operand 92 states and 96 transitions. Second operand 24 states. [2018-01-24 13:01:59,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:01:59,063 INFO L93 Difference]: Finished difference Result 165 states and 173 transitions. [2018-01-24 13:01:59,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 13:01:59,063 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 87 [2018-01-24 13:01:59,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:01:59,064 INFO L225 Difference]: With dead ends: 165 [2018-01-24 13:01:59,064 INFO L226 Difference]: Without dead ends: 93 [2018-01-24 13:01:59,064 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 360 GetRequests, 324 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 457 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=451, Invalid=809, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 13:01:59,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-01-24 13:01:59,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2018-01-24 13:01:59,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-01-24 13:01:59,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 97 transitions. [2018-01-24 13:01:59,070 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 97 transitions. Word has length 87 [2018-01-24 13:01:59,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:01:59,070 INFO L432 AbstractCegarLoop]: Abstraction has 93 states and 97 transitions. [2018-01-24 13:01:59,071 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 13:01:59,071 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 97 transitions. [2018-01-24 13:01:59,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-24 13:01:59,071 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:01:59,072 INFO L322 BasicCegarLoop]: trace histogram [10, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:01:59,072 INFO L371 AbstractCegarLoop]: === Iteration 21 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:01:59,072 INFO L82 PathProgramCache]: Analyzing trace with hash 168651968, now seen corresponding path program 6 times [2018-01-24 13:01:59,072 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:01:59,072 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:59,073 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:01:59,073 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:01:59,073 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:01:59,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:01:59,086 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:01:59,373 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:59,373 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:59,373 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:01:59,382 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:01:59,382 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:01:59,400 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:01:59,412 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:01:59,423 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:01:59,450 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:01:59,492 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:01:59,611 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:01:59,613 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:01:59,616 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:01:59,689 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:59,689 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:01:59,904 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:01:59,935 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:01:59,935 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:01:59,939 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:01:59,939 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:01:59,967 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:01:59,993 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:02:00,040 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:02:00,294 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:02:00,922 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:02:02,521 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:02:02,553 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:02:02,559 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:02:02,569 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:02,569 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:02:02,615 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:02,617 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:02:02,617 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 38 [2018-01-24 13:02:02,617 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:02:02,618 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 13:02:02,618 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 13:02:02,618 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=501, Invalid=905, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 13:02:02,618 INFO L87 Difference]: Start difference. First operand 93 states and 97 transitions. Second operand 26 states. [2018-01-24 13:02:02,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:02:02,655 INFO L93 Difference]: Finished difference Result 166 states and 174 transitions. [2018-01-24 13:02:02,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 13:02:02,655 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 88 [2018-01-24 13:02:02,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:02:02,656 INFO L225 Difference]: With dead ends: 166 [2018-01-24 13:02:02,656 INFO L226 Difference]: Without dead ends: 94 [2018-01-24 13:02:02,657 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 365 GetRequests, 326 SyntacticMatches, 2 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 548 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=528, Invalid=954, Unknown=0, NotChecked=0, Total=1482 [2018-01-24 13:02:02,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-01-24 13:02:02,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 94. [2018-01-24 13:02:02,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-01-24 13:02:02,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 98 transitions. [2018-01-24 13:02:02,665 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 98 transitions. Word has length 88 [2018-01-24 13:02:02,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:02:02,666 INFO L432 AbstractCegarLoop]: Abstraction has 94 states and 98 transitions. [2018-01-24 13:02:02,666 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 13:02:02,666 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 98 transitions. [2018-01-24 13:02:02,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-01-24 13:02:02,667 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:02:02,667 INFO L322 BasicCegarLoop]: trace histogram [11, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:02:02,667 INFO L371 AbstractCegarLoop]: === Iteration 22 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:02:02,667 INFO L82 PathProgramCache]: Analyzing trace with hash -1829020909, now seen corresponding path program 7 times [2018-01-24 13:02:02,668 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:02:02,668 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:02:02,668 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:02:02,668 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:02:02,669 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:02:02,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:02:02,687 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:02:02,896 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:02,896 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:02:02,896 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:02:02,901 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:02:02,902 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:02:02,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:02:02,935 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:02:03,022 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:03,022 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:02:03,539 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:03,559 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:02:03,559 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:02:03,566 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:02:03,566 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:02:03,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:02:03,633 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:02:03,643 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:03,643 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:02:03,718 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:03,720 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:02:03,720 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 41 [2018-01-24 13:02:03,720 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:02:03,720 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 13:02:03,720 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 13:02:03,721 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=582, Invalid=1058, Unknown=0, NotChecked=0, Total=1640 [2018-01-24 13:02:03,721 INFO L87 Difference]: Start difference. First operand 94 states and 98 transitions. Second operand 28 states. [2018-01-24 13:02:03,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:02:03,858 INFO L93 Difference]: Finished difference Result 167 states and 175 transitions. [2018-01-24 13:02:03,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 13:02:03,859 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 89 [2018-01-24 13:02:03,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:02:03,860 INFO L225 Difference]: With dead ends: 167 [2018-01-24 13:02:03,860 INFO L226 Difference]: Without dead ends: 95 [2018-01-24 13:02:03,861 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 370 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 647 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=611, Invalid=1111, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 13:02:03,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2018-01-24 13:02:03,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2018-01-24 13:02:03,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-01-24 13:02:03,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 99 transitions. [2018-01-24 13:02:03,867 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 99 transitions. Word has length 89 [2018-01-24 13:02:03,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:02:03,867 INFO L432 AbstractCegarLoop]: Abstraction has 95 states and 99 transitions. [2018-01-24 13:02:03,867 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 13:02:03,868 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 99 transitions. [2018-01-24 13:02:03,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-01-24 13:02:03,868 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:02:03,868 INFO L322 BasicCegarLoop]: trace histogram [12, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:02:03,868 INFO L371 AbstractCegarLoop]: === Iteration 23 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:02:03,869 INFO L82 PathProgramCache]: Analyzing trace with hash 667629344, now seen corresponding path program 8 times [2018-01-24 13:02:03,869 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:02:03,869 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:02:03,869 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:02:03,869 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:02:03,869 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:02:03,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:02:03,883 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:02:04,041 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:04,041 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:02:04,041 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:02:04,047 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:02:04,047 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:02:04,062 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:02:04,077 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:02:04,079 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:02:04,082 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:02:04,165 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:04,165 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:02:04,422 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:04,442 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:02:04,442 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:02:04,445 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:02:04,445 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:02:04,469 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:02:04,509 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:02:04,531 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:02:04,537 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:02:04,550 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:04,550 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:02:04,613 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:04,614 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:02:04,614 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 44 [2018-01-24 13:02:04,615 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:02:04,615 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 13:02:04,615 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 13:02:04,615 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=669, Invalid=1223, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 13:02:04,616 INFO L87 Difference]: Start difference. First operand 95 states and 99 transitions. Second operand 30 states. [2018-01-24 13:02:04,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:02:04,661 INFO L93 Difference]: Finished difference Result 168 states and 176 transitions. [2018-01-24 13:02:04,661 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 13:02:04,661 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 90 [2018-01-24 13:02:04,661 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:02:04,662 INFO L225 Difference]: With dead ends: 168 [2018-01-24 13:02:04,662 INFO L226 Difference]: Without dead ends: 96 [2018-01-24 13:02:04,663 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 375 GetRequests, 330 SyntacticMatches, 2 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 754 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=700, Invalid=1280, Unknown=0, NotChecked=0, Total=1980 [2018-01-24 13:02:04,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-01-24 13:02:04,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 96. [2018-01-24 13:02:04,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-01-24 13:02:04,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 100 transitions. [2018-01-24 13:02:04,671 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 100 transitions. Word has length 90 [2018-01-24 13:02:04,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:02:04,672 INFO L432 AbstractCegarLoop]: Abstraction has 96 states and 100 transitions. [2018-01-24 13:02:04,672 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 13:02:04,672 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 100 transitions. [2018-01-24 13:02:04,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-01-24 13:02:04,673 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:02:04,673 INFO L322 BasicCegarLoop]: trace histogram [13, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:02:04,673 INFO L371 AbstractCegarLoop]: === Iteration 24 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 13:02:04,673 INFO L82 PathProgramCache]: Analyzing trace with hash 754375859, now seen corresponding path program 9 times [2018-01-24 13:02:04,673 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:02:04,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:02:04,674 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:02:04,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:02:04,674 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:02:04,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:02:04,693 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:02:04,957 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:04,957 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:02:04,957 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:02:04,962 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:02:04,962 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:02:04,981 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:04,998 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:05,015 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:05,032 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:05,063 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:05,099 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:05,279 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:05,360 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:05,362 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:02:05,365 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:02:05,480 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:05,480 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:02:05,768 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 13:02:05,788 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:02:05,789 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:02:05,791 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:02:05,792 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:02:05,818 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:05,847 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:05,920 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:06,080 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:18,096 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:02:30,143 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown