java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/loop-acceleration/array3_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 13:48:08,520 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 13:48:08,522 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 13:48:08,538 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 13:48:08,538 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 13:48:08,539 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 13:48:08,540 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 13:48:08,541 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 13:48:08,542 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 13:48:08,543 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 13:48:08,544 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 13:48:08,545 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 13:48:08,546 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 13:48:08,547 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 13:48:08,548 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 13:48:08,551 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 13:48:08,553 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 13:48:08,555 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 13:48:08,556 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 13:48:08,558 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 13:48:08,560 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-01-24 13:48:08,566 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 13:48:08,566 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 13:48:08,567 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf [2018-01-24 13:48:08,575 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 13:48:08,575 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 13:48:08,576 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 13:48:08,576 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 13:48:08,576 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 13:48:08,577 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 13:48:08,577 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 13:48:08,577 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 13:48:08,577 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 13:48:08,577 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 13:48:08,578 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 13:48:08,578 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 13:48:08,578 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 13:48:08,578 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 13:48:08,578 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 13:48:08,578 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 13:48:08,578 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 13:48:08,578 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 13:48:08,579 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 13:48:08,579 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 13:48:08,579 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 13:48:08,579 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 13:48:08,579 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 13:48:08,580 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:48:08,580 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 13:48:08,580 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 13:48:08,580 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 13:48:08,580 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 13:48:08,581 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-01-24 13:48:08,581 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 13:48:08,581 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 13:48:08,581 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 13:48:08,582 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 13:48:08,582 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 13:48:08,614 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 13:48:08,625 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 13:48:08,628 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 13:48:08,629 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 13:48:08,629 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 13:48:08,630 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/array3_false-valid-deref.i [2018-01-24 13:48:08,744 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 13:48:08,748 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 13:48:08,749 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 13:48:08,749 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 13:48:08,754 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 13:48:08,755 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:48:08" (1/1) ... [2018-01-24 13:48:08,758 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@69e4c894 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:48:08, skipping insertion in model container [2018-01-24 13:48:08,758 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:48:08" (1/1) ... [2018-01-24 13:48:08,772 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:48:08,785 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:48:08,894 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:48:08,905 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:48:08,910 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:48:08 WrapperNode [2018-01-24 13:48:08,910 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 13:48:08,911 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 13:48:08,911 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 13:48:08,911 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 13:48:08,922 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:48:08" (1/1) ... [2018-01-24 13:48:08,922 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:48:08" (1/1) ... [2018-01-24 13:48:08,929 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:48:08" (1/1) ... [2018-01-24 13:48:08,929 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:48:08" (1/1) ... [2018-01-24 13:48:08,931 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:48:08" (1/1) ... [2018-01-24 13:48:08,934 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:48:08" (1/1) ... [2018-01-24 13:48:08,935 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:48:08" (1/1) ... [2018-01-24 13:48:08,936 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 13:48:08,936 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 13:48:08,936 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 13:48:08,936 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 13:48:08,937 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:48:08" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:48:08,984 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 13:48:08,984 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 13:48:08,984 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 13:48:08,984 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 13:48:08,985 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 13:48:08,985 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 13:48:08,985 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 13:48:08,985 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 13:48:08,985 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 13:48:08,985 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 13:48:09,110 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 13:48:09,125 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:48:09 BoogieIcfgContainer [2018-01-24 13:48:09,125 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 13:48:09,126 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 13:48:09,126 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 13:48:09,127 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 13:48:09,128 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 01:48:08" (1/3) ... [2018-01-24 13:48:09,129 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@423f30ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:48:09, skipping insertion in model container [2018-01-24 13:48:09,129 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:48:08" (2/3) ... [2018-01-24 13:48:09,129 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@423f30ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:48:09, skipping insertion in model container [2018-01-24 13:48:09,129 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:48:09" (3/3) ... [2018-01-24 13:48:09,131 INFO L105 eAbstractionObserver]: Analyzing ICFG array3_false-valid-deref.i [2018-01-24 13:48:09,137 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 13:48:09,144 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2018-01-24 13:48:09,178 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 13:48:09,178 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 13:48:09,178 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 13:48:09,178 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 13:48:09,179 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 13:48:09,179 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 13:48:09,179 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 13:48:09,179 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 13:48:09,180 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 13:48:09,196 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states. [2018-01-24 13:48:09,201 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 13:48:09,201 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:09,202 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:09,202 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:09,206 INFO L82 PathProgramCache]: Analyzing trace with hash 1213833872, now seen corresponding path program 1 times [2018-01-24 13:48:09,208 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:09,248 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:09,248 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:09,248 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:09,248 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:09,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:09,281 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:09,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:48:09,415 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:48:09,415 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 13:48:09,416 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:48:09,419 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 13:48:09,434 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 13:48:09,435 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 13:48:09,438 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 4 states. [2018-01-24 13:48:09,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:09,566 INFO L93 Difference]: Finished difference Result 69 states and 95 transitions. [2018-01-24 13:48:09,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 13:48:09,568 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 8 [2018-01-24 13:48:09,568 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:09,574 INFO L225 Difference]: With dead ends: 69 [2018-01-24 13:48:09,574 INFO L226 Difference]: Without dead ends: 35 [2018-01-24 13:48:09,577 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 13:48:09,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-01-24 13:48:09,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 31. [2018-01-24 13:48:09,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-01-24 13:48:09,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 32 transitions. [2018-01-24 13:48:09,667 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 32 transitions. Word has length 8 [2018-01-24 13:48:09,667 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:09,667 INFO L432 AbstractCegarLoop]: Abstraction has 31 states and 32 transitions. [2018-01-24 13:48:09,667 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 13:48:09,668 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 32 transitions. [2018-01-24 13:48:09,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-01-24 13:48:09,668 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:09,668 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:09,669 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:09,669 INFO L82 PathProgramCache]: Analyzing trace with hash -863334142, now seen corresponding path program 1 times [2018-01-24 13:48:09,669 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:09,670 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:09,670 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:09,670 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:09,670 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:09,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:09,685 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:09,773 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:48:09,773 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:48:09,774 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:48:09,774 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:48:09,775 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:48:09,776 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:48:09,776 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:48:09,776 INFO L87 Difference]: Start difference. First operand 31 states and 32 transitions. Second operand 6 states. [2018-01-24 13:48:09,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:09,865 INFO L93 Difference]: Finished difference Result 35 states and 36 transitions. [2018-01-24 13:48:09,865 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:48:09,865 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 16 [2018-01-24 13:48:09,866 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:09,866 INFO L225 Difference]: With dead ends: 35 [2018-01-24 13:48:09,867 INFO L226 Difference]: Without dead ends: 34 [2018-01-24 13:48:09,867 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:48:09,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-01-24 13:48:09,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 29. [2018-01-24 13:48:09,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2018-01-24 13:48:09,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 30 transitions. [2018-01-24 13:48:09,874 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 30 transitions. Word has length 16 [2018-01-24 13:48:09,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:09,874 INFO L432 AbstractCegarLoop]: Abstraction has 29 states and 30 transitions. [2018-01-24 13:48:09,874 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:48:09,874 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 30 transitions. [2018-01-24 13:48:09,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-24 13:48:09,875 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:09,876 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:09,876 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:09,876 INFO L82 PathProgramCache]: Analyzing trace with hash -1135364244, now seen corresponding path program 1 times [2018-01-24 13:48:09,876 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:09,877 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:09,878 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:09,878 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:09,878 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:09,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:09,892 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:09,965 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 13:48:09,966 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:09,966 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:09,984 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:09,984 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:48:09,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:10,002 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:10,020 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 13:48:10,020 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:10,062 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 13:48:10,082 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:10,082 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:10,085 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:10,086 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:48:10,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:10,100 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:10,107 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 13:48:10,108 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:10,121 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 13:48:10,123 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:10,123 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-01-24 13:48:10,123 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:10,123 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 13:48:10,124 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 13:48:10,124 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:48:10,124 INFO L87 Difference]: Start difference. First operand 29 states and 30 transitions. Second operand 5 states. [2018-01-24 13:48:10,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:10,181 INFO L93 Difference]: Finished difference Result 58 states and 60 transitions. [2018-01-24 13:48:10,182 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:48:10,182 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2018-01-24 13:48:10,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:10,183 INFO L225 Difference]: With dead ends: 58 [2018-01-24 13:48:10,183 INFO L226 Difference]: Without dead ends: 44 [2018-01-24 13:48:10,184 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:48:10,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-01-24 13:48:10,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 33. [2018-01-24 13:48:10,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-01-24 13:48:10,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 34 transitions. [2018-01-24 13:48:10,190 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 34 transitions. Word has length 28 [2018-01-24 13:48:10,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:10,191 INFO L432 AbstractCegarLoop]: Abstraction has 33 states and 34 transitions. [2018-01-24 13:48:10,191 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 13:48:10,191 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 34 transitions. [2018-01-24 13:48:10,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 13:48:10,192 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:10,192 INFO L322 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:10,192 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:10,193 INFO L82 PathProgramCache]: Analyzing trace with hash 1230203493, now seen corresponding path program 2 times [2018-01-24 13:48:10,193 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:10,194 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:10,194 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:10,194 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:10,194 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:10,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:10,207 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:10,272 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 13:48:10,273 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:10,273 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:10,284 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:48:10,284 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:10,289 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:10,292 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:10,293 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:10,294 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:10,301 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 13:48:10,301 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:10,404 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 13:48:10,424 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:10,424 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:10,427 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:48:10,428 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:10,435 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:10,443 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:10,450 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:10,454 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:10,462 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 13:48:10,462 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:10,474 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 13:48:10,475 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:10,475 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-01-24 13:48:10,476 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:10,476 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:48:10,476 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:48:10,477 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:48:10,477 INFO L87 Difference]: Start difference. First operand 33 states and 34 transitions. Second operand 6 states. [2018-01-24 13:48:10,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:10,542 INFO L93 Difference]: Finished difference Result 67 states and 70 transitions. [2018-01-24 13:48:10,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:48:10,543 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 32 [2018-01-24 13:48:10,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:10,544 INFO L225 Difference]: With dead ends: 67 [2018-01-24 13:48:10,544 INFO L226 Difference]: Without dead ends: 53 [2018-01-24 13:48:10,544 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:48:10,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-01-24 13:48:10,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 37. [2018-01-24 13:48:10,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-01-24 13:48:10,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 38 transitions. [2018-01-24 13:48:10,549 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 38 transitions. Word has length 32 [2018-01-24 13:48:10,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:10,549 INFO L432 AbstractCegarLoop]: Abstraction has 37 states and 38 transitions. [2018-01-24 13:48:10,550 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:48:10,550 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 38 transitions. [2018-01-24 13:48:10,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-24 13:48:10,551 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:10,551 INFO L322 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:10,551 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:10,551 INFO L82 PathProgramCache]: Analyzing trace with hash 417265886, now seen corresponding path program 3 times [2018-01-24 13:48:10,551 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:10,552 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:10,552 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:10,553 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:10,553 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:10,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:10,565 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:10,632 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 13:48:10,632 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:10,632 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:10,640 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:48:10,640 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:48:10,646 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:10,648 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:10,650 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:10,650 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:10,653 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:10,668 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-24 13:48:10,668 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:10,724 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-24 13:48:10,758 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:10,758 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:10,762 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:48:10,763 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:48:10,770 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:10,774 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:10,782 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:10,787 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:10,791 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:10,796 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-24 13:48:10,796 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:10,807 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-24 13:48:10,808 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:10,809 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 4, 4] total 13 [2018-01-24 13:48:10,809 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:10,809 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:48:10,810 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:48:10,810 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:48:10,810 INFO L87 Difference]: Start difference. First operand 37 states and 38 transitions. Second operand 10 states. [2018-01-24 13:48:10,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:10,990 INFO L93 Difference]: Finished difference Result 76 states and 80 transitions. [2018-01-24 13:48:10,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:48:10,990 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 36 [2018-01-24 13:48:10,991 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:10,992 INFO L225 Difference]: With dead ends: 76 [2018-01-24 13:48:10,992 INFO L226 Difference]: Without dead ends: 62 [2018-01-24 13:48:10,992 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 138 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:48:10,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-01-24 13:48:10,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 46. [2018-01-24 13:48:10,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-01-24 13:48:10,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 47 transitions. [2018-01-24 13:48:10,999 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 47 transitions. Word has length 36 [2018-01-24 13:48:10,999 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:10,999 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 47 transitions. [2018-01-24 13:48:11,000 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:48:11,000 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 47 transitions. [2018-01-24 13:48:11,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-01-24 13:48:11,001 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:11,001 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:11,001 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:11,002 INFO L82 PathProgramCache]: Analyzing trace with hash 576961419, now seen corresponding path program 4 times [2018-01-24 13:48:11,002 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:11,002 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:11,003 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:11,003 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:11,003 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:11,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:11,015 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:11,097 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:48:11,097 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:11,097 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:11,102 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:48:11,102 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:48:11,115 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:11,118 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:11,125 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:48:11,125 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:11,193 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:48:11,213 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:11,213 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:11,216 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:48:11,216 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:48:11,241 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:11,245 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:11,254 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:48:11,254 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:11,266 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:48:11,268 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:11,268 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-01-24 13:48:11,268 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:11,268 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:48:11,269 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:48:11,269 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-24 13:48:11,269 INFO L87 Difference]: Start difference. First operand 46 states and 47 transitions. Second operand 8 states. [2018-01-24 13:48:11,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:11,354 INFO L93 Difference]: Finished difference Result 90 states and 94 transitions. [2018-01-24 13:48:11,355 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:48:11,355 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 45 [2018-01-24 13:48:11,355 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:11,356 INFO L225 Difference]: With dead ends: 90 [2018-01-24 13:48:11,356 INFO L226 Difference]: Without dead ends: 71 [2018-01-24 13:48:11,357 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 174 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-24 13:48:11,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-01-24 13:48:11,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 50. [2018-01-24 13:48:11,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 13:48:11,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 51 transitions. [2018-01-24 13:48:11,365 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 51 transitions. Word has length 45 [2018-01-24 13:48:11,365 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:11,365 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 51 transitions. [2018-01-24 13:48:11,365 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:48:11,365 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 51 transitions. [2018-01-24 13:48:11,367 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-01-24 13:48:11,367 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:11,367 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:11,367 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:11,368 INFO L82 PathProgramCache]: Analyzing trace with hash -194823758, now seen corresponding path program 5 times [2018-01-24 13:48:11,368 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:11,369 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:11,369 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:11,369 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:11,369 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:11,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:11,382 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:11,494 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:48:11,494 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:11,494 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:11,502 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:48:11,502 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:11,507 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,508 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,511 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,512 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,514 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,516 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,519 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,520 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:11,523 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:11,535 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:48:11,535 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:11,625 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:48:11,657 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:11,657 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:11,660 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:48:11,661 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:11,666 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,668 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,672 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,685 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,694 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,713 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:11,719 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:11,722 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:11,729 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:48:11,729 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:11,741 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:48:11,742 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:11,743 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-01-24 13:48:11,743 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:11,743 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 13:48:11,744 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 13:48:11,744 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-24 13:48:11,744 INFO L87 Difference]: Start difference. First operand 50 states and 51 transitions. Second operand 9 states. [2018-01-24 13:48:11,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:11,813 INFO L93 Difference]: Finished difference Result 99 states and 104 transitions. [2018-01-24 13:48:11,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 13:48:11,813 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 49 [2018-01-24 13:48:11,813 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:11,815 INFO L225 Difference]: With dead ends: 99 [2018-01-24 13:48:11,815 INFO L226 Difference]: Without dead ends: 80 [2018-01-24 13:48:11,816 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-24 13:48:11,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-24 13:48:11,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 54. [2018-01-24 13:48:11,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-01-24 13:48:11,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 55 transitions. [2018-01-24 13:48:11,823 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 55 transitions. Word has length 49 [2018-01-24 13:48:11,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:11,823 INFO L432 AbstractCegarLoop]: Abstraction has 54 states and 55 transitions. [2018-01-24 13:48:11,823 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 13:48:11,823 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 55 transitions. [2018-01-24 13:48:11,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-01-24 13:48:11,824 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:11,824 INFO L322 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:11,827 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:11,828 INFO L82 PathProgramCache]: Analyzing trace with hash -1600566183, now seen corresponding path program 6 times [2018-01-24 13:48:11,828 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:11,829 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:11,829 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:11,829 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:11,829 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:11,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:11,841 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:12,001 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 13:48:12,001 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:12,001 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:12,007 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:48:12,007 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:48:12,012 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,013 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,015 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,016 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,017 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,019 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,020 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,021 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:12,023 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:12,040 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 13:48:12,040 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:12,088 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 13:48:12,108 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:12,108 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:12,111 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:48:12,111 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:48:12,117 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,119 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,124 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,129 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,136 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,145 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,156 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:12,162 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:12,165 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:12,170 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 13:48:12,170 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:12,180 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 13:48:12,181 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:12,182 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 5, 5, 5, 5] total 18 [2018-01-24 13:48:12,182 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:12,183 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 13:48:12,183 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 13:48:12,183 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=203, Unknown=0, NotChecked=0, Total=306 [2018-01-24 13:48:12,183 INFO L87 Difference]: Start difference. First operand 54 states and 55 transitions. Second operand 14 states. [2018-01-24 13:48:12,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:12,292 INFO L93 Difference]: Finished difference Result 108 states and 114 transitions. [2018-01-24 13:48:12,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 13:48:12,295 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 53 [2018-01-24 13:48:12,296 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:12,297 INFO L225 Difference]: With dead ends: 108 [2018-01-24 13:48:12,297 INFO L226 Difference]: Without dead ends: 89 [2018-01-24 13:48:12,297 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 204 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 100 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=103, Invalid=203, Unknown=0, NotChecked=0, Total=306 [2018-01-24 13:48:12,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-01-24 13:48:12,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 63. [2018-01-24 13:48:12,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-01-24 13:48:12,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 64 transitions. [2018-01-24 13:48:12,306 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 64 transitions. Word has length 53 [2018-01-24 13:48:12,306 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:12,306 INFO L432 AbstractCegarLoop]: Abstraction has 63 states and 64 transitions. [2018-01-24 13:48:12,307 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 13:48:12,307 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 64 transitions. [2018-01-24 13:48:12,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 13:48:12,308 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:12,308 INFO L322 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:12,308 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:12,308 INFO L82 PathProgramCache]: Analyzing trace with hash 1495641218, now seen corresponding path program 7 times [2018-01-24 13:48:12,308 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:12,309 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:12,309 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:12,310 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:12,310 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:12,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:12,324 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:12,454 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 13:48:12,454 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:12,454 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:12,465 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:12,465 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:48:12,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:12,484 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:12,501 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 13:48:12,501 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:12,782 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 13:48:12,803 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:12,803 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:12,806 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:12,806 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:48:12,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:12,840 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:12,852 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 13:48:12,853 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:12,868 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 13:48:12,870 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:12,870 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-01-24 13:48:12,871 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:12,871 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 13:48:12,871 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 13:48:12,872 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-24 13:48:12,872 INFO L87 Difference]: Start difference. First operand 63 states and 64 transitions. Second operand 11 states. [2018-01-24 13:48:12,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:12,980 INFO L93 Difference]: Finished difference Result 122 states and 128 transitions. [2018-01-24 13:48:12,980 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 13:48:12,980 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 62 [2018-01-24 13:48:12,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:12,981 INFO L225 Difference]: With dead ends: 122 [2018-01-24 13:48:12,981 INFO L226 Difference]: Without dead ends: 98 [2018-01-24 13:48:12,982 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 239 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-24 13:48:12,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-01-24 13:48:12,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 67. [2018-01-24 13:48:12,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-01-24 13:48:12,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 68 transitions. [2018-01-24 13:48:12,990 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 68 transitions. Word has length 62 [2018-01-24 13:48:12,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:12,990 INFO L432 AbstractCegarLoop]: Abstraction has 67 states and 68 transitions. [2018-01-24 13:48:12,990 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 13:48:12,990 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 68 transitions. [2018-01-24 13:48:12,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-01-24 13:48:12,991 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:12,991 INFO L322 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:12,991 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:12,991 INFO L82 PathProgramCache]: Analyzing trace with hash -1534369477, now seen corresponding path program 8 times [2018-01-24 13:48:12,992 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:12,992 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:12,992 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:12,992 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:12,992 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:13,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:13,006 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:13,150 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 13:48:13,150 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:13,150 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:13,156 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:48:13,156 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:13,161 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:13,168 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:13,170 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:13,171 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:13,181 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 13:48:13,182 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:13,376 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 13:48:13,396 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:13,396 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:13,399 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:48:13,399 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:13,404 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:13,413 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:13,421 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:13,424 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:13,432 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 13:48:13,432 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:13,445 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 13:48:13,447 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:13,447 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-01-24 13:48:13,447 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:13,447 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 13:48:13,448 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 13:48:13,448 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-24 13:48:13,448 INFO L87 Difference]: Start difference. First operand 67 states and 68 transitions. Second operand 12 states. [2018-01-24 13:48:13,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:13,528 INFO L93 Difference]: Finished difference Result 131 states and 138 transitions. [2018-01-24 13:48:13,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 13:48:13,529 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 66 [2018-01-24 13:48:13,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:13,530 INFO L225 Difference]: With dead ends: 131 [2018-01-24 13:48:13,530 INFO L226 Difference]: Without dead ends: 107 [2018-01-24 13:48:13,531 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 274 GetRequests, 254 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-24 13:48:13,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-01-24 13:48:13,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 71. [2018-01-24 13:48:13,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-01-24 13:48:13,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 72 transitions. [2018-01-24 13:48:13,536 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 72 transitions. Word has length 66 [2018-01-24 13:48:13,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:13,537 INFO L432 AbstractCegarLoop]: Abstraction has 71 states and 72 transitions. [2018-01-24 13:48:13,537 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 13:48:13,537 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 72 transitions. [2018-01-24 13:48:13,538 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-01-24 13:48:13,538 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:13,538 INFO L322 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:13,538 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:13,538 INFO L82 PathProgramCache]: Analyzing trace with hash -1473900172, now seen corresponding path program 9 times [2018-01-24 13:48:13,538 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:13,539 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:13,539 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:13,539 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:13,539 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:13,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:13,551 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:13,688 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 13:48:13,688 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:13,688 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:13,695 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:48:13,695 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:48:13,703 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:13,705 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:13,706 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:13,707 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:13,709 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:13,709 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:13,711 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:13,729 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 13:48:13,730 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:13,780 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 13:48:13,800 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:13,800 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:13,803 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:48:13,803 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:48:13,809 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:13,812 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:13,820 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:13,831 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:13,846 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:13,854 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:13,858 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:13,865 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 13:48:13,865 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:13,889 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 13:48:13,890 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:13,891 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 6, 6, 6, 6] total 23 [2018-01-24 13:48:13,891 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:13,891 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 13:48:13,891 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 13:48:13,891 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=168, Invalid=338, Unknown=0, NotChecked=0, Total=506 [2018-01-24 13:48:13,891 INFO L87 Difference]: Start difference. First operand 71 states and 72 transitions. Second operand 18 states. [2018-01-24 13:48:14,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:14,088 INFO L93 Difference]: Finished difference Result 140 states and 148 transitions. [2018-01-24 13:48:14,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 13:48:14,089 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 70 [2018-01-24 13:48:14,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:14,090 INFO L225 Difference]: With dead ends: 140 [2018-01-24 13:48:14,090 INFO L226 Difference]: Without dead ends: 116 [2018-01-24 13:48:14,090 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 291 GetRequests, 270 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 175 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=168, Invalid=338, Unknown=0, NotChecked=0, Total=506 [2018-01-24 13:48:14,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-01-24 13:48:14,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 80. [2018-01-24 13:48:14,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-01-24 13:48:14,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 81 transitions. [2018-01-24 13:48:14,144 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 81 transitions. Word has length 70 [2018-01-24 13:48:14,144 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:14,144 INFO L432 AbstractCegarLoop]: Abstraction has 80 states and 81 transitions. [2018-01-24 13:48:14,144 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 13:48:14,144 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 81 transitions. [2018-01-24 13:48:14,145 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-01-24 13:48:14,146 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:14,146 INFO L322 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:14,146 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:14,146 INFO L82 PathProgramCache]: Analyzing trace with hash -1757583627, now seen corresponding path program 10 times [2018-01-24 13:48:14,146 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:14,147 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:14,147 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:14,147 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:14,148 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:14,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:14,160 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:14,269 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 13:48:14,270 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:14,270 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:14,277 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:48:14,277 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:48:14,290 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:14,292 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:14,302 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 13:48:14,303 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:14,450 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 13:48:14,470 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:14,471 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:14,473 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:48:14,474 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:48:14,500 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:14,504 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:14,515 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 13:48:14,515 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:14,532 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 13:48:14,534 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:14,534 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-01-24 13:48:14,534 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:14,534 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 13:48:14,534 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 13:48:14,535 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-24 13:48:14,535 INFO L87 Difference]: Start difference. First operand 80 states and 81 transitions. Second operand 14 states. [2018-01-24 13:48:14,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:14,641 INFO L93 Difference]: Finished difference Result 154 states and 162 transitions. [2018-01-24 13:48:14,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 13:48:14,641 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 79 [2018-01-24 13:48:14,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:14,642 INFO L225 Difference]: With dead ends: 154 [2018-01-24 13:48:14,642 INFO L226 Difference]: Without dead ends: 125 [2018-01-24 13:48:14,642 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 328 GetRequests, 304 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-24 13:48:14,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2018-01-24 13:48:14,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 84. [2018-01-24 13:48:14,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-01-24 13:48:14,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 85 transitions. [2018-01-24 13:48:14,650 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 85 transitions. Word has length 79 [2018-01-24 13:48:14,651 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:14,651 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 85 transitions. [2018-01-24 13:48:14,651 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 13:48:14,651 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 85 transitions. [2018-01-24 13:48:14,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-01-24 13:48:14,652 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:14,652 INFO L322 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:14,652 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:14,652 INFO L82 PathProgramCache]: Analyzing trace with hash -2099078308, now seen corresponding path program 11 times [2018-01-24 13:48:14,652 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:14,653 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:14,653 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:14,653 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:14,653 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:14,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:14,666 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:14,805 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 13:48:14,805 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:14,805 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:14,813 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:48:14,813 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:14,818 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,819 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,821 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,822 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,823 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,825 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,826 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,829 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,831 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,833 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,835 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,838 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,842 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:14,843 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:14,844 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:14,853 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 13:48:14,853 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:15,068 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 13:48:15,088 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:15,089 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:15,091 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:48:15,092 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:15,097 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,099 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,104 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,108 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,113 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,119 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,127 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,136 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,148 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,163 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,182 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,205 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,289 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:15,300 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:15,303 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:15,315 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 13:48:15,315 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:15,332 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 13:48:15,333 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:15,334 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-01-24 13:48:15,334 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:15,334 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 13:48:15,334 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 13:48:15,334 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-24 13:48:15,334 INFO L87 Difference]: Start difference. First operand 84 states and 85 transitions. Second operand 15 states. [2018-01-24 13:48:15,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:15,443 INFO L93 Difference]: Finished difference Result 163 states and 172 transitions. [2018-01-24 13:48:15,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 13:48:15,444 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 83 [2018-01-24 13:48:15,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:15,444 INFO L225 Difference]: With dead ends: 163 [2018-01-24 13:48:15,444 INFO L226 Difference]: Without dead ends: 134 [2018-01-24 13:48:15,445 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 345 GetRequests, 319 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-24 13:48:15,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-01-24 13:48:15,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 88. [2018-01-24 13:48:15,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-01-24 13:48:15,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 89 transitions. [2018-01-24 13:48:15,451 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 89 transitions. Word has length 83 [2018-01-24 13:48:15,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:15,452 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 89 transitions. [2018-01-24 13:48:15,452 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 13:48:15,452 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 89 transitions. [2018-01-24 13:48:15,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 13:48:15,452 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:15,452 INFO L322 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:15,452 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:15,453 INFO L82 PathProgramCache]: Analyzing trace with hash -159824829, now seen corresponding path program 12 times [2018-01-24 13:48:15,453 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:15,453 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:15,453 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:15,453 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:15,453 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:15,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:15,466 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:15,624 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 13:48:15,624 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:15,624 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:15,632 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:48:15,632 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:48:15,638 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,639 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,641 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,642 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,643 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,645 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,647 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,648 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,650 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,652 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,654 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,655 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:15,657 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:15,705 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 13:48:15,705 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:15,787 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 13:48:15,808 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:15,808 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:15,812 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:48:15,812 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:48:15,820 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,822 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,829 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,837 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,848 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,863 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,882 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,900 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,917 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,951 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,977 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:15,985 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:15,989 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:15,998 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 13:48:15,998 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:16,015 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 13:48:16,016 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:16,016 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 7, 7, 7, 7] total 28 [2018-01-24 13:48:16,017 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:16,017 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 13:48:16,017 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 13:48:16,017 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=249, Invalid=507, Unknown=0, NotChecked=0, Total=756 [2018-01-24 13:48:16,017 INFO L87 Difference]: Start difference. First operand 88 states and 89 transitions. Second operand 22 states. [2018-01-24 13:48:16,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:16,177 INFO L93 Difference]: Finished difference Result 172 states and 182 transitions. [2018-01-24 13:48:16,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 13:48:16,177 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 87 [2018-01-24 13:48:16,178 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:16,178 INFO L225 Difference]: With dead ends: 172 [2018-01-24 13:48:16,178 INFO L226 Difference]: Without dead ends: 143 [2018-01-24 13:48:16,179 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 362 GetRequests, 336 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 270 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=249, Invalid=507, Unknown=0, NotChecked=0, Total=756 [2018-01-24 13:48:16,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-01-24 13:48:16,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 97. [2018-01-24 13:48:16,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-01-24 13:48:16,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 98 transitions. [2018-01-24 13:48:16,190 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 98 transitions. Word has length 87 [2018-01-24 13:48:16,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:16,191 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 98 transitions. [2018-01-24 13:48:16,191 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 13:48:16,191 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 98 transitions. [2018-01-24 13:48:16,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-01-24 13:48:16,192 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:16,192 INFO L322 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:16,192 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:16,192 INFO L82 PathProgramCache]: Analyzing trace with hash -2110093160, now seen corresponding path program 13 times [2018-01-24 13:48:16,192 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:16,193 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:16,193 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:16,193 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:16,193 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:16,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:16,207 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:16,401 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 13:48:16,401 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:16,401 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:16,406 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:16,407 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:48:16,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:16,423 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:16,432 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 13:48:16,433 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:16,627 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 13:48:16,647 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:16,647 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:16,650 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:16,650 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:48:16,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:16,679 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:16,693 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 13:48:16,694 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:16,710 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 13:48:16,712 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:16,712 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-01-24 13:48:16,712 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:16,712 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 13:48:16,712 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 13:48:16,713 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-24 13:48:16,713 INFO L87 Difference]: Start difference. First operand 97 states and 98 transitions. Second operand 17 states. [2018-01-24 13:48:16,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:16,835 INFO L93 Difference]: Finished difference Result 186 states and 196 transitions. [2018-01-24 13:48:16,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 13:48:16,835 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 96 [2018-01-24 13:48:16,835 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:16,836 INFO L225 Difference]: With dead ends: 186 [2018-01-24 13:48:16,836 INFO L226 Difference]: Without dead ends: 152 [2018-01-24 13:48:16,836 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 399 GetRequests, 369 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-24 13:48:16,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-24 13:48:16,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 101. [2018-01-24 13:48:16,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-01-24 13:48:16,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 102 transitions. [2018-01-24 13:48:16,844 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 102 transitions. Word has length 96 [2018-01-24 13:48:16,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:16,844 INFO L432 AbstractCegarLoop]: Abstraction has 101 states and 102 transitions. [2018-01-24 13:48:16,844 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 13:48:16,844 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 102 transitions. [2018-01-24 13:48:16,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-01-24 13:48:16,845 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:16,845 INFO L322 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:16,845 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:16,846 INFO L82 PathProgramCache]: Analyzing trace with hash 1842728721, now seen corresponding path program 14 times [2018-01-24 13:48:16,846 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:16,846 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:16,847 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:16,847 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:16,847 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:16,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:16,860 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:17,003 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 13:48:17,004 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:17,004 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:17,009 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:48:17,009 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:17,015 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:17,023 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:17,024 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:17,026 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:17,036 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 13:48:17,036 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:17,255 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 13:48:17,275 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:17,275 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:17,278 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:48:17,278 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:17,284 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:17,297 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:17,308 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:17,312 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:17,323 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 13:48:17,324 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:17,348 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 13:48:17,350 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:17,350 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-01-24 13:48:17,350 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:17,350 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 13:48:17,351 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 13:48:17,351 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 13:48:17,352 INFO L87 Difference]: Start difference. First operand 101 states and 102 transitions. Second operand 18 states. [2018-01-24 13:48:17,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:17,592 INFO L93 Difference]: Finished difference Result 195 states and 206 transitions. [2018-01-24 13:48:17,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 13:48:17,592 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 100 [2018-01-24 13:48:17,592 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:17,593 INFO L225 Difference]: With dead ends: 195 [2018-01-24 13:48:17,593 INFO L226 Difference]: Without dead ends: 161 [2018-01-24 13:48:17,594 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 416 GetRequests, 384 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 13:48:17,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-01-24 13:48:17,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 105. [2018-01-24 13:48:17,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-01-24 13:48:17,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 106 transitions. [2018-01-24 13:48:17,602 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 106 transitions. Word has length 100 [2018-01-24 13:48:17,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:17,602 INFO L432 AbstractCegarLoop]: Abstraction has 105 states and 106 transitions. [2018-01-24 13:48:17,602 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 13:48:17,602 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 106 transitions. [2018-01-24 13:48:17,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-01-24 13:48:17,602 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:17,603 INFO L322 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:17,603 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:17,603 INFO L82 PathProgramCache]: Analyzing trace with hash -184078070, now seen corresponding path program 15 times [2018-01-24 13:48:17,603 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:17,603 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:17,604 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:17,604 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:17,604 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:17,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:17,613 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:17,831 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 13:48:17,832 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:17,832 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:17,839 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:48:17,839 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:48:17,845 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:17,847 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:17,848 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:17,850 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:17,851 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:17,853 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:17,856 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:17,856 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:17,859 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:17,893 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 13:48:17,893 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:18,092 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 13:48:18,113 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:18,113 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:18,118 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:48:18,118 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:48:18,126 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:18,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:18,134 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:18,141 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:18,151 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:18,166 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:18,185 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:18,192 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:18,196 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:18,203 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 13:48:18,203 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:18,219 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 13:48:18,221 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:18,221 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 8, 8, 8, 8] total 33 [2018-01-24 13:48:18,221 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:18,222 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 13:48:18,222 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 13:48:18,222 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=346, Invalid=710, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 13:48:18,222 INFO L87 Difference]: Start difference. First operand 105 states and 106 transitions. Second operand 26 states. [2018-01-24 13:48:18,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:18,476 INFO L93 Difference]: Finished difference Result 204 states and 216 transitions. [2018-01-24 13:48:18,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 13:48:18,477 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 104 [2018-01-24 13:48:18,477 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:18,478 INFO L225 Difference]: With dead ends: 204 [2018-01-24 13:48:18,478 INFO L226 Difference]: Without dead ends: 170 [2018-01-24 13:48:18,478 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 433 GetRequests, 402 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 385 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=346, Invalid=710, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 13:48:18,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2018-01-24 13:48:18,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 114. [2018-01-24 13:48:18,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-01-24 13:48:18,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 115 transitions. [2018-01-24 13:48:18,488 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 115 transitions. Word has length 104 [2018-01-24 13:48:18,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:18,488 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 115 transitions. [2018-01-24 13:48:18,488 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 13:48:18,488 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 115 transitions. [2018-01-24 13:48:18,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-01-24 13:48:18,488 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:18,489 INFO L322 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:18,489 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:18,489 INFO L82 PathProgramCache]: Analyzing trace with hash 950262623, now seen corresponding path program 16 times [2018-01-24 13:48:18,489 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:18,490 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:18,490 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:18,490 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:18,490 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:18,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:18,500 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:18,659 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 13:48:18,659 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:18,659 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:18,664 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:48:18,664 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:48:18,679 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:18,681 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:18,697 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 13:48:18,697 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:19,011 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 13:48:19,031 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:19,031 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:19,034 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:48:19,035 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:48:19,078 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:19,082 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:19,101 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 13:48:19,101 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:19,151 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 13:48:19,153 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:19,153 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-01-24 13:48:19,153 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:19,153 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 13:48:19,154 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 13:48:19,154 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 13:48:19,154 INFO L87 Difference]: Start difference. First operand 114 states and 115 transitions. Second operand 20 states. [2018-01-24 13:48:19,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:19,357 INFO L93 Difference]: Finished difference Result 218 states and 230 transitions. [2018-01-24 13:48:19,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 13:48:19,357 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 113 [2018-01-24 13:48:19,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:19,358 INFO L225 Difference]: With dead ends: 218 [2018-01-24 13:48:19,358 INFO L226 Difference]: Without dead ends: 179 [2018-01-24 13:48:19,359 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 470 GetRequests, 434 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 13:48:19,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-01-24 13:48:19,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 118. [2018-01-24 13:48:19,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-24 13:48:19,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 119 transitions. [2018-01-24 13:48:19,368 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 119 transitions. Word has length 113 [2018-01-24 13:48:19,368 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:19,368 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 119 transitions. [2018-01-24 13:48:19,368 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 13:48:19,368 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 119 transitions. [2018-01-24 13:48:19,369 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-01-24 13:48:19,369 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:19,369 INFO L322 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:19,369 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:19,369 INFO L82 PathProgramCache]: Analyzing trace with hash 1664169478, now seen corresponding path program 17 times [2018-01-24 13:48:19,369 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:19,370 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:19,370 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:19,370 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:19,370 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:19,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:19,380 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:19,553 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 13:48:19,553 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:19,554 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:19,558 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:48:19,559 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:19,564 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,565 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,566 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,567 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,568 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,569 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,570 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,572 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,573 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,575 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,577 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,579 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,582 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,585 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,589 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,592 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,597 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,601 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,613 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,614 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:19,616 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:19,633 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 13:48:19,634 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:19,925 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 13:48:19,945 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:19,945 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:19,948 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:48:19,948 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:19,954 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,956 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,960 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,965 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,970 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,976 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,984 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:19,993 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:20,004 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:20,017 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:20,032 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:20,049 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:20,072 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:20,098 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:20,131 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:20,167 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:20,212 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:20,265 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:20,572 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:20,591 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:20,595 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:20,607 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 13:48:20,607 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:20,624 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 13:48:20,626 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:20,626 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-01-24 13:48:20,627 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:20,627 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 13:48:20,627 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 13:48:20,628 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 13:48:20,628 INFO L87 Difference]: Start difference. First operand 118 states and 119 transitions. Second operand 21 states. [2018-01-24 13:48:20,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:20,768 INFO L93 Difference]: Finished difference Result 227 states and 240 transitions. [2018-01-24 13:48:20,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 13:48:20,768 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 117 [2018-01-24 13:48:20,768 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:20,769 INFO L225 Difference]: With dead ends: 227 [2018-01-24 13:48:20,769 INFO L226 Difference]: Without dead ends: 188 [2018-01-24 13:48:20,770 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 487 GetRequests, 449 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 13:48:20,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-01-24 13:48:20,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 122. [2018-01-24 13:48:20,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-01-24 13:48:20,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 123 transitions. [2018-01-24 13:48:20,784 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 123 transitions. Word has length 117 [2018-01-24 13:48:20,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:20,784 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 123 transitions. [2018-01-24 13:48:20,784 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 13:48:20,785 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 123 transitions. [2018-01-24 13:48:20,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-01-24 13:48:20,785 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:20,785 INFO L322 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:20,785 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:20,785 INFO L82 PathProgramCache]: Analyzing trace with hash 2092098861, now seen corresponding path program 18 times [2018-01-24 13:48:20,786 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:20,786 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:20,786 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:20,786 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:20,786 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:20,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:20,797 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:21,012 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 722 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 13:48:21,012 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:21,012 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:21,019 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:48:21,019 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:48:21,025 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,026 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,028 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,028 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,030 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,031 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,032 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,033 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,035 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,036 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,038 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,040 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,042 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,044 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,047 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,047 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:21,049 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:21,099 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-24 13:48:21,099 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:21,214 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-24 13:48:21,234 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:21,234 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:21,237 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:48:21,237 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:48:21,245 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,247 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,251 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,257 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,263 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,273 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,284 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,301 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,316 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,338 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,365 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,400 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,439 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,513 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,571 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:21,583 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:21,588 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:21,596 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-24 13:48:21,596 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:21,629 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-24 13:48:21,631 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:21,631 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 9, 9, 9, 9] total 38 [2018-01-24 13:48:21,631 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:21,632 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 13:48:21,632 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 13:48:21,632 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=459, Invalid=947, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 13:48:21,632 INFO L87 Difference]: Start difference. First operand 122 states and 123 transitions. Second operand 30 states. [2018-01-24 13:48:21,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:21,959 INFO L93 Difference]: Finished difference Result 236 states and 250 transitions. [2018-01-24 13:48:21,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 13:48:21,959 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 121 [2018-01-24 13:48:21,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:21,960 INFO L225 Difference]: With dead ends: 236 [2018-01-24 13:48:21,960 INFO L226 Difference]: Without dead ends: 197 [2018-01-24 13:48:21,961 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 504 GetRequests, 468 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 520 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=459, Invalid=947, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 13:48:21,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2018-01-24 13:48:21,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 131. [2018-01-24 13:48:21,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-01-24 13:48:21,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 132 transitions. [2018-01-24 13:48:21,977 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 132 transitions. Word has length 121 [2018-01-24 13:48:21,977 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:21,977 INFO L432 AbstractCegarLoop]: Abstraction has 131 states and 132 transitions. [2018-01-24 13:48:21,977 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 13:48:21,977 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 132 transitions. [2018-01-24 13:48:21,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-01-24 13:48:21,978 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:21,978 INFO L322 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:21,978 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:21,978 INFO L82 PathProgramCache]: Analyzing trace with hash 734718894, now seen corresponding path program 19 times [2018-01-24 13:48:21,978 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:21,979 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:21,979 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:21,979 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:21,979 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:21,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:21,992 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:22,324 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 13:48:22,324 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:22,324 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:22,330 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:22,330 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:48:22,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:22,350 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:22,372 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 13:48:22,372 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:22,823 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 13:48:22,843 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:22,843 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:22,846 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:22,846 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:48:22,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:22,885 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:22,901 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 13:48:22,901 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:22,922 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 13:48:22,923 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:22,923 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-01-24 13:48:22,923 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:22,924 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 13:48:22,924 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 13:48:22,924 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 13:48:22,924 INFO L87 Difference]: Start difference. First operand 131 states and 132 transitions. Second operand 23 states. [2018-01-24 13:48:23,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:23,189 INFO L93 Difference]: Finished difference Result 250 states and 264 transitions. [2018-01-24 13:48:23,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 13:48:23,189 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 130 [2018-01-24 13:48:23,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:23,190 INFO L225 Difference]: With dead ends: 250 [2018-01-24 13:48:23,191 INFO L226 Difference]: Without dead ends: 206 [2018-01-24 13:48:23,191 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 541 GetRequests, 499 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 13:48:23,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-01-24 13:48:23,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 135. [2018-01-24 13:48:23,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-24 13:48:23,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 136 transitions. [2018-01-24 13:48:23,210 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 136 transitions. Word has length 130 [2018-01-24 13:48:23,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:23,210 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 136 transitions. [2018-01-24 13:48:23,210 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 13:48:23,210 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 136 transitions. [2018-01-24 13:48:23,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-01-24 13:48:23,211 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:23,211 INFO L322 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:23,211 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:23,212 INFO L82 PathProgramCache]: Analyzing trace with hash 1367823335, now seen corresponding path program 20 times [2018-01-24 13:48:23,212 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:23,212 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:23,213 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:23,213 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:23,213 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:23,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:23,224 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:23,523 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 13:48:23,524 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:23,524 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:23,528 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:48:23,529 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:23,535 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:23,546 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:23,548 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:23,550 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:23,564 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 13:48:23,564 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:24,200 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 13:48:24,231 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:24,235 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:24,238 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:48:24,238 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:24,247 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:24,269 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:24,283 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:24,288 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:24,312 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 13:48:24,312 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:24,353 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 13:48:24,355 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:24,355 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 46 [2018-01-24 13:48:24,355 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:24,355 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 13:48:24,356 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 13:48:24,356 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 13:48:24,357 INFO L87 Difference]: Start difference. First operand 135 states and 136 transitions. Second operand 24 states. [2018-01-24 13:48:24,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:24,633 INFO L93 Difference]: Finished difference Result 259 states and 274 transitions. [2018-01-24 13:48:24,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 13:48:24,633 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 134 [2018-01-24 13:48:24,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:24,635 INFO L225 Difference]: With dead ends: 259 [2018-01-24 13:48:24,635 INFO L226 Difference]: Without dead ends: 215 [2018-01-24 13:48:24,636 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 558 GetRequests, 514 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 13:48:24,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states. [2018-01-24 13:48:24,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 139. [2018-01-24 13:48:24,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-01-24 13:48:24,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 140 transitions. [2018-01-24 13:48:24,648 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 140 transitions. Word has length 134 [2018-01-24 13:48:24,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:24,648 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 140 transitions. [2018-01-24 13:48:24,648 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 13:48:24,649 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 140 transitions. [2018-01-24 13:48:24,649 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-24 13:48:24,649 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:24,649 INFO L322 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:24,649 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:24,649 INFO L82 PathProgramCache]: Analyzing trace with hash -168626272, now seen corresponding path program 21 times [2018-01-24 13:48:24,649 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:24,650 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:24,650 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:24,650 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:24,650 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:24,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:24,661 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:24,908 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 968 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 13:48:24,908 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:24,909 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:24,913 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:48:24,914 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:48:24,920 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:24,922 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:24,923 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:24,925 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:24,926 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:24,928 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:24,931 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:24,934 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:24,936 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:24,937 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:24,940 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:25,013 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-24 13:48:25,013 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:25,190 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-24 13:48:25,210 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:25,210 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:25,213 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:48:25,213 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:48:25,222 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:25,225 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:25,231 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:25,241 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:25,251 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:25,265 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:25,284 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:25,311 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:25,348 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:25,357 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:25,361 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:25,376 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-24 13:48:25,376 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:25,402 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-24 13:48:25,403 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:25,403 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 10, 10, 10, 10] total 43 [2018-01-24 13:48:25,404 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:25,404 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-01-24 13:48:25,404 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-01-24 13:48:25,404 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=588, Invalid=1218, Unknown=0, NotChecked=0, Total=1806 [2018-01-24 13:48:25,405 INFO L87 Difference]: Start difference. First operand 139 states and 140 transitions. Second operand 34 states. [2018-01-24 13:48:25,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:25,837 INFO L93 Difference]: Finished difference Result 268 states and 284 transitions. [2018-01-24 13:48:25,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 13:48:25,837 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 138 [2018-01-24 13:48:25,838 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:25,839 INFO L225 Difference]: With dead ends: 268 [2018-01-24 13:48:25,839 INFO L226 Difference]: Without dead ends: 224 [2018-01-24 13:48:25,840 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 575 GetRequests, 534 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 675 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=588, Invalid=1218, Unknown=0, NotChecked=0, Total=1806 [2018-01-24 13:48:25,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-01-24 13:48:25,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 148. [2018-01-24 13:48:25,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-01-24 13:48:25,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 149 transitions. [2018-01-24 13:48:25,865 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 149 transitions. Word has length 138 [2018-01-24 13:48:25,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:25,865 INFO L432 AbstractCegarLoop]: Abstraction has 148 states and 149 transitions. [2018-01-24 13:48:25,865 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-01-24 13:48:25,865 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 149 transitions. [2018-01-24 13:48:25,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2018-01-24 13:48:25,866 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:25,866 INFO L322 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:25,866 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:25,866 INFO L82 PathProgramCache]: Analyzing trace with hash -219252535, now seen corresponding path program 22 times [2018-01-24 13:48:25,867 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:25,867 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:25,867 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:25,867 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:25,868 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:25,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:25,881 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:26,260 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 13:48:26,260 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:26,260 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:26,270 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:48:26,271 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:48:26,294 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:26,297 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:26,320 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 13:48:26,321 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:26,853 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 13:48:26,873 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:26,873 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:26,876 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:48:26,876 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:48:26,925 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:26,929 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:26,944 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 13:48:26,945 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:26,967 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 13:48:26,968 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:26,968 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-01-24 13:48:26,968 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:26,969 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 13:48:26,969 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 13:48:26,970 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 13:48:26,970 INFO L87 Difference]: Start difference. First operand 148 states and 149 transitions. Second operand 26 states. [2018-01-24 13:48:27,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:27,219 INFO L93 Difference]: Finished difference Result 282 states and 298 transitions. [2018-01-24 13:48:27,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 13:48:27,219 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 147 [2018-01-24 13:48:27,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:27,220 INFO L225 Difference]: With dead ends: 282 [2018-01-24 13:48:27,220 INFO L226 Difference]: Without dead ends: 233 [2018-01-24 13:48:27,221 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 612 GetRequests, 564 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 13:48:27,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2018-01-24 13:48:27,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 152. [2018-01-24 13:48:27,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-01-24 13:48:27,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 153 transitions. [2018-01-24 13:48:27,247 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 153 transitions. Word has length 147 [2018-01-24 13:48:27,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:27,247 INFO L432 AbstractCegarLoop]: Abstraction has 152 states and 153 transitions. [2018-01-24 13:48:27,247 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 13:48:27,247 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 153 transitions. [2018-01-24 13:48:27,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2018-01-24 13:48:27,248 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:27,248 INFO L322 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:27,249 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:27,249 INFO L82 PathProgramCache]: Analyzing trace with hash -2062915152, now seen corresponding path program 23 times [2018-01-24 13:48:27,249 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:27,250 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:27,250 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:27,250 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:27,250 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:27,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:27,264 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:27,629 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 13:48:27,629 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:27,629 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:27,634 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:48:27,634 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:27,640 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,642 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,642 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,643 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,644 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,645 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,647 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,648 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,649 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,651 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,653 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,655 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,658 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,660 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,663 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,667 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,671 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,675 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,680 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,686 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,692 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,699 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,706 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,715 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,734 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:27,735 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:27,737 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:27,753 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 13:48:27,753 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:28,260 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 13:48:28,280 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:28,280 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:28,283 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:48:28,283 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:28,290 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,292 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,296 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,300 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,305 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,311 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,319 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,328 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,339 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,352 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,367 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,385 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,406 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,429 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,457 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,491 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,530 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,574 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,627 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,689 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,762 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,846 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:28,953 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:29,066 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:30,015 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:30,052 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:30,057 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:30,073 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 13:48:30,074 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:30,103 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 13:48:30,105 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:30,106 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 52 [2018-01-24 13:48:30,106 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:30,106 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 13:48:30,106 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 13:48:30,107 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 13:48:30,107 INFO L87 Difference]: Start difference. First operand 152 states and 153 transitions. Second operand 27 states. [2018-01-24 13:48:30,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:30,320 INFO L93 Difference]: Finished difference Result 291 states and 308 transitions. [2018-01-24 13:48:30,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 13:48:30,320 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 151 [2018-01-24 13:48:30,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:30,321 INFO L225 Difference]: With dead ends: 291 [2018-01-24 13:48:30,321 INFO L226 Difference]: Without dead ends: 242 [2018-01-24 13:48:30,322 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 629 GetRequests, 579 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 13:48:30,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states. [2018-01-24 13:48:30,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 156. [2018-01-24 13:48:30,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-01-24 13:48:30,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 157 transitions. [2018-01-24 13:48:30,338 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 157 transitions. Word has length 151 [2018-01-24 13:48:30,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:30,338 INFO L432 AbstractCegarLoop]: Abstraction has 156 states and 157 transitions. [2018-01-24 13:48:30,338 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 13:48:30,338 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 157 transitions. [2018-01-24 13:48:30,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-01-24 13:48:30,339 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:30,339 INFO L322 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:30,339 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:30,340 INFO L82 PathProgramCache]: Analyzing trace with hash -731541737, now seen corresponding path program 24 times [2018-01-24 13:48:30,340 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:30,340 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:30,340 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:30,341 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:30,341 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:30,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:30,354 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:30,759 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 1250 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 13:48:30,759 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:30,760 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:30,765 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:48:30,765 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:48:30,775 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,777 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,779 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,780 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,782 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,784 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,787 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,789 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,792 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,795 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,798 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,807 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,810 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,814 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,819 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,823 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,828 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,833 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,839 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:30,842 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:30,845 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:30,997 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-24 13:48:30,997 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:31,283 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-24 13:48:31,304 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:31,305 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:31,308 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:48:31,308 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:48:31,319 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,321 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,328 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,335 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,345 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,360 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,378 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,392 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,409 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,446 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,473 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,517 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,557 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,631 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,691 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:31,968 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:32,332 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:32,768 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:33,419 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:33,445 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:33,449 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:33,474 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-24 13:48:33,474 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:33,495 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-24 13:48:33,496 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:33,497 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 11, 11, 11, 11] total 48 [2018-01-24 13:48:33,497 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:33,497 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-01-24 13:48:33,497 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-01-24 13:48:33,498 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=733, Invalid=1523, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 13:48:33,498 INFO L87 Difference]: Start difference. First operand 156 states and 157 transitions. Second operand 38 states. [2018-01-24 13:48:34,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:34,012 INFO L93 Difference]: Finished difference Result 300 states and 318 transitions. [2018-01-24 13:48:34,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 13:48:34,012 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 155 [2018-01-24 13:48:34,013 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:34,013 INFO L225 Difference]: With dead ends: 300 [2018-01-24 13:48:34,014 INFO L226 Difference]: Without dead ends: 251 [2018-01-24 13:48:34,014 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 646 GetRequests, 600 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 850 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=733, Invalid=1523, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 13:48:34,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states. [2018-01-24 13:48:34,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 165. [2018-01-24 13:48:34,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-01-24 13:48:34,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 166 transitions. [2018-01-24 13:48:34,038 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 166 transitions. Word has length 155 [2018-01-24 13:48:34,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:34,038 INFO L432 AbstractCegarLoop]: Abstraction has 165 states and 166 transitions. [2018-01-24 13:48:34,038 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-01-24 13:48:34,038 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 166 transitions. [2018-01-24 13:48:34,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-01-24 13:48:34,039 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:34,040 INFO L322 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:34,040 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:34,040 INFO L82 PathProgramCache]: Analyzing trace with hash 7304644, now seen corresponding path program 25 times [2018-01-24 13:48:34,040 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:34,041 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:34,041 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:34,041 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:34,041 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:34,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:34,054 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:34,633 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 13:48:34,633 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:34,633 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:34,638 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:34,638 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:48:34,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:34,665 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:34,693 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 13:48:34,694 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:35,390 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 13:48:35,410 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:35,410 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:35,413 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:35,413 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:48:35,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:35,463 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:35,487 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 13:48:35,488 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:35,508 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 13:48:35,509 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:35,509 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 56 [2018-01-24 13:48:35,509 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:35,510 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 13:48:35,510 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 13:48:35,511 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 13:48:35,511 INFO L87 Difference]: Start difference. First operand 165 states and 166 transitions. Second operand 29 states. [2018-01-24 13:48:35,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:35,900 INFO L93 Difference]: Finished difference Result 314 states and 332 transitions. [2018-01-24 13:48:35,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 13:48:35,900 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 164 [2018-01-24 13:48:35,901 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:35,902 INFO L225 Difference]: With dead ends: 314 [2018-01-24 13:48:35,902 INFO L226 Difference]: Without dead ends: 260 [2018-01-24 13:48:35,903 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 683 GetRequests, 629 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 13:48:35,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 260 states. [2018-01-24 13:48:35,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 260 to 169. [2018-01-24 13:48:35,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-01-24 13:48:35,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 170 transitions. [2018-01-24 13:48:35,938 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 170 transitions. Word has length 164 [2018-01-24 13:48:35,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:35,939 INFO L432 AbstractCegarLoop]: Abstraction has 169 states and 170 transitions. [2018-01-24 13:48:35,939 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-24 13:48:35,939 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 170 transitions. [2018-01-24 13:48:35,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2018-01-24 13:48:35,940 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:35,940 INFO L322 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:35,940 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:35,940 INFO L82 PathProgramCache]: Analyzing trace with hash -1420521539, now seen corresponding path program 26 times [2018-01-24 13:48:35,940 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:35,941 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:35,941 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:35,941 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:35,941 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:35,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:35,954 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:36,699 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 13:48:36,699 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:36,699 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:36,704 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:48:36,704 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:36,711 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:36,725 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:36,728 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:36,730 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:36,749 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 13:48:36,749 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:37,364 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 13:48:37,384 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:37,385 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:37,387 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:48:37,388 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:37,397 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:37,422 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:37,439 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:37,443 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:37,466 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 13:48:37,467 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:37,489 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 13:48:37,490 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:37,490 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 58 [2018-01-24 13:48:37,490 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:37,490 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 13:48:37,491 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 13:48:37,491 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 13:48:37,491 INFO L87 Difference]: Start difference. First operand 169 states and 170 transitions. Second operand 30 states. [2018-01-24 13:48:37,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:37,812 INFO L93 Difference]: Finished difference Result 323 states and 342 transitions. [2018-01-24 13:48:37,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-24 13:48:37,813 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 168 [2018-01-24 13:48:37,813 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:37,814 INFO L225 Difference]: With dead ends: 323 [2018-01-24 13:48:37,814 INFO L226 Difference]: Without dead ends: 269 [2018-01-24 13:48:37,815 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 700 GetRequests, 644 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 13:48:37,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states. [2018-01-24 13:48:37,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 173. [2018-01-24 13:48:37,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-01-24 13:48:37,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 174 transitions. [2018-01-24 13:48:37,837 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 174 transitions. Word has length 168 [2018-01-24 13:48:37,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:37,837 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 174 transitions. [2018-01-24 13:48:37,837 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 13:48:37,838 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 174 transitions. [2018-01-24 13:48:37,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-01-24 13:48:37,838 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:37,838 INFO L322 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:37,838 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:37,838 INFO L82 PathProgramCache]: Analyzing trace with hash -910555850, now seen corresponding path program 27 times [2018-01-24 13:48:37,839 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:37,839 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:37,839 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:37,839 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:37,839 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:37,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:37,848 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:38,559 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 1568 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 13:48:38,559 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:38,559 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:38,564 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:48:38,564 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:48:38,571 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,573 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,574 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,575 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,577 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,579 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,581 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,584 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,587 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,590 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,595 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,596 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:38,599 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:38,686 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-24 13:48:38,687 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:38,893 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-24 13:48:38,924 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:38,924 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:38,927 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:48:38,927 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:48:38,937 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,939 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,944 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,952 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,962 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,975 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:38,995 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:39,022 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:39,058 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:39,104 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:39,163 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:48:39,174 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:39,178 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:39,190 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-24 13:48:39,191 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:39,213 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-24 13:48:39,214 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:39,214 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 12, 12, 12, 12] total 53 [2018-01-24 13:48:39,214 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:39,215 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-01-24 13:48:39,215 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-01-24 13:48:39,215 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=894, Invalid=1862, Unknown=0, NotChecked=0, Total=2756 [2018-01-24 13:48:39,215 INFO L87 Difference]: Start difference. First operand 173 states and 174 transitions. Second operand 42 states. [2018-01-24 13:48:39,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:39,648 INFO L93 Difference]: Finished difference Result 332 states and 352 transitions. [2018-01-24 13:48:39,648 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-24 13:48:39,648 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 172 [2018-01-24 13:48:39,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:39,650 INFO L225 Difference]: With dead ends: 332 [2018-01-24 13:48:39,650 INFO L226 Difference]: Without dead ends: 278 [2018-01-24 13:48:39,650 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 717 GetRequests, 666 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1045 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=894, Invalid=1862, Unknown=0, NotChecked=0, Total=2756 [2018-01-24 13:48:39,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2018-01-24 13:48:39,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 182. [2018-01-24 13:48:39,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-24 13:48:39,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 183 transitions. [2018-01-24 13:48:39,697 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 183 transitions. Word has length 172 [2018-01-24 13:48:39,697 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:39,697 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 183 transitions. [2018-01-24 13:48:39,698 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-01-24 13:48:39,698 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 183 transitions. [2018-01-24 13:48:39,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2018-01-24 13:48:39,699 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:39,699 INFO L322 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:39,699 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:39,699 INFO L82 PathProgramCache]: Analyzing trace with hash 1830068019, now seen corresponding path program 28 times [2018-01-24 13:48:39,699 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:39,700 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:39,700 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:39,700 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:39,700 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:39,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:39,714 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:40,206 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 13:48:40,207 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:40,207 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:40,212 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:48:40,212 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:48:40,235 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:40,237 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:40,268 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 13:48:40,268 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:41,166 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 13:48:41,185 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:41,185 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:41,188 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:48:41,188 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:48:41,259 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:41,265 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:41,302 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 13:48:41,302 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:41,364 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 13:48:41,366 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:41,366 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32] total 62 [2018-01-24 13:48:41,366 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:41,367 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-01-24 13:48:41,386 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-01-24 13:48:41,386 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-24 13:48:41,386 INFO L87 Difference]: Start difference. First operand 182 states and 183 transitions. Second operand 32 states. [2018-01-24 13:48:42,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:42,159 INFO L93 Difference]: Finished difference Result 346 states and 366 transitions. [2018-01-24 13:48:42,159 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-24 13:48:42,159 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 181 [2018-01-24 13:48:42,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:42,160 INFO L225 Difference]: With dead ends: 346 [2018-01-24 13:48:42,160 INFO L226 Difference]: Without dead ends: 287 [2018-01-24 13:48:42,161 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 754 GetRequests, 694 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-24 13:48:42,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states. [2018-01-24 13:48:42,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 186. [2018-01-24 13:48:42,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-01-24 13:48:42,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 187 transitions. [2018-01-24 13:48:42,200 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 187 transitions. Word has length 181 [2018-01-24 13:48:42,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:42,201 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 187 transitions. [2018-01-24 13:48:42,201 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-01-24 13:48:42,201 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 187 transitions. [2018-01-24 13:48:42,202 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2018-01-24 13:48:42,202 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:42,202 INFO L322 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:42,202 INFO L371 AbstractCegarLoop]: === Iteration 31 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:42,202 INFO L82 PathProgramCache]: Analyzing trace with hash -1177971110, now seen corresponding path program 29 times [2018-01-24 13:48:42,202 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:42,203 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:42,203 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:42,203 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:42,203 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:42,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:42,217 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:42,808 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 13:48:42,808 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:42,809 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:42,813 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:48:42,814 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:42,821 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,835 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,836 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,844 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,848 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,858 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,869 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,883 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,885 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,897 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,911 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,913 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,917 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,920 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,923 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,927 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,931 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,935 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,940 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,949 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,958 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,968 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,979 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,988 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:42,998 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,012 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,030 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,042 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,056 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,071 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,098 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,099 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:43,101 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:43,123 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 13:48:43,123 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:43,881 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 13:48:43,902 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:43,902 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 59 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:43,905 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:48:43,905 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:48:43,913 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,914 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,918 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,922 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,928 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,934 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,941 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,950 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,961 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,974 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:43,989 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,006 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,028 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,052 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,079 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,111 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,146 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,186 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,231 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,283 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,342 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,410 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,487 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,573 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,682 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,804 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:44,942 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:45,102 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:45,297 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:45,505 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:47,796 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:48:47,861 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:47,867 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:47,894 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 13:48:47,895 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:47,921 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 13:48:47,924 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:47,924 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 64 [2018-01-24 13:48:47,924 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:47,925 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-24 13:48:47,925 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-24 13:48:47,925 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-24 13:48:47,925 INFO L87 Difference]: Start difference. First operand 186 states and 187 transitions. Second operand 33 states. [2018-01-24 13:48:48,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:48,248 INFO L93 Difference]: Finished difference Result 355 states and 376 transitions. [2018-01-24 13:48:48,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-01-24 13:48:48,248 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 185 [2018-01-24 13:48:48,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:48,249 INFO L225 Difference]: With dead ends: 355 [2018-01-24 13:48:48,250 INFO L226 Difference]: Without dead ends: 296 [2018-01-24 13:48:48,250 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 771 GetRequests, 709 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-24 13:48:48,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 296 states. [2018-01-24 13:48:48,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 296 to 190. [2018-01-24 13:48:48,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-01-24 13:48:48,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 191 transitions. [2018-01-24 13:48:48,288 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 191 transitions. Word has length 185 [2018-01-24 13:48:48,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:48,288 INFO L432 AbstractCegarLoop]: Abstraction has 190 states and 191 transitions. [2018-01-24 13:48:48,288 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-24 13:48:48,288 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 191 transitions. [2018-01-24 13:48:48,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 190 [2018-01-24 13:48:48,289 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:48,289 INFO L322 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:48,289 INFO L371 AbstractCegarLoop]: === Iteration 32 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:48,289 INFO L82 PathProgramCache]: Analyzing trace with hash 659595777, now seen corresponding path program 30 times [2018-01-24 13:48:48,289 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:48,290 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:48,290 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:48,290 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:48,290 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:48,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:48,303 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:48,744 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 1922 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 13:48:48,745 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:48,745 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:48,749 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:48:48,750 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:48:48,757 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,758 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,759 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,760 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,761 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,762 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,764 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,765 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,766 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,768 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,770 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,772 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,774 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,777 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,779 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,782 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,785 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,788 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,792 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,795 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,800 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,805 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,810 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:48,812 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:48,814 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:48,882 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-24 13:48:48,883 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:49,125 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-24 13:48:49,145 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:49,145 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 61 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:49,148 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:48:49,148 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:48:49,157 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,159 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,163 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,169 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,176 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,185 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,197 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,213 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,228 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,249 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,276 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,311 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,350 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,422 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,480 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:49,741 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:50,042 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:50,597 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:51,199 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:52,175 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:53,320 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:54,631 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:55,102 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:48:55,128 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:48:55,134 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:55,148 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-24 13:48:55,148 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:55,174 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-24 13:48:55,176 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:55,177 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 13, 13, 13, 13] total 58 [2018-01-24 13:48:55,177 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:55,177 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-01-24 13:48:55,178 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-01-24 13:48:55,178 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1071, Invalid=2235, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 13:48:55,178 INFO L87 Difference]: Start difference. First operand 190 states and 191 transitions. Second operand 46 states. [2018-01-24 13:48:55,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:48:55,720 INFO L93 Difference]: Finished difference Result 364 states and 386 transitions. [2018-01-24 13:48:55,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-24 13:48:55,720 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 189 [2018-01-24 13:48:55,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:48:55,722 INFO L225 Difference]: With dead ends: 364 [2018-01-24 13:48:55,722 INFO L226 Difference]: Without dead ends: 305 [2018-01-24 13:48:55,722 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 788 GetRequests, 732 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1260 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1071, Invalid=2235, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 13:48:55,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 305 states. [2018-01-24 13:48:55,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 305 to 199. [2018-01-24 13:48:55,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199 states. [2018-01-24 13:48:55,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 200 transitions. [2018-01-24 13:48:55,768 INFO L78 Accepts]: Start accepts. Automaton has 199 states and 200 transitions. Word has length 189 [2018-01-24 13:48:55,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:48:55,769 INFO L432 AbstractCegarLoop]: Abstraction has 199 states and 200 transitions. [2018-01-24 13:48:55,769 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-01-24 13:48:55,769 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 200 transitions. [2018-01-24 13:48:55,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-01-24 13:48:55,769 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:48:55,770 INFO L322 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:48:55,770 INFO L371 AbstractCegarLoop]: === Iteration 33 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 13:48:55,770 INFO L82 PathProgramCache]: Analyzing trace with hash -1088370982, now seen corresponding path program 31 times [2018-01-24 13:48:55,770 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:48:55,771 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:55,771 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:48:55,771 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:48:55,771 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:48:55,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:55,785 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:48:56,263 INFO L134 CoverageAnalysis]: Checked inductivity of 2402 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 354 trivial. 0 not checked. [2018-01-24 13:48:56,263 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:56,263 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:48:56,268 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:56,268 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:48:56,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:56,295 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:56,334 INFO L134 CoverageAnalysis]: Checked inductivity of 2402 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 354 trivial. 0 not checked. [2018-01-24 13:48:56,335 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:57,203 INFO L134 CoverageAnalysis]: Checked inductivity of 2402 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 354 trivial. 0 not checked. [2018-01-24 13:48:57,222 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:48:57,222 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 63 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:48:57,226 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:48:57,226 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:48:57,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:48:57,289 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:48:57,331 INFO L134 CoverageAnalysis]: Checked inductivity of 2402 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 354 trivial. 0 not checked. [2018-01-24 13:48:57,331 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:48:57,369 INFO L134 CoverageAnalysis]: Checked inductivity of 2402 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 354 trivial. 0 not checked. [2018-01-24 13:48:57,370 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:48:57,370 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35, 35, 35] total 68 [2018-01-24 13:48:57,371 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:48:57,371 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-01-24 13:48:57,371 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-01-24 13:48:57,372 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-01-24 13:48:57,372 INFO L87 Difference]: Start difference. First operand 199 states and 200 transitions. Second operand 35 states. Received shutdown request... [2018-01-24 13:48:57,744 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-24 13:48:57,744 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 13:48:57,749 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 13:48:57,749 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 01:48:57 BoogieIcfgContainer [2018-01-24 13:48:57,749 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 13:48:57,750 INFO L168 Benchmark]: Toolchain (without parser) took 49005.47 ms. Allocated memory was 303.0 MB in the beginning and 753.9 MB in the end (delta: 450.9 MB). Free memory was 264.1 MB in the beginning and 389.4 MB in the end (delta: -125.4 MB). Peak memory consumption was 325.5 MB. Max. memory is 5.3 GB. [2018-01-24 13:48:57,751 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 303.0 MB. Free memory is still 269.1 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 13:48:57,751 INFO L168 Benchmark]: CACSL2BoogieTranslator took 162.13 ms. Allocated memory is still 303.0 MB. Free memory was 264.1 MB in the beginning and 255.8 MB in the end (delta: 8.2 MB). Peak memory consumption was 8.2 MB. Max. memory is 5.3 GB. [2018-01-24 13:48:57,752 INFO L168 Benchmark]: Boogie Preprocessor took 24.68 ms. Allocated memory is still 303.0 MB. Free memory was 255.8 MB in the beginning and 253.9 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 13:48:57,752 INFO L168 Benchmark]: RCFGBuilder took 188.61 ms. Allocated memory is still 303.0 MB. Free memory was 253.9 MB in the beginning and 242.1 MB in the end (delta: 11.7 MB). Peak memory consumption was 11.7 MB. Max. memory is 5.3 GB. [2018-01-24 13:48:57,752 INFO L168 Benchmark]: TraceAbstraction took 48623.88 ms. Allocated memory was 303.0 MB in the beginning and 753.9 MB in the end (delta: 450.9 MB). Free memory was 242.1 MB in the beginning and 389.4 MB in the end (delta: -147.3 MB). Peak memory consumption was 303.6 MB. Max. memory is 5.3 GB. [2018-01-24 13:48:57,754 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 303.0 MB. Free memory is still 269.1 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 162.13 ms. Allocated memory is still 303.0 MB. Free memory was 264.1 MB in the beginning and 255.8 MB in the end (delta: 8.2 MB). Peak memory consumption was 8.2 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 24.68 ms. Allocated memory is still 303.0 MB. Free memory was 255.8 MB in the beginning and 253.9 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 188.61 ms. Allocated memory is still 303.0 MB. Free memory was 253.9 MB in the beginning and 242.1 MB in the end (delta: 11.7 MB). Peak memory consumption was 11.7 MB. Max. memory is 5.3 GB. * TraceAbstraction took 48623.88 ms. Allocated memory was 303.0 MB in the beginning and 753.9 MB in the end (delta: 450.9 MB). Free memory was 242.1 MB in the beginning and 389.4 MB in the end (delta: -147.3 MB). Peak memory consumption was 303.6 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was constructing difference of abstraction (199states) and interpolant automaton (currently 35 states, 35 states before enhancement), while ReachableStatesComputation was computing reachable states (347 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 15]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 15). Cancelled while BasicCegarLoop was constructing difference of abstraction (199states) and interpolant automaton (currently 35 states, 35 states before enhancement), while ReachableStatesComputation was computing reachable states (347 states constructedinput type IntersectNwa). - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 27 locations, 2 error locations. TIMEOUT Result, 48.5s OverallTime, 33 OverallIterations, 33 TraceHistogramMax, 8.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 544 SDtfs, 4121 SDslu, 5161 SDs, 0 SdLazy, 8437 SolverSat, 1294 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 14378 GetRequests, 13291 SyntacticMatches, 0 SemanticMatches, 1087 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5325 ImplicationChecksByTransitivity, 15.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=199occurred in iteration=32, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.6s AutomataMinimizationTime, 32 MinimizatonAttempts, 1789 StatesRemovedByMinimization, 32 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.3s SsaConstructionTime, 17.5s SatisfiabilityAnalysisTime, 20.4s InterpolantComputationTime, 10383 NumberOfCodeBlocks, 9783 NumberOfCodeBlocksAsserted, 495 NumberOfCheckSat, 17132 ConstructedInterpolants, 0 QuantifiedInterpolants, 5368510 SizeOfPredicates, 42 NumberOfNonLiveVariables, 9928 ConjunctsInSsa, 1108 ConjunctsInUnsatCore, 157 InterpolantComputations, 2 PerfectInterpolantSequences, 45750/134620 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_13-48-57-761.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_13-48-57-761.csv Completed graceful shutdown