java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test12_true-valid-memsafety.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 13:29:48,605 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 13:29:48,608 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 13:29:48,623 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 13:29:48,623 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 13:29:48,624 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 13:29:48,626 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 13:29:48,627 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 13:29:48,629 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 13:29:48,630 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 13:29:48,631 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 13:29:48,631 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 13:29:48,632 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 13:29:48,634 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 13:29:48,635 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 13:29:48,637 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 13:29:48,640 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 13:29:48,642 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 13:29:48,643 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 13:29:48,645 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 13:29:48,647 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 13:29:48,648 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 13:29:48,648 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 13:29:48,649 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 13:29:48,650 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 13:29:48,651 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 13:29:48,652 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 13:29:48,652 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 13:29:48,653 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 13:29:48,653 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 13:29:48,654 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 13:29:48,654 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf [2018-01-24 13:29:48,664 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 13:29:48,664 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 13:29:48,665 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 13:29:48,665 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 13:29:48,666 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 13:29:48,666 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 13:29:48,666 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 13:29:48,666 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 13:29:48,666 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 13:29:48,667 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 13:29:48,667 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 13:29:48,667 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 13:29:48,667 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 13:29:48,667 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 13:29:48,667 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 13:29:48,667 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 13:29:48,667 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 13:29:48,668 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 13:29:48,668 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 13:29:48,668 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 13:29:48,668 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 13:29:48,668 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 13:29:48,668 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 13:29:48,669 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:29:48,669 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 13:29:48,669 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 13:29:48,669 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 13:29:48,669 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 13:29:48,670 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-01-24 13:29:48,670 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 13:29:48,670 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 13:29:48,670 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 13:29:48,671 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 13:29:48,671 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 13:29:48,704 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 13:29:48,716 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 13:29:48,720 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 13:29:48,721 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 13:29:48,722 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 13:29:48,722 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test12_true-valid-memsafety.i [2018-01-24 13:29:48,921 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 13:29:48,925 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 13:29:48,926 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 13:29:48,926 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 13:29:48,932 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 13:29:48,933 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:29:48" (1/1) ... [2018-01-24 13:29:48,936 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@31a394a6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:29:48, skipping insertion in model container [2018-01-24 13:29:48,936 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:29:48" (1/1) ... [2018-01-24 13:29:48,951 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:29:49,009 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:29:49,167 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:29:49,215 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:29:49,233 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:29:49 WrapperNode [2018-01-24 13:29:49,233 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 13:29:49,236 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 13:29:49,236 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 13:29:49,236 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 13:29:49,257 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:29:49" (1/1) ... [2018-01-24 13:29:49,258 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:29:49" (1/1) ... [2018-01-24 13:29:49,276 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:29:49" (1/1) ... [2018-01-24 13:29:49,277 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:29:49" (1/1) ... [2018-01-24 13:29:49,298 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:29:49" (1/1) ... [2018-01-24 13:29:49,313 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:29:49" (1/1) ... [2018-01-24 13:29:49,322 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:29:49" (1/1) ... [2018-01-24 13:29:49,328 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 13:29:49,328 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 13:29:49,328 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 13:29:49,329 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 13:29:49,330 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:29:49" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:29:49,381 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 13:29:49,382 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 13:29:49,382 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~$Pointer$~X~int~TO~int [2018-01-24 13:29:49,382 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-01-24 13:29:49,382 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-01-24 13:29:49,382 INFO L136 BoogieDeclarations]: Found implementation of procedure __ldv_list_add [2018-01-24 13:29:49,382 INFO L136 BoogieDeclarations]: Found implementation of procedure __ldv_list_del [2018-01-24 13:29:49,383 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_list_add [2018-01-24 13:29:49,383 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_list_del [2018-01-24 13:29:49,383 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_alloc [2018-01-24 13:29:49,383 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_fill [2018-01-24 13:29:49,383 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_free [2018-01-24 13:29:49,383 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_submit_msg [2018-01-24 13:29:49,384 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_destroy_msgs [2018-01-24 13:29:49,384 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-01-24 13:29:49,384 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-01-24 13:29:49,384 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-01-24 13:29:49,384 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-01-24 13:29:49,384 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_get_clientdata [2018-01-24 13:29:49,385 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_set_clientdata [2018-01-24 13:29:49,385 INFO L136 BoogieDeclarations]: Found implementation of procedure master_xfer [2018-01-24 13:29:49,385 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_transfer [2018-01-24 13:29:49,385 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_m88ts2022_rd_reg [2018-01-24 13:29:49,385 INFO L136 BoogieDeclarations]: Found implementation of procedure alloc_fix_12 [2018-01-24 13:29:49,386 INFO L136 BoogieDeclarations]: Found implementation of procedure free_12 [2018-01-24 13:29:49,386 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-01-24 13:29:49,386 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 13:29:49,386 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 13:29:49,386 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 13:29:49,387 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-01-24 13:29:49,387 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-01-24 13:29:49,387 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 13:29:49,387 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 13:29:49,387 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 13:29:49,387 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2018-01-24 13:29:49,387 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2018-01-24 13:29:49,388 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-01-24 13:29:49,388 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-01-24 13:29:49,388 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 13:29:49,388 INFO L128 BoogieDeclarations]: Found specification of procedure memcpy [2018-01-24 13:29:49,388 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-01-24 13:29:49,388 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-01-24 13:29:49,389 INFO L128 BoogieDeclarations]: Found specification of procedure __ldv_list_add [2018-01-24 13:29:49,389 INFO L128 BoogieDeclarations]: Found specification of procedure __ldv_list_del [2018-01-24 13:29:49,389 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_list_add [2018-01-24 13:29:49,389 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_list_del [2018-01-24 13:29:49,389 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_alloc [2018-01-24 13:29:49,389 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_fill [2018-01-24 13:29:49,389 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_free [2018-01-24 13:29:49,390 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_submit_msg [2018-01-24 13:29:49,390 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_destroy_msgs [2018-01-24 13:29:49,390 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-01-24 13:29:49,390 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-01-24 13:29:49,390 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-01-24 13:29:49,390 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-01-24 13:29:49,390 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_get_clientdata [2018-01-24 13:29:49,391 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_set_clientdata [2018-01-24 13:29:49,391 INFO L128 BoogieDeclarations]: Found specification of procedure master_xfer [2018-01-24 13:29:49,391 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_transfer [2018-01-24 13:29:49,391 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~$Pointer$~X~int~TO~int [2018-01-24 13:29:49,391 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_m88ts2022_rd_reg [2018-01-24 13:29:49,391 INFO L128 BoogieDeclarations]: Found specification of procedure alloc_fix_12 [2018-01-24 13:29:49,391 INFO L128 BoogieDeclarations]: Found specification of procedure free_12 [2018-01-24 13:29:49,392 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-01-24 13:29:49,392 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 13:29:49,392 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 13:29:49,392 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 13:29:50,705 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-01-24 13:29:50,842 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 13:29:50,843 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:29:50 BoogieIcfgContainer [2018-01-24 13:29:50,843 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 13:29:50,844 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 13:29:50,844 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 13:29:50,846 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 13:29:50,846 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 01:29:48" (1/3) ... [2018-01-24 13:29:50,847 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5a30d1cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:29:50, skipping insertion in model container [2018-01-24 13:29:50,847 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:29:49" (2/3) ... [2018-01-24 13:29:50,848 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5a30d1cf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:29:50, skipping insertion in model container [2018-01-24 13:29:50,848 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:29:50" (3/3) ... [2018-01-24 13:29:50,850 INFO L105 eAbstractionObserver]: Analyzing ICFG memleaks_test12_true-valid-memsafety.i [2018-01-24 13:29:50,857 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 13:29:50,867 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 141 error locations. [2018-01-24 13:29:50,946 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 13:29:50,946 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 13:29:50,946 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 13:29:50,946 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 13:29:50,946 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 13:29:50,947 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 13:29:50,947 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 13:29:50,947 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 13:29:50,948 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 13:29:50,977 INFO L276 IsEmpty]: Start isEmpty. Operand 398 states. [2018-01-24 13:29:50,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-01-24 13:29:50,982 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:29:50,983 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-01-24 13:29:50,983 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:29:50,987 INFO L82 PathProgramCache]: Analyzing trace with hash 18685926, now seen corresponding path program 1 times [2018-01-24 13:29:50,989 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:29:51,040 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:51,040 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:51,040 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:51,040 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:29:51,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:51,190 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:29:51,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:29:51,280 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:29:51,281 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 13:29:51,281 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:29:51,285 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 13:29:51,300 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 13:29:51,301 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 13:29:51,304 INFO L87 Difference]: Start difference. First operand 398 states. Second operand 3 states. [2018-01-24 13:29:52,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:29:52,042 INFO L93 Difference]: Finished difference Result 668 states and 724 transitions. [2018-01-24 13:29:52,042 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 13:29:52,043 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2018-01-24 13:29:52,043 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:29:52,059 INFO L225 Difference]: With dead ends: 668 [2018-01-24 13:29:52,059 INFO L226 Difference]: Without dead ends: 481 [2018-01-24 13:29:52,064 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 13:29:52,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-01-24 13:29:52,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 436. [2018-01-24 13:29:52,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 436 states. [2018-01-24 13:29:52,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 491 transitions. [2018-01-24 13:29:52,152 INFO L78 Accepts]: Start accepts. Automaton has 436 states and 491 transitions. Word has length 4 [2018-01-24 13:29:52,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:29:52,152 INFO L432 AbstractCegarLoop]: Abstraction has 436 states and 491 transitions. [2018-01-24 13:29:52,152 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 13:29:52,152 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 491 transitions. [2018-01-24 13:29:52,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-01-24 13:29:52,153 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:29:52,153 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-01-24 13:29:52,153 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:29:52,153 INFO L82 PathProgramCache]: Analyzing trace with hash 18685927, now seen corresponding path program 1 times [2018-01-24 13:29:52,153 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:29:52,155 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:52,155 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:52,155 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:52,155 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:29:52,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:52,170 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:29:52,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:29:52,215 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:29:52,215 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 13:29:52,215 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:29:52,217 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 13:29:52,217 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 13:29:52,217 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 13:29:52,217 INFO L87 Difference]: Start difference. First operand 436 states and 491 transitions. Second operand 3 states. [2018-01-24 13:29:52,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:29:52,546 INFO L93 Difference]: Finished difference Result 570 states and 656 transitions. [2018-01-24 13:29:52,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 13:29:52,546 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2018-01-24 13:29:52,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:29:52,552 INFO L225 Difference]: With dead ends: 570 [2018-01-24 13:29:52,552 INFO L226 Difference]: Without dead ends: 567 [2018-01-24 13:29:52,554 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 13:29:52,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states. [2018-01-24 13:29:52,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 497. [2018-01-24 13:29:52,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 497 states. [2018-01-24 13:29:52,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 497 states to 497 states and 602 transitions. [2018-01-24 13:29:52,602 INFO L78 Accepts]: Start accepts. Automaton has 497 states and 602 transitions. Word has length 4 [2018-01-24 13:29:52,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:29:52,602 INFO L432 AbstractCegarLoop]: Abstraction has 497 states and 602 transitions. [2018-01-24 13:29:52,602 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 13:29:52,603 INFO L276 IsEmpty]: Start isEmpty. Operand 497 states and 602 transitions. [2018-01-24 13:29:52,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-01-24 13:29:52,603 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:29:52,603 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:29:52,604 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:29:52,604 INFO L82 PathProgramCache]: Analyzing trace with hash -769194584, now seen corresponding path program 1 times [2018-01-24 13:29:52,604 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:29:52,605 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:52,605 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:52,605 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:52,606 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:29:52,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:52,630 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:29:52,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:29:52,689 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:29:52,689 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 13:29:52,689 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:29:52,690 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:29:52,690 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:29:52,690 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:29:52,690 INFO L87 Difference]: Start difference. First operand 497 states and 602 transitions. Second operand 6 states. [2018-01-24 13:29:52,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:29:52,829 INFO L93 Difference]: Finished difference Result 624 states and 762 transitions. [2018-01-24 13:29:52,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:29:52,829 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-01-24 13:29:52,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:29:52,834 INFO L225 Difference]: With dead ends: 624 [2018-01-24 13:29:52,834 INFO L226 Difference]: Without dead ends: 543 [2018-01-24 13:29:52,835 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:29:52,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states. [2018-01-24 13:29:52,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 496. [2018-01-24 13:29:52,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 496 states. [2018-01-24 13:29:52,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 496 states to 496 states and 604 transitions. [2018-01-24 13:29:52,868 INFO L78 Accepts]: Start accepts. Automaton has 496 states and 604 transitions. Word has length 21 [2018-01-24 13:29:52,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:29:52,868 INFO L432 AbstractCegarLoop]: Abstraction has 496 states and 604 transitions. [2018-01-24 13:29:52,868 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:29:52,869 INFO L276 IsEmpty]: Start isEmpty. Operand 496 states and 604 transitions. [2018-01-24 13:29:52,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-01-24 13:29:52,870 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:29:52,870 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:29:52,870 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:29:52,870 INFO L82 PathProgramCache]: Analyzing trace with hash 976272294, now seen corresponding path program 1 times [2018-01-24 13:29:52,870 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:29:52,872 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:52,872 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:52,872 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:52,873 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:29:52,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:52,900 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:29:52,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:29:52,991 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:29:52,991 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 13:29:52,991 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:29:52,992 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 13:29:52,992 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 13:29:52,992 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:29:52,992 INFO L87 Difference]: Start difference. First operand 496 states and 604 transitions. Second operand 5 states. [2018-01-24 13:29:53,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:29:53,501 INFO L93 Difference]: Finished difference Result 572 states and 705 transitions. [2018-01-24 13:29:53,501 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:29:53,501 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2018-01-24 13:29:53,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:29:53,505 INFO L225 Difference]: With dead ends: 572 [2018-01-24 13:29:53,505 INFO L226 Difference]: Without dead ends: 571 [2018-01-24 13:29:53,506 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:29:53,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 571 states. [2018-01-24 13:29:53,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 571 to 538. [2018-01-24 13:29:53,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-01-24 13:29:53,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 661 transitions. [2018-01-24 13:29:53,542 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 661 transitions. Word has length 21 [2018-01-24 13:29:53,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:29:53,542 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 661 transitions. [2018-01-24 13:29:53,542 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 13:29:53,543 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 661 transitions. [2018-01-24 13:29:53,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-01-24 13:29:53,543 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:29:53,544 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:29:53,544 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:29:53,544 INFO L82 PathProgramCache]: Analyzing trace with hash 976272295, now seen corresponding path program 1 times [2018-01-24 13:29:53,544 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:29:53,546 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:53,546 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:53,546 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:53,546 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:29:53,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:53,567 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:29:53,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:29:53,854 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:29:53,854 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 13:29:53,854 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:29:53,855 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:29:53,855 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:29:53,855 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:29:53,855 INFO L87 Difference]: Start difference. First operand 538 states and 661 transitions. Second operand 7 states. [2018-01-24 13:29:55,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:29:55,489 INFO L93 Difference]: Finished difference Result 669 states and 772 transitions. [2018-01-24 13:29:55,490 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:29:55,490 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 21 [2018-01-24 13:29:55,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:29:55,494 INFO L225 Difference]: With dead ends: 669 [2018-01-24 13:29:55,495 INFO L226 Difference]: Without dead ends: 668 [2018-01-24 13:29:55,495 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 5 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=51, Invalid=105, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:29:55,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 668 states. [2018-01-24 13:29:55,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 668 to 538. [2018-01-24 13:29:55,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-01-24 13:29:55,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 660 transitions. [2018-01-24 13:29:55,562 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 660 transitions. Word has length 21 [2018-01-24 13:29:55,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:29:55,563 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 660 transitions. [2018-01-24 13:29:55,563 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:29:55,563 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 660 transitions. [2018-01-24 13:29:55,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-01-24 13:29:55,564 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:29:55,565 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:29:55,565 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:29:55,565 INFO L82 PathProgramCache]: Analyzing trace with hash 886332479, now seen corresponding path program 1 times [2018-01-24 13:29:55,566 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:29:55,567 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:55,568 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:55,568 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:55,568 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:29:55,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:55,583 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:29:55,636 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:29:55,636 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:29:55,637 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:29:55,649 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:55,649 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:29:55,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:55,691 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:29:55,782 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:29:55,782 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:29:55,811 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:29:55,847 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:29:55,847 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:29:55,854 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:55,854 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:29:55,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:55,909 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:29:55,913 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:29:55,914 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:29:55,946 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:29:55,948 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:29:55,948 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 4, 4, 4] total 8 [2018-01-24 13:29:55,948 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:29:55,948 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:29:55,949 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:29:55,949 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:29:55,949 INFO L87 Difference]: Start difference. First operand 538 states and 660 transitions. Second operand 8 states. [2018-01-24 13:29:56,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:29:56,147 INFO L93 Difference]: Finished difference Result 1019 states and 1220 transitions. [2018-01-24 13:29:56,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:29:56,148 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 24 [2018-01-24 13:29:56,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:29:56,151 INFO L225 Difference]: With dead ends: 1019 [2018-01-24 13:29:56,151 INFO L226 Difference]: Without dead ends: 503 [2018-01-24 13:29:56,155 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 99 GetRequests, 93 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:29:56,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 503 states. [2018-01-24 13:29:56,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 503 to 495. [2018-01-24 13:29:56,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 495 states. [2018-01-24 13:29:56,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 495 states to 495 states and 574 transitions. [2018-01-24 13:29:56,191 INFO L78 Accepts]: Start accepts. Automaton has 495 states and 574 transitions. Word has length 24 [2018-01-24 13:29:56,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:29:56,191 INFO L432 AbstractCegarLoop]: Abstraction has 495 states and 574 transitions. [2018-01-24 13:29:56,191 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:29:56,191 INFO L276 IsEmpty]: Start isEmpty. Operand 495 states and 574 transitions. [2018-01-24 13:29:56,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-01-24 13:29:56,192 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:29:56,192 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:29:56,193 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:29:56,193 INFO L82 PathProgramCache]: Analyzing trace with hash -1359343331, now seen corresponding path program 1 times [2018-01-24 13:29:56,193 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:29:56,194 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:56,195 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:56,195 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:56,195 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:29:56,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:56,212 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:29:56,534 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:29:56,534 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:29:56,534 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:29:56,543 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:56,543 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:29:56,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:56,580 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:29:56,630 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:29:56,630 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:29:56,773 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:29:56,809 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:29:56,809 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:29:56,815 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:56,816 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:29:56,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:56,869 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:29:56,910 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:29:56,910 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:29:57,222 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:29:57,231 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:29:57,231 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 5 [2018-01-24 13:29:57,231 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:29:57,232 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:29:57,232 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:29:57,232 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:29:57,232 INFO L87 Difference]: Start difference. First operand 495 states and 574 transitions. Second operand 6 states. [2018-01-24 13:29:57,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:29:57,904 INFO L93 Difference]: Finished difference Result 497 states and 581 transitions. [2018-01-24 13:29:57,905 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 13:29:57,905 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 26 [2018-01-24 13:29:57,905 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:29:57,908 INFO L225 Difference]: With dead ends: 497 [2018-01-24 13:29:57,908 INFO L226 Difference]: Without dead ends: 496 [2018-01-24 13:29:57,909 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 109 GetRequests, 88 SyntacticMatches, 16 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:29:57,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states. [2018-01-24 13:29:57,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 494. [2018-01-24 13:29:57,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 494 states. [2018-01-24 13:29:57,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 494 states to 494 states and 572 transitions. [2018-01-24 13:29:57,944 INFO L78 Accepts]: Start accepts. Automaton has 494 states and 572 transitions. Word has length 26 [2018-01-24 13:29:57,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:29:57,944 INFO L432 AbstractCegarLoop]: Abstraction has 494 states and 572 transitions. [2018-01-24 13:29:57,944 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:29:57,944 INFO L276 IsEmpty]: Start isEmpty. Operand 494 states and 572 transitions. [2018-01-24 13:29:57,946 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-01-24 13:29:57,946 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:29:57,947 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:29:57,947 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:29:57,947 INFO L82 PathProgramCache]: Analyzing trace with hash -1359343330, now seen corresponding path program 1 times [2018-01-24 13:29:57,947 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:29:57,949 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:57,950 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:57,950 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:29:57,950 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:29:57,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:57,978 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:29:58,045 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:29:58,046 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:29:58,046 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:29:58,057 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:58,057 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:29:58,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:58,092 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:29:58,121 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:29:58,123 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:29:58,125 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:29:58,125 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-24 13:29:58,156 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:29:58,156 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:29:58,533 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:29:58,567 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:29:58,568 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:29:58,577 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:29:58,577 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:29:58,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:29:58,636 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:29:58,643 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:29:58,643 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:29:58,654 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:29:58,655 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-24 13:29:58,763 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:29:58,763 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:29:58,868 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:29:58,870 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:29:58,871 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 7 [2018-01-24 13:29:58,871 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:29:58,871 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:29:58,872 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:29:58,872 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:29:58,872 INFO L87 Difference]: Start difference. First operand 494 states and 572 transitions. Second operand 7 states. [2018-01-24 13:30:01,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:30:01,014 INFO L93 Difference]: Finished difference Result 602 states and 710 transitions. [2018-01-24 13:30:01,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 13:30:01,037 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 26 [2018-01-24 13:30:01,038 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:30:01,042 INFO L225 Difference]: With dead ends: 602 [2018-01-24 13:30:01,042 INFO L226 Difference]: Without dead ends: 592 [2018-01-24 13:30:01,043 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 86 SyntacticMatches, 17 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-01-24 13:30:01,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states. [2018-01-24 13:30:01,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 521. [2018-01-24 13:30:01,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 521 states. [2018-01-24 13:30:01,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 620 transitions. [2018-01-24 13:30:01,084 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 620 transitions. Word has length 26 [2018-01-24 13:30:01,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:30:01,085 INFO L432 AbstractCegarLoop]: Abstraction has 521 states and 620 transitions. [2018-01-24 13:30:01,085 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:30:01,085 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 620 transitions. [2018-01-24 13:30:01,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-01-24 13:30:01,086 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:30:01,086 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:30:01,086 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:30:01,087 INFO L82 PathProgramCache]: Analyzing trace with hash -1359343329, now seen corresponding path program 1 times [2018-01-24 13:30:01,087 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:30:01,090 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:01,090 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:30:01,090 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:01,091 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:30:01,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:30:01,108 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:30:01,431 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:30:01,431 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:30:01,431 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:30:01,431 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:30:01,431 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 13:30:01,431 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 13:30:01,431 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:30:01,432 INFO L87 Difference]: Start difference. First operand 521 states and 620 transitions. Second operand 5 states. [2018-01-24 13:30:01,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:30:01,494 INFO L93 Difference]: Finished difference Result 955 states and 1116 transitions. [2018-01-24 13:30:01,495 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:30:01,495 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 26 [2018-01-24 13:30:01,495 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:30:01,497 INFO L225 Difference]: With dead ends: 955 [2018-01-24 13:30:01,498 INFO L226 Difference]: Without dead ends: 523 [2018-01-24 13:30:01,500 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:30:01,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 523 states. [2018-01-24 13:30:01,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 523 to 520. [2018-01-24 13:30:01,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 520 states. [2018-01-24 13:30:01,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 520 states to 520 states and 617 transitions. [2018-01-24 13:30:01,532 INFO L78 Accepts]: Start accepts. Automaton has 520 states and 617 transitions. Word has length 26 [2018-01-24 13:30:01,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:30:01,532 INFO L432 AbstractCegarLoop]: Abstraction has 520 states and 617 transitions. [2018-01-24 13:30:01,532 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 13:30:01,533 INFO L276 IsEmpty]: Start isEmpty. Operand 520 states and 617 transitions. [2018-01-24 13:30:01,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 13:30:01,533 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:30:01,534 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:30:01,534 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:30:01,534 INFO L82 PathProgramCache]: Analyzing trace with hash -1082862565, now seen corresponding path program 1 times [2018-01-24 13:30:01,534 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:30:01,535 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:01,536 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:30:01,536 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:01,536 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:30:01,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:30:01,551 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:30:01,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:30:01,640 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:30:01,640 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 13:30:01,640 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:30:01,641 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 13:30:01,641 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 13:30:01,641 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:30:01,641 INFO L87 Difference]: Start difference. First operand 520 states and 617 transitions. Second operand 5 states. [2018-01-24 13:30:02,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:30:02,298 INFO L93 Difference]: Finished difference Result 543 states and 651 transitions. [2018-01-24 13:30:02,298 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:30:02,298 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-01-24 13:30:02,298 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:30:02,300 INFO L225 Difference]: With dead ends: 543 [2018-01-24 13:30:02,301 INFO L226 Difference]: Without dead ends: 541 [2018-01-24 13:30:02,301 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:30:02,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541 states. [2018-01-24 13:30:02,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541 to 537. [2018-01-24 13:30:02,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 537 states. [2018-01-24 13:30:02,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 537 states to 537 states and 638 transitions. [2018-01-24 13:30:02,329 INFO L78 Accepts]: Start accepts. Automaton has 537 states and 638 transitions. Word has length 27 [2018-01-24 13:30:02,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:30:02,330 INFO L432 AbstractCegarLoop]: Abstraction has 537 states and 638 transitions. [2018-01-24 13:30:02,330 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 13:30:02,330 INFO L276 IsEmpty]: Start isEmpty. Operand 537 states and 638 transitions. [2018-01-24 13:30:02,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 13:30:02,331 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:30:02,331 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:30:02,331 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:30:02,331 INFO L82 PathProgramCache]: Analyzing trace with hash -1082862564, now seen corresponding path program 1 times [2018-01-24 13:30:02,332 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:30:02,333 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:02,333 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:30:02,333 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:02,333 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:30:02,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:30:02,346 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:30:02,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:30:02,550 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:30:02,550 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-01-24 13:30:02,550 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:30:02,550 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:30:02,551 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:30:02,551 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:30:02,551 INFO L87 Difference]: Start difference. First operand 537 states and 638 transitions. Second operand 8 states. [2018-01-24 13:30:02,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:30:02,924 INFO L93 Difference]: Finished difference Result 627 states and 738 transitions. [2018-01-24 13:30:02,924 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:30:02,924 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27 [2018-01-24 13:30:02,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:30:02,926 INFO L225 Difference]: With dead ends: 627 [2018-01-24 13:30:02,927 INFO L226 Difference]: Without dead ends: 488 [2018-01-24 13:30:02,928 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2018-01-24 13:30:02,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states. [2018-01-24 13:30:02,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 477. [2018-01-24 13:30:02,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 477 states. [2018-01-24 13:30:02,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 477 states and 550 transitions. [2018-01-24 13:30:02,955 INFO L78 Accepts]: Start accepts. Automaton has 477 states and 550 transitions. Word has length 27 [2018-01-24 13:30:02,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:30:02,956 INFO L432 AbstractCegarLoop]: Abstraction has 477 states and 550 transitions. [2018-01-24 13:30:02,956 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:30:02,956 INFO L276 IsEmpty]: Start isEmpty. Operand 477 states and 550 transitions. [2018-01-24 13:30:02,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-24 13:30:02,957 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:30:02,957 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:30:02,957 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:30:02,957 INFO L82 PathProgramCache]: Analyzing trace with hash -1622671872, now seen corresponding path program 1 times [2018-01-24 13:30:02,957 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:30:02,959 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:02,959 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:30:02,959 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:02,959 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:30:02,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:30:02,971 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:30:03,042 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:30:03,043 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:30:03,043 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 13:30:03,043 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:30:03,043 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:30:03,043 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:30:03,043 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:30:03,044 INFO L87 Difference]: Start difference. First operand 477 states and 550 transitions. Second operand 6 states. [2018-01-24 13:30:03,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:30:03,092 INFO L93 Difference]: Finished difference Result 497 states and 568 transitions. [2018-01-24 13:30:03,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:30:03,097 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2018-01-24 13:30:03,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:30:03,100 INFO L225 Difference]: With dead ends: 497 [2018-01-24 13:30:03,100 INFO L226 Difference]: Without dead ends: 478 [2018-01-24 13:30:03,100 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:30:03,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states. [2018-01-24 13:30:03,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 476. [2018-01-24 13:30:03,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 476 states. [2018-01-24 13:30:03,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 476 states to 476 states and 547 transitions. [2018-01-24 13:30:03,118 INFO L78 Accepts]: Start accepts. Automaton has 476 states and 547 transitions. Word has length 28 [2018-01-24 13:30:03,119 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:30:03,119 INFO L432 AbstractCegarLoop]: Abstraction has 476 states and 547 transitions. [2018-01-24 13:30:03,119 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:30:03,119 INFO L276 IsEmpty]: Start isEmpty. Operand 476 states and 547 transitions. [2018-01-24 13:30:03,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-24 13:30:03,119 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:30:03,120 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:30:03,120 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:30:03,120 INFO L82 PathProgramCache]: Analyzing trace with hash -1622671871, now seen corresponding path program 1 times [2018-01-24 13:30:03,120 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:30:03,121 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:03,121 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:30:03,122 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:03,122 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:30:03,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:30:03,136 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:30:03,677 WARN L146 SmtUtils]: Spent 370ms on a formula simplification. DAG size of input: 18 DAG size of output 14 [2018-01-24 13:30:04,032 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:30:04,032 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:30:04,032 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:30:04,061 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:30:04,061 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:30:04,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:30:04,091 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:30:04,112 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2018-01-24 13:30:04,112 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:04,130 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-01-24 13:30:04,131 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:04,132 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-01-24 13:30:04,133 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:04,151 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-01-24 13:30:04,151 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:04,172 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-01-24 13:30:04,172 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:50, output treesize:46 [2018-01-24 13:30:04,443 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:04,460 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:04,463 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2018-01-24 13:30:04,464 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:04,563 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:04,564 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 37 [2018-01-24 13:30:04,565 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:04,626 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:04,628 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 35 [2018-01-24 13:30:04,628 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:04,678 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:04,680 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:04,683 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 25 [2018-01-24 13:30:04,683 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:04,741 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-01-24 13:30:04,741 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:67, output treesize:49 [2018-01-24 13:30:04,999 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:30:04,999 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:30:05,208 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 15 [2018-01-24 13:30:13,598 WARN L146 SmtUtils]: Spent 8063ms on a formula simplification. DAG size of input: 68 DAG size of output 31 [2018-01-24 13:30:13,679 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 50 [2018-01-24 13:30:14,541 WARN L146 SmtUtils]: Spent 506ms on a formula simplification. DAG size of input: 76 DAG size of output 37 [2018-01-24 13:30:14,892 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2018-01-24 13:30:14,893 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:14,917 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 18 [2018-01-24 13:30:14,917 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:14,933 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 31 [2018-01-24 13:30:14,955 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-01-24 13:30:14,955 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:14,961 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:30:14,979 INFO L267 ElimStorePlain]: Start of recursive call 1: 6 dim-0 vars, 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-01-24 13:30:14,979 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 10 variables, input treesize:82, output treesize:21 [2018-01-24 13:30:15,023 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:30:15,045 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:30:15,045 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:30:15,057 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:30:15,058 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:30:15,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:30:15,106 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:30:15,119 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2018-01-24 13:30:15,120 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:15,207 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-01-24 13:30:15,207 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:15,209 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-01-24 13:30:15,210 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:15,242 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-01-24 13:30:15,243 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:15,257 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-01-24 13:30:15,258 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:50, output treesize:46 [2018-01-24 13:30:15,293 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:15,293 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:15,294 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2018-01-24 13:30:15,294 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:15,312 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:15,314 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 35 [2018-01-24 13:30:15,314 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:15,333 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:15,334 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 37 [2018-01-24 13:30:15,334 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:15,353 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:15,353 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:15,354 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 25 [2018-01-24 13:30:15,354 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:15,368 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-01-24 13:30:15,369 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:67, output treesize:49 [2018-01-24 13:30:15,376 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:30:15,376 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:30:15,486 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 13:30:21,878 WARN L146 SmtUtils]: Spent 4188ms on a formula simplification. DAG size of input: 72 DAG size of output 26 [2018-01-24 13:30:21,891 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 25 [2018-01-24 13:30:22,436 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2018-01-24 13:30:22,437 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:22,455 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 31 [2018-01-24 13:30:22,473 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-01-24 13:30:22,473 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:22,479 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:30:22,492 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 18 [2018-01-24 13:30:22,492 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:22,504 INFO L267 ElimStorePlain]: Start of recursive call 1: 6 dim-0 vars, 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-01-24 13:30:22,505 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 10 variables, input treesize:82, output treesize:21 [2018-01-24 13:30:22,511 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:30:22,512 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:30:22,512 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9, 9, 9] total 26 [2018-01-24 13:30:22,512 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:30:22,512 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 13:30:22,513 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 13:30:22,513 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=617, Unknown=3, NotChecked=0, Total=702 [2018-01-24 13:30:22,513 INFO L87 Difference]: Start difference. First operand 476 states and 547 transitions. Second operand 18 states. [2018-01-24 13:30:22,839 WARN L146 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 67 DAG size of output 64 [2018-01-24 13:30:43,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:30:43,982 INFO L93 Difference]: Finished difference Result 666 states and 776 transitions. [2018-01-24 13:30:43,983 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 13:30:43,983 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 28 [2018-01-24 13:30:43,983 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:30:43,985 INFO L225 Difference]: With dead ends: 666 [2018-01-24 13:30:43,986 INFO L226 Difference]: Without dead ends: 663 [2018-01-24 13:30:43,986 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 128 GetRequests, 91 SyntacticMatches, 5 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 258 ImplicationChecksByTransitivity, 22.2s TimeCoverageRelationStatistics Valid=157, Invalid=960, Unknown=5, NotChecked=0, Total=1122 [2018-01-24 13:30:43,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 663 states. [2018-01-24 13:30:44,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 663 to 485. [2018-01-24 13:30:44,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 485 states. [2018-01-24 13:30:44,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 485 states to 485 states and 562 transitions. [2018-01-24 13:30:44,027 INFO L78 Accepts]: Start accepts. Automaton has 485 states and 562 transitions. Word has length 28 [2018-01-24 13:30:44,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:30:44,027 INFO L432 AbstractCegarLoop]: Abstraction has 485 states and 562 transitions. [2018-01-24 13:30:44,027 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 13:30:44,028 INFO L276 IsEmpty]: Start isEmpty. Operand 485 states and 562 transitions. [2018-01-24 13:30:44,028 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-24 13:30:44,028 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:30:44,029 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:30:44,029 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:30:44,029 INFO L82 PathProgramCache]: Analyzing trace with hash -1622671872, now seen corresponding path program 1 times [2018-01-24 13:30:44,029 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:30:44,031 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:44,031 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:30:44,031 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:44,031 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:30:44,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:30:44,044 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:30:44,413 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:30:44,413 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:30:44,413 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:30:44,426 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:30:44,426 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:30:44,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:30:44,485 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:30:44,507 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:30:44,507 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:44,521 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:30:44,522 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-24 13:30:44,613 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:44,614 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:44,615 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-01-24 13:30:44,615 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:44,621 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 13:30:44,621 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-01-24 13:30:44,639 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:30:44,639 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:30:45,249 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:30:45,269 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:30:45,270 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:30:45,273 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:30:45,273 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:30:45,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:30:45,315 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:30:45,319 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:30:45,319 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:45,321 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:30:45,321 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-24 13:30:45,367 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:45,375 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:45,376 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-01-24 13:30:45,376 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:45,459 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 13:30:45,460 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-01-24 13:30:45,462 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:30:45,462 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:30:46,247 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:30:46,249 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:30:46,250 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 16 [2018-01-24 13:30:46,250 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:30:46,250 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 13:30:46,250 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 13:30:46,251 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2018-01-24 13:30:46,251 INFO L87 Difference]: Start difference. First operand 485 states and 562 transitions. Second operand 11 states. [2018-01-24 13:30:47,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:30:47,542 INFO L93 Difference]: Finished difference Result 594 states and 698 transitions. [2018-01-24 13:30:47,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 13:30:47,542 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 28 [2018-01-24 13:30:47,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:30:47,546 INFO L225 Difference]: With dead ends: 594 [2018-01-24 13:30:47,546 INFO L226 Difference]: Without dead ends: 591 [2018-01-24 13:30:47,546 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 92 SyntacticMatches, 12 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 107 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=85, Invalid=335, Unknown=0, NotChecked=0, Total=420 [2018-01-24 13:30:47,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 591 states. [2018-01-24 13:30:47,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 591 to 473. [2018-01-24 13:30:47,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2018-01-24 13:30:47,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 544 transitions. [2018-01-24 13:30:47,586 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 544 transitions. Word has length 28 [2018-01-24 13:30:47,587 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:30:47,587 INFO L432 AbstractCegarLoop]: Abstraction has 473 states and 544 transitions. [2018-01-24 13:30:47,587 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 13:30:47,587 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 544 transitions. [2018-01-24 13:30:47,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-01-24 13:30:47,588 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:30:47,588 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:30:47,588 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-01-24 13:30:47,588 INFO L82 PathProgramCache]: Analyzing trace with hash 1049980534, now seen corresponding path program 1 times [2018-01-24 13:30:47,589 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:30:47,590 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:47,590 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:30:47,590 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:30:47,590 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:30:47,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:30:47,604 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:30:47,800 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:30:47,800 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:30:47,801 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:30:47,807 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:30:47,807 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:30:47,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:30:47,833 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:30:47,835 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 13:30:47,835 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:47,836 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:30:47,837 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-24 13:30:47,839 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-01-24 13:30:47,840 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:47,841 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:30:47,841 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:9, output treesize:3 [2018-01-24 13:30:47,889 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:47,893 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:47,894 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-01-24 13:30:47,894 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:47,926 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:30:47,927 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-01-24 13:30:47,975 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 12 [2018-01-24 13:30:47,975 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:48,015 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 8 [2018-01-24 13:30:48,015 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:48,194 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 13:30:48,194 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:41, output treesize:3 [2018-01-24 13:30:48,199 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 13:30:48,200 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 15 [2018-01-24 13:30:48,200 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:48,205 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 13:30:48,206 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:25, output treesize:15 [2018-01-24 13:30:48,252 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 13:30:48,252 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:30:48,268 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 12 [2018-01-24 13:30:48,268 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:30:48,290 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-01-24 13:30:48,290 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:28, output treesize:23 Received shutdown request... [2018-01-24 13:30:48,435 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-01-24 13:30:48,435 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 13:30:48,445 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 13:30:48,445 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 01:30:48 BoogieIcfgContainer [2018-01-24 13:30:48,445 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 13:30:48,447 INFO L168 Benchmark]: Toolchain (without parser) took 59525.31 ms. Allocated memory was 301.5 MB in the beginning and 590.9 MB in the end (delta: 289.4 MB). Free memory was 260.4 MB in the beginning and 480.3 MB in the end (delta: -220.0 MB). Peak memory consumption was 69.4 MB. Max. memory is 5.3 GB. [2018-01-24 13:30:48,448 INFO L168 Benchmark]: CDTParser took 0.24 ms. Allocated memory is still 301.5 MB. Free memory is still 267.3 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 13:30:48,448 INFO L168 Benchmark]: CACSL2BoogieTranslator took 309.33 ms. Allocated memory is still 301.5 MB. Free memory was 260.4 MB in the beginning and 243.3 MB in the end (delta: 17.0 MB). Peak memory consumption was 17.0 MB. Max. memory is 5.3 GB. [2018-01-24 13:30:48,449 INFO L168 Benchmark]: Boogie Preprocessor took 92.38 ms. Allocated memory is still 301.5 MB. Free memory was 243.3 MB in the beginning and 240.4 MB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 5.3 GB. [2018-01-24 13:30:48,449 INFO L168 Benchmark]: RCFGBuilder took 1514.73 ms. Allocated memory is still 301.5 MB. Free memory was 240.4 MB in the beginning and 235.8 MB in the end (delta: 4.6 MB). Peak memory consumption was 69.0 MB. Max. memory is 5.3 GB. [2018-01-24 13:30:48,451 INFO L168 Benchmark]: TraceAbstraction took 57601.63 ms. Allocated memory was 301.5 MB in the beginning and 590.9 MB in the end (delta: 289.4 MB). Free memory was 235.8 MB in the beginning and 480.4 MB in the end (delta: -244.6 MB). Peak memory consumption was 44.8 MB. Max. memory is 5.3 GB. [2018-01-24 13:30:48,452 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24 ms. Allocated memory is still 301.5 MB. Free memory is still 267.3 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 309.33 ms. Allocated memory is still 301.5 MB. Free memory was 260.4 MB in the beginning and 243.3 MB in the end (delta: 17.0 MB). Peak memory consumption was 17.0 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 92.38 ms. Allocated memory is still 301.5 MB. Free memory was 243.3 MB in the beginning and 240.4 MB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 1514.73 ms. Allocated memory is still 301.5 MB. Free memory was 240.4 MB in the beginning and 235.8 MB in the end (delta: 4.6 MB). Peak memory consumption was 69.0 MB. Max. memory is 5.3 GB. * TraceAbstraction took 57601.63 ms. Allocated memory was 301.5 MB in the beginning and 590.9 MB in the end (delta: 289.4 MB). Free memory was 235.8 MB in the beginning and 480.4 MB in the end (delta: -244.6 MB). Peak memory consumption was 44.8 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1121). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1121). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1157). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1157). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1116). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1115). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1115). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1116). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1164). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1163). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1163). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1163). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1164). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1163). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1620]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1620). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1512). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1512). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1110). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1107). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1110). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1107). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1108). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1109). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1109). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1108). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1541). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1560). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1542). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1541). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1560). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1546). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1564). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1551). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1564). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1551). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1546). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1542). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1508). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1508). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1570). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1575). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1571). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1571). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1570). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1575). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1572). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1572). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1593). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1610). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1614). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1585). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1585). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1608). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1614). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1598). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1600). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1606). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1589). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1612). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1598). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1608). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1610). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1612). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1593). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1589). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1600). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1606). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1146). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1146). Cancelled while BasicCegarLoop was analyzing trace of length 30 with TraceHistMax 2, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 3 xjuncts. - StatisticsResult: Ultimate Automizer benchmark data CFG has 28 procedures, 416 locations, 141 error locations. TIMEOUT Result, 57.5s OverallTime, 15 OverallIterations, 2 TraceHistogramMax, 30.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5546 SDtfs, 2232 SDslu, 17106 SDs, 0 SdLazy, 10257 SolverSat, 477 SolverUnsat, 22 SolverUnknown, 0 SolverNotchecked, 23.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 638 GetRequests, 464 SyntacticMatches, 60 SemanticMatches, 114 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 394 ImplicationChecksByTransitivity, 26.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=538occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.5s AutomataMinimizationTime, 14 MinimizatonAttempts, 722 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 24.4s InterpolantComputationTime, 575 NumberOfCodeBlocks, 575 NumberOfCodeBlocksAsserted, 24 NumberOfCheckSat, 805 ConstructedInterpolants, 80 QuantifiedInterpolants, 139230 SizeOfPredicates, 26 NumberOfNonLiveVariables, 1412 ConjunctsInSsa, 134 ConjunctsInUnsatCore, 34 InterpolantComputations, 9 PerfectInterpolantSequences, 61/130 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test12_true-valid-memsafety.i_svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_13-30-48-472.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test12_true-valid-memsafety.i_svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_13-30-48-472.csv Completed graceful shutdown