java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_1_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 13:32:23,928 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 13:32:23,930 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 13:32:23,944 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 13:32:23,945 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 13:32:23,945 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 13:32:23,947 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 13:32:23,948 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 13:32:23,950 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 13:32:23,951 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 13:32:23,952 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 13:32:23,952 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 13:32:23,953 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 13:32:23,954 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 13:32:23,955 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 13:32:23,958 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 13:32:23,960 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 13:32:23,962 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 13:32:23,963 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 13:32:23,964 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 13:32:23,966 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 13:32:23,966 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 13:32:23,967 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 13:32:23,967 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 13:32:23,968 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 13:32:23,969 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 13:32:23,970 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 13:32:23,970 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 13:32:23,970 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 13:32:23,971 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 13:32:23,971 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 13:32:23,972 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf [2018-01-24 13:32:23,981 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 13:32:23,981 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 13:32:23,982 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 13:32:23,982 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 13:32:23,983 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 13:32:23,983 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 13:32:23,983 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 13:32:23,984 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 13:32:23,984 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 13:32:23,984 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 13:32:23,984 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 13:32:23,984 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 13:32:23,985 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 13:32:23,985 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 13:32:23,985 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 13:32:23,985 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 13:32:23,985 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 13:32:23,986 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 13:32:23,986 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 13:32:23,986 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 13:32:23,986 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 13:32:23,986 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 13:32:23,987 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 13:32:23,987 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:32:23,987 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 13:32:23,987 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 13:32:23,987 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 13:32:23,988 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 13:32:23,988 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-01-24 13:32:23,988 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 13:32:23,988 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 13:32:23,988 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 13:32:23,989 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 13:32:23,990 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 13:32:24,025 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 13:32:24,034 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 13:32:24,037 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 13:32:24,038 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 13:32:24,038 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 13:32:24,039 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_1_true-valid-memsafety_true-termination.i [2018-01-24 13:32:24,215 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 13:32:24,221 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 13:32:24,222 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 13:32:24,223 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 13:32:24,229 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 13:32:24,230 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:32:24" (1/1) ... [2018-01-24 13:32:24,234 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@27a221e1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:32:24, skipping insertion in model container [2018-01-24 13:32:24,234 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:32:24" (1/1) ... [2018-01-24 13:32:24,252 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:32:24,300 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:32:24,421 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:32:24,446 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:32:24,456 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:32:24 WrapperNode [2018-01-24 13:32:24,456 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 13:32:24,457 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 13:32:24,457 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 13:32:24,457 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 13:32:24,469 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:32:24" (1/1) ... [2018-01-24 13:32:24,469 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:32:24" (1/1) ... [2018-01-24 13:32:24,479 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:32:24" (1/1) ... [2018-01-24 13:32:24,479 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:32:24" (1/1) ... [2018-01-24 13:32:24,486 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:32:24" (1/1) ... [2018-01-24 13:32:24,489 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:32:24" (1/1) ... [2018-01-24 13:32:24,490 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:32:24" (1/1) ... [2018-01-24 13:32:24,492 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 13:32:24,493 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 13:32:24,493 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 13:32:24,493 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 13:32:24,494 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:32:24" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:32:24,540 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 13:32:24,541 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 13:32:24,541 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2018-01-24 13:32:24,541 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-01-24 13:32:24,541 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-01-24 13:32:24,541 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_atomic_sub_return [2018-01-24 13:32:24,541 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_sub [2018-01-24 13:32:24,541 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-01-24 13:32:24,541 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_put [2018-01-24 13:32:24,541 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-01-24 13:32:24,541 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-01-24 13:32:24,542 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_put [2018-01-24 13:32:24,542 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-01-24 13:32:24,542 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-01-24 13:32:24,542 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-01-24 13:32:24,542 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-01-24 13:32:24,542 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 13:32:24,542 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-01-24 13:32:24,542 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-01-24 13:32:24,542 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 13:32:24,543 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 13:32:24,543 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 13:32:24,543 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 13:32:24,543 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 13:32:24,543 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-01-24 13:32:24,543 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-01-24 13:32:24,543 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-01-24 13:32:24,543 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-01-24 13:32:24,544 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 13:32:24,544 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-01-24 13:32:24,544 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-01-24 13:32:24,544 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-01-24 13:32:24,544 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_atomic_sub_return [2018-01-24 13:32:24,544 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_sub [2018-01-24 13:32:24,544 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2018-01-24 13:32:24,544 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-01-24 13:32:24,544 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_put [2018-01-24 13:32:24,544 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-01-24 13:32:24,544 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-01-24 13:32:24,545 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_put [2018-01-24 13:32:24,545 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-01-24 13:32:24,545 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-01-24 13:32:24,545 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-01-24 13:32:24,545 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-01-24 13:32:24,545 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 13:32:24,545 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 13:32:24,545 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 13:32:24,768 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-01-24 13:32:24,927 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 13:32:24,928 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:32:24 BoogieIcfgContainer [2018-01-24 13:32:24,928 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 13:32:24,929 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 13:32:24,929 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 13:32:24,932 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 13:32:24,932 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 01:32:24" (1/3) ... [2018-01-24 13:32:24,933 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@53b992df and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:32:24, skipping insertion in model container [2018-01-24 13:32:24,933 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:32:24" (2/3) ... [2018-01-24 13:32:24,934 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@53b992df and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:32:24, skipping insertion in model container [2018-01-24 13:32:24,934 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:32:24" (3/3) ... [2018-01-24 13:32:24,936 INFO L105 eAbstractionObserver]: Analyzing ICFG memleaks_test22_1_true-valid-memsafety_true-termination.i [2018-01-24 13:32:24,945 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 13:32:24,953 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 19 error locations. [2018-01-24 13:32:25,003 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 13:32:25,003 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 13:32:25,003 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 13:32:25,003 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 13:32:25,003 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 13:32:25,004 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 13:32:25,004 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 13:32:25,004 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 13:32:25,005 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 13:32:25,030 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states. [2018-01-24 13:32:25,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 13:32:25,038 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:25,039 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:25,043 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:25,049 INFO L82 PathProgramCache]: Analyzing trace with hash -401333144, now seen corresponding path program 1 times [2018-01-24 13:32:25,052 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:25,110 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:25,110 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:25,111 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:25,111 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:25,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:25,170 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:25,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:25,337 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:25,337 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:32:25,337 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:25,415 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 13:32:25,430 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 13:32:25,431 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:32:25,434 INFO L87 Difference]: Start difference. First operand 118 states. Second operand 5 states. [2018-01-24 13:32:25,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:25,504 INFO L93 Difference]: Finished difference Result 224 states and 237 transitions. [2018-01-24 13:32:25,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:32:25,506 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 13:32:25,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:25,521 INFO L225 Difference]: With dead ends: 224 [2018-01-24 13:32:25,521 INFO L226 Difference]: Without dead ends: 121 [2018-01-24 13:32:25,524 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:32:25,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-01-24 13:32:25,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 119. [2018-01-24 13:32:25,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-01-24 13:32:25,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 126 transitions. [2018-01-24 13:32:25,563 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 126 transitions. Word has length 17 [2018-01-24 13:32:25,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:25,563 INFO L432 AbstractCegarLoop]: Abstraction has 119 states and 126 transitions. [2018-01-24 13:32:25,563 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 13:32:25,564 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 126 transitions. [2018-01-24 13:32:25,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-24 13:32:25,564 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:25,564 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:25,565 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:25,565 INFO L82 PathProgramCache]: Analyzing trace with hash 1306365930, now seen corresponding path program 1 times [2018-01-24 13:32:25,565 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:25,566 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:25,566 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:25,566 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:25,566 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:25,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:25,611 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:25,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:25,679 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:25,679 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:32:25,679 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:25,680 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:32:25,681 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:32:25,681 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:32:25,681 INFO L87 Difference]: Start difference. First operand 119 states and 126 transitions. Second operand 6 states. [2018-01-24 13:32:25,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:25,879 INFO L93 Difference]: Finished difference Result 121 states and 128 transitions. [2018-01-24 13:32:25,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:32:25,879 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2018-01-24 13:32:25,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:25,881 INFO L225 Difference]: With dead ends: 121 [2018-01-24 13:32:25,881 INFO L226 Difference]: Without dead ends: 120 [2018-01-24 13:32:25,882 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:32:25,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-01-24 13:32:25,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 118. [2018-01-24 13:32:25,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-24 13:32:25,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 125 transitions. [2018-01-24 13:32:25,892 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 125 transitions. Word has length 19 [2018-01-24 13:32:25,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:25,893 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 125 transitions. [2018-01-24 13:32:25,893 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:32:25,893 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 125 transitions. [2018-01-24 13:32:25,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-24 13:32:25,893 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:25,893 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:25,894 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:25,894 INFO L82 PathProgramCache]: Analyzing trace with hash 1306365931, now seen corresponding path program 1 times [2018-01-24 13:32:25,894 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:25,895 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:25,895 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:25,895 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:25,895 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:25,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:25,914 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:26,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:26,150 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:26,151 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 13:32:26,151 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:26,151 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:32:26,151 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:32:26,152 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:32:26,152 INFO L87 Difference]: Start difference. First operand 118 states and 125 transitions. Second operand 7 states. [2018-01-24 13:32:26,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:26,344 INFO L93 Difference]: Finished difference Result 120 states and 127 transitions. [2018-01-24 13:32:26,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 13:32:26,344 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-01-24 13:32:26,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:26,346 INFO L225 Difference]: With dead ends: 120 [2018-01-24 13:32:26,346 INFO L226 Difference]: Without dead ends: 119 [2018-01-24 13:32:26,347 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-01-24 13:32:26,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-01-24 13:32:26,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 117. [2018-01-24 13:32:26,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-01-24 13:32:26,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 124 transitions. [2018-01-24 13:32:26,361 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 124 transitions. Word has length 19 [2018-01-24 13:32:26,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:26,361 INFO L432 AbstractCegarLoop]: Abstraction has 117 states and 124 transitions. [2018-01-24 13:32:26,361 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:32:26,361 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 124 transitions. [2018-01-24 13:32:26,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-01-24 13:32:26,363 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:26,363 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:26,363 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:26,363 INFO L82 PathProgramCache]: Analyzing trace with hash -860603530, now seen corresponding path program 1 times [2018-01-24 13:32:26,364 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:26,365 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:26,365 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:26,365 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:26,366 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:26,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:26,389 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:26,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:26,458 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:26,458 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-01-24 13:32:26,458 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:26,459 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:32:26,459 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:32:26,459 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:32:26,459 INFO L87 Difference]: Start difference. First operand 117 states and 124 transitions. Second operand 7 states. [2018-01-24 13:32:26,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:26,550 INFO L93 Difference]: Finished difference Result 183 states and 192 transitions. [2018-01-24 13:32:26,551 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:32:26,551 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 29 [2018-01-24 13:32:26,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:26,553 INFO L225 Difference]: With dead ends: 183 [2018-01-24 13:32:26,554 INFO L226 Difference]: Without dead ends: 129 [2018-01-24 13:32:26,554 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:32:26,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2018-01-24 13:32:26,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 125. [2018-01-24 13:32:26,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-01-24 13:32:26,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 132 transitions. [2018-01-24 13:32:26,568 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 132 transitions. Word has length 29 [2018-01-24 13:32:26,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:26,569 INFO L432 AbstractCegarLoop]: Abstraction has 125 states and 132 transitions. [2018-01-24 13:32:26,569 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:32:26,569 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 132 transitions. [2018-01-24 13:32:26,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 13:32:26,570 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:26,571 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:26,571 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:26,571 INFO L82 PathProgramCache]: Analyzing trace with hash 23284980, now seen corresponding path program 1 times [2018-01-24 13:32:26,571 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:26,573 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:26,573 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:26,573 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:26,573 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:26,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:26,584 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:26,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:26,625 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:26,625 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 13:32:26,626 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:26,627 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 13:32:26,627 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 13:32:26,627 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 13:32:26,627 INFO L87 Difference]: Start difference. First operand 125 states and 132 transitions. Second operand 3 states. [2018-01-24 13:32:26,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:26,741 INFO L93 Difference]: Finished difference Result 141 states and 148 transitions. [2018-01-24 13:32:26,741 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 13:32:26,741 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2018-01-24 13:32:26,742 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:26,743 INFO L225 Difference]: With dead ends: 141 [2018-01-24 13:32:26,743 INFO L226 Difference]: Without dead ends: 129 [2018-01-24 13:32:26,744 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 13:32:26,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2018-01-24 13:32:26,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 121. [2018-01-24 13:32:26,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2018-01-24 13:32:26,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 127 transitions. [2018-01-24 13:32:26,761 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 127 transitions. Word has length 27 [2018-01-24 13:32:26,761 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:26,761 INFO L432 AbstractCegarLoop]: Abstraction has 121 states and 127 transitions. [2018-01-24 13:32:26,761 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 13:32:26,761 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 127 transitions. [2018-01-24 13:32:26,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-01-24 13:32:26,762 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:26,762 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:26,762 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:26,763 INFO L82 PathProgramCache]: Analyzing trace with hash -1295663626, now seen corresponding path program 1 times [2018-01-24 13:32:26,763 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:26,764 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:26,764 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:26,764 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:26,764 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:26,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:26,775 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:26,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:26,840 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:26,840 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 13:32:26,840 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:26,840 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:32:26,840 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:32:26,841 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:32:26,841 INFO L87 Difference]: Start difference. First operand 121 states and 127 transitions. Second operand 6 states. [2018-01-24 13:32:26,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:26,861 INFO L93 Difference]: Finished difference Result 125 states and 130 transitions. [2018-01-24 13:32:26,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:32:26,861 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 29 [2018-01-24 13:32:26,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:26,863 INFO L225 Difference]: With dead ends: 125 [2018-01-24 13:32:26,863 INFO L226 Difference]: Without dead ends: 113 [2018-01-24 13:32:26,864 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:32:26,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-01-24 13:32:26,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-01-24 13:32:26,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-01-24 13:32:26,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 118 transitions. [2018-01-24 13:32:26,874 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 118 transitions. Word has length 29 [2018-01-24 13:32:26,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:26,875 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 118 transitions. [2018-01-24 13:32:26,875 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:32:26,875 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 118 transitions. [2018-01-24 13:32:26,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-24 13:32:26,876 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:26,876 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:26,876 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:26,876 INFO L82 PathProgramCache]: Analyzing trace with hash 522747174, now seen corresponding path program 1 times [2018-01-24 13:32:26,877 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:26,878 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:26,878 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:26,878 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:26,878 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:26,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:26,894 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:26,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:26,921 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:26,921 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 13:32:26,921 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:26,921 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 13:32:26,922 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 13:32:26,922 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 13:32:26,922 INFO L87 Difference]: Start difference. First operand 113 states and 118 transitions. Second operand 4 states. [2018-01-24 13:32:26,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:26,942 INFO L93 Difference]: Finished difference Result 205 states and 215 transitions. [2018-01-24 13:32:26,944 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 13:32:26,944 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2018-01-24 13:32:26,944 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:26,945 INFO L225 Difference]: With dead ends: 205 [2018-01-24 13:32:26,945 INFO L226 Difference]: Without dead ends: 114 [2018-01-24 13:32:26,946 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:32:26,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-01-24 13:32:26,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. [2018-01-24 13:32:26,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-01-24 13:32:26,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 119 transitions. [2018-01-24 13:32:26,955 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 119 transitions. Word has length 34 [2018-01-24 13:32:26,955 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:26,955 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 119 transitions. [2018-01-24 13:32:26,955 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 13:32:26,956 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 119 transitions. [2018-01-24 13:32:26,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-01-24 13:32:26,957 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:26,957 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:26,957 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:26,957 INFO L82 PathProgramCache]: Analyzing trace with hash -1305776369, now seen corresponding path program 1 times [2018-01-24 13:32:26,957 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:26,958 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:26,958 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:26,959 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:26,959 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:26,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:26,973 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:27,035 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:27,036 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:27,036 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:32:27,051 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:27,051 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:32:27,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:27,097 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:27,120 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:27,120 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:27,222 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:27,243 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:27,243 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:32:27,247 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:27,247 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:32:27,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:27,303 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:27,310 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:27,310 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:27,369 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:27,371 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:32:27,371 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 13:32:27,371 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:32:27,372 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:32:27,372 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:32:27,372 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2018-01-24 13:32:27,372 INFO L87 Difference]: Start difference. First operand 114 states and 119 transitions. Second operand 6 states. [2018-01-24 13:32:27,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:27,396 INFO L93 Difference]: Finished difference Result 206 states and 216 transitions. [2018-01-24 13:32:27,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:32:27,397 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-01-24 13:32:27,398 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:27,398 INFO L225 Difference]: With dead ends: 206 [2018-01-24 13:32:27,399 INFO L226 Difference]: Without dead ends: 115 [2018-01-24 13:32:27,399 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 134 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=37, Invalid=53, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:32:27,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-01-24 13:32:27,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-01-24 13:32:27,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-01-24 13:32:27,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 120 transitions. [2018-01-24 13:32:27,409 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 120 transitions. Word has length 35 [2018-01-24 13:32:27,409 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:27,409 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 120 transitions. [2018-01-24 13:32:27,409 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:32:27,410 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 120 transitions. [2018-01-24 13:32:27,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-24 13:32:27,412 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:27,412 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:27,412 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:27,412 INFO L82 PathProgramCache]: Analyzing trace with hash 2139535942, now seen corresponding path program 2 times [2018-01-24 13:32:27,412 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:27,414 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:27,414 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:27,414 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:27,414 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:27,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:27,432 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:27,492 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:27,492 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:27,492 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:32:27,501 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:32:27,501 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:32:27,530 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:32:27,533 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:32:27,539 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:27,575 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:32:27,578 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:32:27,597 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:32:27,598 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:32:27,628 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:32:27,628 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:32:28,415 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:32:28,416 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:32,908 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:32:32,928 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:32:32,928 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [14, 13] imperfect sequences [6] total 31 [2018-01-24 13:32:32,928 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:32,929 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 13:32:32,929 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 13:32:32,930 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=838, Unknown=2, NotChecked=0, Total=930 [2018-01-24 13:32:32,930 INFO L87 Difference]: Start difference. First operand 115 states and 120 transitions. Second operand 15 states. [2018-01-24 13:32:33,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:33,712 INFO L93 Difference]: Finished difference Result 115 states and 120 transitions. [2018-01-24 13:32:33,712 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 13:32:33,712 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 36 [2018-01-24 13:32:33,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:33,714 INFO L225 Difference]: With dead ends: 115 [2018-01-24 13:32:33,714 INFO L226 Difference]: Without dead ends: 114 [2018-01-24 13:32:33,714 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 81 GetRequests, 47 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 237 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=118, Invalid=1070, Unknown=2, NotChecked=0, Total=1190 [2018-01-24 13:32:33,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-01-24 13:32:33,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. [2018-01-24 13:32:33,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-01-24 13:32:33,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 119 transitions. [2018-01-24 13:32:33,730 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 119 transitions. Word has length 36 [2018-01-24 13:32:33,730 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:33,730 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 119 transitions. [2018-01-24 13:32:33,730 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 13:32:33,730 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 119 transitions. [2018-01-24 13:32:33,731 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-24 13:32:33,731 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:33,732 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:33,732 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:33,732 INFO L82 PathProgramCache]: Analyzing trace with hash 2139535941, now seen corresponding path program 1 times [2018-01-24 13:32:33,732 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:33,733 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:33,734 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:32:33,734 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:33,734 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:33,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:33,749 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:33,815 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:32:33,816 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:33,816 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-01-24 13:32:33,816 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:33,816 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:32:33,816 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:32:33,816 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:32:33,817 INFO L87 Difference]: Start difference. First operand 114 states and 119 transitions. Second operand 10 states. [2018-01-24 13:32:34,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:34,010 INFO L93 Difference]: Finished difference Result 114 states and 119 transitions. [2018-01-24 13:32:34,010 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:32:34,010 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 36 [2018-01-24 13:32:34,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:34,011 INFO L225 Difference]: With dead ends: 114 [2018-01-24 13:32:34,011 INFO L226 Difference]: Without dead ends: 113 [2018-01-24 13:32:34,011 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:32:34,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-01-24 13:32:34,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-01-24 13:32:34,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-01-24 13:32:34,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 118 transitions. [2018-01-24 13:32:34,022 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 118 transitions. Word has length 36 [2018-01-24 13:32:34,022 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:34,022 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 118 transitions. [2018-01-24 13:32:34,022 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:32:34,022 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 118 transitions. [2018-01-24 13:32:34,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 13:32:34,023 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:34,023 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:34,023 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:34,024 INFO L82 PathProgramCache]: Analyzing trace with hash 562133952, now seen corresponding path program 1 times [2018-01-24 13:32:34,024 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:34,025 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:34,025 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:34,025 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:34,025 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:34,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:34,039 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:34,146 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:32:34,146 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:34,146 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-01-24 13:32:34,146 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:34,147 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:32:34,147 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:32:34,147 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:32:34,147 INFO L87 Difference]: Start difference. First operand 113 states and 118 transitions. Second operand 10 states. [2018-01-24 13:32:34,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:34,358 INFO L93 Difference]: Finished difference Result 113 states and 118 transitions. [2018-01-24 13:32:34,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:32:34,358 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 41 [2018-01-24 13:32:34,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:34,359 INFO L225 Difference]: With dead ends: 113 [2018-01-24 13:32:34,359 INFO L226 Difference]: Without dead ends: 111 [2018-01-24 13:32:34,359 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:32:34,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-01-24 13:32:34,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2018-01-24 13:32:34,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-01-24 13:32:34,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 116 transitions. [2018-01-24 13:32:34,373 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 116 transitions. Word has length 41 [2018-01-24 13:32:34,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:34,374 INFO L432 AbstractCegarLoop]: Abstraction has 111 states and 116 transitions. [2018-01-24 13:32:34,374 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:32:34,374 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 116 transitions. [2018-01-24 13:32:34,375 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 13:32:34,375 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:34,375 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:34,375 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:34,375 INFO L82 PathProgramCache]: Analyzing trace with hash 562133953, now seen corresponding path program 1 times [2018-01-24 13:32:34,376 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:34,377 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:34,377 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:34,377 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:34,377 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:34,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:34,393 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:34,456 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:34,456 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:34,456 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:32:34,470 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:34,470 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:32:34,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:34,504 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:34,520 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:34,520 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:34,685 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:34,705 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:34,705 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:32:34,709 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:34,709 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:32:34,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:34,758 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:34,764 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:34,764 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:34,785 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:34,814 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:32:34,814 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 13:32:34,815 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:32:34,815 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:32:34,815 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:32:34,815 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=63, Unknown=0, NotChecked=0, Total=110 [2018-01-24 13:32:34,815 INFO L87 Difference]: Start difference. First operand 111 states and 116 transitions. Second operand 7 states. [2018-01-24 13:32:34,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:34,840 INFO L93 Difference]: Finished difference Result 199 states and 209 transitions. [2018-01-24 13:32:34,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:32:34,841 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 41 [2018-01-24 13:32:34,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:34,842 INFO L225 Difference]: With dead ends: 199 [2018-01-24 13:32:34,842 INFO L226 Difference]: Without dead ends: 112 [2018-01-24 13:32:34,842 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 169 GetRequests, 157 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=77, Unknown=0, NotChecked=0, Total=132 [2018-01-24 13:32:34,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-01-24 13:32:34,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-01-24 13:32:34,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-01-24 13:32:34,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 117 transitions. [2018-01-24 13:32:34,852 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 117 transitions. Word has length 41 [2018-01-24 13:32:34,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:34,853 INFO L432 AbstractCegarLoop]: Abstraction has 112 states and 117 transitions. [2018-01-24 13:32:34,853 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:32:34,853 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 117 transitions. [2018-01-24 13:32:34,854 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 13:32:34,854 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:34,854 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:34,854 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:34,854 INFO L82 PathProgramCache]: Analyzing trace with hash 258949560, now seen corresponding path program 2 times [2018-01-24 13:32:34,854 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:34,855 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:34,855 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:34,855 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:34,855 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:34,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:34,871 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:34,920 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:34,920 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:34,921 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:32:34,926 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:32:34,926 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:32:34,946 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:32:34,948 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:32:34,951 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:34,956 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:32:34,956 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:32:34,974 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:32:34,974 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:32:34,985 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:32:34,985 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:32:35,523 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:32:35,523 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:37,863 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:32:37,884 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:32:37,884 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15, 13] imperfect sequences [7] total 33 [2018-01-24 13:32:37,884 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:37,884 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 13:32:37,885 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 13:32:37,885 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=950, Unknown=1, NotChecked=0, Total=1056 [2018-01-24 13:32:37,885 INFO L87 Difference]: Start difference. First operand 112 states and 117 transitions. Second operand 16 states. [2018-01-24 13:32:38,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:38,536 INFO L93 Difference]: Finished difference Result 112 states and 117 transitions. [2018-01-24 13:32:38,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 13:32:38,536 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 42 [2018-01-24 13:32:38,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:38,537 INFO L225 Difference]: With dead ends: 112 [2018-01-24 13:32:38,537 INFO L226 Difference]: Without dead ends: 110 [2018-01-24 13:32:38,538 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 57 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 311 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=136, Invalid=1195, Unknown=1, NotChecked=0, Total=1332 [2018-01-24 13:32:38,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-01-24 13:32:38,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 110. [2018-01-24 13:32:38,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-24 13:32:38,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 115 transitions. [2018-01-24 13:32:38,549 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 115 transitions. Word has length 42 [2018-01-24 13:32:38,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:38,549 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 115 transitions. [2018-01-24 13:32:38,549 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 13:32:38,549 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 115 transitions. [2018-01-24 13:32:38,550 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-01-24 13:32:38,550 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:38,550 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:38,550 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:38,550 INFO L82 PathProgramCache]: Analyzing trace with hash -916811563, now seen corresponding path program 1 times [2018-01-24 13:32:38,550 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:38,551 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:38,551 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:32:38,551 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:38,552 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:38,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:38,562 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:38,642 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:32:38,643 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:38,643 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-01-24 13:32:38,643 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:38,643 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:32:38,643 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:32:38,643 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:32:38,643 INFO L87 Difference]: Start difference. First operand 110 states and 115 transitions. Second operand 8 states. [2018-01-24 13:32:38,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:38,681 INFO L93 Difference]: Finished difference Result 173 states and 180 transitions. [2018-01-24 13:32:38,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:32:38,682 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 47 [2018-01-24 13:32:38,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:38,682 INFO L225 Difference]: With dead ends: 173 [2018-01-24 13:32:38,682 INFO L226 Difference]: Without dead ends: 110 [2018-01-24 13:32:38,683 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:32:38,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-01-24 13:32:38,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 110. [2018-01-24 13:32:38,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-24 13:32:38,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 114 transitions. [2018-01-24 13:32:38,694 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 114 transitions. Word has length 47 [2018-01-24 13:32:38,694 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:38,694 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 114 transitions. [2018-01-24 13:32:38,694 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:32:38,694 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 114 transitions. [2018-01-24 13:32:38,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 13:32:38,695 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:38,695 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:38,695 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:38,695 INFO L82 PathProgramCache]: Analyzing trace with hash -396278647, now seen corresponding path program 1 times [2018-01-24 13:32:38,695 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:38,696 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:38,696 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:38,696 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:38,696 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:38,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:38,708 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:38,781 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:32:38,782 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:38,782 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-01-24 13:32:38,782 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:38,782 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:32:38,783 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:32:38,783 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:32:38,783 INFO L87 Difference]: Start difference. First operand 110 states and 114 transitions. Second operand 10 states. [2018-01-24 13:32:38,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:38,897 INFO L93 Difference]: Finished difference Result 175 states and 181 transitions. [2018-01-24 13:32:38,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:32:38,898 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 52 [2018-01-24 13:32:38,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:38,898 INFO L225 Difference]: With dead ends: 175 [2018-01-24 13:32:38,898 INFO L226 Difference]: Without dead ends: 110 [2018-01-24 13:32:38,899 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:32:38,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-01-24 13:32:38,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 110. [2018-01-24 13:32:38,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-24 13:32:38,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 113 transitions. [2018-01-24 13:32:38,909 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 113 transitions. Word has length 52 [2018-01-24 13:32:38,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:38,909 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 113 transitions. [2018-01-24 13:32:38,910 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:32:38,910 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 113 transitions. [2018-01-24 13:32:38,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-01-24 13:32:38,910 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:38,910 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:38,910 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:38,910 INFO L82 PathProgramCache]: Analyzing trace with hash 401221152, now seen corresponding path program 1 times [2018-01-24 13:32:38,910 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:38,911 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:38,911 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:38,911 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:38,911 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:38,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:38,926 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:39,135 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:32:39,135 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:39,135 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2018-01-24 13:32:39,136 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:39,136 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 13:32:39,136 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 13:32:39,136 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=379, Unknown=0, NotChecked=0, Total=420 [2018-01-24 13:32:39,136 INFO L87 Difference]: Start difference. First operand 110 states and 113 transitions. Second operand 21 states. [2018-01-24 13:32:39,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:39,527 INFO L93 Difference]: Finished difference Result 119 states and 122 transitions. [2018-01-24 13:32:39,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 13:32:39,527 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 63 [2018-01-24 13:32:39,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:39,528 INFO L225 Difference]: With dead ends: 119 [2018-01-24 13:32:39,528 INFO L226 Difference]: Without dead ends: 117 [2018-01-24 13:32:39,529 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 57 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=69, Invalid=687, Unknown=0, NotChecked=0, Total=756 [2018-01-24 13:32:39,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-01-24 13:32:39,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 108. [2018-01-24 13:32:39,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-01-24 13:32:39,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 111 transitions. [2018-01-24 13:32:39,539 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 111 transitions. Word has length 63 [2018-01-24 13:32:39,540 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:39,540 INFO L432 AbstractCegarLoop]: Abstraction has 108 states and 111 transitions. [2018-01-24 13:32:39,540 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 13:32:39,540 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 111 transitions. [2018-01-24 13:32:39,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-01-24 13:32:39,541 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:39,541 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:39,541 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:39,541 INFO L82 PathProgramCache]: Analyzing trace with hash 401221153, now seen corresponding path program 1 times [2018-01-24 13:32:39,541 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:39,542 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:39,542 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:39,542 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:39,542 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:39,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:39,574 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:39,710 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:39,710 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:39,710 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:32:39,721 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:39,721 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:32:39,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:39,773 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:39,789 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:39,789 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:40,144 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:40,179 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:40,179 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:32:40,183 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:40,183 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:32:40,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:40,283 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:40,291 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:40,292 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:40,389 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:40,391 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:32:40,391 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 13:32:40,391 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:32:40,391 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:32:40,392 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:32:40,392 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=88, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:32:40,392 INFO L87 Difference]: Start difference. First operand 108 states and 111 transitions. Second operand 8 states. [2018-01-24 13:32:40,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:40,423 INFO L93 Difference]: Finished difference Result 192 states and 198 transitions. [2018-01-24 13:32:40,423 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 13:32:40,423 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 63 [2018-01-24 13:32:40,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:40,424 INFO L225 Difference]: With dead ends: 192 [2018-01-24 13:32:40,424 INFO L226 Difference]: Without dead ends: 109 [2018-01-24 13:32:40,425 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 258 GetRequests, 244 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=77, Invalid=105, Unknown=0, NotChecked=0, Total=182 [2018-01-24 13:32:40,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-01-24 13:32:40,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 109. [2018-01-24 13:32:40,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-01-24 13:32:40,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 112 transitions. [2018-01-24 13:32:40,441 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 112 transitions. Word has length 63 [2018-01-24 13:32:40,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:40,441 INFO L432 AbstractCegarLoop]: Abstraction has 109 states and 112 transitions. [2018-01-24 13:32:40,441 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:32:40,441 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 112 transitions. [2018-01-24 13:32:40,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-01-24 13:32:40,442 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:40,442 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:40,442 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:40,443 INFO L82 PathProgramCache]: Analyzing trace with hash -421459752, now seen corresponding path program 2 times [2018-01-24 13:32:40,443 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:40,444 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:40,444 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:40,444 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:40,444 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:40,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:40,465 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:40,525 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:40,526 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:40,526 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:32:40,538 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:32:40,538 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:32:40,579 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:32:40,585 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:32:40,590 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:40,606 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:32:40,606 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:32:40,666 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:32:40,667 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:32:40,684 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:32:40,685 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:32:41,358 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:32:41,358 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:42,026 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:32:42,050 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:32:42,050 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [20, 18] imperfect sequences [8] total 44 [2018-01-24 13:32:42,050 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:42,051 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 13:32:42,051 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 13:32:42,051 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=146, Invalid=1746, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 13:32:42,052 INFO L87 Difference]: Start difference. First operand 109 states and 112 transitions. Second operand 21 states. [2018-01-24 13:32:43,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:43,050 INFO L93 Difference]: Finished difference Result 109 states and 112 transitions. [2018-01-24 13:32:43,050 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 13:32:43,050 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 64 [2018-01-24 13:32:43,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:43,051 INFO L225 Difference]: With dead ends: 109 [2018-01-24 13:32:43,051 INFO L226 Difference]: Without dead ends: 107 [2018-01-24 13:32:43,052 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 141 GetRequests, 91 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 630 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=195, Invalid=2255, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 13:32:43,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-01-24 13:32:43,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 107. [2018-01-24 13:32:43,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-01-24 13:32:43,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 110 transitions. [2018-01-24 13:32:43,070 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 110 transitions. Word has length 64 [2018-01-24 13:32:43,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:43,070 INFO L432 AbstractCegarLoop]: Abstraction has 107 states and 110 transitions. [2018-01-24 13:32:43,070 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 13:32:43,070 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 110 transitions. [2018-01-24 13:32:43,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 13:32:43,071 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:43,071 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:43,071 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:43,072 INFO L82 PathProgramCache]: Analyzing trace with hash -713687403, now seen corresponding path program 1 times [2018-01-24 13:32:43,072 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:43,072 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:43,072 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:32:43,073 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:43,073 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:43,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:43,085 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:43,196 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:32:43,196 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:43,196 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-01-24 13:32:43,196 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:43,196 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 13:32:43,197 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 13:32:43,197 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-01-24 13:32:43,197 INFO L87 Difference]: Start difference. First operand 107 states and 110 transitions. Second operand 11 states. [2018-01-24 13:32:43,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:43,269 INFO L93 Difference]: Finished difference Result 113 states and 115 transitions. [2018-01-24 13:32:43,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 13:32:43,270 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 62 [2018-01-24 13:32:43,270 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:43,270 INFO L225 Difference]: With dead ends: 113 [2018-01-24 13:32:43,270 INFO L226 Difference]: Without dead ends: 107 [2018-01-24 13:32:43,271 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-01-24 13:32:43,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-01-24 13:32:43,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 107. [2018-01-24 13:32:43,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-01-24 13:32:43,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 109 transitions. [2018-01-24 13:32:43,288 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 109 transitions. Word has length 62 [2018-01-24 13:32:43,289 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:43,289 INFO L432 AbstractCegarLoop]: Abstraction has 107 states and 109 transitions. [2018-01-24 13:32:43,289 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 13:32:43,289 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 109 transitions. [2018-01-24 13:32:43,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-24 13:32:43,290 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:43,290 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:43,290 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:43,291 INFO L82 PathProgramCache]: Analyzing trace with hash -1331716926, now seen corresponding path program 1 times [2018-01-24 13:32:43,291 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:43,291 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:43,292 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:43,292 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:43,292 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:43,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:43,313 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:43,854 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:32:43,855 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:32:43,855 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2018-01-24 13:32:43,855 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:43,855 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 13:32:43,855 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 13:32:43,856 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=507, Unknown=0, NotChecked=0, Total=552 [2018-01-24 13:32:43,856 INFO L87 Difference]: Start difference. First operand 107 states and 109 transitions. Second operand 24 states. [2018-01-24 13:32:44,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:44,355 INFO L93 Difference]: Finished difference Result 112 states and 114 transitions. [2018-01-24 13:32:44,355 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 13:32:44,356 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 78 [2018-01-24 13:32:44,356 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:44,356 INFO L225 Difference]: With dead ends: 112 [2018-01-24 13:32:44,356 INFO L226 Difference]: Without dead ends: 110 [2018-01-24 13:32:44,357 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=85, Invalid=1037, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 13:32:44,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-01-24 13:32:44,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 105. [2018-01-24 13:32:44,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-01-24 13:32:44,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 107 transitions. [2018-01-24 13:32:44,368 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 107 transitions. Word has length 78 [2018-01-24 13:32:44,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:44,369 INFO L432 AbstractCegarLoop]: Abstraction has 105 states and 107 transitions. [2018-01-24 13:32:44,369 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 13:32:44,369 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 107 transitions. [2018-01-24 13:32:44,369 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-24 13:32:44,369 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:44,370 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:44,370 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:44,370 INFO L82 PathProgramCache]: Analyzing trace with hash -1331716925, now seen corresponding path program 1 times [2018-01-24 13:32:44,370 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:44,371 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:44,371 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:44,371 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:44,371 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:44,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:44,391 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:44,462 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:44,462 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:44,462 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:32:44,475 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:44,476 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:32:44,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:44,525 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:44,538 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:44,538 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:44,663 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:44,685 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:44,686 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:32:44,690 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:44,690 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:32:44,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:44,787 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:44,795 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:44,795 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:44,986 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:44,988 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:32:44,988 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 13:32:44,988 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:32:44,989 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 13:32:44,989 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 13:32:44,989 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=117, Unknown=0, NotChecked=0, Total=210 [2018-01-24 13:32:44,989 INFO L87 Difference]: Start difference. First operand 105 states and 107 transitions. Second operand 9 states. [2018-01-24 13:32:45,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:45,022 INFO L93 Difference]: Finished difference Result 185 states and 189 transitions. [2018-01-24 13:32:45,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:32:45,024 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 78 [2018-01-24 13:32:45,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:45,025 INFO L225 Difference]: With dead ends: 185 [2018-01-24 13:32:45,025 INFO L226 Difference]: Without dead ends: 106 [2018-01-24 13:32:45,026 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 319 GetRequests, 303 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=103, Invalid=137, Unknown=0, NotChecked=0, Total=240 [2018-01-24 13:32:45,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-01-24 13:32:45,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 106. [2018-01-24 13:32:45,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-01-24 13:32:45,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 108 transitions. [2018-01-24 13:32:45,044 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 108 transitions. Word has length 78 [2018-01-24 13:32:45,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:45,044 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 108 transitions. [2018-01-24 13:32:45,045 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 13:32:45,045 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 108 transitions. [2018-01-24 13:32:45,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-01-24 13:32:45,046 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:45,046 INFO L322 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:45,046 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:45,046 INFO L82 PathProgramCache]: Analyzing trace with hash 1544426796, now seen corresponding path program 2 times [2018-01-24 13:32:45,046 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:45,047 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:45,047 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:45,047 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:45,048 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:45,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:45,067 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:45,160 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:45,160 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:45,160 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:32:45,167 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:32:45,167 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:32:45,214 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:32:45,222 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:32:45,229 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:45,233 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:32:45,234 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:32:45,252 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:32:45,253 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:32:45,269 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:32:45,269 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:32:47,470 WARN L143 SmtUtils]: Spent 2017ms on a formula simplification that was a NOOP. DAG size: 21 [2018-01-24 13:32:48,424 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 13:32:48,424 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:49,496 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 13:32:49,517 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:32:49,518 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [24, 22] imperfect sequences [9] total 53 [2018-01-24 13:32:49,518 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:32:49,518 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 13:32:49,518 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 13:32:49,519 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=181, Invalid=2575, Unknown=0, NotChecked=0, Total=2756 [2018-01-24 13:32:49,519 INFO L87 Difference]: Start difference. First operand 106 states and 108 transitions. Second operand 25 states. [2018-01-24 13:32:51,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:51,122 INFO L93 Difference]: Finished difference Result 106 states and 108 transitions. [2018-01-24 13:32:51,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 13:32:51,122 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 79 [2018-01-24 13:32:51,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:51,124 INFO L225 Difference]: With dead ends: 106 [2018-01-24 13:32:51,124 INFO L226 Difference]: Without dead ends: 104 [2018-01-24 13:32:51,125 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 174 GetRequests, 111 SyntacticMatches, 4 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 985 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=246, Invalid=3414, Unknown=0, NotChecked=0, Total=3660 [2018-01-24 13:32:51,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-01-24 13:32:51,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 104. [2018-01-24 13:32:51,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-01-24 13:32:51,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 106 transitions. [2018-01-24 13:32:51,138 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 106 transitions. Word has length 79 [2018-01-24 13:32:51,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:51,138 INFO L432 AbstractCegarLoop]: Abstraction has 104 states and 106 transitions. [2018-01-24 13:32:51,139 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 13:32:51,139 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 106 transitions. [2018-01-24 13:32:51,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-01-24 13:32:51,139 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:51,139 INFO L322 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:51,139 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:51,140 INFO L82 PathProgramCache]: Analyzing trace with hash -814306387, now seen corresponding path program 1 times [2018-01-24 13:32:51,140 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:51,140 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:51,140 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:32:51,140 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:51,140 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:51,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:51,155 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:51,360 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:51,361 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:51,361 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:32:51,369 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:51,369 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:32:51,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:51,418 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:51,430 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:51,430 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:51,614 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:51,635 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:51,635 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:32:51,638 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:51,638 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:32:51,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:51,787 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:51,795 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:51,795 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:51,883 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:51,885 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:32:51,885 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 13:32:51,885 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:32:51,885 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:32:51,885 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:32:51,886 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=150, Unknown=0, NotChecked=0, Total=272 [2018-01-24 13:32:51,886 INFO L87 Difference]: Start difference. First operand 104 states and 106 transitions. Second operand 10 states. [2018-01-24 13:32:51,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:51,921 INFO L93 Difference]: Finished difference Result 182 states and 186 transitions. [2018-01-24 13:32:51,921 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 13:32:51,922 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 83 [2018-01-24 13:32:51,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:51,922 INFO L225 Difference]: With dead ends: 182 [2018-01-24 13:32:51,922 INFO L226 Difference]: Without dead ends: 105 [2018-01-24 13:32:51,923 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 340 GetRequests, 322 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=133, Invalid=173, Unknown=0, NotChecked=0, Total=306 [2018-01-24 13:32:51,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-01-24 13:32:51,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2018-01-24 13:32:51,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-01-24 13:32:51,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 107 transitions. [2018-01-24 13:32:51,946 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 107 transitions. Word has length 83 [2018-01-24 13:32:51,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:51,946 INFO L432 AbstractCegarLoop]: Abstraction has 105 states and 107 transitions. [2018-01-24 13:32:51,946 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:32:51,946 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 107 transitions. [2018-01-24 13:32:51,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-01-24 13:32:51,947 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:51,947 INFO L322 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:51,947 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:51,947 INFO L82 PathProgramCache]: Analyzing trace with hash -1853879068, now seen corresponding path program 2 times [2018-01-24 13:32:51,948 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:51,949 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:51,949 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:32:51,949 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:51,949 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:51,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:51,974 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:52,141 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:52,141 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:52,141 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:32:52,152 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:32:52,152 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:32:52,195 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:32:52,215 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:32:52,216 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:32:52,220 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:52,272 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:52,272 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:52,506 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:52,529 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:52,530 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:32:52,534 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:32:52,534 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:32:52,603 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:32:52,693 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:32:52,734 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:32:52,743 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:52,749 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:52,749 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:52,832 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:52,833 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:32:52,834 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 13:32:52,834 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:32:52,834 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 13:32:52,834 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 13:32:52,835 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=187, Unknown=0, NotChecked=0, Total=342 [2018-01-24 13:32:52,835 INFO L87 Difference]: Start difference. First operand 105 states and 107 transitions. Second operand 11 states. [2018-01-24 13:32:52,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:32:52,867 INFO L93 Difference]: Finished difference Result 183 states and 187 transitions. [2018-01-24 13:32:52,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:32:52,867 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 84 [2018-01-24 13:32:52,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:32:52,868 INFO L225 Difference]: With dead ends: 183 [2018-01-24 13:32:52,868 INFO L226 Difference]: Without dead ends: 106 [2018-01-24 13:32:52,869 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 345 GetRequests, 325 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=167, Invalid=213, Unknown=0, NotChecked=0, Total=380 [2018-01-24 13:32:52,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-01-24 13:32:52,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 106. [2018-01-24 13:32:52,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-01-24 13:32:52,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 108 transitions. [2018-01-24 13:32:52,891 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 108 transitions. Word has length 84 [2018-01-24 13:32:52,891 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:32:52,891 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 108 transitions. [2018-01-24 13:32:52,891 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 13:32:52,891 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 108 transitions. [2018-01-24 13:32:52,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-01-24 13:32:52,892 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:32:52,892 INFO L322 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:32:52,892 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:32:52,892 INFO L82 PathProgramCache]: Analyzing trace with hash 279106189, now seen corresponding path program 3 times [2018-01-24 13:32:52,893 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:32:52,893 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:52,894 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:32:52,894 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:32:52,894 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:32:52,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:32:52,915 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:32:53,030 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:53,031 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:53,031 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:32:53,037 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:32:53,037 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:32:53,071 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:32:53,082 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:32:53,117 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:32:53,361 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:32:53,647 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:32:53,649 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:32:53,653 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:32:53,670 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:53,670 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:32:53,859 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:32:53,880 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:32:53,880 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:32:53,883 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:32:53,884 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:32:53,937 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:32:54,019 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:32:54,901 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:33:06,944 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:33:08,958 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:33:09,055 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:33:09,067 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:09,076 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:09,076 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:09,222 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:09,226 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:33:09,226 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 13:33:09,227 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:33:09,227 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 13:33:09,227 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 13:33:09,227 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=228, Unknown=0, NotChecked=0, Total=420 [2018-01-24 13:33:09,228 INFO L87 Difference]: Start difference. First operand 106 states and 108 transitions. Second operand 12 states. [2018-01-24 13:33:09,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:09,280 INFO L93 Difference]: Finished difference Result 184 states and 188 transitions. [2018-01-24 13:33:09,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 13:33:09,280 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 85 [2018-01-24 13:33:09,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:09,281 INFO L225 Difference]: With dead ends: 184 [2018-01-24 13:33:09,281 INFO L226 Difference]: Without dead ends: 107 [2018-01-24 13:33:09,281 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 350 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=205, Invalid=257, Unknown=0, NotChecked=0, Total=462 [2018-01-24 13:33:09,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-01-24 13:33:09,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 107. [2018-01-24 13:33:09,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-01-24 13:33:09,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 109 transitions. [2018-01-24 13:33:09,297 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 109 transitions. Word has length 85 [2018-01-24 13:33:09,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:09,297 INFO L432 AbstractCegarLoop]: Abstraction has 107 states and 109 transitions. [2018-01-24 13:33:09,297 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 13:33:09,298 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 109 transitions. [2018-01-24 13:33:09,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-01-24 13:33:09,298 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:09,298 INFO L322 BasicCegarLoop]: trace histogram [8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:09,299 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:09,299 INFO L82 PathProgramCache]: Analyzing trace with hash 1977139716, now seen corresponding path program 4 times [2018-01-24 13:33:09,299 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:09,300 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:09,300 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:33:09,300 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:09,300 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:09,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:09,323 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:09,497 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:09,497 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:09,497 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:09,504 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:33:09,505 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:33:09,559 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:33:09,563 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:09,585 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:09,585 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:09,843 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:09,864 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:09,864 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:33:09,867 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:33:09,867 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:33:10,017 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:33:10,025 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:10,034 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:10,034 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:10,132 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:10,134 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:33:10,134 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 13:33:10,134 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:33:10,135 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 13:33:10,135 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 13:33:10,135 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=232, Invalid=274, Unknown=0, NotChecked=0, Total=506 [2018-01-24 13:33:10,135 INFO L87 Difference]: Start difference. First operand 107 states and 109 transitions. Second operand 13 states. [2018-01-24 13:33:10,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:10,181 INFO L93 Difference]: Finished difference Result 185 states and 189 transitions. [2018-01-24 13:33:10,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 13:33:10,181 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 86 [2018-01-24 13:33:10,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:10,182 INFO L225 Difference]: With dead ends: 185 [2018-01-24 13:33:10,182 INFO L226 Difference]: Without dead ends: 108 [2018-01-24 13:33:10,183 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 355 GetRequests, 331 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=246, Invalid=306, Unknown=0, NotChecked=0, Total=552 [2018-01-24 13:33:10,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2018-01-24 13:33:10,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 108. [2018-01-24 13:33:10,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-01-24 13:33:10,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 110 transitions. [2018-01-24 13:33:10,207 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 110 transitions. Word has length 86 [2018-01-24 13:33:10,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:10,207 INFO L432 AbstractCegarLoop]: Abstraction has 108 states and 110 transitions. [2018-01-24 13:33:10,207 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 13:33:10,207 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 110 transitions. [2018-01-24 13:33:10,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 13:33:10,208 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:10,208 INFO L322 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:10,208 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:10,208 INFO L82 PathProgramCache]: Analyzing trace with hash -1218395795, now seen corresponding path program 5 times [2018-01-24 13:33:10,208 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:10,209 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:10,209 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:33:10,209 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:10,210 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:10,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:10,229 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:10,364 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:10,364 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:10,364 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:10,371 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:33:10,371 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:33:10,385 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:10,387 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:10,392 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:10,413 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:10,430 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:10,517 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:10,522 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:33:10,527 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:10,540 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:10,540 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:10,841 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:10,862 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:10,862 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:33:10,867 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:33:10,867 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:33:10,885 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:10,891 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:10,903 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:10,921 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:10,949 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:11,034 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:33:11,071 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:33:11,081 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:11,090 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:11,091 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:11,293 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:11,295 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:33:11,295 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 13:33:11,295 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:33:11,295 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 13:33:11,296 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 13:33:11,296 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=272, Invalid=328, Unknown=0, NotChecked=0, Total=600 [2018-01-24 13:33:11,296 INFO L87 Difference]: Start difference. First operand 108 states and 110 transitions. Second operand 14 states. [2018-01-24 13:33:11,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:33:11,374 INFO L93 Difference]: Finished difference Result 186 states and 190 transitions. [2018-01-24 13:33:11,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 13:33:11,374 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 87 [2018-01-24 13:33:11,374 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:33:11,375 INFO L225 Difference]: With dead ends: 186 [2018-01-24 13:33:11,375 INFO L226 Difference]: Without dead ends: 109 [2018-01-24 13:33:11,375 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 360 GetRequests, 334 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 84 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=287, Invalid=363, Unknown=0, NotChecked=0, Total=650 [2018-01-24 13:33:11,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-01-24 13:33:11,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 109. [2018-01-24 13:33:11,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-01-24 13:33:11,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 111 transitions. [2018-01-24 13:33:11,399 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 111 transitions. Word has length 87 [2018-01-24 13:33:11,399 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:33:11,399 INFO L432 AbstractCegarLoop]: Abstraction has 109 states and 111 transitions. [2018-01-24 13:33:11,399 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 13:33:11,399 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 111 transitions. [2018-01-24 13:33:11,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-24 13:33:11,400 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:33:11,400 INFO L322 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:33:11,400 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:33:11,400 INFO L82 PathProgramCache]: Analyzing trace with hash -1495748828, now seen corresponding path program 6 times [2018-01-24 13:33:11,401 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:33:11,401 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:11,402 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:33:11,402 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:33:11,402 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:33:11,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:33:11,424 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:33:11,976 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:11,977 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:11,977 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:33:11,987 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:33:11,987 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:33:12,030 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:33:12,042 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:33:12,059 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:33:12,461 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:33:12,748 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:33:14,267 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:33:14,269 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:33:14,274 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:33:14,306 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:14,306 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:33:14,569 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:33:14,590 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:33:14,591 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:33:14,594 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:33:14,594 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:33:14,657 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:33:14,742 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:33:15,419 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown