java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_5_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 13:21:14,600 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 13:21:14,602 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 13:21:14,615 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 13:21:14,615 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 13:21:14,616 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 13:21:14,618 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 13:21:14,619 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 13:21:14,621 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 13:21:14,622 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 13:21:14,623 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 13:21:14,623 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 13:21:14,624 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 13:21:14,626 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 13:21:14,627 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 13:21:14,630 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 13:21:14,632 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 13:21:14,634 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 13:21:14,635 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 13:21:14,636 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 13:21:14,639 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 13:21:14,639 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 13:21:14,639 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 13:21:14,640 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 13:21:14,641 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 13:21:14,642 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 13:21:14,643 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 13:21:14,643 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 13:21:14,644 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 13:21:14,644 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 13:21:14,645 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 13:21:14,645 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf [2018-01-24 13:21:14,655 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 13:21:14,655 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 13:21:14,656 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 13:21:14,657 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 13:21:14,657 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 13:21:14,657 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 13:21:14,657 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 13:21:14,658 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 13:21:14,658 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 13:21:14,658 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 13:21:14,658 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 13:21:14,659 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 13:21:14,659 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 13:21:14,659 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 13:21:14,659 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 13:21:14,659 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 13:21:14,660 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 13:21:14,660 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 13:21:14,660 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 13:21:14,660 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 13:21:14,660 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 13:21:14,661 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 13:21:14,661 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 13:21:14,661 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:21:14,661 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 13:21:14,662 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 13:21:14,662 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 13:21:14,662 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 13:21:14,662 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-01-24 13:21:14,662 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 13:21:14,662 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 13:21:14,663 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 13:21:14,663 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 13:21:14,664 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 13:21:14,699 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 13:21:14,713 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 13:21:14,717 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 13:21:14,719 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 13:21:14,719 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 13:21:14,720 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_5_false-valid-deref.i [2018-01-24 13:21:14,897 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 13:21:14,903 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 13:21:14,904 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 13:21:14,904 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 13:21:14,910 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 13:21:14,911 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:21:14" (1/1) ... [2018-01-24 13:21:14,914 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4be9a57f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:21:14, skipping insertion in model container [2018-01-24 13:21:14,915 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 01:21:14" (1/1) ... [2018-01-24 13:21:14,933 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:21:14,982 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 13:21:15,102 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:21:15,123 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 13:21:15,135 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:21:15 WrapperNode [2018-01-24 13:21:15,135 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 13:21:15,136 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 13:21:15,136 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 13:21:15,136 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 13:21:15,149 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:21:15" (1/1) ... [2018-01-24 13:21:15,150 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:21:15" (1/1) ... [2018-01-24 13:21:15,161 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:21:15" (1/1) ... [2018-01-24 13:21:15,161 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:21:15" (1/1) ... [2018-01-24 13:21:15,171 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:21:15" (1/1) ... [2018-01-24 13:21:15,175 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:21:15" (1/1) ... [2018-01-24 13:21:15,177 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:21:15" (1/1) ... [2018-01-24 13:21:15,180 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 13:21:15,180 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 13:21:15,180 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 13:21:15,180 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 13:21:15,181 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:21:15" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 13:21:15,226 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 13:21:15,226 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 13:21:15,226 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2018-01-24 13:21:15,226 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-01-24 13:21:15,227 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-01-24 13:21:15,227 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_atomic_sub_return [2018-01-24 13:21:15,227 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_sub [2018-01-24 13:21:15,227 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-01-24 13:21:15,227 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_put [2018-01-24 13:21:15,227 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-01-24 13:21:15,227 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-01-24 13:21:15,227 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_put [2018-01-24 13:21:15,227 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-01-24 13:21:15,227 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-01-24 13:21:15,228 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-01-24 13:21:15,228 INFO L136 BoogieDeclarations]: Found implementation of procedure f_22_put [2018-01-24 13:21:15,228 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-01-24 13:21:15,228 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 13:21:15,228 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 13:21:15,228 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 13:21:15,228 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-01-24 13:21:15,228 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-01-24 13:21:15,228 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 13:21:15,229 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 13:21:15,229 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 13:21:15,229 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-01-24 13:21:15,229 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-01-24 13:21:15,229 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-01-24 13:21:15,230 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-01-24 13:21:15,230 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 13:21:15,230 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-01-24 13:21:15,230 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-01-24 13:21:15,230 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-01-24 13:21:15,230 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_atomic_sub_return [2018-01-24 13:21:15,230 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_sub [2018-01-24 13:21:15,231 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2018-01-24 13:21:15,231 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-01-24 13:21:15,231 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_put [2018-01-24 13:21:15,231 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-01-24 13:21:15,231 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-01-24 13:21:15,231 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_put [2018-01-24 13:21:15,232 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-01-24 13:21:15,232 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-01-24 13:21:15,232 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-01-24 13:21:15,232 INFO L128 BoogieDeclarations]: Found specification of procedure f_22_put [2018-01-24 13:21:15,232 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-01-24 13:21:15,232 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 13:21:15,233 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 13:21:15,233 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 13:21:15,479 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-01-24 13:21:15,625 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 13:21:15,626 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:21:15 BoogieIcfgContainer [2018-01-24 13:21:15,626 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 13:21:15,627 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 13:21:15,628 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 13:21:15,630 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 13:21:15,631 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 01:21:14" (1/3) ... [2018-01-24 13:21:15,632 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2acde846 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:21:15, skipping insertion in model container [2018-01-24 13:21:15,632 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 01:21:15" (2/3) ... [2018-01-24 13:21:15,632 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2acde846 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 01:21:15, skipping insertion in model container [2018-01-24 13:21:15,633 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 01:21:15" (3/3) ... [2018-01-24 13:21:15,635 INFO L105 eAbstractionObserver]: Analyzing ICFG memleaks_test22_5_false-valid-deref.i [2018-01-24 13:21:15,644 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 13:21:15,653 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 19 error locations. [2018-01-24 13:21:15,706 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 13:21:15,707 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 13:21:15,707 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 13:21:15,707 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 13:21:15,707 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 13:21:15,707 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 13:21:15,708 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 13:21:15,708 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 13:21:15,709 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 13:21:15,733 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states. [2018-01-24 13:21:15,740 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 13:21:15,740 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:15,741 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:15,742 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:15,747 INFO L82 PathProgramCache]: Analyzing trace with hash 1211515492, now seen corresponding path program 1 times [2018-01-24 13:21:15,750 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:15,811 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:15,811 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:15,811 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:15,811 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:15,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:15,873 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:16,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:16,008 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:16,008 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:21:16,009 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:16,082 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 13:21:16,097 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 13:21:16,098 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:21:16,101 INFO L87 Difference]: Start difference. First operand 123 states. Second operand 5 states. [2018-01-24 13:21:16,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:16,181 INFO L93 Difference]: Finished difference Result 234 states and 249 transitions. [2018-01-24 13:21:16,182 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:21:16,184 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 13:21:16,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:16,197 INFO L225 Difference]: With dead ends: 234 [2018-01-24 13:21:16,198 INFO L226 Difference]: Without dead ends: 126 [2018-01-24 13:21:16,202 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:21:16,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-01-24 13:21:16,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 124. [2018-01-24 13:21:16,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-01-24 13:21:16,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 132 transitions. [2018-01-24 13:21:16,249 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 132 transitions. Word has length 17 [2018-01-24 13:21:16,249 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:16,249 INFO L432 AbstractCegarLoop]: Abstraction has 124 states and 132 transitions. [2018-01-24 13:21:16,249 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 13:21:16,250 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 132 transitions. [2018-01-24 13:21:16,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-24 13:21:16,250 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:16,250 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:16,251 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:16,251 INFO L82 PathProgramCache]: Analyzing trace with hash 774524518, now seen corresponding path program 1 times [2018-01-24 13:21:16,251 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:16,252 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:16,252 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:16,253 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:16,253 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:16,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:16,275 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:16,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:16,360 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:16,360 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 13:21:16,360 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:16,362 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:21:16,362 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:21:16,362 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:21:16,363 INFO L87 Difference]: Start difference. First operand 124 states and 132 transitions. Second operand 6 states. [2018-01-24 13:21:16,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:16,569 INFO L93 Difference]: Finished difference Result 126 states and 134 transitions. [2018-01-24 13:21:16,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:21:16,569 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2018-01-24 13:21:16,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:16,571 INFO L225 Difference]: With dead ends: 126 [2018-01-24 13:21:16,571 INFO L226 Difference]: Without dead ends: 125 [2018-01-24 13:21:16,572 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:21:16,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2018-01-24 13:21:16,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 123. [2018-01-24 13:21:16,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-01-24 13:21:16,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 131 transitions. [2018-01-24 13:21:16,583 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 131 transitions. Word has length 19 [2018-01-24 13:21:16,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:16,583 INFO L432 AbstractCegarLoop]: Abstraction has 123 states and 131 transitions. [2018-01-24 13:21:16,583 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:21:16,583 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 131 transitions. [2018-01-24 13:21:16,583 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-24 13:21:16,584 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:16,584 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:16,584 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:16,584 INFO L82 PathProgramCache]: Analyzing trace with hash 774524519, now seen corresponding path program 1 times [2018-01-24 13:21:16,584 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:16,585 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:16,585 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:16,585 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:16,585 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:16,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:16,607 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:16,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:16,834 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:16,834 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 13:21:16,834 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:16,834 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:21:16,834 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:21:16,835 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:21:16,835 INFO L87 Difference]: Start difference. First operand 123 states and 131 transitions. Second operand 7 states. [2018-01-24 13:21:17,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:17,062 INFO L93 Difference]: Finished difference Result 125 states and 133 transitions. [2018-01-24 13:21:17,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 13:21:17,063 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-01-24 13:21:17,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:17,066 INFO L225 Difference]: With dead ends: 125 [2018-01-24 13:21:17,066 INFO L226 Difference]: Without dead ends: 124 [2018-01-24 13:21:17,066 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-01-24 13:21:17,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-01-24 13:21:17,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 122. [2018-01-24 13:21:17,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-01-24 13:21:17,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 130 transitions. [2018-01-24 13:21:17,081 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 130 transitions. Word has length 19 [2018-01-24 13:21:17,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:17,081 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 130 transitions. [2018-01-24 13:21:17,081 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:21:17,081 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 130 transitions. [2018-01-24 13:21:17,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-01-24 13:21:17,083 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:17,083 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:17,083 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:17,083 INFO L82 PathProgramCache]: Analyzing trace with hash 1886266821, now seen corresponding path program 1 times [2018-01-24 13:21:17,084 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:17,085 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:17,085 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:17,086 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:17,086 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:17,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:17,111 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:17,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:17,250 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:17,250 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-01-24 13:21:17,251 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:17,251 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 13:21:17,251 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 13:21:17,251 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-01-24 13:21:17,251 INFO L87 Difference]: Start difference. First operand 122 states and 130 transitions. Second operand 9 states. [2018-01-24 13:21:17,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:17,388 INFO L93 Difference]: Finished difference Result 198 states and 213 transitions. [2018-01-24 13:21:17,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:21:17,389 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 31 [2018-01-24 13:21:17,389 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:17,390 INFO L225 Difference]: With dead ends: 198 [2018-01-24 13:21:17,391 INFO L226 Difference]: Without dead ends: 139 [2018-01-24 13:21:17,391 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-01-24 13:21:17,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-01-24 13:21:17,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 135. [2018-01-24 13:21:17,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-24 13:21:17,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 144 transitions. [2018-01-24 13:21:17,407 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 144 transitions. Word has length 31 [2018-01-24 13:21:17,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:17,408 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 144 transitions. [2018-01-24 13:21:17,408 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 13:21:17,408 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 144 transitions. [2018-01-24 13:21:17,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-24 13:21:17,410 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:17,410 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:17,410 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:17,410 INFO L82 PathProgramCache]: Analyzing trace with hash 107698799, now seen corresponding path program 1 times [2018-01-24 13:21:17,411 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:17,412 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:17,412 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:17,412 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:17,412 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:17,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:17,431 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:17,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:17,541 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:17,541 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-01-24 13:21:17,542 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:17,543 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:21:17,543 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:21:17,543 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:21:17,544 INFO L87 Difference]: Start difference. First operand 135 states and 144 transitions. Second operand 10 states. [2018-01-24 13:21:17,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:17,761 INFO L93 Difference]: Finished difference Result 135 states and 144 transitions. [2018-01-24 13:21:17,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:21:17,761 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 34 [2018-01-24 13:21:17,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:17,762 INFO L225 Difference]: With dead ends: 135 [2018-01-24 13:21:17,763 INFO L226 Difference]: Without dead ends: 134 [2018-01-24 13:21:17,763 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:21:17,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-01-24 13:21:17,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2018-01-24 13:21:17,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-24 13:21:17,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 143 transitions. [2018-01-24 13:21:17,774 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 143 transitions. Word has length 34 [2018-01-24 13:21:17,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:17,774 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 143 transitions. [2018-01-24 13:21:17,775 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:21:17,775 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 143 transitions. [2018-01-24 13:21:17,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-24 13:21:17,776 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:17,776 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:17,776 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:17,777 INFO L82 PathProgramCache]: Analyzing trace with hash 107698800, now seen corresponding path program 1 times [2018-01-24 13:21:17,777 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:17,778 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:17,778 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:17,778 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:17,779 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:17,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:17,795 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:17,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:17,840 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:17,840 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 13:21:17,840 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:17,841 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 13:21:17,841 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 13:21:17,841 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 13:21:17,841 INFO L87 Difference]: Start difference. First operand 134 states and 143 transitions. Second operand 4 states. [2018-01-24 13:21:17,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:17,871 INFO L93 Difference]: Finished difference Result 230 states and 245 transitions. [2018-01-24 13:21:17,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 13:21:17,873 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2018-01-24 13:21:17,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:17,875 INFO L225 Difference]: With dead ends: 230 [2018-01-24 13:21:17,876 INFO L226 Difference]: Without dead ends: 135 [2018-01-24 13:21:17,877 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 13:21:17,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-01-24 13:21:17,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 135. [2018-01-24 13:21:17,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-24 13:21:17,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 144 transitions. [2018-01-24 13:21:17,890 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 144 transitions. Word has length 34 [2018-01-24 13:21:17,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:17,890 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 144 transitions. [2018-01-24 13:21:17,890 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 13:21:17,890 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 144 transitions. [2018-01-24 13:21:17,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-01-24 13:21:17,892 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:17,892 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:17,892 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:17,892 INFO L82 PathProgramCache]: Analyzing trace with hash -1590593736, now seen corresponding path program 1 times [2018-01-24 13:21:17,893 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:17,894 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:17,894 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:17,894 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:17,894 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:17,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:17,913 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:17,960 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:17,960 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:17,961 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:17,970 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:17,970 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:21:18,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:18,015 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:18,061 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:18,061 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:18,147 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:18,170 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:18,171 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:21:18,179 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:18,179 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:21:18,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:18,230 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:18,237 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:18,237 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:18,268 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:18,313 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:21:18,313 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 13:21:18,313 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:21:18,314 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:21:18,314 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:21:18,314 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2018-01-24 13:21:18,314 INFO L87 Difference]: Start difference. First operand 135 states and 144 transitions. Second operand 6 states. [2018-01-24 13:21:18,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:18,338 INFO L93 Difference]: Finished difference Result 231 states and 246 transitions. [2018-01-24 13:21:18,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 13:21:18,338 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-01-24 13:21:18,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:18,340 INFO L225 Difference]: With dead ends: 231 [2018-01-24 13:21:18,340 INFO L226 Difference]: Without dead ends: 136 [2018-01-24 13:21:18,341 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 134 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=53, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:21:18,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-01-24 13:21:18,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2018-01-24 13:21:18,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-01-24 13:21:18,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 145 transitions. [2018-01-24 13:21:18,353 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 145 transitions. Word has length 35 [2018-01-24 13:21:18,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:18,353 INFO L432 AbstractCegarLoop]: Abstraction has 136 states and 145 transitions. [2018-01-24 13:21:18,353 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:21:18,353 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 145 transitions. [2018-01-24 13:21:18,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-24 13:21:18,355 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:18,355 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:18,355 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:18,355 INFO L82 PathProgramCache]: Analyzing trace with hash 1596912496, now seen corresponding path program 2 times [2018-01-24 13:21:18,355 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:18,356 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:18,356 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:18,357 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:18,357 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:18,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:18,377 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:18,435 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:18,436 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:18,436 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:18,445 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:21:18,446 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:21:18,485 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:18,489 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:18,494 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:18,529 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:21:18,531 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:21:18,554 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:21:18,555 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:21:18,581 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:21:18,581 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:21:19,442 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:21:19,442 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:19,856 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:21:19,877 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:21:19,878 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [14, 13] imperfect sequences [6] total 31 [2018-01-24 13:21:19,878 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:19,878 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 13:21:19,878 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 13:21:19,878 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=840, Unknown=0, NotChecked=0, Total=930 [2018-01-24 13:21:19,879 INFO L87 Difference]: Start difference. First operand 136 states and 145 transitions. Second operand 15 states. [2018-01-24 13:21:20,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:20,802 INFO L93 Difference]: Finished difference Result 153 states and 162 transitions. [2018-01-24 13:21:20,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 13:21:20,802 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 36 [2018-01-24 13:21:20,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:20,803 INFO L225 Difference]: With dead ends: 153 [2018-01-24 13:21:20,804 INFO L226 Difference]: Without dead ends: 152 [2018-01-24 13:21:20,804 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 81 GetRequests, 47 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 251 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=118, Invalid=1072, Unknown=0, NotChecked=0, Total=1190 [2018-01-24 13:21:20,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-24 13:21:20,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 135. [2018-01-24 13:21:20,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-24 13:21:20,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 144 transitions. [2018-01-24 13:21:20,818 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 144 transitions. Word has length 36 [2018-01-24 13:21:20,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:20,818 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 144 transitions. [2018-01-24 13:21:20,818 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 13:21:20,819 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 144 transitions. [2018-01-24 13:21:20,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-24 13:21:20,820 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:20,820 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:20,820 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:20,820 INFO L82 PathProgramCache]: Analyzing trace with hash 2040634480, now seen corresponding path program 1 times [2018-01-24 13:21:20,821 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:20,822 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:20,822 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:21:20,822 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:20,823 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:20,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:20,832 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:20,872 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 13:21:20,873 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:20,873 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 13:21:20,873 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:20,873 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 13:21:20,874 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 13:21:20,874 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 13:21:20,874 INFO L87 Difference]: Start difference. First operand 135 states and 144 transitions. Second operand 3 states. [2018-01-24 13:21:21,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:21,073 INFO L93 Difference]: Finished difference Result 154 states and 165 transitions. [2018-01-24 13:21:21,073 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 13:21:21,073 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2018-01-24 13:21:21,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:21,074 INFO L225 Difference]: With dead ends: 154 [2018-01-24 13:21:21,074 INFO L226 Difference]: Without dead ends: 141 [2018-01-24 13:21:21,075 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 13:21:21,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-01-24 13:21:21,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 131. [2018-01-24 13:21:21,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-01-24 13:21:21,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 139 transitions. [2018-01-24 13:21:21,096 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 139 transitions. Word has length 36 [2018-01-24 13:21:21,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:21,096 INFO L432 AbstractCegarLoop]: Abstraction has 131 states and 139 transitions. [2018-01-24 13:21:21,096 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 13:21:21,096 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 139 transitions. [2018-01-24 13:21:21,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-01-24 13:21:21,098 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:21,098 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:21,098 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:21,099 INFO L82 PathProgramCache]: Analyzing trace with hash 746437934, now seen corresponding path program 1 times [2018-01-24 13:21:21,099 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:21,100 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:21,100 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:21,100 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:21,100 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:21,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:21,109 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:21,140 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 13:21:21,140 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:21,140 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 13:21:21,140 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:21,141 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 13:21:21,141 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 13:21:21,141 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 13:21:21,141 INFO L87 Difference]: Start difference. First operand 131 states and 139 transitions. Second operand 6 states. [2018-01-24 13:21:21,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:21,170 INFO L93 Difference]: Finished difference Result 135 states and 142 transitions. [2018-01-24 13:21:21,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:21:21,170 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 38 [2018-01-24 13:21:21,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:21,171 INFO L225 Difference]: With dead ends: 135 [2018-01-24 13:21:21,172 INFO L226 Difference]: Without dead ends: 118 [2018-01-24 13:21:21,172 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 13:21:21,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-01-24 13:21:21,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 118. [2018-01-24 13:21:21,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-24 13:21:21,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 124 transitions. [2018-01-24 13:21:21,189 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 124 transitions. Word has length 38 [2018-01-24 13:21:21,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:21,189 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 124 transitions. [2018-01-24 13:21:21,190 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 13:21:21,190 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 124 transitions. [2018-01-24 13:21:21,190 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 13:21:21,190 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:21,191 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:21,191 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:21,191 INFO L82 PathProgramCache]: Analyzing trace with hash 1456559415, now seen corresponding path program 1 times [2018-01-24 13:21:21,191 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:21,192 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:21,192 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:21,193 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:21,193 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:21,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:21,208 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:21,331 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 13:21:21,332 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:21,332 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-01-24 13:21:21,332 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:21,333 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:21:21,333 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:21:21,333 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:21:21,333 INFO L87 Difference]: Start difference. First operand 118 states and 124 transitions. Second operand 10 states. [2018-01-24 13:21:21,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:21,860 INFO L93 Difference]: Finished difference Result 118 states and 124 transitions. [2018-01-24 13:21:21,860 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:21:21,860 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 41 [2018-01-24 13:21:21,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:21,861 INFO L225 Difference]: With dead ends: 118 [2018-01-24 13:21:21,861 INFO L226 Difference]: Without dead ends: 116 [2018-01-24 13:21:21,862 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:21:21,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-01-24 13:21:21,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 116. [2018-01-24 13:21:21,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 116 states. [2018-01-24 13:21:21,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 122 transitions. [2018-01-24 13:21:21,874 INFO L78 Accepts]: Start accepts. Automaton has 116 states and 122 transitions. Word has length 41 [2018-01-24 13:21:21,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:21,874 INFO L432 AbstractCegarLoop]: Abstraction has 116 states and 122 transitions. [2018-01-24 13:21:21,874 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:21:21,875 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 122 transitions. [2018-01-24 13:21:21,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 13:21:21,875 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:21,875 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:21,875 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:21,876 INFO L82 PathProgramCache]: Analyzing trace with hash 1456559416, now seen corresponding path program 1 times [2018-01-24 13:21:21,876 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:21,877 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:21,877 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:21,877 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:21,877 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:21,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:21,891 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:21,951 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:21,951 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:21,951 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:21,958 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:21,958 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:21:21,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:21,990 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:22,056 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:22,057 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:22,152 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:22,172 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:22,172 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:21:22,175 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:22,176 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:21:22,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:22,226 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:22,232 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:22,232 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:22,263 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:22,265 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:21:22,265 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 13:21:22,265 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:21:22,266 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 13:21:22,266 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 13:21:22,266 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=63, Unknown=0, NotChecked=0, Total=110 [2018-01-24 13:21:22,266 INFO L87 Difference]: Start difference. First operand 116 states and 122 transitions. Second operand 7 states. [2018-01-24 13:21:22,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:22,308 INFO L93 Difference]: Finished difference Result 209 states and 221 transitions. [2018-01-24 13:21:22,308 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 13:21:22,308 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 41 [2018-01-24 13:21:22,308 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:22,309 INFO L225 Difference]: With dead ends: 209 [2018-01-24 13:21:22,309 INFO L226 Difference]: Without dead ends: 117 [2018-01-24 13:21:22,310 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 169 GetRequests, 157 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=77, Unknown=0, NotChecked=0, Total=132 [2018-01-24 13:21:22,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-01-24 13:21:22,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2018-01-24 13:21:22,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-01-24 13:21:22,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 123 transitions. [2018-01-24 13:21:22,321 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 123 transitions. Word has length 41 [2018-01-24 13:21:22,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:22,322 INFO L432 AbstractCegarLoop]: Abstraction has 117 states and 123 transitions. [2018-01-24 13:21:22,322 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 13:21:22,322 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 123 transitions. [2018-01-24 13:21:22,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 13:21:22,322 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:22,323 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:22,323 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:22,323 INFO L82 PathProgramCache]: Analyzing trace with hash -98646160, now seen corresponding path program 2 times [2018-01-24 13:21:22,323 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:22,324 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:22,324 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:22,324 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:22,324 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:22,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:22,338 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:22,425 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:22,425 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:22,425 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:22,432 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:21:22,433 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:21:22,450 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:22,452 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:22,456 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:22,463 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:21:22,463 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:21:22,476 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:21:22,476 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:21:22,486 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:21:22,487 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:21:24,689 WARN L143 SmtUtils]: Spent 2035ms on a formula simplification that was a NOOP. DAG size: 27 [2018-01-24 13:21:25,029 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:21:25,029 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:27,573 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:21:27,593 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:21:27,594 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15, 13] imperfect sequences [7] total 33 [2018-01-24 13:21:27,594 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:27,594 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 13:21:27,594 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 13:21:27,595 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=950, Unknown=1, NotChecked=0, Total=1056 [2018-01-24 13:21:27,595 INFO L87 Difference]: Start difference. First operand 117 states and 123 transitions. Second operand 16 states. [2018-01-24 13:21:28,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:28,277 INFO L93 Difference]: Finished difference Result 117 states and 123 transitions. [2018-01-24 13:21:28,277 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 13:21:28,277 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 42 [2018-01-24 13:21:28,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:28,278 INFO L225 Difference]: With dead ends: 117 [2018-01-24 13:21:28,278 INFO L226 Difference]: Without dead ends: 115 [2018-01-24 13:21:28,278 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 57 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 311 ImplicationChecksByTransitivity, 5.1s TimeCoverageRelationStatistics Valid=136, Invalid=1195, Unknown=1, NotChecked=0, Total=1332 [2018-01-24 13:21:28,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-01-24 13:21:28,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-01-24 13:21:28,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-01-24 13:21:28,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 121 transitions. [2018-01-24 13:21:28,290 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 121 transitions. Word has length 42 [2018-01-24 13:21:28,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:28,290 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 121 transitions. [2018-01-24 13:21:28,291 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 13:21:28,291 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 121 transitions. [2018-01-24 13:21:28,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-01-24 13:21:28,291 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:28,292 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:28,292 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:28,292 INFO L82 PathProgramCache]: Analyzing trace with hash 293114675, now seen corresponding path program 1 times [2018-01-24 13:21:28,292 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:28,293 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:28,293 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:21:28,293 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:28,293 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:28,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:28,304 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:28,390 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:21:28,390 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:28,390 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-01-24 13:21:28,390 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:28,390 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:21:28,391 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:21:28,391 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-01-24 13:21:28,391 INFO L87 Difference]: Start difference. First operand 115 states and 121 transitions. Second operand 8 states. [2018-01-24 13:21:28,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:28,445 INFO L93 Difference]: Finished difference Result 183 states and 192 transitions. [2018-01-24 13:21:28,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:21:28,446 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 49 [2018-01-24 13:21:28,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:28,446 INFO L225 Difference]: With dead ends: 183 [2018-01-24 13:21:28,447 INFO L226 Difference]: Without dead ends: 115 [2018-01-24 13:21:28,447 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:21:28,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-01-24 13:21:28,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-01-24 13:21:28,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-01-24 13:21:28,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 120 transitions. [2018-01-24 13:21:28,458 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 120 transitions. Word has length 49 [2018-01-24 13:21:28,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:28,458 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 120 transitions. [2018-01-24 13:21:28,458 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:21:28,458 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 120 transitions. [2018-01-24 13:21:28,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-01-24 13:21:28,458 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:28,459 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:28,459 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:28,459 INFO L82 PathProgramCache]: Analyzing trace with hash 1097015104, now seen corresponding path program 1 times [2018-01-24 13:21:28,459 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:28,460 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:28,460 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:28,460 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:28,460 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:28,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:28,469 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:28,540 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:21:28,541 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:28,541 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-01-24 13:21:28,541 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:28,541 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:21:28,541 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:21:28,541 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-01-24 13:21:28,541 INFO L87 Difference]: Start difference. First operand 115 states and 120 transitions. Second operand 10 states. [2018-01-24 13:21:28,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:28,617 INFO L93 Difference]: Finished difference Result 185 states and 193 transitions. [2018-01-24 13:21:28,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:21:28,618 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 54 [2018-01-24 13:21:28,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:28,618 INFO L225 Difference]: With dead ends: 185 [2018-01-24 13:21:28,618 INFO L226 Difference]: Without dead ends: 115 [2018-01-24 13:21:28,619 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:21:28,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-01-24 13:21:28,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-01-24 13:21:28,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-01-24 13:21:28,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 119 transitions. [2018-01-24 13:21:28,632 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 119 transitions. Word has length 54 [2018-01-24 13:21:28,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:28,632 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 119 transitions. [2018-01-24 13:21:28,632 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:21:28,633 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 119 transitions. [2018-01-24 13:21:28,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-01-24 13:21:28,633 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:28,634 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:28,634 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:28,634 INFO L82 PathProgramCache]: Analyzing trace with hash -399143288, now seen corresponding path program 1 times [2018-01-24 13:21:28,634 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:28,635 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:28,635 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:28,635 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:28,635 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:28,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:28,656 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:28,963 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 13:21:28,963 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:28,963 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2018-01-24 13:21:28,963 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:28,964 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 13:21:28,964 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 13:21:28,964 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=461, Unknown=0, NotChecked=0, Total=506 [2018-01-24 13:21:28,964 INFO L87 Difference]: Start difference. First operand 115 states and 119 transitions. Second operand 23 states. [2018-01-24 13:21:29,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:29,510 INFO L93 Difference]: Finished difference Result 144 states and 154 transitions. [2018-01-24 13:21:29,510 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 13:21:29,510 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 65 [2018-01-24 13:21:29,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:29,511 INFO L225 Difference]: With dead ends: 144 [2018-01-24 13:21:29,511 INFO L226 Difference]: Without dead ends: 142 [2018-01-24 13:21:29,511 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=77, Invalid=853, Unknown=0, NotChecked=0, Total=930 [2018-01-24 13:21:29,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-01-24 13:21:29,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 137. [2018-01-24 13:21:29,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-01-24 13:21:29,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 147 transitions. [2018-01-24 13:21:29,531 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 147 transitions. Word has length 65 [2018-01-24 13:21:29,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:29,532 INFO L432 AbstractCegarLoop]: Abstraction has 137 states and 147 transitions. [2018-01-24 13:21:29,532 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 13:21:29,532 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 147 transitions. [2018-01-24 13:21:29,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-01-24 13:21:29,533 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:29,533 INFO L322 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:29,533 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:29,533 INFO L82 PathProgramCache]: Analyzing trace with hash -399143287, now seen corresponding path program 1 times [2018-01-24 13:21:29,533 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:29,534 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:29,535 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:29,535 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:29,535 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:29,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:29,557 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:29,614 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:29,615 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:29,615 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:29,626 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:29,626 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:21:29,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:29,673 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:29,687 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:29,687 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:29,786 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:29,807 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:29,807 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:21:29,811 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:29,812 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:21:29,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:29,911 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:29,917 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:29,918 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:29,979 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:29,980 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:21:29,980 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 13:21:29,980 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:21:29,981 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 13:21:29,981 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 13:21:29,981 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=88, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:21:29,981 INFO L87 Difference]: Start difference. First operand 137 states and 147 transitions. Second operand 8 states. [2018-01-24 13:21:30,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:30,012 INFO L93 Difference]: Finished difference Result 250 states and 270 transitions. [2018-01-24 13:21:30,013 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 13:21:30,013 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 65 [2018-01-24 13:21:30,013 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:30,014 INFO L225 Difference]: With dead ends: 250 [2018-01-24 13:21:30,014 INFO L226 Difference]: Without dead ends: 138 [2018-01-24 13:21:30,015 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 266 GetRequests, 252 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=77, Invalid=105, Unknown=0, NotChecked=0, Total=182 [2018-01-24 13:21:30,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-01-24 13:21:30,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2018-01-24 13:21:30,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-01-24 13:21:30,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 148 transitions. [2018-01-24 13:21:30,035 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 148 transitions. Word has length 65 [2018-01-24 13:21:30,035 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:30,035 INFO L432 AbstractCegarLoop]: Abstraction has 138 states and 148 transitions. [2018-01-24 13:21:30,035 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 13:21:30,035 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 148 transitions. [2018-01-24 13:21:30,036 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-01-24 13:21:30,036 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:30,036 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:30,036 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:30,036 INFO L82 PathProgramCache]: Analyzing trace with hash 559798465, now seen corresponding path program 2 times [2018-01-24 13:21:30,037 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:30,038 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:30,038 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:30,038 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:30,038 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:30,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:30,060 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:30,158 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:30,158 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:30,158 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:30,167 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:21:30,167 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:21:30,201 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:30,205 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:30,209 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:30,213 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:21:30,214 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:21:30,227 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:21:30,228 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:21:30,243 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:21:30,243 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:21:31,156 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:21:31,157 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:32,336 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:21:32,356 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:21:32,356 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [22, 20] imperfect sequences [8] total 48 [2018-01-24 13:21:32,357 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:32,357 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 13:21:32,357 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 13:21:32,357 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=2096, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 13:21:32,358 INFO L87 Difference]: Start difference. First operand 138 states and 148 transitions. Second operand 23 states. [2018-01-24 13:21:33,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:33,506 INFO L93 Difference]: Finished difference Result 138 states and 148 transitions. [2018-01-24 13:21:33,507 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 13:21:33,507 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 66 [2018-01-24 13:21:33,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:33,508 INFO L225 Difference]: With dead ends: 138 [2018-01-24 13:21:33,508 INFO L226 Difference]: Without dead ends: 136 [2018-01-24 13:21:33,509 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 146 GetRequests, 91 SyntacticMatches, 2 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 766 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=217, Invalid=2753, Unknown=0, NotChecked=0, Total=2970 [2018-01-24 13:21:33,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-01-24 13:21:33,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2018-01-24 13:21:33,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-01-24 13:21:33,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 144 transitions. [2018-01-24 13:21:33,524 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 144 transitions. Word has length 66 [2018-01-24 13:21:33,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:33,524 INFO L432 AbstractCegarLoop]: Abstraction has 136 states and 144 transitions. [2018-01-24 13:21:33,524 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 13:21:33,524 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 144 transitions. [2018-01-24 13:21:33,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-01-24 13:21:33,525 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:33,525 INFO L322 BasicCegarLoop]: trace histogram [4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:33,525 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:33,525 INFO L82 PathProgramCache]: Analyzing trace with hash -1638383027, now seen corresponding path program 1 times [2018-01-24 13:21:33,525 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:33,526 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:33,526 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:21:33,527 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:33,527 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:33,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:33,542 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:33,994 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:21:33,994 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:33,994 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-01-24 13:21:33,994 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:33,995 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 13:21:33,995 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 13:21:33,995 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=133, Unknown=0, NotChecked=0, Total=156 [2018-01-24 13:21:33,995 INFO L87 Difference]: Start difference. First operand 136 states and 144 transitions. Second operand 13 states. [2018-01-24 13:21:34,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:34,285 INFO L93 Difference]: Finished difference Result 194 states and 204 transitions. [2018-01-24 13:21:34,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 13:21:34,285 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 73 [2018-01-24 13:21:34,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:34,286 INFO L225 Difference]: With dead ends: 194 [2018-01-24 13:21:34,287 INFO L226 Difference]: Without dead ends: 134 [2018-01-24 13:21:34,287 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=39, Invalid=233, Unknown=0, NotChecked=0, Total=272 [2018-01-24 13:21:34,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-01-24 13:21:34,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2018-01-24 13:21:34,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-24 13:21:34,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 140 transitions. [2018-01-24 13:21:34,302 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 140 transitions. Word has length 73 [2018-01-24 13:21:34,302 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:34,302 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 140 transitions. [2018-01-24 13:21:34,303 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 13:21:34,303 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 140 transitions. [2018-01-24 13:21:34,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-01-24 13:21:34,303 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:34,303 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:34,303 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:34,303 INFO L82 PathProgramCache]: Analyzing trace with hash 154562580, now seen corresponding path program 1 times [2018-01-24 13:21:34,304 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:34,304 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:34,304 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:34,304 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:34,305 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:34,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:34,324 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:34,803 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 13:21:34,804 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 13:21:34,804 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [] total 26 [2018-01-24 13:21:34,804 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:34,804 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 13:21:34,804 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 13:21:34,804 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=649, Unknown=0, NotChecked=0, Total=702 [2018-01-24 13:21:34,805 INFO L87 Difference]: Start difference. First operand 134 states and 140 transitions. Second operand 27 states. [2018-01-24 13:21:35,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:35,548 INFO L93 Difference]: Finished difference Result 146 states and 156 transitions. [2018-01-24 13:21:35,549 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 13:21:35,549 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 80 [2018-01-24 13:21:35,549 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:35,549 INFO L225 Difference]: With dead ends: 146 [2018-01-24 13:21:35,550 INFO L226 Difference]: Without dead ends: 144 [2018-01-24 13:21:35,550 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=93, Invalid=1239, Unknown=0, NotChecked=0, Total=1332 [2018-01-24 13:21:35,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-01-24 13:21:35,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 140. [2018-01-24 13:21:35,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-01-24 13:21:35,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 150 transitions. [2018-01-24 13:21:35,567 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 150 transitions. Word has length 80 [2018-01-24 13:21:35,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:35,568 INFO L432 AbstractCegarLoop]: Abstraction has 140 states and 150 transitions. [2018-01-24 13:21:35,568 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 13:21:35,568 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 150 transitions. [2018-01-24 13:21:35,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-01-24 13:21:35,569 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:35,569 INFO L322 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:35,569 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:35,569 INFO L82 PathProgramCache]: Analyzing trace with hash 154562581, now seen corresponding path program 1 times [2018-01-24 13:21:35,569 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:35,570 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:35,570 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:35,570 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:35,570 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:35,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:35,585 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:35,723 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:35,723 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:35,724 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:35,736 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:35,737 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:21:35,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:35,793 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:35,851 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:35,852 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:35,966 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:35,996 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:35,996 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:21:36,001 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:36,001 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:21:36,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:36,136 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:36,144 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:36,144 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:36,266 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:36,269 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:21:36,269 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 13:21:36,269 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:21:36,269 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 13:21:36,269 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 13:21:36,269 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=117, Unknown=0, NotChecked=0, Total=210 [2018-01-24 13:21:36,270 INFO L87 Difference]: Start difference. First operand 140 states and 150 transitions. Second operand 9 states. [2018-01-24 13:21:36,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:36,335 INFO L93 Difference]: Finished difference Result 255 states and 275 transitions. [2018-01-24 13:21:36,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 13:21:36,336 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 80 [2018-01-24 13:21:36,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:36,336 INFO L225 Difference]: With dead ends: 255 [2018-01-24 13:21:36,336 INFO L226 Difference]: Without dead ends: 141 [2018-01-24 13:21:36,337 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 327 GetRequests, 311 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=103, Invalid=137, Unknown=0, NotChecked=0, Total=240 [2018-01-24 13:21:36,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-01-24 13:21:36,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2018-01-24 13:21:36,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-01-24 13:21:36,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 151 transitions. [2018-01-24 13:21:36,353 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 151 transitions. Word has length 80 [2018-01-24 13:21:36,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:36,354 INFO L432 AbstractCegarLoop]: Abstraction has 141 states and 151 transitions. [2018-01-24 13:21:36,354 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 13:21:36,354 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 151 transitions. [2018-01-24 13:21:36,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-01-24 13:21:36,354 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:36,354 INFO L322 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:36,354 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:36,355 INFO L82 PathProgramCache]: Analyzing trace with hash -585535779, now seen corresponding path program 2 times [2018-01-24 13:21:36,355 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:36,355 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:36,355 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:36,355 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:36,356 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:36,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:36,372 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:36,569 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:36,569 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:36,569 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:36,598 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:21:36,598 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:21:36,657 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:36,670 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:36,675 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:36,690 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-01-24 13:21:36,691 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 13:21:36,724 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-01-24 13:21:36,725 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 13:21:36,735 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-01-24 13:21:36,735 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-01-24 13:21:37,692 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 13:21:37,692 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:38,701 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 13:21:38,722 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 13:21:38,722 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [26, 24] imperfect sequences [9] total 57 [2018-01-24 13:21:38,722 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 13:21:38,722 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 13:21:38,723 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 13:21:38,723 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=195, Invalid=2997, Unknown=0, NotChecked=0, Total=3192 [2018-01-24 13:21:38,723 INFO L87 Difference]: Start difference. First operand 141 states and 151 transitions. Second operand 27 states. [2018-01-24 13:21:40,839 WARN L143 SmtUtils]: Spent 2053ms on a formula simplification that was a NOOP. DAG size: 39 [2018-01-24 13:21:42,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:42,041 INFO L93 Difference]: Finished difference Result 141 states and 151 transitions. [2018-01-24 13:21:42,042 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 13:21:42,042 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 81 [2018-01-24 13:21:42,042 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:42,043 INFO L225 Difference]: With dead ends: 141 [2018-01-24 13:21:42,043 INFO L226 Difference]: Without dead ends: 139 [2018-01-24 13:21:42,045 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 179 GetRequests, 111 SyntacticMatches, 4 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1153 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=268, Invalid=4022, Unknown=0, NotChecked=0, Total=4290 [2018-01-24 13:21:42,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-01-24 13:21:42,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2018-01-24 13:21:42,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-01-24 13:21:42,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 148 transitions. [2018-01-24 13:21:42,075 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 148 transitions. Word has length 81 [2018-01-24 13:21:42,075 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:42,075 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 148 transitions. [2018-01-24 13:21:42,075 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 13:21:42,075 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 148 transitions. [2018-01-24 13:21:42,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-01-24 13:21:42,076 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:42,076 INFO L322 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:42,076 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:42,077 INFO L82 PathProgramCache]: Analyzing trace with hash -1024705250, now seen corresponding path program 1 times [2018-01-24 13:21:42,077 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:42,078 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:42,078 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:21:42,078 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:42,078 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:42,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:42,101 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:42,183 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:42,184 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:42,184 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:42,191 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:42,191 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:21:42,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:42,255 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:42,266 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:42,266 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:42,398 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:42,419 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:42,419 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:21:42,422 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:42,422 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 13:21:42,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:42,514 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:42,519 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:42,520 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:42,583 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:42,585 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:21:42,585 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 13:21:42,585 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:21:42,585 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 13:21:42,586 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 13:21:42,586 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=150, Unknown=0, NotChecked=0, Total=272 [2018-01-24 13:21:42,586 INFO L87 Difference]: Start difference. First operand 139 states and 148 transitions. Second operand 10 states. [2018-01-24 13:21:42,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:42,618 INFO L93 Difference]: Finished difference Result 252 states and 270 transitions. [2018-01-24 13:21:42,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 13:21:42,619 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 85 [2018-01-24 13:21:42,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:42,619 INFO L225 Difference]: With dead ends: 252 [2018-01-24 13:21:42,620 INFO L226 Difference]: Without dead ends: 140 [2018-01-24 13:21:42,620 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 348 GetRequests, 330 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=133, Invalid=173, Unknown=0, NotChecked=0, Total=306 [2018-01-24 13:21:42,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-01-24 13:21:42,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2018-01-24 13:21:42,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-01-24 13:21:42,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 149 transitions. [2018-01-24 13:21:42,643 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 149 transitions. Word has length 85 [2018-01-24 13:21:42,643 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:42,643 INFO L432 AbstractCegarLoop]: Abstraction has 140 states and 149 transitions. [2018-01-24 13:21:42,643 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 13:21:42,643 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 149 transitions. [2018-01-24 13:21:42,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-01-24 13:21:42,643 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:42,643 INFO L322 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:42,644 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:42,644 INFO L82 PathProgramCache]: Analyzing trace with hash -796837034, now seen corresponding path program 2 times [2018-01-24 13:21:42,644 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:42,644 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:42,645 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 13:21:42,645 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:42,645 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:42,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:42,666 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:42,767 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:42,767 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:42,768 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:42,775 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:21:42,775 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:21:42,830 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:42,843 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:42,846 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:42,851 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:42,883 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:42,883 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:43,051 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:43,085 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:43,085 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:21:43,091 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 13:21:43,091 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:21:43,151 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:43,261 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:43,303 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:43,312 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:43,320 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:43,320 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:43,421 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:43,424 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:21:43,424 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 13:21:43,424 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:21:43,424 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 13:21:43,425 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 13:21:43,425 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=187, Unknown=0, NotChecked=0, Total=342 [2018-01-24 13:21:43,425 INFO L87 Difference]: Start difference. First operand 140 states and 149 transitions. Second operand 11 states. [2018-01-24 13:21:43,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:43,471 INFO L93 Difference]: Finished difference Result 253 states and 271 transitions. [2018-01-24 13:21:43,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 13:21:43,471 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 86 [2018-01-24 13:21:43,471 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:43,472 INFO L225 Difference]: With dead ends: 253 [2018-01-24 13:21:43,472 INFO L226 Difference]: Without dead ends: 141 [2018-01-24 13:21:43,472 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 353 GetRequests, 333 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=167, Invalid=213, Unknown=0, NotChecked=0, Total=380 [2018-01-24 13:21:43,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-01-24 13:21:43,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2018-01-24 13:21:43,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-01-24 13:21:43,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 150 transitions. [2018-01-24 13:21:43,492 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 150 transitions. Word has length 86 [2018-01-24 13:21:43,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:43,492 INFO L432 AbstractCegarLoop]: Abstraction has 141 states and 150 transitions. [2018-01-24 13:21:43,492 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 13:21:43,492 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 150 transitions. [2018-01-24 13:21:43,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 13:21:43,492 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:43,492 INFO L322 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:43,493 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:43,493 INFO L82 PathProgramCache]: Analyzing trace with hash 1972110366, now seen corresponding path program 3 times [2018-01-24 13:21:43,493 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:43,494 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:43,494 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:21:43,494 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:43,494 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:43,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:43,509 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:43,620 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:43,621 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:43,621 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:43,629 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:21:43,629 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:21:43,664 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:21:43,676 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:21:43,707 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:21:43,925 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:21:44,039 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:21:44,041 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:44,044 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:44,053 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:44,053 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:44,227 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:44,248 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:44,248 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:21:44,252 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 13:21:44,252 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 13:21:44,323 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:21:44,423 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:21:44,996 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:21:48,020 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:21:49,442 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 13:21:49,502 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:49,511 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:49,517 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:49,517 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:49,623 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:49,626 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:21:49,626 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 13:21:49,627 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:21:49,627 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 13:21:49,627 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 13:21:49,627 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=228, Unknown=0, NotChecked=0, Total=420 [2018-01-24 13:21:49,628 INFO L87 Difference]: Start difference. First operand 141 states and 150 transitions. Second operand 12 states. [2018-01-24 13:21:49,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:49,723 INFO L93 Difference]: Finished difference Result 254 states and 272 transitions. [2018-01-24 13:21:49,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 13:21:49,723 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 87 [2018-01-24 13:21:49,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:49,724 INFO L225 Difference]: With dead ends: 254 [2018-01-24 13:21:49,724 INFO L226 Difference]: Without dead ends: 142 [2018-01-24 13:21:49,725 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 358 GetRequests, 336 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=205, Invalid=257, Unknown=0, NotChecked=0, Total=462 [2018-01-24 13:21:49,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-01-24 13:21:49,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 142. [2018-01-24 13:21:49,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-01-24 13:21:49,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 151 transitions. [2018-01-24 13:21:49,749 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 151 transitions. Word has length 87 [2018-01-24 13:21:49,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:49,749 INFO L432 AbstractCegarLoop]: Abstraction has 142 states and 151 transitions. [2018-01-24 13:21:49,750 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 13:21:49,750 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 151 transitions. [2018-01-24 13:21:49,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-24 13:21:49,750 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:49,750 INFO L322 BasicCegarLoop]: trace histogram [8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:49,751 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:49,751 INFO L82 PathProgramCache]: Analyzing trace with hash 1910133846, now seen corresponding path program 4 times [2018-01-24 13:21:49,751 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:49,752 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:49,752 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:21:49,752 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:49,752 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:49,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:49,771 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:49,877 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:49,877 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:49,877 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:49,885 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:21:49,886 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:21:49,946 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:49,950 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:49,974 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:49,975 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:50,326 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:50,346 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:50,346 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:21:50,350 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 13:21:50,350 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 13:21:50,481 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:50,489 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:50,496 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:50,496 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:50,587 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:50,589 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:21:50,589 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 13:21:50,589 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:21:50,589 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 13:21:50,590 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 13:21:50,590 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=232, Invalid=274, Unknown=0, NotChecked=0, Total=506 [2018-01-24 13:21:50,590 INFO L87 Difference]: Start difference. First operand 142 states and 151 transitions. Second operand 13 states. [2018-01-24 13:21:50,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:50,635 INFO L93 Difference]: Finished difference Result 255 states and 273 transitions. [2018-01-24 13:21:50,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 13:21:50,636 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 88 [2018-01-24 13:21:50,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:50,637 INFO L225 Difference]: With dead ends: 255 [2018-01-24 13:21:50,637 INFO L226 Difference]: Without dead ends: 143 [2018-01-24 13:21:50,638 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 363 GetRequests, 339 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=246, Invalid=306, Unknown=0, NotChecked=0, Total=552 [2018-01-24 13:21:50,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-01-24 13:21:50,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 143. [2018-01-24 13:21:50,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-01-24 13:21:50,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 152 transitions. [2018-01-24 13:21:50,669 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 152 transitions. Word has length 88 [2018-01-24 13:21:50,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:50,670 INFO L432 AbstractCegarLoop]: Abstraction has 143 states and 152 transitions. [2018-01-24 13:21:50,670 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 13:21:50,670 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 152 transitions. [2018-01-24 13:21:50,670 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-01-24 13:21:50,671 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:50,671 INFO L322 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:50,671 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:50,671 INFO L82 PathProgramCache]: Analyzing trace with hash -11138274, now seen corresponding path program 5 times [2018-01-24 13:21:50,671 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:50,672 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:50,672 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:21:50,672 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:50,672 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:50,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:50,693 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:50,867 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:50,867 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:50,867 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:50,874 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:21:50,875 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:21:50,895 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:50,898 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:50,904 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:50,921 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:50,997 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:51,104 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:51,112 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:51,116 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:51,129 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:51,130 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:51,491 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:51,512 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:51,512 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:21:51,515 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 13:21:51,516 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 13:21:51,533 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:51,537 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:51,546 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:51,562 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:51,590 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:51,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 13:21:51,718 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:51,726 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:51,733 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:51,733 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:51,874 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:51,876 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 13:21:51,876 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 13:21:51,876 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 13:21:51,877 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 13:21:51,877 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 13:21:51,877 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=272, Invalid=328, Unknown=0, NotChecked=0, Total=600 [2018-01-24 13:21:51,877 INFO L87 Difference]: Start difference. First operand 143 states and 152 transitions. Second operand 14 states. [2018-01-24 13:21:51,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 13:21:51,933 INFO L93 Difference]: Finished difference Result 256 states and 274 transitions. [2018-01-24 13:21:51,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 13:21:51,934 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 89 [2018-01-24 13:21:51,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 13:21:51,934 INFO L225 Difference]: With dead ends: 256 [2018-01-24 13:21:51,935 INFO L226 Difference]: Without dead ends: 144 [2018-01-24 13:21:51,935 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 368 GetRequests, 342 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 84 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=287, Invalid=363, Unknown=0, NotChecked=0, Total=650 [2018-01-24 13:21:51,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-01-24 13:21:51,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 144. [2018-01-24 13:21:51,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-01-24 13:21:51,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 153 transitions. [2018-01-24 13:21:51,968 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 153 transitions. Word has length 89 [2018-01-24 13:21:51,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 13:21:51,968 INFO L432 AbstractCegarLoop]: Abstraction has 144 states and 153 transitions. [2018-01-24 13:21:51,968 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 13:21:51,968 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 153 transitions. [2018-01-24 13:21:51,969 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-01-24 13:21:51,969 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 13:21:51,969 INFO L322 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 13:21:51,969 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-01-24 13:21:51,969 INFO L82 PathProgramCache]: Analyzing trace with hash 558968150, now seen corresponding path program 6 times [2018-01-24 13:21:51,970 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 13:21:51,970 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:51,971 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 13:21:51,971 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 13:21:51,971 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 13:21:51,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 13:21:51,991 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 13:21:52,155 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:52,156 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:52,156 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 13:21:52,164 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:21:52,164 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:21:52,217 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:21:52,236 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:21:52,278 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:21:52,393 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:21:52,613 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:21:53,121 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:21:53,122 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 13:21:53,127 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 13:21:53,145 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:53,145 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 13:21:53,381 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 13:21:53,402 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 13:21:53,402 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 13:21:53,405 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 13:21:53,405 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 13:21:53,460 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:21:53,561 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 13:22:05,588 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown