java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/array-examples/standard_strcpy_false-valid-deref_ground.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 12:58:32,362 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 12:58:32,364 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 12:58:32,379 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 12:58:32,380 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 12:58:32,381 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 12:58:32,382 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 12:58:32,383 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 12:58:32,385 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 12:58:32,386 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 12:58:32,387 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 12:58:32,387 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 12:58:32,388 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 12:58:32,389 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 12:58:32,390 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 12:58:32,393 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 12:58:32,395 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 12:58:32,397 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 12:58:32,398 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 12:58:32,399 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 12:58:32,402 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 12:58:32,402 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 12:58:32,402 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 12:58:32,403 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 12:58:32,404 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 12:58:32,405 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 12:58:32,406 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 12:58:32,406 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 12:58:32,407 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 12:58:32,407 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 12:58:32,407 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 12:58:32,408 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf [2018-01-24 12:58:32,416 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 12:58:32,416 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 12:58:32,417 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 12:58:32,417 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 12:58:32,418 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 12:58:32,418 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 12:58:32,418 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 12:58:32,418 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 12:58:32,418 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 12:58:32,418 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 12:58:32,419 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 12:58:32,419 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 12:58:32,419 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 12:58:32,419 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 12:58:32,419 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 12:58:32,419 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 12:58:32,419 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 12:58:32,419 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 12:58:32,420 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 12:58:32,420 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 12:58:32,420 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 12:58:32,420 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 12:58:32,420 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 12:58:32,421 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 12:58:32,421 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 12:58:32,421 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 12:58:32,421 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 12:58:32,421 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 12:58:32,422 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-01-24 12:58:32,422 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 12:58:32,422 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 12:58:32,422 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 12:58:32,423 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 12:58:32,423 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 12:58:32,456 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 12:58:32,469 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 12:58:32,472 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 12:58:32,473 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 12:58:32,474 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 12:58:32,474 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/standard_strcpy_false-valid-deref_ground.i [2018-01-24 12:58:32,591 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 12:58:32,596 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 12:58:32,597 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 12:58:32,597 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 12:58:32,603 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 12:58:32,604 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 12:58:32" (1/1) ... [2018-01-24 12:58:32,606 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@29a4c9af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:32, skipping insertion in model container [2018-01-24 12:58:32,606 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 12:58:32" (1/1) ... [2018-01-24 12:58:32,620 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 12:58:32,633 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 12:58:32,740 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 12:58:32,752 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 12:58:32,756 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:32 WrapperNode [2018-01-24 12:58:32,756 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 12:58:32,757 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 12:58:32,757 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 12:58:32,757 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 12:58:32,768 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:32" (1/1) ... [2018-01-24 12:58:32,768 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:32" (1/1) ... [2018-01-24 12:58:32,776 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:32" (1/1) ... [2018-01-24 12:58:32,776 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:32" (1/1) ... [2018-01-24 12:58:32,777 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:32" (1/1) ... [2018-01-24 12:58:32,780 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:32" (1/1) ... [2018-01-24 12:58:32,782 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:32" (1/1) ... [2018-01-24 12:58:32,783 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 12:58:32,784 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 12:58:32,784 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 12:58:32,784 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 12:58:32,785 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:32" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 12:58:32,853 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 12:58:32,853 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 12:58:32,854 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 12:58:32,854 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 12:58:32,854 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 12:58:32,854 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 12:58:32,854 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 12:58:32,854 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 12:58:32,854 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 12:58:32,986 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 12:58:32,987 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 12:58:32 BoogieIcfgContainer [2018-01-24 12:58:32,987 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 12:58:32,988 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 12:58:32,988 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 12:58:32,989 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 12:58:32,990 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 12:58:32" (1/3) ... [2018-01-24 12:58:32,990 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5431e13c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 12:58:32, skipping insertion in model container [2018-01-24 12:58:32,991 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:32" (2/3) ... [2018-01-24 12:58:32,991 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5431e13c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 12:58:32, skipping insertion in model container [2018-01-24 12:58:32,991 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 12:58:32" (3/3) ... [2018-01-24 12:58:32,993 INFO L105 eAbstractionObserver]: Analyzing ICFG standard_strcpy_false-valid-deref_ground.i [2018-01-24 12:58:33,003 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 12:58:33,013 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 5 error locations. [2018-01-24 12:58:33,051 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 12:58:33,051 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 12:58:33,051 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 12:58:33,051 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 12:58:33,051 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 12:58:33,052 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 12:58:33,052 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 12:58:33,052 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 12:58:33,053 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 12:58:33,074 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states. [2018-01-24 12:58:33,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2018-01-24 12:58:33,081 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:33,082 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:33,083 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:33,088 INFO L82 PathProgramCache]: Analyzing trace with hash -42218404, now seen corresponding path program 1 times [2018-01-24 12:58:33,091 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:33,148 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:33,148 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:33,148 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:33,148 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:33,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:33,192 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:33,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:33,250 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:58:33,250 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 12:58:33,250 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 12:58:33,252 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 12:58:33,262 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 12:58:33,263 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 12:58:33,265 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 3 states. [2018-01-24 12:58:33,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:33,353 INFO L93 Difference]: Finished difference Result 71 states and 84 transitions. [2018-01-24 12:58:33,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 12:58:33,355 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2018-01-24 12:58:33,355 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:33,363 INFO L225 Difference]: With dead ends: 71 [2018-01-24 12:58:33,364 INFO L226 Difference]: Without dead ends: 40 [2018-01-24 12:58:33,368 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 12:58:33,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-01-24 12:58:33,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 31. [2018-01-24 12:58:33,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-01-24 12:58:33,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 33 transitions. [2018-01-24 12:58:33,463 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 33 transitions. Word has length 7 [2018-01-24 12:58:33,463 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:33,463 INFO L432 AbstractCegarLoop]: Abstraction has 31 states and 33 transitions. [2018-01-24 12:58:33,463 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 12:58:33,463 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 33 transitions. [2018-01-24 12:58:33,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-01-24 12:58:33,464 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:33,464 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:33,464 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:33,464 INFO L82 PathProgramCache]: Analyzing trace with hash -207595369, now seen corresponding path program 1 times [2018-01-24 12:58:33,464 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:33,466 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:33,466 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:33,466 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:33,466 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:33,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:33,478 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:33,528 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:33,528 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:33,528 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:33,546 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:33,547 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:33,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:33,562 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:33,578 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:33,579 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:33,632 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:33,653 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:33,653 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:33,657 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:33,658 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:33,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:33,667 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:33,688 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:33,688 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:33,742 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:33,743 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:33,744 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3, 3, 3] total 5 [2018-01-24 12:58:33,744 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:33,745 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 12:58:33,745 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 12:58:33,745 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 12:58:33,745 INFO L87 Difference]: Start difference. First operand 31 states and 33 transitions. Second operand 4 states. [2018-01-24 12:58:33,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:33,791 INFO L93 Difference]: Finished difference Result 57 states and 62 transitions. [2018-01-24 12:58:33,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 12:58:33,791 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-01-24 12:58:33,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:33,793 INFO L225 Difference]: With dead ends: 57 [2018-01-24 12:58:33,793 INFO L226 Difference]: Without dead ends: 54 [2018-01-24 12:58:33,794 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 43 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 12:58:33,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-24 12:58:33,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 36. [2018-01-24 12:58:33,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-01-24 12:58:33,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 39 transitions. [2018-01-24 12:58:33,801 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 39 transitions. Word has length 12 [2018-01-24 12:58:33,801 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:33,802 INFO L432 AbstractCegarLoop]: Abstraction has 36 states and 39 transitions. [2018-01-24 12:58:33,802 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 12:58:33,802 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 39 transitions. [2018-01-24 12:58:33,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-01-24 12:58:33,802 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:33,803 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:33,803 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:33,803 INFO L82 PathProgramCache]: Analyzing trace with hash -209255178, now seen corresponding path program 1 times [2018-01-24 12:58:33,803 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:33,804 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:33,804 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:33,804 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:33,805 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:33,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:33,810 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:33,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:33,844 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:58:33,844 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 12:58:33,844 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 12:58:33,844 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 12:58:33,845 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 12:58:33,845 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 12:58:33,845 INFO L87 Difference]: Start difference. First operand 36 states and 39 transitions. Second operand 4 states. [2018-01-24 12:58:33,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:33,878 INFO L93 Difference]: Finished difference Result 51 states and 54 transitions. [2018-01-24 12:58:33,878 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 12:58:33,878 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-01-24 12:58:33,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:33,879 INFO L225 Difference]: With dead ends: 51 [2018-01-24 12:58:33,879 INFO L226 Difference]: Without dead ends: 36 [2018-01-24 12:58:33,880 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 12:58:33,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2018-01-24 12:58:33,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2018-01-24 12:58:33,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-01-24 12:58:33,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 38 transitions. [2018-01-24 12:58:33,886 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 38 transitions. Word has length 12 [2018-01-24 12:58:33,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:33,887 INFO L432 AbstractCegarLoop]: Abstraction has 36 states and 38 transitions. [2018-01-24 12:58:33,887 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 12:58:33,887 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 38 transitions. [2018-01-24 12:58:33,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 12:58:33,888 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:33,888 INFO L322 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:33,888 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:33,888 INFO L82 PathProgramCache]: Analyzing trace with hash 2132883772, now seen corresponding path program 2 times [2018-01-24 12:58:33,888 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:33,890 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:33,890 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:33,890 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:33,890 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:33,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:33,898 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:33,947 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:33,947 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:33,948 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:33,954 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:33,954 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:33,958 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:33,963 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:33,964 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:33,966 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:33,974 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:33,974 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:34,048 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,081 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:34,081 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:34,085 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:34,085 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:34,090 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:34,093 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:34,096 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:34,099 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:34,105 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,105 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:34,112 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,113 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:34,113 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-01-24 12:58:34,113 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:34,113 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 12:58:34,114 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 12:58:34,114 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 12:58:34,114 INFO L87 Difference]: Start difference. First operand 36 states and 38 transitions. Second operand 5 states. [2018-01-24 12:58:34,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:34,182 INFO L93 Difference]: Finished difference Result 62 states and 67 transitions. [2018-01-24 12:58:34,182 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 12:58:34,182 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 12:58:34,183 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:34,184 INFO L225 Difference]: With dead ends: 62 [2018-01-24 12:58:34,184 INFO L226 Difference]: Without dead ends: 59 [2018-01-24 12:58:34,184 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 62 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 12:58:34,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-01-24 12:58:34,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 41. [2018-01-24 12:58:34,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-01-24 12:58:34,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 44 transitions. [2018-01-24 12:58:34,191 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 44 transitions. Word has length 17 [2018-01-24 12:58:34,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:34,191 INFO L432 AbstractCegarLoop]: Abstraction has 41 states and 44 transitions. [2018-01-24 12:58:34,191 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 12:58:34,192 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 44 transitions. [2018-01-24 12:58:34,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 12:58:34,192 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:34,192 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:34,193 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:34,193 INFO L82 PathProgramCache]: Analyzing trace with hash 2131223963, now seen corresponding path program 1 times [2018-01-24 12:58:34,193 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:34,194 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:34,194 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:34,194 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:34,194 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:34,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:34,201 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:34,242 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,242 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:34,243 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:34,247 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:34,248 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:34,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:34,253 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:34,254 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 12:58:34,254 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:34,265 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 12:58:34,285 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 12:58:34,285 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2, 2] imperfect sequences [5] total 6 [2018-01-24 12:58:34,285 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 12:58:34,285 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 12:58:34,285 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 12:58:34,286 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 12:58:34,286 INFO L87 Difference]: Start difference. First operand 41 states and 44 transitions. Second operand 3 states. [2018-01-24 12:58:34,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:34,296 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2018-01-24 12:58:34,296 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 12:58:34,296 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 17 [2018-01-24 12:58:34,297 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:34,297 INFO L225 Difference]: With dead ends: 49 [2018-01-24 12:58:34,297 INFO L226 Difference]: Without dead ends: 47 [2018-01-24 12:58:34,298 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 12:58:34,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-01-24 12:58:34,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 45. [2018-01-24 12:58:34,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-01-24 12:58:34,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 48 transitions. [2018-01-24 12:58:34,302 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 48 transitions. Word has length 17 [2018-01-24 12:58:34,302 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:34,302 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 48 transitions. [2018-01-24 12:58:34,302 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 12:58:34,303 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 48 transitions. [2018-01-24 12:58:34,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-01-24 12:58:34,303 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:34,303 INFO L322 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:34,303 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:34,304 INFO L82 PathProgramCache]: Analyzing trace with hash 2059138999, now seen corresponding path program 3 times [2018-01-24 12:58:34,304 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:34,304 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:34,305 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:34,305 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:34,305 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:34,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:34,310 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:34,383 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,383 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:34,383 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:34,390 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:34,390 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:34,393 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:34,402 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:34,403 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:34,405 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:34,405 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:34,407 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:34,415 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,415 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:34,485 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,505 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:34,505 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:34,508 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:34,508 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:34,513 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:34,515 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:34,519 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:34,524 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:34,527 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:34,529 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:34,535 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,535 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:34,543 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,544 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:34,544 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 12:58:34,544 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:34,545 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 12:58:34,545 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 12:58:34,545 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 12:58:34,545 INFO L87 Difference]: Start difference. First operand 45 states and 48 transitions. Second operand 6 states. [2018-01-24 12:58:34,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:34,638 INFO L93 Difference]: Finished difference Result 92 states and 99 transitions. [2018-01-24 12:58:34,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 12:58:34,638 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-01-24 12:58:34,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:34,640 INFO L225 Difference]: With dead ends: 92 [2018-01-24 12:58:34,640 INFO L226 Difference]: Without dead ends: 89 [2018-01-24 12:58:34,640 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 81 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 12:58:34,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-01-24 12:58:34,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 50. [2018-01-24 12:58:34,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 12:58:34,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-01-24 12:58:34,646 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 22 [2018-01-24 12:58:34,646 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:34,647 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-01-24 12:58:34,647 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 12:58:34,647 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-01-24 12:58:34,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 12:58:34,647 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:34,648 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:34,648 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:34,648 INFO L82 PathProgramCache]: Analyzing trace with hash -6617899, now seen corresponding path program 1 times [2018-01-24 12:58:34,648 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:34,649 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:34,649 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:34,649 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:34,649 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:34,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:34,657 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:34,699 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,700 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:34,700 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:34,708 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:34,708 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:34,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:34,719 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:34,744 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,744 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:34,759 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,779 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:34,779 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:34,782 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:34,782 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:34,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:34,794 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:34,800 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,800 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:34,815 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,816 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:34,816 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 9 [2018-01-24 12:58:34,816 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:34,816 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 12:58:34,816 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 12:58:34,816 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-01-24 12:58:34,817 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 8 states. [2018-01-24 12:58:34,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:34,867 INFO L93 Difference]: Finished difference Result 71 states and 76 transitions. [2018-01-24 12:58:34,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 12:58:34,867 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27 [2018-01-24 12:58:34,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:34,868 INFO L225 Difference]: With dead ends: 71 [2018-01-24 12:58:34,868 INFO L226 Difference]: Without dead ends: 50 [2018-01-24 12:58:34,869 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 101 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-01-24 12:58:34,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-01-24 12:58:34,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2018-01-24 12:58:34,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 12:58:34,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 53 transitions. [2018-01-24 12:58:34,873 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 53 transitions. Word has length 27 [2018-01-24 12:58:34,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:34,873 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 53 transitions. [2018-01-24 12:58:34,873 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 12:58:34,873 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 53 transitions. [2018-01-24 12:58:34,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 12:58:34,874 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:34,874 INFO L322 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:34,874 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:34,874 INFO L82 PathProgramCache]: Analyzing trace with hash -1173615076, now seen corresponding path program 4 times [2018-01-24 12:58:34,874 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:34,875 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:34,875 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:34,875 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:34,875 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:34,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:34,882 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:34,952 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,952 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:34,952 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:34,958 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:34,958 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:34,964 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:34,965 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:34,971 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:34,971 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:35,094 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:35,114 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:35,114 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:35,118 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:35,118 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:35,132 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:35,136 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:35,144 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:35,145 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:35,160 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:35,161 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:35,161 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 12:58:35,161 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:35,162 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 12:58:35,162 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 12:58:35,162 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 12:58:35,162 INFO L87 Difference]: Start difference. First operand 50 states and 53 transitions. Second operand 7 states. [2018-01-24 12:58:35,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:35,238 INFO L93 Difference]: Finished difference Result 97 states and 104 transitions. [2018-01-24 12:58:35,239 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 12:58:35,239 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 27 [2018-01-24 12:58:35,239 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:35,240 INFO L225 Difference]: With dead ends: 97 [2018-01-24 12:58:35,240 INFO L226 Difference]: Without dead ends: 94 [2018-01-24 12:58:35,240 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 100 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 12:58:35,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-01-24 12:58:35,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 55. [2018-01-24 12:58:35,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-01-24 12:58:35,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 59 transitions. [2018-01-24 12:58:35,247 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 59 transitions. Word has length 27 [2018-01-24 12:58:35,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:35,247 INFO L432 AbstractCegarLoop]: Abstraction has 55 states and 59 transitions. [2018-01-24 12:58:35,247 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 12:58:35,247 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 59 transitions. [2018-01-24 12:58:35,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 12:58:35,248 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:35,249 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:35,249 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:35,249 INFO L82 PathProgramCache]: Analyzing trace with hash 155329936, now seen corresponding path program 2 times [2018-01-24 12:58:35,249 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:35,250 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:35,250 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:35,251 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:35,251 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:35,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:35,258 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:35,323 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:35,324 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:35,324 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:35,331 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:35,331 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:35,334 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:35,341 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:35,342 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:35,344 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:35,369 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:35,369 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:35,479 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:35,511 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:35,511 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:35,516 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:35,516 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:35,520 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:35,525 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:35,530 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:35,533 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:35,540 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:35,540 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:35,570 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (14)] Exception during sending of exit command (exit): Broken pipe [2018-01-24 12:58:35,577 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:35,577 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 14 [2018-01-24 12:58:35,577 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:35,578 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 12:58:35,578 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 12:58:35,578 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2018-01-24 12:58:35,578 INFO L87 Difference]: Start difference. First operand 55 states and 59 transitions. Second operand 9 states. [2018-01-24 12:58:35,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:35,753 INFO L93 Difference]: Finished difference Result 72 states and 78 transitions. [2018-01-24 12:58:35,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 12:58:35,753 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 32 [2018-01-24 12:58:35,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:35,754 INFO L225 Difference]: With dead ends: 72 [2018-01-24 12:58:35,754 INFO L226 Difference]: Without dead ends: 55 [2018-01-24 12:58:35,755 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 120 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 12:58:35,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-01-24 12:58:35,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2018-01-24 12:58:35,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-01-24 12:58:35,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 58 transitions. [2018-01-24 12:58:35,761 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 58 transitions. Word has length 32 [2018-01-24 12:58:35,761 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:35,761 INFO L432 AbstractCegarLoop]: Abstraction has 55 states and 58 transitions. [2018-01-24 12:58:35,761 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 12:58:35,761 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 58 transitions. [2018-01-24 12:58:35,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 12:58:35,762 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:35,762 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:35,763 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:35,763 INFO L82 PathProgramCache]: Analyzing trace with hash -1011667241, now seen corresponding path program 5 times [2018-01-24 12:58:35,763 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:35,764 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:35,764 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:35,764 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:35,764 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:35,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:35,771 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:35,882 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:35,883 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:35,883 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:35,888 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:35,889 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:35,892 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:35,893 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:35,894 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:35,895 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:35,896 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:35,898 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:35,898 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:35,900 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:35,915 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:35,915 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:35,987 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:36,007 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:36,007 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:36,010 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:36,010 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:36,013 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:36,015 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:36,019 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:36,024 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:36,032 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:36,043 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:36,049 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:36,052 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:36,059 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:36,059 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:36,069 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:36,071 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:36,071 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 12:58:36,071 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:36,071 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 12:58:36,072 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 12:58:36,072 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 12:58:36,072 INFO L87 Difference]: Start difference. First operand 55 states and 58 transitions. Second operand 8 states. [2018-01-24 12:58:36,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:36,145 INFO L93 Difference]: Finished difference Result 102 states and 109 transitions. [2018-01-24 12:58:36,145 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 12:58:36,145 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 32 [2018-01-24 12:58:36,146 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:36,147 INFO L225 Difference]: With dead ends: 102 [2018-01-24 12:58:36,147 INFO L226 Difference]: Without dead ends: 99 [2018-01-24 12:58:36,147 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 119 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 12:58:36,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-01-24 12:58:36,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 60. [2018-01-24 12:58:36,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 12:58:36,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 64 transitions. [2018-01-24 12:58:36,153 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 64 transitions. Word has length 32 [2018-01-24 12:58:36,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:36,153 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 64 transitions. [2018-01-24 12:58:36,153 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 12:58:36,153 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 64 transitions. [2018-01-24 12:58:36,154 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 12:58:36,154 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:36,154 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:36,154 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:36,154 INFO L82 PathProgramCache]: Analyzing trace with hash -903265867, now seen corresponding path program 3 times [2018-01-24 12:58:36,154 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:36,155 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:36,155 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:36,155 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:36,155 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:36,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:36,161 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:36,242 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:36,242 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:36,242 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:36,253 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:36,253 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:36,257 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:36,260 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:36,261 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:36,262 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:36,279 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 12:58:36,279 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:36,297 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 12:58:36,317 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:36,317 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:36,320 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:36,320 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:36,324 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:36,327 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:36,331 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:36,333 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:36,335 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 12:58:36,335 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:36,346 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 12:58:36,348 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:36,348 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 3, 3, 3, 3] total 12 [2018-01-24 12:58:36,348 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:36,348 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 12:58:36,349 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 12:58:36,349 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2018-01-24 12:58:36,349 INFO L87 Difference]: Start difference. First operand 60 states and 64 transitions. Second operand 11 states. [2018-01-24 12:58:36,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:36,448 INFO L93 Difference]: Finished difference Result 97 states and 113 transitions. [2018-01-24 12:58:36,448 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 12:58:36,448 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2018-01-24 12:58:36,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:36,449 INFO L225 Difference]: With dead ends: 97 [2018-01-24 12:58:36,449 INFO L226 Difference]: Without dead ends: 74 [2018-01-24 12:58:36,450 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-01-24 12:58:36,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-01-24 12:58:36,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 72. [2018-01-24 12:58:36,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-01-24 12:58:36,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 77 transitions. [2018-01-24 12:58:36,457 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 77 transitions. Word has length 37 [2018-01-24 12:58:36,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:36,457 INFO L432 AbstractCegarLoop]: Abstraction has 72 states and 77 transitions. [2018-01-24 12:58:36,457 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 12:58:36,458 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 77 transitions. [2018-01-24 12:58:36,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 12:58:36,460 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:36,460 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:36,460 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:36,460 INFO L82 PathProgramCache]: Analyzing trace with hash -2070263044, now seen corresponding path program 6 times [2018-01-24 12:58:36,460 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:36,461 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:36,461 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:36,461 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:36,461 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:36,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:36,468 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:36,579 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:36,579 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:36,580 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:36,586 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:36,586 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:36,589 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,591 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,592 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,593 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,594 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,595 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,596 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,597 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:36,598 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:36,610 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:36,610 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:36,690 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:36,710 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:36,710 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:36,713 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:36,713 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:36,716 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,717 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,721 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,724 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,730 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,736 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,745 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:36,749 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:36,751 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:36,757 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:36,758 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:36,765 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:36,766 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:36,766 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 12:58:36,766 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:36,766 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 12:58:36,767 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 12:58:36,767 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 12:58:36,767 INFO L87 Difference]: Start difference. First operand 72 states and 77 transitions. Second operand 9 states. [2018-01-24 12:58:36,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:36,870 INFO L93 Difference]: Finished difference Result 155 states and 170 transitions. [2018-01-24 12:58:36,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 12:58:36,870 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 37 [2018-01-24 12:58:36,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:36,871 INFO L225 Difference]: With dead ends: 155 [2018-01-24 12:58:36,871 INFO L226 Difference]: Without dead ends: 152 [2018-01-24 12:58:36,872 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 138 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 12:58:36,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-24 12:58:36,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 77. [2018-01-24 12:58:36,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-01-24 12:58:36,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 83 transitions. [2018-01-24 12:58:36,878 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 83 transitions. Word has length 37 [2018-01-24 12:58:36,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:36,879 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 83 transitions. [2018-01-24 12:58:36,879 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 12:58:36,879 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 83 transitions. [2018-01-24 12:58:36,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 12:58:36,879 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:36,879 INFO L322 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:36,880 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:36,880 INFO L82 PathProgramCache]: Analyzing trace with hash 1122500087, now seen corresponding path program 7 times [2018-01-24 12:58:36,880 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:36,880 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:36,881 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:36,881 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:36,881 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:36,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:36,886 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:36,986 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:36,986 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:36,986 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:37,000 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:37,001 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:37,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:37,011 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:37,023 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:37,023 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:37,135 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:37,155 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:37,155 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:37,158 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:37,158 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:37,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:37,171 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:37,178 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:37,179 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:37,193 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:37,195 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:37,195 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 12:58:37,195 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:37,195 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 12:58:37,195 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 12:58:37,196 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 12:58:37,196 INFO L87 Difference]: Start difference. First operand 77 states and 83 transitions. Second operand 10 states. [2018-01-24 12:58:37,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:37,364 INFO L93 Difference]: Finished difference Result 185 states and 204 transitions. [2018-01-24 12:58:37,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 12:58:37,365 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-01-24 12:58:37,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:37,366 INFO L225 Difference]: With dead ends: 185 [2018-01-24 12:58:37,366 INFO L226 Difference]: Without dead ends: 182 [2018-01-24 12:58:37,366 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 157 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 12:58:37,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-01-24 12:58:37,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 82. [2018-01-24 12:58:37,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-24 12:58:37,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 89 transitions. [2018-01-24 12:58:37,376 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 89 transitions. Word has length 42 [2018-01-24 12:58:37,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:37,376 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 89 transitions. [2018-01-24 12:58:37,376 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 12:58:37,377 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 89 transitions. [2018-01-24 12:58:37,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-01-24 12:58:37,377 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:37,377 INFO L322 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:37,377 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:37,377 INFO L82 PathProgramCache]: Analyzing trace with hash -676728868, now seen corresponding path program 8 times [2018-01-24 12:58:37,378 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:37,378 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:37,378 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:37,378 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:37,378 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:37,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:37,384 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:37,541 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:37,541 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:37,541 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:37,547 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:37,547 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:37,551 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:37,556 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:37,567 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:37,569 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:37,577 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:37,577 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:37,695 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:37,715 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:37,715 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:37,721 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:37,722 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:37,725 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:37,734 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:37,739 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:37,742 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:37,750 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:37,751 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:37,765 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:37,768 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:37,768 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 12:58:37,769 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:37,769 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 12:58:37,769 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 12:58:37,769 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 12:58:37,769 INFO L87 Difference]: Start difference. First operand 82 states and 89 transitions. Second operand 11 states. [2018-01-24 12:58:37,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:37,982 INFO L93 Difference]: Finished difference Result 215 states and 238 transitions. [2018-01-24 12:58:37,983 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 12:58:37,983 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 47 [2018-01-24 12:58:37,983 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:37,985 INFO L225 Difference]: With dead ends: 215 [2018-01-24 12:58:37,985 INFO L226 Difference]: Without dead ends: 212 [2018-01-24 12:58:37,985 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 176 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 12:58:37,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states. [2018-01-24 12:58:37,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 87. [2018-01-24 12:58:37,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-01-24 12:58:38,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 95 transitions. [2018-01-24 12:58:38,001 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 95 transitions. Word has length 47 [2018-01-24 12:58:38,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:38,002 INFO L432 AbstractCegarLoop]: Abstraction has 87 states and 95 transitions. [2018-01-24 12:58:38,002 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 12:58:38,002 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 95 transitions. [2018-01-24 12:58:38,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 12:58:38,003 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:38,003 INFO L322 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:38,003 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:38,003 INFO L82 PathProgramCache]: Analyzing trace with hash -633576169, now seen corresponding path program 9 times [2018-01-24 12:58:38,004 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:38,004 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:38,004 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:38,005 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:38,005 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:38,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:38,012 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:38,243 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:38,244 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:38,244 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:38,254 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:38,254 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:38,258 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,259 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,260 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,262 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,263 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,265 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,266 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,268 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,270 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,272 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,273 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:38,275 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:38,286 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:38,287 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:38,583 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:38,603 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:38,603 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:38,606 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:38,606 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:38,609 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,611 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,614 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,618 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,624 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,630 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,637 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,646 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,657 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,673 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:38,678 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:38,681 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:38,689 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:38,689 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:38,713 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:38,715 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:38,715 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 12:58:38,715 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:38,715 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 12:58:38,715 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 12:58:38,716 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 12:58:38,716 INFO L87 Difference]: Start difference. First operand 87 states and 95 transitions. Second operand 12 states. [2018-01-24 12:58:38,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:38,977 INFO L93 Difference]: Finished difference Result 245 states and 272 transitions. [2018-01-24 12:58:38,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 12:58:38,977 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 52 [2018-01-24 12:58:38,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:38,979 INFO L225 Difference]: With dead ends: 245 [2018-01-24 12:58:38,979 INFO L226 Difference]: Without dead ends: 242 [2018-01-24 12:58:38,980 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 195 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 12:58:38,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states. [2018-01-24 12:58:38,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 92. [2018-01-24 12:58:38,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-01-24 12:58:38,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 101 transitions. [2018-01-24 12:58:38,990 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 101 transitions. Word has length 52 [2018-01-24 12:58:38,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:38,990 INFO L432 AbstractCegarLoop]: Abstraction has 92 states and 101 transitions. [2018-01-24 12:58:38,990 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 12:58:38,990 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 101 transitions. [2018-01-24 12:58:38,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-01-24 12:58:38,991 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:38,991 INFO L322 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:38,991 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:38,991 INFO L82 PathProgramCache]: Analyzing trace with hash -1365705540, now seen corresponding path program 10 times [2018-01-24 12:58:38,991 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:38,992 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:38,992 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:38,992 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:38,992 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:38,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:38,999 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:39,107 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:39,107 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:39,108 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:39,114 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:39,114 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:39,124 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:39,125 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:39,136 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:39,136 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:39,355 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:39,379 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:39,379 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:39,383 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:39,383 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:39,416 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:39,419 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:39,434 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:39,435 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:39,447 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:39,449 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:39,449 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 12:58:39,449 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:39,449 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 12:58:39,449 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 12:58:39,450 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 12:58:39,450 INFO L87 Difference]: Start difference. First operand 92 states and 101 transitions. Second operand 13 states. [2018-01-24 12:58:39,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:39,699 INFO L93 Difference]: Finished difference Result 275 states and 306 transitions. [2018-01-24 12:58:39,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 12:58:39,700 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2018-01-24 12:58:39,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:39,701 INFO L225 Difference]: With dead ends: 275 [2018-01-24 12:58:39,701 INFO L226 Difference]: Without dead ends: 272 [2018-01-24 12:58:39,702 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 214 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 12:58:39,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2018-01-24 12:58:39,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 97. [2018-01-24 12:58:39,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-01-24 12:58:39,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 107 transitions. [2018-01-24 12:58:39,716 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 107 transitions. Word has length 57 [2018-01-24 12:58:39,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:39,716 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 107 transitions. [2018-01-24 12:58:39,717 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 12:58:39,717 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 107 transitions. [2018-01-24 12:58:39,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 12:58:39,718 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:39,718 INFO L322 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:39,718 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:39,718 INFO L82 PathProgramCache]: Analyzing trace with hash -1933470172, now seen corresponding path program 4 times [2018-01-24 12:58:39,718 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:39,719 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:39,719 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:39,719 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:39,719 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:39,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:39,728 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:39,841 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 10 proven. 59 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-01-24 12:58:39,842 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:39,842 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:39,847 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:39,847 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:39,856 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:39,857 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:39,880 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 12:58:39,881 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:39,951 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 12:58:39,973 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:39,973 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:39,976 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:39,976 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:40,001 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:40,004 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:40,033 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 12:58:40,033 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:40,048 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 12:58:40,050 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:40,050 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 5, 5, 5, 5] total 18 [2018-01-24 12:58:40,050 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:40,050 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 12:58:40,051 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 12:58:40,051 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=269, Unknown=0, NotChecked=0, Total=342 [2018-01-24 12:58:40,051 INFO L87 Difference]: Start difference. First operand 97 states and 107 transitions. Second operand 15 states. [2018-01-24 12:58:40,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:40,211 INFO L93 Difference]: Finished difference Result 134 states and 152 transitions. [2018-01-24 12:58:40,211 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 12:58:40,211 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 62 [2018-01-24 12:58:40,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:40,213 INFO L225 Difference]: With dead ends: 134 [2018-01-24 12:58:40,213 INFO L226 Difference]: Without dead ends: 105 [2018-01-24 12:58:40,213 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 260 GetRequests, 238 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 112 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=103, Invalid=359, Unknown=0, NotChecked=0, Total=462 [2018-01-24 12:58:40,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-01-24 12:58:40,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 103. [2018-01-24 12:58:40,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-01-24 12:58:40,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 113 transitions. [2018-01-24 12:58:40,224 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 113 transitions. Word has length 62 [2018-01-24 12:58:40,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:40,224 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 113 transitions. [2018-01-24 12:58:40,224 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 12:58:40,224 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 113 transitions. [2018-01-24 12:58:40,225 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 12:58:40,225 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:40,225 INFO L322 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:40,225 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:40,225 INFO L82 PathProgramCache]: Analyzing trace with hash -116235209, now seen corresponding path program 11 times [2018-01-24 12:58:40,226 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:40,226 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:40,226 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:40,227 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:40,227 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:40,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:40,234 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:40,408 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:40,408 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:40,408 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:40,415 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:40,415 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:40,418 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,420 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,421 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,422 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,424 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,428 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,429 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,436 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,441 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,445 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,447 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,453 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,455 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:40,457 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:40,470 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:40,470 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:40,764 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:40,798 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:40,799 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:40,801 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:40,801 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:40,804 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,806 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,810 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,814 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,819 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,826 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,833 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,845 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,858 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,872 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,888 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,908 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:40,914 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:40,917 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:40,928 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:40,929 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:40,939 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:40,940 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:40,940 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 12:58:40,940 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:40,941 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 12:58:40,941 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 12:58:40,941 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 12:58:40,941 INFO L87 Difference]: Start difference. First operand 103 states and 113 transitions. Second operand 14 states. [2018-01-24 12:58:41,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:41,233 INFO L93 Difference]: Finished difference Result 328 states and 367 transitions. [2018-01-24 12:58:41,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 12:58:41,234 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 62 [2018-01-24 12:58:41,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:41,236 INFO L225 Difference]: With dead ends: 328 [2018-01-24 12:58:41,236 INFO L226 Difference]: Without dead ends: 325 [2018-01-24 12:58:41,236 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 233 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 12:58:41,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2018-01-24 12:58:41,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 108. [2018-01-24 12:58:41,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-01-24 12:58:41,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 119 transitions. [2018-01-24 12:58:41,251 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 119 transitions. Word has length 62 [2018-01-24 12:58:41,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:41,252 INFO L432 AbstractCegarLoop]: Abstraction has 108 states and 119 transitions. [2018-01-24 12:58:41,252 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 12:58:41,252 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 119 transitions. [2018-01-24 12:58:41,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-01-24 12:58:41,253 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:41,253 INFO L322 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:41,253 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:41,253 INFO L82 PathProgramCache]: Analyzing trace with hash -414879332, now seen corresponding path program 12 times [2018-01-24 12:58:41,253 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:41,254 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:41,254 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:41,254 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:41,255 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:41,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:41,264 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:41,434 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:41,434 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:41,434 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:41,438 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:41,439 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:41,442 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,442 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,443 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,444 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,445 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,446 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,447 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,448 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,449 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,450 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,452 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,453 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,455 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,455 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:41,457 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:41,470 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:41,471 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:41,667 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:41,687 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:41,687 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 34 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:41,690 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:41,690 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:41,694 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,695 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,698 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,702 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,706 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,712 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,719 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,730 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,744 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,760 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,775 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,798 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,825 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:41,831 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:41,835 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:41,844 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:41,845 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:41,859 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:41,860 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:41,860 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 12:58:41,861 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:41,861 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 12:58:41,861 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 12:58:41,862 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 12:58:41,862 INFO L87 Difference]: Start difference. First operand 108 states and 119 transitions. Second operand 15 states. [2018-01-24 12:58:42,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:42,150 INFO L93 Difference]: Finished difference Result 364 states and 408 transitions. [2018-01-24 12:58:42,150 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 12:58:42,150 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 67 [2018-01-24 12:58:42,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:42,152 INFO L225 Difference]: With dead ends: 364 [2018-01-24 12:58:42,152 INFO L226 Difference]: Without dead ends: 361 [2018-01-24 12:58:42,152 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 280 GetRequests, 252 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 12:58:42,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 361 states. [2018-01-24 12:58:42,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 361 to 113. [2018-01-24 12:58:42,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-01-24 12:58:42,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 125 transitions. [2018-01-24 12:58:42,166 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 125 transitions. Word has length 67 [2018-01-24 12:58:42,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:42,166 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 125 transitions. [2018-01-24 12:58:42,166 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 12:58:42,166 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 125 transitions. [2018-01-24 12:58:42,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-01-24 12:58:42,167 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:42,167 INFO L322 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:42,167 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:42,167 INFO L82 PathProgramCache]: Analyzing trace with hash -1135871145, now seen corresponding path program 13 times [2018-01-24 12:58:42,167 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:42,168 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:42,168 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:42,168 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:42,168 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:42,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:42,175 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:42,358 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:42,358 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:42,358 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:42,363 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:42,363 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:42,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:42,376 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:42,387 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:42,387 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:42,663 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:42,683 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:42,683 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 36 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:42,686 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:42,687 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:42,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:42,709 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:42,727 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:42,728 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:42,746 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:42,748 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:42,748 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 29 [2018-01-24 12:58:42,748 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:42,749 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 12:58:42,749 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 12:58:42,749 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 12:58:42,749 INFO L87 Difference]: Start difference. First operand 113 states and 125 transitions. Second operand 16 states. [2018-01-24 12:58:43,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:43,186 INFO L93 Difference]: Finished difference Result 400 states and 449 transitions. [2018-01-24 12:58:43,223 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 12:58:43,224 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2018-01-24 12:58:43,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:43,225 INFO L225 Difference]: With dead ends: 400 [2018-01-24 12:58:43,225 INFO L226 Difference]: Without dead ends: 397 [2018-01-24 12:58:43,226 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 301 GetRequests, 271 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 12:58:43,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 397 states. [2018-01-24 12:58:43,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 397 to 118. [2018-01-24 12:58:43,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-24 12:58:43,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 131 transitions. [2018-01-24 12:58:43,237 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 131 transitions. Word has length 72 [2018-01-24 12:58:43,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:43,237 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 131 transitions. [2018-01-24 12:58:43,237 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 12:58:43,237 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 131 transitions. [2018-01-24 12:58:43,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-01-24 12:58:43,238 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:43,238 INFO L322 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:43,238 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:43,238 INFO L82 PathProgramCache]: Analyzing trace with hash 1226682691, now seen corresponding path program 5 times [2018-01-24 12:58:43,238 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:43,239 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:43,239 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:43,239 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:43,239 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:43,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:43,246 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:43,352 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 24 proven. 89 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 12:58:43,352 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:43,352 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:43,358 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:43,358 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:43,361 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,363 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,365 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,368 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,370 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,373 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,373 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:43,375 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:43,411 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 12:58:43,412 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:43,472 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 12:58:43,492 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:43,492 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 38 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:43,495 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:43,495 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:43,498 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,502 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,509 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,517 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,528 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,545 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,553 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:43,556 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:43,565 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 12:58:43,565 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:43,579 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 12:58:43,580 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:43,580 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 6, 6, 6, 6] total 22 [2018-01-24 12:58:43,580 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:43,581 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 12:58:43,581 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 12:58:43,581 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=406, Unknown=0, NotChecked=0, Total=506 [2018-01-24 12:58:43,581 INFO L87 Difference]: Start difference. First operand 118 states and 131 transitions. Second operand 18 states. [2018-01-24 12:58:43,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:43,734 INFO L93 Difference]: Finished difference Result 161 states and 183 transitions. [2018-01-24 12:58:43,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 12:58:43,734 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 77 [2018-01-24 12:58:43,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:43,735 INFO L225 Difference]: With dead ends: 161 [2018-01-24 12:58:43,735 INFO L226 Difference]: Without dead ends: 126 [2018-01-24 12:58:43,736 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 323 GetRequests, 296 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 169 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=146, Invalid=556, Unknown=0, NotChecked=0, Total=702 [2018-01-24 12:58:43,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-01-24 12:58:43,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 124. [2018-01-24 12:58:43,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-01-24 12:58:43,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 137 transitions. [2018-01-24 12:58:43,746 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 137 transitions. Word has length 77 [2018-01-24 12:58:43,746 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:43,746 INFO L432 AbstractCegarLoop]: Abstraction has 124 states and 137 transitions. [2018-01-24 12:58:43,746 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 12:58:43,746 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 137 transitions. [2018-01-24 12:58:43,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-01-24 12:58:43,746 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:43,747 INFO L322 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:43,747 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:43,747 INFO L82 PathProgramCache]: Analyzing trace with hash 571297404, now seen corresponding path program 14 times [2018-01-24 12:58:43,747 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:43,747 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:43,747 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:43,747 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:43,748 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:43,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:43,754 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:43,935 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:43,935 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:43,935 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:43,940 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:43,940 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:43,943 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,948 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:43,949 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:43,951 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:43,966 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:43,966 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:44,244 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:44,264 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:44,264 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 40 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:44,267 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:44,267 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:44,271 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:44,280 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:44,288 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:44,291 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:44,305 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:44,305 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:44,319 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:44,320 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:44,320 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 31 [2018-01-24 12:58:44,320 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:44,320 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 12:58:44,321 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 12:58:44,321 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 12:58:44,321 INFO L87 Difference]: Start difference. First operand 124 states and 137 transitions. Second operand 17 states. [2018-01-24 12:58:44,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:44,883 INFO L93 Difference]: Finished difference Result 465 states and 524 transitions. [2018-01-24 12:58:44,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 12:58:44,884 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 77 [2018-01-24 12:58:44,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:44,887 INFO L225 Difference]: With dead ends: 465 [2018-01-24 12:58:44,887 INFO L226 Difference]: Without dead ends: 462 [2018-01-24 12:58:44,888 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 322 GetRequests, 290 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 12:58:44,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-01-24 12:58:44,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 129. [2018-01-24 12:58:44,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-01-24 12:58:44,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 143 transitions. [2018-01-24 12:58:44,909 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 143 transitions. Word has length 77 [2018-01-24 12:58:44,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:44,909 INFO L432 AbstractCegarLoop]: Abstraction has 129 states and 143 transitions. [2018-01-24 12:58:44,910 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 12:58:44,910 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 143 transitions. [2018-01-24 12:58:44,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-01-24 12:58:44,911 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:44,911 INFO L322 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:44,911 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:44,911 INFO L82 PathProgramCache]: Analyzing trace with hash 239807095, now seen corresponding path program 15 times [2018-01-24 12:58:44,911 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:44,912 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:44,912 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:44,912 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:44,912 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:44,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:44,920 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:45,423 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:45,423 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:45,423 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:45,431 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:45,431 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:45,435 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,436 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,437 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,438 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,439 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,443 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,445 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,450 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,456 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,458 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,464 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,466 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,470 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,473 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,476 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,480 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,488 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:45,490 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:45,509 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:45,509 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:45,860 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:45,891 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:45,892 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 42 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:45,895 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:45,895 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:45,899 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,901 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,906 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,911 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,919 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,927 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,934 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,943 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,954 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,969 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:45,988 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,008 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,031 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,059 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,100 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,147 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:46,156 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:46,160 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:46,176 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:46,177 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:46,204 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:46,206 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:46,206 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 33 [2018-01-24 12:58:46,206 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:46,206 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 12:58:46,207 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 12:58:46,207 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 12:58:46,207 INFO L87 Difference]: Start difference. First operand 129 states and 143 transitions. Second operand 18 states. [2018-01-24 12:58:46,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:46,973 INFO L93 Difference]: Finished difference Result 507 states and 572 transitions. [2018-01-24 12:58:46,974 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 12:58:46,974 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 82 [2018-01-24 12:58:46,974 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:46,976 INFO L225 Difference]: With dead ends: 507 [2018-01-24 12:58:46,976 INFO L226 Difference]: Without dead ends: 504 [2018-01-24 12:58:46,977 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 309 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 12:58:46,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states. [2018-01-24 12:58:46,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 134. [2018-01-24 12:58:46,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-24 12:58:46,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 149 transitions. [2018-01-24 12:58:46,998 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 149 transitions. Word has length 82 [2018-01-24 12:58:46,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:46,998 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 149 transitions. [2018-01-24 12:58:46,998 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 12:58:46,999 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 149 transitions. [2018-01-24 12:58:46,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 12:58:46,999 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:47,000 INFO L322 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:47,000 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:47,000 INFO L82 PathProgramCache]: Analyzing trace with hash -1580297380, now seen corresponding path program 16 times [2018-01-24 12:58:47,000 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:47,001 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:47,001 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:47,001 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:47,001 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:47,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:47,008 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:47,393 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:47,394 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:47,394 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:47,400 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:47,401 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:47,417 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:47,420 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:47,438 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:47,438 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:47,823 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:47,844 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:47,844 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 44 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:47,847 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:47,847 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:47,916 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:47,920 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:47,934 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:47,934 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:47,954 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:47,956 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:47,956 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 35 [2018-01-24 12:58:47,956 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:47,957 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 12:58:47,957 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 12:58:47,957 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 12:58:47,958 INFO L87 Difference]: Start difference. First operand 134 states and 149 transitions. Second operand 19 states. [2018-01-24 12:58:48,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:48,509 INFO L93 Difference]: Finished difference Result 549 states and 620 transitions. [2018-01-24 12:58:48,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 12:58:48,509 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 87 [2018-01-24 12:58:48,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:48,511 INFO L225 Difference]: With dead ends: 549 [2018-01-24 12:58:48,511 INFO L226 Difference]: Without dead ends: 546 [2018-01-24 12:58:48,512 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 364 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 12:58:48,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states. [2018-01-24 12:58:48,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 139. [2018-01-24 12:58:48,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-01-24 12:58:48,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 155 transitions. [2018-01-24 12:58:48,529 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 155 transitions. Word has length 87 [2018-01-24 12:58:48,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:48,529 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 155 transitions. [2018-01-24 12:58:48,529 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 12:58:48,529 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 155 transitions. [2018-01-24 12:58:48,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 12:58:48,530 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:48,530 INFO L322 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:48,530 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:48,530 INFO L82 PathProgramCache]: Analyzing trace with hash 677887160, now seen corresponding path program 6 times [2018-01-24 12:58:48,530 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:48,531 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:48,531 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:48,531 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:48,531 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:48,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:48,539 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:49,098 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 44 proven. 124 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-01-24 12:58:49,098 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:49,099 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:49,110 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:49,110 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:49,115 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:49,124 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:49,133 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:49,148 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:49,162 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:49,177 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:49,188 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:49,201 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:49,203 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:49,510 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 12:58:49,510 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:49,986 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 12:58:50,013 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:50,013 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 46 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:50,017 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:50,017 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:50,022 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:50,024 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:50,030 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:50,039 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:50,050 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:50,066 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:50,098 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:50,113 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:50,117 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:50,133 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 12:58:50,133 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:50,150 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 12:58:50,151 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:50,151 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 7, 7, 7, 7] total 26 [2018-01-24 12:58:50,151 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:50,152 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 12:58:50,152 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 12:58:50,152 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=571, Unknown=0, NotChecked=0, Total=702 [2018-01-24 12:58:50,152 INFO L87 Difference]: Start difference. First operand 139 states and 155 transitions. Second operand 21 states. [2018-01-24 12:58:50,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:50,356 INFO L93 Difference]: Finished difference Result 188 states and 214 transitions. [2018-01-24 12:58:50,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 12:58:50,356 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 92 [2018-01-24 12:58:50,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:50,358 INFO L225 Difference]: With dead ends: 188 [2018-01-24 12:58:50,358 INFO L226 Difference]: Without dead ends: 147 [2018-01-24 12:58:50,359 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 386 GetRequests, 354 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 238 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=196, Invalid=796, Unknown=0, NotChecked=0, Total=992 [2018-01-24 12:58:50,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-01-24 12:58:50,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 145. [2018-01-24 12:58:50,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-01-24 12:58:50,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 161 transitions. [2018-01-24 12:58:50,381 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 161 transitions. Word has length 92 [2018-01-24 12:58:50,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:50,381 INFO L432 AbstractCegarLoop]: Abstraction has 145 states and 161 transitions. [2018-01-24 12:58:50,381 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 12:58:50,381 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 161 transitions. [2018-01-24 12:58:50,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 12:58:50,382 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:50,383 INFO L322 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:50,383 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:50,383 INFO L82 PathProgramCache]: Analyzing trace with hash -957222505, now seen corresponding path program 17 times [2018-01-24 12:58:50,383 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:50,384 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:50,384 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:50,384 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:50,384 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:50,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:50,392 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:50,630 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:50,630 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:50,630 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:50,636 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:50,636 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:50,639 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,642 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,643 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,644 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,645 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,646 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,648 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,649 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,651 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,656 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,662 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,668 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,671 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,674 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,677 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,681 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,685 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,690 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,691 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:50,694 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:50,714 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:50,714 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:51,139 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,159 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:51,160 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 48 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:51,162 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:51,163 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:51,166 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,168 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,173 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,178 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,184 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,191 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,199 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,210 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,225 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,243 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,260 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,281 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,305 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,343 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,387 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,424 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,467 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,518 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,531 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:51,535 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:51,558 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,558 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:51,580 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,582 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:51,582 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 37 [2018-01-24 12:58:51,582 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:51,582 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 12:58:51,583 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 12:58:51,583 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 12:58:51,583 INFO L87 Difference]: Start difference. First operand 145 states and 161 transitions. Second operand 20 states. [2018-01-24 12:58:52,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:52,150 INFO L93 Difference]: Finished difference Result 626 states and 709 transitions. [2018-01-24 12:58:52,151 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 12:58:52,151 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 92 [2018-01-24 12:58:52,151 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:52,154 INFO L225 Difference]: With dead ends: 626 [2018-01-24 12:58:52,154 INFO L226 Difference]: Without dead ends: 623 [2018-01-24 12:58:52,155 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 385 GetRequests, 347 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 12:58:52,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 623 states. [2018-01-24 12:58:52,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 623 to 150. [2018-01-24 12:58:52,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-01-24 12:58:52,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 167 transitions. [2018-01-24 12:58:52,186 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 167 transitions. Word has length 92 [2018-01-24 12:58:52,187 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:52,187 INFO L432 AbstractCegarLoop]: Abstraction has 150 states and 167 transitions. [2018-01-24 12:58:52,187 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 12:58:52,187 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 167 transitions. [2018-01-24 12:58:52,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-01-24 12:58:52,188 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:52,188 INFO L322 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:52,188 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:52,188 INFO L82 PathProgramCache]: Analyzing trace with hash 736575548, now seen corresponding path program 18 times [2018-01-24 12:58:52,188 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:52,189 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:52,189 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:52,189 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:52,190 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:52,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:52,198 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:52,500 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:52,501 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:52,501 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:52,508 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:52,508 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:52,511 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,512 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,513 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,514 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,515 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,515 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,516 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,518 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,519 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,520 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,521 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,523 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,524 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,525 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,527 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,529 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,531 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,533 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,536 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,536 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:52,539 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:52,557 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:52,557 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:53,091 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:53,112 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:53,112 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 50 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:53,114 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:53,115 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:53,118 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,120 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,123 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,127 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,132 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,137 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,144 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,153 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,168 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,184 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,205 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,226 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,247 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,272 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,300 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,333 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,371 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,418 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,534 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:53,547 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:53,551 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:53,567 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:53,567 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:53,593 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:53,594 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:53,594 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 39 [2018-01-24 12:58:53,595 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:53,595 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 12:58:53,595 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 12:58:53,596 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 12:58:53,596 INFO L87 Difference]: Start difference. First operand 150 states and 167 transitions. Second operand 21 states. [2018-01-24 12:58:54,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:54,243 INFO L93 Difference]: Finished difference Result 674 states and 764 transitions. [2018-01-24 12:58:54,243 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 12:58:54,243 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 97 [2018-01-24 12:58:54,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:54,246 INFO L225 Difference]: With dead ends: 674 [2018-01-24 12:58:54,246 INFO L226 Difference]: Without dead ends: 671 [2018-01-24 12:58:54,247 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 406 GetRequests, 366 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 12:58:54,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 671 states. [2018-01-24 12:58:54,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 671 to 155. [2018-01-24 12:58:54,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 155 states. [2018-01-24 12:58:54,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 173 transitions. [2018-01-24 12:58:54,282 INFO L78 Accepts]: Start accepts. Automaton has 155 states and 173 transitions. Word has length 97 [2018-01-24 12:58:54,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:54,282 INFO L432 AbstractCegarLoop]: Abstraction has 155 states and 173 transitions. [2018-01-24 12:58:54,282 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 12:58:54,282 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 173 transitions. [2018-01-24 12:58:54,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-24 12:58:54,283 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:54,283 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:54,283 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:54,284 INFO L82 PathProgramCache]: Analyzing trace with hash -891985897, now seen corresponding path program 7 times [2018-01-24 12:58:54,284 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:54,284 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:54,285 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:54,285 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:54,285 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:54,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:54,295 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:54,488 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 70 proven. 164 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 12:58:54,488 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:54,488 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:54,493 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:54,493 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:54,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:54,508 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:54,699 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 12:58:54,699 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:54,867 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 12:58:54,888 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:54,888 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 52 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:54,892 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:54,892 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:54,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:54,929 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:54,998 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 12:58:54,999 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:55,019 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 12:58:55,020 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:55,020 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 8, 8, 8, 8] total 30 [2018-01-24 12:58:55,020 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:55,021 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 12:58:55,021 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 12:58:55,021 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=764, Unknown=0, NotChecked=0, Total=930 [2018-01-24 12:58:55,021 INFO L87 Difference]: Start difference. First operand 155 states and 173 transitions. Second operand 24 states. [2018-01-24 12:58:55,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:55,292 INFO L93 Difference]: Finished difference Result 210 states and 239 transitions. [2018-01-24 12:58:55,292 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 12:58:55,292 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 107 [2018-01-24 12:58:55,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:55,293 INFO L225 Difference]: With dead ends: 210 [2018-01-24 12:58:55,293 INFO L226 Difference]: Without dead ends: 163 [2018-01-24 12:58:55,293 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 449 GetRequests, 412 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 319 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=253, Invalid=1079, Unknown=0, NotChecked=0, Total=1332 [2018-01-24 12:58:55,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-01-24 12:58:55,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 161. [2018-01-24 12:58:55,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 161 states. [2018-01-24 12:58:55,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 179 transitions. [2018-01-24 12:58:55,323 INFO L78 Accepts]: Start accepts. Automaton has 161 states and 179 transitions. Word has length 107 [2018-01-24 12:58:55,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:55,323 INFO L432 AbstractCegarLoop]: Abstraction has 161 states and 179 transitions. [2018-01-24 12:58:55,323 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 12:58:55,323 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 179 transitions. [2018-01-24 12:58:55,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-24 12:58:55,324 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:55,324 INFO L322 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:55,324 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:55,325 INFO L82 PathProgramCache]: Analyzing trace with hash -878554953, now seen corresponding path program 19 times [2018-01-24 12:58:55,325 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:55,325 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:55,326 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:55,326 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:55,326 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:55,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:55,334 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:55,659 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:55,659 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:55,659 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:55,664 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:55,664 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:55,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:55,677 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:55,695 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:55,695 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:56,136 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:56,157 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:56,157 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 54 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:56,160 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:56,160 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:56,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:56,186 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:56,209 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:56,210 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:56,229 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:56,230 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:56,231 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 41 [2018-01-24 12:58:56,231 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:56,231 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 12:58:56,231 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 12:58:56,231 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 12:58:56,232 INFO L87 Difference]: Start difference. First operand 161 states and 179 transitions. Second operand 22 states. [2018-01-24 12:58:56,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:56,914 INFO L93 Difference]: Finished difference Result 757 states and 860 transitions. [2018-01-24 12:58:56,914 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 12:58:56,914 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 102 [2018-01-24 12:58:56,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:56,916 INFO L225 Difference]: With dead ends: 757 [2018-01-24 12:58:56,916 INFO L226 Difference]: Without dead ends: 754 [2018-01-24 12:58:56,917 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 427 GetRequests, 385 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 12:58:56,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 754 states. [2018-01-24 12:58:56,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 754 to 166. [2018-01-24 12:58:56,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-01-24 12:58:56,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 185 transitions. [2018-01-24 12:58:56,956 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 185 transitions. Word has length 102 [2018-01-24 12:58:56,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:56,956 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 185 transitions. [2018-01-24 12:58:56,956 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 12:58:56,956 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 185 transitions. [2018-01-24 12:58:56,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-24 12:58:56,957 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:56,957 INFO L322 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:56,957 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:56,957 INFO L82 PathProgramCache]: Analyzing trace with hash -399157988, now seen corresponding path program 20 times [2018-01-24 12:58:56,957 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:56,958 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:56,958 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:56,958 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:56,958 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:56,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:56,965 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:57,315 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:57,316 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:57,316 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:57,320 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:57,320 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:57,324 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:57,332 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:57,333 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:57,336 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:57,354 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:57,354 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:57,863 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:57,882 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:57,882 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 56 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:57,885 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:57,885 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:57,891 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:57,909 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:57,919 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:57,924 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:57,967 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:57,968 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:58,002 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:58,003 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:58,004 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 43 [2018-01-24 12:58:58,004 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:58,004 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 12:58:58,004 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 12:58:58,005 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 12:58:58,005 INFO L87 Difference]: Start difference. First operand 166 states and 185 transitions. Second operand 23 states. [2018-01-24 12:58:58,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:58,872 INFO L93 Difference]: Finished difference Result 811 states and 922 transitions. [2018-01-24 12:58:58,873 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 12:58:58,873 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 107 [2018-01-24 12:58:58,873 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:58,875 INFO L225 Difference]: With dead ends: 811 [2018-01-24 12:58:58,875 INFO L226 Difference]: Without dead ends: 808 [2018-01-24 12:58:58,876 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 404 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 12:58:58,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 808 states. [2018-01-24 12:58:58,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 808 to 171. [2018-01-24 12:58:58,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-01-24 12:58:58,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 191 transitions. [2018-01-24 12:58:58,920 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 191 transitions. Word has length 107 [2018-01-24 12:58:58,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:58,921 INFO L432 AbstractCegarLoop]: Abstraction has 171 states and 191 transitions. [2018-01-24 12:58:58,921 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 12:58:58,921 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 191 transitions. [2018-01-24 12:58:58,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-01-24 12:58:58,922 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:58,922 INFO L322 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:58,922 INFO L371 AbstractCegarLoop]: === Iteration 31 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:58,923 INFO L82 PathProgramCache]: Analyzing trace with hash 792610775, now seen corresponding path program 21 times [2018-01-24 12:58:58,923 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:58,923 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:58,924 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:58,924 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:58,924 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:58,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:58,933 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:59,416 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:59,416 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:59,416 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:59,423 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:59,423 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:59,427 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,428 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,429 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,430 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,431 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,432 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,433 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,435 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,436 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,438 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,440 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,443 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,446 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,449 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,452 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,456 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,459 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,463 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,468 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,474 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,480 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,485 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:59,485 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:59,488 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:59,518 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:59,518 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:00,079 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:00,099 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:00,099 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 58 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:00,102 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:00,102 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:00,107 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,108 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,111 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,115 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,121 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,135 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,144 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,155 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,170 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,189 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,209 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,232 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,261 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,302 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,350 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,396 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,450 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,511 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,597 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,693 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,786 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:00,799 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:00,803 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:00,825 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:00,826 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:00,849 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:00,851 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:00,851 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 45 [2018-01-24 12:59:00,851 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:00,851 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 12:59:00,851 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 12:59:00,852 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 12:59:00,852 INFO L87 Difference]: Start difference. First operand 171 states and 191 transitions. Second operand 24 states. [2018-01-24 12:59:01,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:01,734 INFO L93 Difference]: Finished difference Result 865 states and 984 transitions. [2018-01-24 12:59:01,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 12:59:01,735 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 112 [2018-01-24 12:59:01,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:01,737 INFO L225 Difference]: With dead ends: 865 [2018-01-24 12:59:01,737 INFO L226 Difference]: Without dead ends: 862 [2018-01-24 12:59:01,738 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 423 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 12:59:01,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 862 states. [2018-01-24 12:59:01,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 862 to 176. [2018-01-24 12:59:01,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-01-24 12:59:01,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 197 transitions. [2018-01-24 12:59:01,787 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 197 transitions. Word has length 112 [2018-01-24 12:59:01,787 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:01,787 INFO L432 AbstractCegarLoop]: Abstraction has 176 states and 197 transitions. [2018-01-24 12:59:01,788 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 12:59:01,788 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 197 transitions. [2018-01-24 12:59:01,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-24 12:59:01,789 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:01,789 INFO L322 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:01,789 INFO L371 AbstractCegarLoop]: === Iteration 32 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:01,789 INFO L82 PathProgramCache]: Analyzing trace with hash -600860340, now seen corresponding path program 8 times [2018-01-24 12:59:01,789 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:01,790 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:01,790 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:01,790 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:01,790 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:01,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:01,801 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:01,982 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 102 proven. 209 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-01-24 12:59:01,982 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:01,982 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:01,986 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:01,987 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:01,991 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:01,999 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:02,001 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:02,003 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:02,074 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 0 proven. 147 refuted. 0 times theorem prover too weak. 248 trivial. 0 not checked. [2018-01-24 12:59:02,074 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:02,210 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 0 proven. 147 refuted. 0 times theorem prover too weak. 248 trivial. 0 not checked. [2018-01-24 12:59:02,229 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:02,229 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 60 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:02,232 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:02,232 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:02,237 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:02,254 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:02,267 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:02,271 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:02,304 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 140 proven. 171 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-01-24 12:59:02,304 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:02,987 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 126 proven. 185 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-01-24 12:59:02,988 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:02,988 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 9, 9, 19, 19] total 52 [2018-01-24 12:59:02,988 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:02,988 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 12:59:02,989 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 12:59:02,989 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=550, Invalid=2206, Unknown=0, NotChecked=0, Total=2756 [2018-01-24 12:59:02,989 INFO L87 Difference]: Start difference. First operand 176 states and 197 transitions. Second operand 27 states. [2018-01-24 12:59:03,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:03,303 INFO L93 Difference]: Finished difference Result 237 states and 270 transitions. [2018-01-24 12:59:03,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 12:59:03,303 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 122 [2018-01-24 12:59:03,304 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:03,304 INFO L225 Difference]: With dead ends: 237 [2018-01-24 12:59:03,304 INFO L226 Difference]: Without dead ends: 184 [2018-01-24 12:59:03,305 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 512 GetRequests, 453 SyntacticMatches, 1 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 951 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=788, Invalid=2752, Unknown=0, NotChecked=0, Total=3540 [2018-01-24 12:59:03,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-01-24 12:59:03,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 182. [2018-01-24 12:59:03,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-24 12:59:03,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 203 transitions. [2018-01-24 12:59:03,334 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 203 transitions. Word has length 122 [2018-01-24 12:59:03,334 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:03,334 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 203 transitions. [2018-01-24 12:59:03,334 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 12:59:03,334 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 203 transitions. [2018-01-24 12:59:03,335 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-01-24 12:59:03,335 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:03,335 INFO L322 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:03,335 INFO L371 AbstractCegarLoop]: === Iteration 33 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:03,335 INFO L82 PathProgramCache]: Analyzing trace with hash 1092014588, now seen corresponding path program 22 times [2018-01-24 12:59:03,335 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:03,336 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:03,336 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:03,336 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:03,336 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:03,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:03,344 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:03,739 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:03,740 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:03,771 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:03,785 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:59:03,786 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:59:03,813 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:03,816 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:03,853 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:03,854 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:04,414 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:04,434 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:04,434 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 62 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:04,437 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:59:04,437 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:59:04,555 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:04,559 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:04,580 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:04,580 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:04,605 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:04,606 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:04,606 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 47 [2018-01-24 12:59:04,606 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:04,607 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 12:59:04,607 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 12:59:04,607 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 12:59:04,607 INFO L87 Difference]: Start difference. First operand 182 states and 203 transitions. Second operand 25 states. [2018-01-24 12:59:05,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:05,569 INFO L93 Difference]: Finished difference Result 960 states and 1094 transitions. [2018-01-24 12:59:05,570 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 12:59:05,570 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 117 [2018-01-24 12:59:05,570 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:05,572 INFO L225 Difference]: With dead ends: 960 [2018-01-24 12:59:05,573 INFO L226 Difference]: Without dead ends: 957 [2018-01-24 12:59:05,573 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 442 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 12:59:05,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957 states. [2018-01-24 12:59:05,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 957 to 187. [2018-01-24 12:59:05,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-01-24 12:59:05,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 209 transitions. [2018-01-24 12:59:05,606 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 209 transitions. Word has length 117 [2018-01-24 12:59:05,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:05,606 INFO L432 AbstractCegarLoop]: Abstraction has 187 states and 209 transitions. [2018-01-24 12:59:05,606 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 12:59:05,606 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 209 transitions. [2018-01-24 12:59:05,607 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-24 12:59:05,607 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:05,607 INFO L322 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:05,607 INFO L371 AbstractCegarLoop]: === Iteration 34 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:05,607 INFO L82 PathProgramCache]: Analyzing trace with hash 1378342647, now seen corresponding path program 23 times [2018-01-24 12:59:05,607 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:05,608 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:05,608 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:05,608 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:05,608 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:05,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:05,614 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:06,299 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:06,299 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:06,299 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:06,304 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:59:06,304 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:06,308 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,309 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,315 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,316 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,318 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,320 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,327 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,329 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,331 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,334 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,338 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,341 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,345 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,351 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,355 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,361 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,366 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,373 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,380 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,387 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,393 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,400 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,411 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,420 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:06,421 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:06,423 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:06,445 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:06,445 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:07,067 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:07,087 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:07,087 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 64 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:07,090 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:59:07,090 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:07,094 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,095 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,099 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,103 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,108 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,116 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,123 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,133 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,144 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,160 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,179 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,198 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,220 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,247 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,288 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,336 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,377 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,423 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,476 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,560 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,663 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,740 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,824 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,918 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:07,941 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:07,945 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:07,975 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:07,975 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:08,005 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:08,006 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:08,007 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 49 [2018-01-24 12:59:08,007 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:08,007 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 12:59:08,007 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 12:59:08,008 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 12:59:08,008 INFO L87 Difference]: Start difference. First operand 187 states and 209 transitions. Second operand 26 states. [2018-01-24 12:59:09,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:09,123 INFO L93 Difference]: Finished difference Result 1020 states and 1163 transitions. [2018-01-24 12:59:09,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 12:59:09,124 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 122 [2018-01-24 12:59:09,124 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:09,127 INFO L225 Difference]: With dead ends: 1020 [2018-01-24 12:59:09,127 INFO L226 Difference]: Without dead ends: 1017 [2018-01-24 12:59:09,127 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 511 GetRequests, 461 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 12:59:09,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1017 states. [2018-01-24 12:59:09,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1017 to 192. [2018-01-24 12:59:09,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192 states. [2018-01-24 12:59:09,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 215 transitions. [2018-01-24 12:59:09,161 INFO L78 Accepts]: Start accepts. Automaton has 192 states and 215 transitions. Word has length 122 [2018-01-24 12:59:09,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:09,162 INFO L432 AbstractCegarLoop]: Abstraction has 192 states and 215 transitions. [2018-01-24 12:59:09,162 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 12:59:09,162 INFO L276 IsEmpty]: Start isEmpty. Operand 192 states and 215 transitions. [2018-01-24 12:59:09,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-01-24 12:59:09,162 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:09,163 INFO L322 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:09,163 INFO L371 AbstractCegarLoop]: === Iteration 35 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:09,163 INFO L82 PathProgramCache]: Analyzing trace with hash -1016482084, now seen corresponding path program 24 times [2018-01-24 12:59:09,163 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:09,163 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:09,164 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:09,164 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:09,164 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:09,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:09,171 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:09,546 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:09,546 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:09,546 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:09,553 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:59:09,553 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:59:09,557 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,560 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,562 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,568 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,570 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,583 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,584 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,586 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,591 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,592 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,601 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,603 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,605 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,607 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,609 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,612 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,615 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,618 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,621 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,624 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,628 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,633 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,637 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,641 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,645 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:09,646 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:09,648 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:09,677 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:09,678 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:10,338 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:10,358 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:10,359 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 66 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:10,361 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:59:10,362 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:59:10,366 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,368 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,372 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,376 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,381 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,386 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,393 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,403 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,414 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,428 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,448 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,469 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,495 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,524 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,553 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,585 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,624 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,672 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,730 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,796 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:10,893 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:11,110 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:11,338 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:11,597 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:11,832 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:11,849 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:11,855 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:11,878 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:11,878 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:11,909 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:11,910 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:11,911 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 51 [2018-01-24 12:59:11,911 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:11,911 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 12:59:11,911 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 12:59:11,912 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 12:59:11,912 INFO L87 Difference]: Start difference. First operand 192 states and 215 transitions. Second operand 27 states. [2018-01-24 12:59:13,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:13,465 INFO L93 Difference]: Finished difference Result 1080 states and 1232 transitions. [2018-01-24 12:59:13,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 12:59:13,466 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 127 [2018-01-24 12:59:13,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:13,469 INFO L225 Difference]: With dead ends: 1080 [2018-01-24 12:59:13,469 INFO L226 Difference]: Without dead ends: 1077 [2018-01-24 12:59:13,470 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 532 GetRequests, 480 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 12:59:13,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1077 states. [2018-01-24 12:59:13,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1077 to 197. [2018-01-24 12:59:13,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-01-24 12:59:13,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 221 transitions. [2018-01-24 12:59:13,513 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 221 transitions. Word has length 127 [2018-01-24 12:59:13,513 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:13,513 INFO L432 AbstractCegarLoop]: Abstraction has 197 states and 221 transitions. [2018-01-24 12:59:13,513 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 12:59:13,513 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 221 transitions. [2018-01-24 12:59:13,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-01-24 12:59:13,514 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:13,514 INFO L322 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:13,514 INFO L371 AbstractCegarLoop]: === Iteration 36 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:13,514 INFO L82 PathProgramCache]: Analyzing trace with hash 795448555, now seen corresponding path program 9 times [2018-01-24 12:59:13,514 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:13,515 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:13,515 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:13,515 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:13,515 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:13,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:13,523 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:13,939 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 140 proven. 259 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-01-24 12:59:13,939 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:13,939 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:13,944 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:13,944 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:13,949 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,951 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,953 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,956 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,958 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,961 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,966 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,970 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,974 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,975 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:13,978 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:14,081 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 12:59:14,081 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:14,296 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 12:59:14,317 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:14,317 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 68 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:14,320 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:14,320 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:14,325 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,328 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,336 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,345 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,359 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,377 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,399 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,439 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,485 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,498 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:14,503 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:14,534 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 12:59:14,534 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:14,574 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 12:59:14,575 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:14,575 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 10, 10, 10, 10] total 38 [2018-01-24 12:59:14,575 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:14,576 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 12:59:14,576 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 12:59:14,576 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=248, Invalid=1234, Unknown=0, NotChecked=0, Total=1482 [2018-01-24 12:59:14,576 INFO L87 Difference]: Start difference. First operand 197 states and 221 transitions. Second operand 30 states. [2018-01-24 12:59:14,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:14,965 INFO L93 Difference]: Finished difference Result 264 states and 301 transitions. [2018-01-24 12:59:14,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-24 12:59:14,965 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 137 [2018-01-24 12:59:14,966 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:14,966 INFO L225 Difference]: With dead ends: 264 [2018-01-24 12:59:14,966 INFO L226 Difference]: Without dead ends: 205 [2018-01-24 12:59:14,967 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 575 GetRequests, 528 SyntacticMatches, 2 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 517 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=388, Invalid=1774, Unknown=0, NotChecked=0, Total=2162 [2018-01-24 12:59:14,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-01-24 12:59:15,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 203. [2018-01-24 12:59:15,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-01-24 12:59:15,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 227 transitions. [2018-01-24 12:59:15,001 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 227 transitions. Word has length 137 [2018-01-24 12:59:15,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:15,001 INFO L432 AbstractCegarLoop]: Abstraction has 203 states and 227 transitions. [2018-01-24 12:59:15,001 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 12:59:15,001 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 227 transitions. [2018-01-24 12:59:15,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-01-24 12:59:15,002 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:15,002 INFO L322 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:15,002 INFO L371 AbstractCegarLoop]: === Iteration 37 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:15,003 INFO L82 PathProgramCache]: Analyzing trace with hash 37813783, now seen corresponding path program 25 times [2018-01-24 12:59:15,003 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:15,003 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:15,003 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:15,003 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:15,003 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:15,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:15,012 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:15,502 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:15,502 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:15,502 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:15,507 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:15,507 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:15,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:15,523 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:15,566 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:15,566 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:16,279 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:16,299 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:16,300 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 70 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:16,302 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:16,302 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:16,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:16,338 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:16,370 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:16,370 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:16,411 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:16,413 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:16,413 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 53 [2018-01-24 12:59:16,413 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:16,413 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 12:59:16,413 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 12:59:16,413 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 12:59:16,414 INFO L87 Difference]: Start difference. First operand 203 states and 227 transitions. Second operand 28 states. [2018-01-24 12:59:18,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:18,332 INFO L93 Difference]: Finished difference Result 1187 states and 1356 transitions. [2018-01-24 12:59:18,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 12:59:18,333 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 132 [2018-01-24 12:59:18,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:18,338 INFO L225 Difference]: With dead ends: 1187 [2018-01-24 12:59:18,338 INFO L226 Difference]: Without dead ends: 1184 [2018-01-24 12:59:18,339 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 499 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 12:59:18,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1184 states. Received shutdown request... [2018-01-24 12:59:18,345 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 12:59:18,351 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 12:59:18,351 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 12:59:18 BoogieIcfgContainer [2018-01-24 12:59:18,351 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 12:59:18,352 INFO L168 Benchmark]: Toolchain (without parser) took 45760.49 ms. Allocated memory was 309.9 MB in the beginning and 721.9 MB in the end (delta: 412.1 MB). Free memory was 270.9 MB in the beginning and 465.8 MB in the end (delta: -194.9 MB). Peak memory consumption was 217.2 MB. Max. memory is 5.3 GB. [2018-01-24 12:59:18,354 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 309.9 MB. Free memory is still 275.9 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 12:59:18,354 INFO L168 Benchmark]: CACSL2BoogieTranslator took 159.70 ms. Allocated memory is still 309.9 MB. Free memory was 269.9 MB in the beginning and 262.7 MB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 5.3 GB. [2018-01-24 12:59:18,354 INFO L168 Benchmark]: Boogie Preprocessor took 26.25 ms. Allocated memory is still 309.9 MB. Free memory was 262.7 MB in the beginning and 260.8 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 12:59:18,355 INFO L168 Benchmark]: RCFGBuilder took 203.49 ms. Allocated memory is still 309.9 MB. Free memory was 260.8 MB in the beginning and 249.1 MB in the end (delta: 11.6 MB). Peak memory consumption was 11.6 MB. Max. memory is 5.3 GB. [2018-01-24 12:59:18,355 INFO L168 Benchmark]: TraceAbstraction took 45363.43 ms. Allocated memory was 309.9 MB in the beginning and 721.9 MB in the end (delta: 412.1 MB). Free memory was 249.1 MB in the beginning and 465.8 MB in the end (delta: -216.7 MB). Peak memory consumption was 195.4 MB. Max. memory is 5.3 GB. [2018-01-24 12:59:18,357 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 309.9 MB. Free memory is still 275.9 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 159.70 ms. Allocated memory is still 309.9 MB. Free memory was 269.9 MB in the beginning and 262.7 MB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 26.25 ms. Allocated memory is still 309.9 MB. Free memory was 262.7 MB in the beginning and 260.8 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 203.49 ms. Allocated memory is still 309.9 MB. Free memory was 260.8 MB in the beginning and 249.1 MB in the end (delta: 11.6 MB). Peak memory consumption was 11.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 45363.43 ms. Allocated memory was 309.9 MB in the beginning and 721.9 MB in the end (delta: 412.1 MB). Free memory was 249.1 MB in the beginning and 465.8 MB in the end (delta: -216.7 MB). Peak memory consumption was 195.4 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 7]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 7). Cancelled while executing MinimizeSevpa. - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while executing MinimizeSevpa. - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while executing MinimizeSevpa. - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while executing MinimizeSevpa. - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while executing MinimizeSevpa. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 32 locations, 5 error locations. TIMEOUT Result, 45.3s OverallTime, 37 OverallIterations, 26 TraceHistogramMax, 15.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3790 SDtfs, 2413 SDslu, 53712 SDs, 0 SdLazy, 27911 SolverSat, 228 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 10476 GetRequests, 9455 SyntacticMatches, 66 SemanticMatches, 955 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2769 ImplicationChecksByTransitivity, 16.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=203occurred in iteration=36, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 37 MinimizatonAttempts, 8032 StatesRemovedByMinimization, 33 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 6.3s SatisfiabilityAnalysisTime, 20.7s InterpolantComputationTime, 7532 NumberOfCodeBlocks, 7502 NumberOfCodeBlocksAsserted, 496 NumberOfCheckSat, 12360 ConstructedInterpolants, 0 QuantifiedInterpolants, 7040076 SizeOfPredicates, 7 NumberOfNonLiveVariables, 7324 ConjunctsInSsa, 1657 ConjunctsInUnsatCore, 175 InterpolantComputations, 4 PerfectInterpolantSequences, 4895/76624 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_12-59-18-365.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_12-59-18-365.csv Completed graceful shutdown