java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/array-examples/standard_strcpy_original_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 12:58:49,028 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 12:58:49,031 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 12:58:49,043 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 12:58:49,043 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 12:58:49,044 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 12:58:49,045 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 12:58:49,047 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 12:58:49,048 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 12:58:49,049 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 12:58:49,049 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 12:58:49,049 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 12:58:49,050 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 12:58:49,051 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 12:58:49,051 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 12:58:49,054 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 12:58:49,056 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 12:58:49,058 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 12:58:49,059 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 12:58:49,060 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 12:58:49,063 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 12:58:49,063 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 12:58:49,063 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 12:58:49,064 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 12:58:49,065 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 12:58:49,067 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 12:58:49,067 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 12:58:49,068 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 12:58:49,068 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 12:58:49,068 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 12:58:49,069 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 12:58:49,069 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf [2018-01-24 12:58:49,079 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 12:58:49,079 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 12:58:49,080 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 12:58:49,080 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 12:58:49,080 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 12:58:49,080 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 12:58:49,081 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 12:58:49,081 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 12:58:49,081 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 12:58:49,082 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 12:58:49,082 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 12:58:49,082 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 12:58:49,082 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 12:58:49,082 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 12:58:49,083 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 12:58:49,083 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 12:58:49,083 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 12:58:49,083 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 12:58:49,083 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 12:58:49,084 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 12:58:49,084 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 12:58:49,084 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 12:58:49,084 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 12:58:49,084 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 12:58:49,084 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 12:58:49,085 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 12:58:49,085 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 12:58:49,085 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 12:58:49,085 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-01-24 12:58:49,085 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 12:58:49,086 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 12:58:49,086 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 12:58:49,087 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 12:58:49,087 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 12:58:49,122 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 12:58:49,135 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 12:58:49,140 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 12:58:49,141 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 12:58:49,142 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 12:58:49,142 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/standard_strcpy_original_false-valid-deref.i [2018-01-24 12:58:49,268 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 12:58:49,274 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 12:58:49,274 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 12:58:49,274 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 12:58:49,280 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 12:58:49,281 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 12:58:49" (1/1) ... [2018-01-24 12:58:49,283 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6fff9f6e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:49, skipping insertion in model container [2018-01-24 12:58:49,284 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 12:58:49" (1/1) ... [2018-01-24 12:58:49,298 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 12:58:49,312 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 12:58:49,430 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 12:58:49,443 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 12:58:49,448 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:49 WrapperNode [2018-01-24 12:58:49,448 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 12:58:49,449 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 12:58:49,449 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 12:58:49,449 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 12:58:49,461 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:49" (1/1) ... [2018-01-24 12:58:49,462 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:49" (1/1) ... [2018-01-24 12:58:49,468 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:49" (1/1) ... [2018-01-24 12:58:49,469 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:49" (1/1) ... [2018-01-24 12:58:49,470 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:49" (1/1) ... [2018-01-24 12:58:49,474 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:49" (1/1) ... [2018-01-24 12:58:49,475 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:49" (1/1) ... [2018-01-24 12:58:49,476 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 12:58:49,477 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 12:58:49,477 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 12:58:49,477 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 12:58:49,478 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:49" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 12:58:49,526 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 12:58:49,526 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 12:58:49,527 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 12:58:49,527 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 12:58:49,527 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 12:58:49,527 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 12:58:49,527 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 12:58:49,527 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 12:58:49,527 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 12:58:49,656 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 12:58:49,657 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 12:58:49 BoogieIcfgContainer [2018-01-24 12:58:49,657 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 12:58:49,658 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 12:58:49,658 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 12:58:49,660 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 12:58:49,661 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 12:58:49" (1/3) ... [2018-01-24 12:58:49,662 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@60ae1371 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 12:58:49, skipping insertion in model container [2018-01-24 12:58:49,662 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 12:58:49" (2/3) ... [2018-01-24 12:58:49,662 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@60ae1371 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 12:58:49, skipping insertion in model container [2018-01-24 12:58:49,662 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 12:58:49" (3/3) ... [2018-01-24 12:58:49,664 INFO L105 eAbstractionObserver]: Analyzing ICFG standard_strcpy_original_false-valid-deref.i [2018-01-24 12:58:49,670 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 12:58:49,677 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2018-01-24 12:58:49,711 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 12:58:49,712 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 12:58:49,712 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 12:58:49,712 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 12:58:49,712 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 12:58:49,713 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 12:58:49,713 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 12:58:49,713 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 12:58:49,714 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 12:58:49,729 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states. [2018-01-24 12:58:49,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2018-01-24 12:58:49,735 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:49,736 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:49,736 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:49,739 INFO L82 PathProgramCache]: Analyzing trace with hash 1734695582, now seen corresponding path program 1 times [2018-01-24 12:58:49,742 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:49,784 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:49,784 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:49,784 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:49,784 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:49,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:49,820 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:49,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:49,879 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 12:58:49,879 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 12:58:49,879 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 12:58:49,882 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 12:58:49,896 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 12:58:49,897 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 12:58:49,899 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 3 states. [2018-01-24 12:58:50,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:50,064 INFO L93 Difference]: Finished difference Result 74 states and 90 transitions. [2018-01-24 12:58:50,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 12:58:50,065 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2018-01-24 12:58:50,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:50,074 INFO L225 Difference]: With dead ends: 74 [2018-01-24 12:58:50,075 INFO L226 Difference]: Without dead ends: 41 [2018-01-24 12:58:50,078 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 12:58:50,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2018-01-24 12:58:50,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 38. [2018-01-24 12:58:50,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-01-24 12:58:50,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 40 transitions. [2018-01-24 12:58:50,174 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 40 transitions. Word has length 7 [2018-01-24 12:58:50,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:50,174 INFO L432 AbstractCegarLoop]: Abstraction has 38 states and 40 transitions. [2018-01-24 12:58:50,174 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 12:58:50,174 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 40 transitions. [2018-01-24 12:58:50,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-01-24 12:58:50,175 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:50,175 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:50,175 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:50,175 INFO L82 PathProgramCache]: Analyzing trace with hash 337601429, now seen corresponding path program 1 times [2018-01-24 12:58:50,176 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:50,177 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:50,177 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:50,177 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:50,177 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:50,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:50,187 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:50,232 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:50,233 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:50,233 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:50,247 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:50,247 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:50,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:50,268 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:50,285 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:50,286 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:50,328 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:50,363 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:50,364 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:50,368 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:50,368 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:50,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:50,377 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:50,388 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:50,388 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:50,404 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:50,406 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:50,406 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3, 3, 3] total 5 [2018-01-24 12:58:50,406 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:50,407 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 12:58:50,407 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 12:58:50,408 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 12:58:50,408 INFO L87 Difference]: Start difference. First operand 38 states and 40 transitions. Second operand 4 states. [2018-01-24 12:58:50,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:50,504 INFO L93 Difference]: Finished difference Result 60 states and 65 transitions. [2018-01-24 12:58:50,504 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 12:58:50,504 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-01-24 12:58:50,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:50,506 INFO L225 Difference]: With dead ends: 60 [2018-01-24 12:58:50,506 INFO L226 Difference]: Without dead ends: 54 [2018-01-24 12:58:50,507 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 43 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 12:58:50,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-24 12:58:50,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 50. [2018-01-24 12:58:50,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 12:58:50,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-01-24 12:58:50,514 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 12 [2018-01-24 12:58:50,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:50,514 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-01-24 12:58:50,514 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 12:58:50,514 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-01-24 12:58:50,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 12:58:50,515 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:50,515 INFO L322 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:50,515 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:50,515 INFO L82 PathProgramCache]: Analyzing trace with hash -1746445058, now seen corresponding path program 2 times [2018-01-24 12:58:50,515 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:50,516 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:50,516 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:50,516 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:50,516 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:50,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:50,522 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:50,593 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:50,594 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:50,594 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:50,599 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:50,599 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:50,604 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,606 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,611 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:50,613 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:50,633 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:50,633 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:50,735 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:50,755 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:50,756 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:50,762 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:50,762 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:50,767 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,770 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:50,774 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:50,778 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:50,786 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:50,786 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:50,809 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:50,810 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:50,810 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-01-24 12:58:50,810 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:50,811 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 12:58:50,811 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 12:58:50,811 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 12:58:50,811 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 5 states. [2018-01-24 12:58:50,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:50,950 INFO L93 Difference]: Finished difference Result 73 states and 80 transitions. [2018-01-24 12:58:50,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 12:58:50,951 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 12:58:50,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:50,953 INFO L225 Difference]: With dead ends: 73 [2018-01-24 12:58:50,954 INFO L226 Difference]: Without dead ends: 67 [2018-01-24 12:58:50,954 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 62 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 12:58:50,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-01-24 12:58:50,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 62. [2018-01-24 12:58:50,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-01-24 12:58:50,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 68 transitions. [2018-01-24 12:58:50,965 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 68 transitions. Word has length 17 [2018-01-24 12:58:50,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:50,965 INFO L432 AbstractCegarLoop]: Abstraction has 62 states and 68 transitions. [2018-01-24 12:58:50,965 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 12:58:50,966 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 68 transitions. [2018-01-24 12:58:50,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-01-24 12:58:50,967 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:50,967 INFO L322 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:50,967 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:50,967 INFO L82 PathProgramCache]: Analyzing trace with hash -228598475, now seen corresponding path program 3 times [2018-01-24 12:58:50,967 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:50,968 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:50,969 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:50,969 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:50,969 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:50,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:50,978 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:51,069 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,069 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:51,069 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:51,081 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:51,081 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:51,084 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:51,086 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:51,087 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:51,088 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:51,089 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:51,090 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:51,100 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,100 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:51,164 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,190 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:51,191 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:51,194 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:51,194 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:51,198 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:51,200 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:51,204 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:51,208 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:51,212 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:51,215 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:51,222 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,223 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:51,239 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,240 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:51,240 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 12:58:51,240 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:51,240 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 12:58:51,240 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 12:58:51,241 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 12:58:51,241 INFO L87 Difference]: Start difference. First operand 62 states and 68 transitions. Second operand 6 states. [2018-01-24 12:58:51,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:51,380 INFO L93 Difference]: Finished difference Result 86 states and 95 transitions. [2018-01-24 12:58:51,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 12:58:51,380 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-01-24 12:58:51,380 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:51,381 INFO L225 Difference]: With dead ends: 86 [2018-01-24 12:58:51,381 INFO L226 Difference]: Without dead ends: 80 [2018-01-24 12:58:51,382 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 81 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 12:58:51,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-24 12:58:51,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 74. [2018-01-24 12:58:51,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-24 12:58:51,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 82 transitions. [2018-01-24 12:58:51,391 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 82 transitions. Word has length 22 [2018-01-24 12:58:51,392 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:51,392 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 82 transitions. [2018-01-24 12:58:51,392 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 12:58:51,392 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 82 transitions. [2018-01-24 12:58:51,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 12:58:51,393 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:51,393 INFO L322 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:51,393 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:51,393 INFO L82 PathProgramCache]: Analyzing trace with hash 756148062, now seen corresponding path program 4 times [2018-01-24 12:58:51,393 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:51,394 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:51,394 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:51,394 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:51,394 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:51,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:51,403 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:51,488 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,488 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:51,488 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:51,513 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:51,514 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:51,524 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:51,527 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:51,537 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,537 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:51,653 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,684 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:51,684 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:51,688 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:51,688 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:51,704 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:51,707 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:51,714 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,714 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:51,729 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,731 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:51,731 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 12:58:51,731 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:51,731 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 12:58:51,732 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 12:58:51,732 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 12:58:51,732 INFO L87 Difference]: Start difference. First operand 74 states and 82 transitions. Second operand 7 states. [2018-01-24 12:58:51,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:51,878 INFO L93 Difference]: Finished difference Result 99 states and 110 transitions. [2018-01-24 12:58:51,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 12:58:51,879 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 27 [2018-01-24 12:58:51,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:51,880 INFO L225 Difference]: With dead ends: 99 [2018-01-24 12:58:51,881 INFO L226 Difference]: Without dead ends: 93 [2018-01-24 12:58:51,881 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 100 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 12:58:51,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-01-24 12:58:51,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 86. [2018-01-24 12:58:51,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-01-24 12:58:51,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 96 transitions. [2018-01-24 12:58:51,892 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 96 transitions. Word has length 27 [2018-01-24 12:58:51,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:51,892 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 96 transitions. [2018-01-24 12:58:51,892 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 12:58:51,893 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 96 transitions. [2018-01-24 12:58:51,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 12:58:51,894 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:51,894 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:51,894 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:51,894 INFO L82 PathProgramCache]: Analyzing trace with hash 671928021, now seen corresponding path program 5 times [2018-01-24 12:58:51,894 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:51,895 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:51,896 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:51,896 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:51,896 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:51,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:51,905 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:51,982 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:51,983 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:51,983 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:51,988 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:51,988 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:51,991 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,992 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,993 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,994 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,995 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,997 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:51,997 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:51,999 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:52,007 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:52,008 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:52,195 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:52,230 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:52,230 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:52,235 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:52,235 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:52,239 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:52,242 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:52,249 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:52,256 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:52,262 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:52,270 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:52,274 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:52,277 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:52,287 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:52,287 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:52,298 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:52,300 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:52,300 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 12:58:52,300 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:52,301 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 12:58:52,301 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 12:58:52,301 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 12:58:52,301 INFO L87 Difference]: Start difference. First operand 86 states and 96 transitions. Second operand 8 states. [2018-01-24 12:58:52,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:52,648 INFO L93 Difference]: Finished difference Result 112 states and 125 transitions. [2018-01-24 12:58:52,649 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 12:58:52,649 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 32 [2018-01-24 12:58:52,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:52,650 INFO L225 Difference]: With dead ends: 112 [2018-01-24 12:58:52,650 INFO L226 Difference]: Without dead ends: 106 [2018-01-24 12:58:52,650 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 119 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 12:58:52,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-01-24 12:58:52,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 98. [2018-01-24 12:58:52,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-01-24 12:58:52,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 110 transitions. [2018-01-24 12:58:52,660 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 110 transitions. Word has length 32 [2018-01-24 12:58:52,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:52,661 INFO L432 AbstractCegarLoop]: Abstraction has 98 states and 110 transitions. [2018-01-24 12:58:52,661 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 12:58:52,661 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 110 transitions. [2018-01-24 12:58:52,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 12:58:52,663 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:52,663 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:52,663 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:52,663 INFO L82 PathProgramCache]: Analyzing trace with hash -203753026, now seen corresponding path program 6 times [2018-01-24 12:58:52,663 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:52,664 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:52,664 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:52,664 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:52,664 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:52,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:52,673 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:52,769 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:52,769 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:52,770 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:52,776 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:52,777 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:52,780 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,781 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,782 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,783 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,783 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,784 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,785 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,786 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:52,787 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:52,796 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:52,796 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:52,914 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:52,935 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:52,935 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:52,938 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:52,938 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:52,941 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,943 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,947 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,951 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,957 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,964 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,973 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:52,977 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:52,981 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:52,991 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:52,992 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:53,004 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:53,006 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:53,006 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 12:58:53,006 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:53,007 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 12:58:53,007 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 12:58:53,007 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 12:58:53,007 INFO L87 Difference]: Start difference. First operand 98 states and 110 transitions. Second operand 9 states. [2018-01-24 12:58:53,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:53,198 INFO L93 Difference]: Finished difference Result 125 states and 140 transitions. [2018-01-24 12:58:53,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 12:58:53,198 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 37 [2018-01-24 12:58:53,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:53,199 INFO L225 Difference]: With dead ends: 125 [2018-01-24 12:58:53,199 INFO L226 Difference]: Without dead ends: 119 [2018-01-24 12:58:53,200 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 138 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 12:58:53,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-01-24 12:58:53,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 110. [2018-01-24 12:58:53,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-24 12:58:53,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 124 transitions. [2018-01-24 12:58:53,208 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 124 transitions. Word has length 37 [2018-01-24 12:58:53,208 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:53,208 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 124 transitions. [2018-01-24 12:58:53,208 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 12:58:53,208 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 124 transitions. [2018-01-24 12:58:53,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 12:58:53,209 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:53,209 INFO L322 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:53,209 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:53,209 INFO L82 PathProgramCache]: Analyzing trace with hash -1846527883, now seen corresponding path program 7 times [2018-01-24 12:58:53,209 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:53,210 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:53,210 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:53,210 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:53,210 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:53,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:53,217 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:53,445 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:53,446 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:53,446 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:53,454 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:53,455 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:53,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:53,463 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:53,481 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:53,481 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:53,628 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:53,648 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:53,648 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:53,651 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:53,652 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:53,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:53,666 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:53,675 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:53,675 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:53,685 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:53,687 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:53,687 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 12:58:53,687 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:53,688 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 12:58:53,688 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 12:58:53,688 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 12:58:53,689 INFO L87 Difference]: Start difference. First operand 110 states and 124 transitions. Second operand 10 states. [2018-01-24 12:58:53,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:53,906 INFO L93 Difference]: Finished difference Result 138 states and 155 transitions. [2018-01-24 12:58:53,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 12:58:53,906 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-01-24 12:58:53,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:53,907 INFO L225 Difference]: With dead ends: 138 [2018-01-24 12:58:53,907 INFO L226 Difference]: Without dead ends: 132 [2018-01-24 12:58:53,908 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 157 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 12:58:53,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-01-24 12:58:53,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 122. [2018-01-24 12:58:53,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-01-24 12:58:53,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 138 transitions. [2018-01-24 12:58:53,917 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 138 transitions. Word has length 42 [2018-01-24 12:58:53,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:53,918 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 138 transitions. [2018-01-24 12:58:53,918 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 12:58:53,918 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 138 transitions. [2018-01-24 12:58:53,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-01-24 12:58:53,920 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:53,920 INFO L322 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:53,920 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:53,920 INFO L82 PathProgramCache]: Analyzing trace with hash 2109248542, now seen corresponding path program 8 times [2018-01-24 12:58:53,920 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:53,921 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:53,921 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:53,921 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:53,921 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:53,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:53,930 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:54,032 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:54,032 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:54,033 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:54,039 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:54,039 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:54,043 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:54,047 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:54,047 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:54,049 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:54,061 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:54,061 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:54,175 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:54,195 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:54,195 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:54,199 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:54,200 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:54,203 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:54,209 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:54,215 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:54,218 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:54,225 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:54,226 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:54,235 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:54,237 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:54,237 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 12:58:54,237 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:54,237 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 12:58:54,237 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 12:58:54,237 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 12:58:54,238 INFO L87 Difference]: Start difference. First operand 122 states and 138 transitions. Second operand 11 states. [2018-01-24 12:58:54,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:54,614 INFO L93 Difference]: Finished difference Result 151 states and 170 transitions. [2018-01-24 12:58:54,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 12:58:54,615 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 47 [2018-01-24 12:58:54,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:54,616 INFO L225 Difference]: With dead ends: 151 [2018-01-24 12:58:54,616 INFO L226 Difference]: Without dead ends: 145 [2018-01-24 12:58:54,617 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 176 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 12:58:54,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-01-24 12:58:54,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 134. [2018-01-24 12:58:54,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-24 12:58:54,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 152 transitions. [2018-01-24 12:58:54,626 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 152 transitions. Word has length 47 [2018-01-24 12:58:54,626 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:54,626 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 152 transitions. [2018-01-24 12:58:54,626 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 12:58:54,627 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 152 transitions. [2018-01-24 12:58:54,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 12:58:54,628 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:54,628 INFO L322 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:54,628 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:54,629 INFO L82 PathProgramCache]: Analyzing trace with hash 408164885, now seen corresponding path program 9 times [2018-01-24 12:58:54,629 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:54,630 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:54,630 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:54,630 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:54,630 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:54,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:54,640 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:54,756 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:54,757 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:54,757 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:54,763 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:54,764 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:54,767 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:54,768 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:54,769 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:54,770 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:54,771 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:54,772 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:54,774 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:54,776 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:54,777 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:54,779 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:54,780 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:54,782 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:54,795 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:54,796 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:54,966 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:54,988 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:54,988 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:54,991 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:58:54,991 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:58:54,995 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:54,997 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:55,001 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:55,006 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:55,012 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:55,020 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:55,027 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:55,037 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:55,049 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:55,065 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:58:55,071 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:55,075 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:55,087 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:55,087 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:55,121 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:55,123 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:55,123 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 12:58:55,123 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:55,124 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 12:58:55,124 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 12:58:55,124 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 12:58:55,124 INFO L87 Difference]: Start difference. First operand 134 states and 152 transitions. Second operand 12 states. [2018-01-24 12:58:55,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:55,419 INFO L93 Difference]: Finished difference Result 164 states and 185 transitions. [2018-01-24 12:58:55,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 12:58:55,419 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 52 [2018-01-24 12:58:55,419 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:55,420 INFO L225 Difference]: With dead ends: 164 [2018-01-24 12:58:55,420 INFO L226 Difference]: Without dead ends: 158 [2018-01-24 12:58:55,421 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 195 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 12:58:55,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-01-24 12:58:55,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 146. [2018-01-24 12:58:55,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-01-24 12:58:55,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 166 transitions. [2018-01-24 12:58:55,437 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 166 transitions. Word has length 52 [2018-01-24 12:58:55,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:55,438 INFO L432 AbstractCegarLoop]: Abstraction has 146 states and 166 transitions. [2018-01-24 12:58:55,438 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 12:58:55,438 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 166 transitions. [2018-01-24 12:58:55,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-01-24 12:58:55,440 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:55,440 INFO L322 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:55,440 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:55,440 INFO L82 PathProgramCache]: Analyzing trace with hash -2136951170, now seen corresponding path program 10 times [2018-01-24 12:58:55,440 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:55,441 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:55,441 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:55,441 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:55,442 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:55,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:55,451 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:55,632 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:55,632 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:55,632 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:55,639 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:55,639 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:55,652 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:55,654 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:55,665 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:55,666 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:55,830 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:55,849 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:55,849 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:55,852 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:58:55,853 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:58:55,883 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:55,886 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:55,895 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:55,896 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:55,916 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:55,918 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:55,918 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 12:58:55,918 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:55,918 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 12:58:55,919 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 12:58:55,919 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 12:58:55,919 INFO L87 Difference]: Start difference. First operand 146 states and 166 transitions. Second operand 13 states. [2018-01-24 12:58:56,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:56,301 INFO L93 Difference]: Finished difference Result 177 states and 200 transitions. [2018-01-24 12:58:56,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 12:58:56,302 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2018-01-24 12:58:56,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:56,303 INFO L225 Difference]: With dead ends: 177 [2018-01-24 12:58:56,303 INFO L226 Difference]: Without dead ends: 171 [2018-01-24 12:58:56,303 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 214 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 12:58:56,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-01-24 12:58:56,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 158. [2018-01-24 12:58:56,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-01-24 12:58:56,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 180 transitions. [2018-01-24 12:58:56,312 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 180 transitions. Word has length 57 [2018-01-24 12:58:56,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:56,313 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 180 transitions. [2018-01-24 12:58:56,313 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 12:58:56,313 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 180 transitions. [2018-01-24 12:58:56,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 12:58:56,313 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:56,313 INFO L322 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:56,313 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:56,314 INFO L82 PathProgramCache]: Analyzing trace with hash 1325560757, now seen corresponding path program 11 times [2018-01-24 12:58:56,314 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:56,314 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:56,314 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:56,314 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:56,315 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:56,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:56,324 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:56,514 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:56,514 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:56,514 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:56,520 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:56,520 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:56,523 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,524 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,525 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,526 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,528 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,529 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,531 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,532 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,535 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,537 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,539 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,543 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,543 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:56,545 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:56,564 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:56,564 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:56,822 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:56,853 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:56,854 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:56,859 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:58:56,859 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:56,862 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,865 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,869 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,874 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,880 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,887 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,895 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,906 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,921 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,937 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,954 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,977 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:56,985 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:56,989 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:57,003 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:57,003 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:57,021 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:57,023 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:57,023 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 12:58:57,023 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:57,023 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 12:58:57,023 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 12:58:57,024 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 12:58:57,024 INFO L87 Difference]: Start difference. First operand 158 states and 180 transitions. Second operand 14 states. [2018-01-24 12:58:57,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:57,428 INFO L93 Difference]: Finished difference Result 190 states and 215 transitions. [2018-01-24 12:58:57,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 12:58:57,428 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 62 [2018-01-24 12:58:57,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:57,429 INFO L225 Difference]: With dead ends: 190 [2018-01-24 12:58:57,429 INFO L226 Difference]: Without dead ends: 184 [2018-01-24 12:58:57,430 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 233 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 12:58:57,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-01-24 12:58:57,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 170. [2018-01-24 12:58:57,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-01-24 12:58:57,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 194 transitions. [2018-01-24 12:58:57,436 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 194 transitions. Word has length 62 [2018-01-24 12:58:57,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:57,437 INFO L432 AbstractCegarLoop]: Abstraction has 170 states and 194 transitions. [2018-01-24 12:58:57,437 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 12:58:57,437 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 194 transitions. [2018-01-24 12:58:57,438 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-01-24 12:58:57,438 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:57,438 INFO L322 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:57,438 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:57,438 INFO L82 PathProgramCache]: Analyzing trace with hash 923361502, now seen corresponding path program 12 times [2018-01-24 12:58:57,439 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:57,439 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:57,440 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:57,440 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:57,440 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:57,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:57,448 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:57,634 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:57,635 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:57,635 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:57,639 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:57,640 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:57,643 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,643 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,644 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,645 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,646 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,647 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,648 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,649 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,653 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,655 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,656 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,658 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,659 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,659 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:57,661 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:57,677 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:57,677 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:57,880 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:57,900 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:57,901 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:57,903 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:58:57,903 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:58:57,906 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,908 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,911 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,915 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,920 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,925 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,934 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,947 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,964 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:57,987 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:58,006 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:58,029 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:58,056 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:58:58,063 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:58,066 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:58,082 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:58,082 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:58,110 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:58,112 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:58,112 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 12:58:58,112 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:58,112 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 12:58:58,113 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 12:58:58,113 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 12:58:58,113 INFO L87 Difference]: Start difference. First operand 170 states and 194 transitions. Second operand 15 states. [2018-01-24 12:58:58,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:58,597 INFO L93 Difference]: Finished difference Result 203 states and 230 transitions. [2018-01-24 12:58:58,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 12:58:58,638 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 67 [2018-01-24 12:58:58,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:58,639 INFO L225 Difference]: With dead ends: 203 [2018-01-24 12:58:58,639 INFO L226 Difference]: Without dead ends: 197 [2018-01-24 12:58:58,640 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 280 GetRequests, 252 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 12:58:58,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2018-01-24 12:58:58,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 182. [2018-01-24 12:58:58,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-24 12:58:58,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 208 transitions. [2018-01-24 12:58:58,647 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 208 transitions. Word has length 67 [2018-01-24 12:58:58,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:58,648 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 208 transitions. [2018-01-24 12:58:58,648 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 12:58:58,648 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 208 transitions. [2018-01-24 12:58:58,648 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-01-24 12:58:58,648 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:58,649 INFO L322 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:58,649 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:58,649 INFO L82 PathProgramCache]: Analyzing trace with hash 356861269, now seen corresponding path program 13 times [2018-01-24 12:58:58,649 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:58,650 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:58,650 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:58:58,650 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:58,650 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:58,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:58,657 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:58,814 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:58,815 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:58,815 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:58,819 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:58,820 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:58,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:58,829 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:58,840 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:58,841 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:59,069 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:59,090 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:59,090 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:58:59,093 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:59,093 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:58:59,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:59,113 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:59,129 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:59,129 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:58:59,151 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:59,152 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:58:59,153 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 29 [2018-01-24 12:58:59,153 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:58:59,153 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 12:58:59,153 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 12:58:59,153 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 12:58:59,154 INFO L87 Difference]: Start difference. First operand 182 states and 208 transitions. Second operand 16 states. [2018-01-24 12:58:59,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:58:59,671 INFO L93 Difference]: Finished difference Result 216 states and 245 transitions. [2018-01-24 12:58:59,671 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 12:58:59,671 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2018-01-24 12:58:59,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:58:59,673 INFO L225 Difference]: With dead ends: 216 [2018-01-24 12:58:59,673 INFO L226 Difference]: Without dead ends: 210 [2018-01-24 12:58:59,673 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 301 GetRequests, 271 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 12:58:59,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states. [2018-01-24 12:58:59,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 194. [2018-01-24 12:58:59,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-01-24 12:58:59,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 222 transitions. [2018-01-24 12:58:59,683 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 222 transitions. Word has length 72 [2018-01-24 12:58:59,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:58:59,684 INFO L432 AbstractCegarLoop]: Abstraction has 194 states and 222 transitions. [2018-01-24 12:58:59,684 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 12:58:59,684 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 222 transitions. [2018-01-24 12:58:59,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-01-24 12:58:59,685 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:58:59,685 INFO L322 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1] [2018-01-24 12:58:59,685 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:58:59,685 INFO L82 PathProgramCache]: Analyzing trace with hash -1075276994, now seen corresponding path program 14 times [2018-01-24 12:58:59,685 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:58:59,686 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:59,686 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:58:59,686 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:58:59,686 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:58:59,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:58:59,695 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:58:59,948 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:59,948 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:58:59,948 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:58:59,956 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:58:59,957 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:58:59,960 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:59,966 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:58:59,968 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:58:59,970 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:58:59,991 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:58:59,991 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:00,353 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:00,385 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:00,385 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:00,392 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:00,392 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:00,396 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:00,408 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:00,420 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:00,424 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:00,438 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:00,438 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:00,459 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:00,460 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:00,460 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 31 [2018-01-24 12:59:00,460 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:00,460 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 12:59:00,460 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 12:59:00,461 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 12:59:00,461 INFO L87 Difference]: Start difference. First operand 194 states and 222 transitions. Second operand 17 states. [2018-01-24 12:59:01,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:01,008 INFO L93 Difference]: Finished difference Result 229 states and 260 transitions. [2018-01-24 12:59:01,008 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 12:59:01,009 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 77 [2018-01-24 12:59:01,009 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:01,010 INFO L225 Difference]: With dead ends: 229 [2018-01-24 12:59:01,010 INFO L226 Difference]: Without dead ends: 223 [2018-01-24 12:59:01,011 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 322 GetRequests, 290 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 12:59:01,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-01-24 12:59:01,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 206. [2018-01-24 12:59:01,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-01-24 12:59:01,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 236 transitions. [2018-01-24 12:59:01,021 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 236 transitions. Word has length 77 [2018-01-24 12:59:01,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:01,021 INFO L432 AbstractCegarLoop]: Abstraction has 206 states and 236 transitions. [2018-01-24 12:59:01,021 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 12:59:01,021 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 236 transitions. [2018-01-24 12:59:01,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-01-24 12:59:01,022 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:01,022 INFO L322 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:01,022 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:01,022 INFO L82 PathProgramCache]: Analyzing trace with hash 904302325, now seen corresponding path program 15 times [2018-01-24 12:59:01,022 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:01,023 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:01,023 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:01,023 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:01,023 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:01,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:01,032 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:01,254 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:01,254 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:01,255 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:01,259 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:01,259 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:01,263 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,264 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,265 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,266 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,267 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,268 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,269 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,270 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,271 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,273 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,274 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,276 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,278 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,280 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,282 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,284 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,285 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:01,287 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:01,307 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:01,307 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:01,612 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:01,632 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:01,632 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:01,635 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:01,635 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:01,640 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,641 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,645 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,648 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,653 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,660 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,666 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,675 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,685 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,700 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,718 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,737 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,760 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,788 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,829 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,877 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:01,886 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:01,889 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:01,906 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:01,906 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:01,928 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:01,929 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:01,929 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 33 [2018-01-24 12:59:01,929 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:01,929 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 12:59:01,930 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 12:59:01,930 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 12:59:01,930 INFO L87 Difference]: Start difference. First operand 206 states and 236 transitions. Second operand 18 states. [2018-01-24 12:59:02,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:02,564 INFO L93 Difference]: Finished difference Result 242 states and 275 transitions. [2018-01-24 12:59:02,564 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 12:59:02,564 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 82 [2018-01-24 12:59:02,565 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:02,566 INFO L225 Difference]: With dead ends: 242 [2018-01-24 12:59:02,566 INFO L226 Difference]: Without dead ends: 236 [2018-01-24 12:59:02,566 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 309 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 12:59:02,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-01-24 12:59:02,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 218. [2018-01-24 12:59:02,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2018-01-24 12:59:02,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 250 transitions. [2018-01-24 12:59:02,574 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 250 transitions. Word has length 82 [2018-01-24 12:59:02,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:02,574 INFO L432 AbstractCegarLoop]: Abstraction has 218 states and 250 transitions. [2018-01-24 12:59:02,574 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 12:59:02,574 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 250 transitions. [2018-01-24 12:59:02,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 12:59:02,575 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:02,575 INFO L322 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:02,575 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:02,575 INFO L82 PathProgramCache]: Analyzing trace with hash 2125745566, now seen corresponding path program 16 times [2018-01-24 12:59:02,575 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:02,576 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:02,576 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:02,576 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:02,576 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:02,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:02,584 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:02,780 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:02,780 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:02,780 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:02,785 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:59:02,786 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:59:02,801 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:02,803 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:02,823 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:02,823 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:03,175 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:03,195 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:03,195 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:03,198 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:59:03,198 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:59:03,263 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:03,266 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:03,281 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:03,281 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:03,297 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:03,298 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:03,299 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 35 [2018-01-24 12:59:03,299 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:03,299 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 12:59:03,299 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 12:59:03,299 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 12:59:03,300 INFO L87 Difference]: Start difference. First operand 218 states and 250 transitions. Second operand 19 states. [2018-01-24 12:59:04,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:04,073 INFO L93 Difference]: Finished difference Result 255 states and 290 transitions. [2018-01-24 12:59:04,073 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 12:59:04,073 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 87 [2018-01-24 12:59:04,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:04,074 INFO L225 Difference]: With dead ends: 255 [2018-01-24 12:59:04,075 INFO L226 Difference]: Without dead ends: 249 [2018-01-24 12:59:04,075 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 364 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 12:59:04,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states. [2018-01-24 12:59:04,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 230. [2018-01-24 12:59:04,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-01-24 12:59:04,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 264 transitions. [2018-01-24 12:59:04,085 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 264 transitions. Word has length 87 [2018-01-24 12:59:04,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:04,085 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 264 transitions. [2018-01-24 12:59:04,085 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 12:59:04,086 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 264 transitions. [2018-01-24 12:59:04,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 12:59:04,087 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:04,087 INFO L322 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:04,087 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:04,087 INFO L82 PathProgramCache]: Analyzing trace with hash 120606869, now seen corresponding path program 17 times [2018-01-24 12:59:04,088 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:04,088 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:04,088 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:04,088 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:04,089 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:04,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:04,098 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:04,327 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:04,327 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:04,327 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:04,332 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:59:04,332 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:04,335 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,336 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,337 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,338 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,339 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,340 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,341 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,342 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,344 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,345 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,347 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,349 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,351 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,354 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,357 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,360 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,364 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,368 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,369 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:04,370 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:04,386 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:04,386 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:04,738 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:04,758 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:04,758 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:04,761 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:59:04,761 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:04,764 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,766 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,770 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,774 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,781 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,787 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,795 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,805 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,819 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,837 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,853 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,873 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,896 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,931 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:04,972 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:05,008 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:05,049 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:05,096 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:05,106 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:05,110 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:05,136 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:05,137 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:05,169 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:05,170 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:05,170 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 37 [2018-01-24 12:59:05,170 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:05,171 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 12:59:05,171 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 12:59:05,171 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 12:59:05,171 INFO L87 Difference]: Start difference. First operand 230 states and 264 transitions. Second operand 20 states. [2018-01-24 12:59:05,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:05,949 INFO L93 Difference]: Finished difference Result 268 states and 305 transitions. [2018-01-24 12:59:05,949 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 12:59:05,949 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 92 [2018-01-24 12:59:05,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:05,951 INFO L225 Difference]: With dead ends: 268 [2018-01-24 12:59:05,951 INFO L226 Difference]: Without dead ends: 262 [2018-01-24 12:59:05,952 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 385 GetRequests, 347 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 12:59:05,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262 states. [2018-01-24 12:59:05,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262 to 242. [2018-01-24 12:59:05,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242 states. [2018-01-24 12:59:05,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 278 transitions. [2018-01-24 12:59:05,960 INFO L78 Accepts]: Start accepts. Automaton has 242 states and 278 transitions. Word has length 92 [2018-01-24 12:59:05,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:05,960 INFO L432 AbstractCegarLoop]: Abstraction has 242 states and 278 transitions. [2018-01-24 12:59:05,960 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 12:59:05,960 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 278 transitions. [2018-01-24 12:59:05,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-01-24 12:59:05,961 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:05,961 INFO L322 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:05,961 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:05,962 INFO L82 PathProgramCache]: Analyzing trace with hash 2070056958, now seen corresponding path program 18 times [2018-01-24 12:59:05,962 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:05,962 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:05,962 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:05,962 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:05,963 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:05,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:05,970 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:06,191 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:06,191 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:06,191 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:06,196 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:59:06,196 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:59:06,199 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,200 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,201 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,202 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,202 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,203 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,204 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,205 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,206 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,207 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,209 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,210 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,212 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,213 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,215 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,216 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,218 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,220 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,223 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,224 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:06,225 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:06,241 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:06,241 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:06,720 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:06,740 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:06,740 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:06,743 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:59:06,743 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:59:06,748 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,750 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,753 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,758 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,762 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,767 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,774 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,784 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,801 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,822 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,844 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,867 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,891 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,919 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,952 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:06,992 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:07,038 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:07,110 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:07,222 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:07,233 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:07,237 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:07,253 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:07,254 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:07,277 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:07,278 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:07,278 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 39 [2018-01-24 12:59:07,278 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:07,279 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 12:59:07,279 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 12:59:07,279 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 12:59:07,279 INFO L87 Difference]: Start difference. First operand 242 states and 278 transitions. Second operand 21 states. [2018-01-24 12:59:08,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:08,119 INFO L93 Difference]: Finished difference Result 281 states and 320 transitions. [2018-01-24 12:59:08,119 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 12:59:08,119 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 97 [2018-01-24 12:59:08,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:08,120 INFO L225 Difference]: With dead ends: 281 [2018-01-24 12:59:08,120 INFO L226 Difference]: Without dead ends: 275 [2018-01-24 12:59:08,121 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 406 GetRequests, 366 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 12:59:08,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 275 states. [2018-01-24 12:59:08,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 275 to 254. [2018-01-24 12:59:08,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 254 states. [2018-01-24 12:59:08,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254 states to 254 states and 292 transitions. [2018-01-24 12:59:08,133 INFO L78 Accepts]: Start accepts. Automaton has 254 states and 292 transitions. Word has length 97 [2018-01-24 12:59:08,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:08,133 INFO L432 AbstractCegarLoop]: Abstraction has 254 states and 292 transitions. [2018-01-24 12:59:08,133 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 12:59:08,134 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 292 transitions. [2018-01-24 12:59:08,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-24 12:59:08,135 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:08,135 INFO L322 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:08,135 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:08,135 INFO L82 PathProgramCache]: Analyzing trace with hash 183274037, now seen corresponding path program 19 times [2018-01-24 12:59:08,136 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:08,136 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:08,136 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:08,137 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:08,137 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:08,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:08,146 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:08,489 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:08,490 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:08,490 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:08,495 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:08,495 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:08,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:08,508 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:08,525 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:08,526 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:09,001 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:09,020 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:09,038 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:09,041 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:09,041 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:09,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:09,069 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:09,086 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:09,087 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:09,107 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:09,108 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:09,108 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 41 [2018-01-24 12:59:09,108 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:09,108 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 12:59:09,108 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 12:59:09,109 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 12:59:09,109 INFO L87 Difference]: Start difference. First operand 254 states and 292 transitions. Second operand 22 states. [2018-01-24 12:59:10,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:10,057 INFO L93 Difference]: Finished difference Result 294 states and 335 transitions. [2018-01-24 12:59:10,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 12:59:10,057 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 102 [2018-01-24 12:59:10,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:10,058 INFO L225 Difference]: With dead ends: 294 [2018-01-24 12:59:10,058 INFO L226 Difference]: Without dead ends: 288 [2018-01-24 12:59:10,059 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 427 GetRequests, 385 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 12:59:10,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2018-01-24 12:59:10,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 266. [2018-01-24 12:59:10,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 266 states. [2018-01-24 12:59:10,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 266 states to 266 states and 306 transitions. [2018-01-24 12:59:10,068 INFO L78 Accepts]: Start accepts. Automaton has 266 states and 306 transitions. Word has length 102 [2018-01-24 12:59:10,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:10,069 INFO L432 AbstractCegarLoop]: Abstraction has 266 states and 306 transitions. [2018-01-24 12:59:10,069 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 12:59:10,069 INFO L276 IsEmpty]: Start isEmpty. Operand 266 states and 306 transitions. [2018-01-24 12:59:10,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-24 12:59:10,070 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:10,070 INFO L322 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:10,070 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:10,071 INFO L82 PathProgramCache]: Analyzing trace with hash -1033282978, now seen corresponding path program 20 times [2018-01-24 12:59:10,071 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:10,071 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:10,071 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:10,072 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:10,072 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:10,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:10,081 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:10,689 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:10,689 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:10,689 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:10,696 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:10,697 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:10,702 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:10,714 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:10,716 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:10,720 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:10,755 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:10,755 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:11,474 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:11,493 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:11,493 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:11,496 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:11,497 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:11,501 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:11,515 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:11,525 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:11,529 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:11,550 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:11,550 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:11,577 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (41)] Exception during sending of exit command (exit): Stream closed [2018-01-24 12:59:11,578 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:11,578 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 43 [2018-01-24 12:59:11,578 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:11,579 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 12:59:11,579 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 12:59:11,580 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 12:59:11,580 INFO L87 Difference]: Start difference. First operand 266 states and 306 transitions. Second operand 23 states. [2018-01-24 12:59:12,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:12,653 INFO L93 Difference]: Finished difference Result 307 states and 350 transitions. [2018-01-24 12:59:12,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 12:59:12,654 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 107 [2018-01-24 12:59:12,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:12,655 INFO L225 Difference]: With dead ends: 307 [2018-01-24 12:59:12,655 INFO L226 Difference]: Without dead ends: 301 [2018-01-24 12:59:12,656 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 404 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 12:59:12,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states. [2018-01-24 12:59:12,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 278. [2018-01-24 12:59:12,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 278 states. [2018-01-24 12:59:12,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 278 states to 278 states and 320 transitions. [2018-01-24 12:59:12,665 INFO L78 Accepts]: Start accepts. Automaton has 278 states and 320 transitions. Word has length 107 [2018-01-24 12:59:12,665 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:12,665 INFO L432 AbstractCegarLoop]: Abstraction has 278 states and 320 transitions. [2018-01-24 12:59:12,665 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 12:59:12,665 INFO L276 IsEmpty]: Start isEmpty. Operand 278 states and 320 transitions. [2018-01-24 12:59:12,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-01-24 12:59:12,666 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:12,666 INFO L322 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:12,666 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:12,666 INFO L82 PathProgramCache]: Analyzing trace with hash -1905968171, now seen corresponding path program 21 times [2018-01-24 12:59:12,666 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:12,667 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:12,667 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:12,667 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:12,667 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:12,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:12,675 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:13,031 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:13,031 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:13,032 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:13,036 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:13,037 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:13,041 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,042 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,043 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,043 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,044 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,045 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,047 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,048 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,049 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,051 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,052 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,054 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,056 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,058 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,061 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,063 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,066 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,069 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,072 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,076 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,081 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,085 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,086 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:13,088 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:13,117 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:13,117 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:13,634 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:13,654 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:13,655 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:13,657 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:13,658 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:13,662 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,664 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,668 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,672 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,678 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,685 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,692 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,701 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,712 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,728 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,746 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,766 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,790 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,817 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,857 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,903 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:13,948 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,001 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,061 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,146 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,241 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,337 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:14,351 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:14,356 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:14,391 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:14,391 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:14,422 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:14,424 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:14,424 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 45 [2018-01-24 12:59:14,424 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:14,424 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 12:59:14,424 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 12:59:14,425 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 12:59:14,425 INFO L87 Difference]: Start difference. First operand 278 states and 320 transitions. Second operand 24 states. [2018-01-24 12:59:15,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:15,658 INFO L93 Difference]: Finished difference Result 320 states and 365 transitions. [2018-01-24 12:59:15,658 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 12:59:15,658 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 112 [2018-01-24 12:59:15,659 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:15,660 INFO L225 Difference]: With dead ends: 320 [2018-01-24 12:59:15,660 INFO L226 Difference]: Without dead ends: 314 [2018-01-24 12:59:15,661 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 423 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 12:59:15,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states. [2018-01-24 12:59:15,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 290. [2018-01-24 12:59:15,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 290 states. [2018-01-24 12:59:15,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290 states to 290 states and 334 transitions. [2018-01-24 12:59:15,671 INFO L78 Accepts]: Start accepts. Automaton has 290 states and 334 transitions. Word has length 112 [2018-01-24 12:59:15,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:15,672 INFO L432 AbstractCegarLoop]: Abstraction has 290 states and 334 transitions. [2018-01-24 12:59:15,672 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 12:59:15,672 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states and 334 transitions. [2018-01-24 12:59:15,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-01-24 12:59:15,673 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:15,673 INFO L322 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:15,673 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:15,673 INFO L82 PathProgramCache]: Analyzing trace with hash -994136898, now seen corresponding path program 22 times [2018-01-24 12:59:15,673 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:15,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:15,674 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:15,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:15,674 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:15,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:15,680 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:16,045 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:16,046 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:16,046 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:16,050 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:59:16,051 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:59:16,077 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:16,080 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:16,113 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:16,113 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:16,739 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:16,759 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:16,759 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:16,762 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:59:16,762 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:59:16,883 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:16,888 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:16,918 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:16,918 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:16,953 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:16,955 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:16,955 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 47 [2018-01-24 12:59:16,955 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:16,955 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 12:59:16,956 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 12:59:16,956 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 12:59:16,956 INFO L87 Difference]: Start difference. First operand 290 states and 334 transitions. Second operand 25 states. [2018-01-24 12:59:18,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:18,193 INFO L93 Difference]: Finished difference Result 333 states and 380 transitions. [2018-01-24 12:59:18,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 12:59:18,193 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 117 [2018-01-24 12:59:18,194 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:18,195 INFO L225 Difference]: With dead ends: 333 [2018-01-24 12:59:18,195 INFO L226 Difference]: Without dead ends: 327 [2018-01-24 12:59:18,195 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 442 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 12:59:18,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states. [2018-01-24 12:59:18,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 302. [2018-01-24 12:59:18,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 302 states. [2018-01-24 12:59:18,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 348 transitions. [2018-01-24 12:59:18,203 INFO L78 Accepts]: Start accepts. Automaton has 302 states and 348 transitions. Word has length 117 [2018-01-24 12:59:18,203 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:18,203 INFO L432 AbstractCegarLoop]: Abstraction has 302 states and 348 transitions. [2018-01-24 12:59:18,203 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 12:59:18,203 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 348 transitions. [2018-01-24 12:59:18,204 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-24 12:59:18,204 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:18,204 INFO L322 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:18,204 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:18,205 INFO L82 PathProgramCache]: Analyzing trace with hash 1248093557, now seen corresponding path program 23 times [2018-01-24 12:59:18,205 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:18,205 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:18,206 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:18,206 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:18,206 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:18,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:18,215 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:18,555 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:18,556 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:18,556 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:18,560 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:59:18,560 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:18,564 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,565 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,566 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,567 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,568 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,569 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,570 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,571 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,573 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,574 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,576 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,578 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,580 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,583 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,586 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,589 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,592 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,596 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,600 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,605 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,610 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,615 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,621 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,628 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:18,629 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:18,631 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:18,652 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:18,652 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:19,222 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:19,241 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:19,261 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:19,265 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 12:59:19,265 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:19,270 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,272 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,277 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,282 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,289 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,298 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,307 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,318 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,333 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,356 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,378 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,398 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,421 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,448 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,489 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,538 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,581 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,631 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,685 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,772 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,878 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:19,959 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:20,046 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:20,142 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:20,165 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:20,170 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:20,199 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:20,199 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:20,234 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:20,236 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:20,236 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 49 [2018-01-24 12:59:20,236 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:20,237 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 12:59:20,237 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 12:59:20,237 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 12:59:20,238 INFO L87 Difference]: Start difference. First operand 302 states and 348 transitions. Second operand 26 states. [2018-01-24 12:59:21,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:21,628 INFO L93 Difference]: Finished difference Result 346 states and 395 transitions. [2018-01-24 12:59:21,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 12:59:21,628 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 122 [2018-01-24 12:59:21,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:21,629 INFO L225 Difference]: With dead ends: 346 [2018-01-24 12:59:21,630 INFO L226 Difference]: Without dead ends: 340 [2018-01-24 12:59:21,630 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 511 GetRequests, 461 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 12:59:21,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states. [2018-01-24 12:59:21,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 314. [2018-01-24 12:59:21,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 314 states. [2018-01-24 12:59:21,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 314 states to 314 states and 362 transitions. [2018-01-24 12:59:21,638 INFO L78 Accepts]: Start accepts. Automaton has 314 states and 362 transitions. Word has length 122 [2018-01-24 12:59:21,638 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:21,638 INFO L432 AbstractCegarLoop]: Abstraction has 314 states and 362 transitions. [2018-01-24 12:59:21,638 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 12:59:21,638 INFO L276 IsEmpty]: Start isEmpty. Operand 314 states and 362 transitions. [2018-01-24 12:59:21,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-01-24 12:59:21,639 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:21,639 INFO L322 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:21,639 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:21,639 INFO L82 PathProgramCache]: Analyzing trace with hash -1210546402, now seen corresponding path program 24 times [2018-01-24 12:59:21,639 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:21,640 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:21,640 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:21,640 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:21,640 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:21,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:21,647 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:22,074 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:22,074 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:22,074 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:22,081 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:59:22,081 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:59:22,085 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,087 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,088 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,089 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,090 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,091 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,092 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,093 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,096 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,098 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,100 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,102 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,104 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,106 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,108 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,111 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,114 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,117 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,120 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,124 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,129 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,135 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,141 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,146 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,153 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:22,155 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:22,158 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:22,182 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:22,182 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:23,344 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:23,364 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:23,365 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:23,368 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 12:59:23,368 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 12:59:23,373 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,375 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,378 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,383 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,387 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,393 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,400 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,410 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,422 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,438 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,461 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,485 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,515 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,550 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,585 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,625 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,674 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,738 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,812 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:23,895 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:24,009 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:24,206 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:24,433 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:24,694 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:24,924 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 12:59:24,941 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:24,946 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:24,971 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:24,971 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:25,013 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:25,014 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:25,015 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 51 [2018-01-24 12:59:25,015 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:25,015 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 12:59:25,015 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 12:59:25,016 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 12:59:25,016 INFO L87 Difference]: Start difference. First operand 314 states and 362 transitions. Second operand 27 states. [2018-01-24 12:59:26,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:26,531 INFO L93 Difference]: Finished difference Result 359 states and 410 transitions. [2018-01-24 12:59:26,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 12:59:26,532 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 127 [2018-01-24 12:59:26,532 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:26,533 INFO L225 Difference]: With dead ends: 359 [2018-01-24 12:59:26,533 INFO L226 Difference]: Without dead ends: 353 [2018-01-24 12:59:26,535 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 532 GetRequests, 480 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 12:59:26,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353 states. [2018-01-24 12:59:26,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353 to 326. [2018-01-24 12:59:26,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 326 states. [2018-01-24 12:59:26,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 376 transitions. [2018-01-24 12:59:26,548 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 376 transitions. Word has length 127 [2018-01-24 12:59:26,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:26,548 INFO L432 AbstractCegarLoop]: Abstraction has 326 states and 376 transitions. [2018-01-24 12:59:26,548 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 12:59:26,548 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 376 transitions. [2018-01-24 12:59:26,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-01-24 12:59:26,550 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:26,550 INFO L322 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:26,550 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:26,550 INFO L82 PathProgramCache]: Analyzing trace with hash 53741333, now seen corresponding path program 25 times [2018-01-24 12:59:26,550 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:26,551 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:26,551 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:26,551 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:26,551 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:26,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:26,561 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:27,124 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:27,124 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:27,124 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:27,130 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:27,130 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:27,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:27,155 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:27,206 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:27,206 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:27,917 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:27,941 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:27,941 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:27,944 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:27,944 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 12:59:27,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:27,978 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:28,003 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:28,004 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:28,038 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:28,039 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:28,039 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 53 [2018-01-24 12:59:28,039 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:28,039 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 12:59:28,040 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 12:59:28,040 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 12:59:28,040 INFO L87 Difference]: Start difference. First operand 326 states and 376 transitions. Second operand 28 states. [2018-01-24 12:59:29,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:29,611 INFO L93 Difference]: Finished difference Result 372 states and 425 transitions. [2018-01-24 12:59:29,611 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 12:59:29,611 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 132 [2018-01-24 12:59:29,612 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:29,613 INFO L225 Difference]: With dead ends: 372 [2018-01-24 12:59:29,613 INFO L226 Difference]: Without dead ends: 366 [2018-01-24 12:59:29,614 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 499 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 12:59:29,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states. [2018-01-24 12:59:29,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 338. [2018-01-24 12:59:29,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 338 states. [2018-01-24 12:59:29,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 338 states to 338 states and 390 transitions. [2018-01-24 12:59:29,622 INFO L78 Accepts]: Start accepts. Automaton has 338 states and 390 transitions. Word has length 132 [2018-01-24 12:59:29,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:29,622 INFO L432 AbstractCegarLoop]: Abstraction has 338 states and 390 transitions. [2018-01-24 12:59:29,622 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 12:59:29,623 INFO L276 IsEmpty]: Start isEmpty. Operand 338 states and 390 transitions. [2018-01-24 12:59:29,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-01-24 12:59:29,623 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:29,624 INFO L322 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:29,624 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:29,624 INFO L82 PathProgramCache]: Analyzing trace with hash -173217410, now seen corresponding path program 26 times [2018-01-24 12:59:29,624 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:29,624 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:29,625 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 12:59:29,625 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:29,625 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:29,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:29,632 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:30,020 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:30,020 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:30,020 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:30,025 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:30,025 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:30,029 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:30,039 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:30,040 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:30,043 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:30,079 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:30,079 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:30,863 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:30,883 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:30,883 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:30,886 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 12:59:30,886 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 12:59:30,891 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:30,908 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 12:59:30,921 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:30,925 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:30,957 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:30,958 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:30,994 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:30,995 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:30,995 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 55 [2018-01-24 12:59:30,996 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:30,996 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 12:59:30,996 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 12:59:30,997 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 12:59:30,997 INFO L87 Difference]: Start difference. First operand 338 states and 390 transitions. Second operand 29 states. [2018-01-24 12:59:32,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:32,687 INFO L93 Difference]: Finished difference Result 385 states and 440 transitions. [2018-01-24 12:59:32,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 12:59:32,687 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 137 [2018-01-24 12:59:32,688 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:32,689 INFO L225 Difference]: With dead ends: 385 [2018-01-24 12:59:32,689 INFO L226 Difference]: Without dead ends: 379 [2018-01-24 12:59:32,690 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 574 GetRequests, 518 SyntacticMatches, 2 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 12:59:32,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379 states. [2018-01-24 12:59:32,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379 to 350. [2018-01-24 12:59:32,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 350 states. [2018-01-24 12:59:32,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 350 states to 350 states and 404 transitions. [2018-01-24 12:59:32,704 INFO L78 Accepts]: Start accepts. Automaton has 350 states and 404 transitions. Word has length 137 [2018-01-24 12:59:32,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:32,704 INFO L432 AbstractCegarLoop]: Abstraction has 350 states and 404 transitions. [2018-01-24 12:59:32,704 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-24 12:59:32,705 INFO L276 IsEmpty]: Start isEmpty. Operand 350 states and 404 transitions. [2018-01-24 12:59:32,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-01-24 12:59:32,706 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:32,706 INFO L322 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:32,706 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:32,707 INFO L82 PathProgramCache]: Analyzing trace with hash 681451701, now seen corresponding path program 27 times [2018-01-24 12:59:32,707 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:32,707 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:32,708 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:32,708 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:32,708 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:32,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:32,719 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:33,426 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:33,426 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:33,426 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:33,431 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:33,432 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:33,438 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,440 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,441 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,443 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,444 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,446 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,448 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,450 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,452 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,454 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,457 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,460 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,463 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,467 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,471 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,476 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,480 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,485 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,490 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,497 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,504 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,510 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,518 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,525 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,534 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,542 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,549 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,555 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:33,557 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:33,560 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:33,587 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:33,588 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:34,489 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:34,509 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:34,509 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:34,512 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 12:59:34,512 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 12:59:34,517 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,518 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,522 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,526 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,532 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,538 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,546 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,555 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,566 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,582 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,601 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,621 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,645 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,672 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,711 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,756 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,800 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,852 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,912 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:34,996 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:35,088 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:35,182 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:35,290 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:35,407 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:35,571 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:35,753 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:35,928 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:36,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 12:59:36,154 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:36,159 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:36,203 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:36,203 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:36,238 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:36,240 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:36,240 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 57 [2018-01-24 12:59:36,240 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:36,241 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 12:59:36,241 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 12:59:36,242 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=897, Invalid=2409, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 12:59:36,242 INFO L87 Difference]: Start difference. First operand 350 states and 404 transitions. Second operand 30 states. [2018-01-24 12:59:38,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:38,049 INFO L93 Difference]: Finished difference Result 398 states and 455 transitions. [2018-01-24 12:59:38,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-24 12:59:38,049 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 142 [2018-01-24 12:59:38,050 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:38,051 INFO L225 Difference]: With dead ends: 398 [2018-01-24 12:59:38,051 INFO L226 Difference]: Without dead ends: 392 [2018-01-24 12:59:38,052 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 595 GetRequests, 537 SyntacticMatches, 2 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=897, Invalid=2409, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 12:59:38,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states. [2018-01-24 12:59:38,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 362. [2018-01-24 12:59:38,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 362 states. [2018-01-24 12:59:38,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 362 states to 362 states and 418 transitions. [2018-01-24 12:59:38,060 INFO L78 Accepts]: Start accepts. Automaton has 362 states and 418 transitions. Word has length 142 [2018-01-24 12:59:38,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:38,061 INFO L432 AbstractCegarLoop]: Abstraction has 362 states and 418 transitions. [2018-01-24 12:59:38,061 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 12:59:38,061 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states and 418 transitions. [2018-01-24 12:59:38,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2018-01-24 12:59:38,062 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:38,062 INFO L322 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:38,062 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:38,062 INFO L82 PathProgramCache]: Analyzing trace with hash 1555157982, now seen corresponding path program 28 times [2018-01-24 12:59:38,062 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:38,063 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:38,063 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:38,063 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:38,063 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:38,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:38,070 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 12:59:38,546 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:38,547 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:38,547 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 12:59:38,551 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:59:38,552 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:59:38,589 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:38,592 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:38,626 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:38,626 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:39,471 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:39,490 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 12:59:39,490 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 12:59:39,519 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 12:59:39,520 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 12:59:39,717 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 12:59:39,722 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 12:59:39,752 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:39,752 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 12:59:39,790 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 12:59:39,792 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 12:59:39,792 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 59 [2018-01-24 12:59:39,792 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 12:59:39,793 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-24 12:59:39,793 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-24 12:59:39,793 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=958, Invalid=2582, Unknown=0, NotChecked=0, Total=3540 [2018-01-24 12:59:39,793 INFO L87 Difference]: Start difference. First operand 362 states and 418 transitions. Second operand 31 states. [2018-01-24 12:59:41,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 12:59:41,659 INFO L93 Difference]: Finished difference Result 411 states and 470 transitions. [2018-01-24 12:59:41,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-24 12:59:41,660 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 147 [2018-01-24 12:59:41,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 12:59:41,661 INFO L225 Difference]: With dead ends: 411 [2018-01-24 12:59:41,661 INFO L226 Difference]: Without dead ends: 405 [2018-01-24 12:59:41,662 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 616 GetRequests, 556 SyntacticMatches, 2 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=958, Invalid=2582, Unknown=0, NotChecked=0, Total=3540 [2018-01-24 12:59:41,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 405 states. [2018-01-24 12:59:41,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 405 to 374. [2018-01-24 12:59:41,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 374 states. [2018-01-24 12:59:41,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 374 states to 374 states and 432 transitions. [2018-01-24 12:59:41,671 INFO L78 Accepts]: Start accepts. Automaton has 374 states and 432 transitions. Word has length 147 [2018-01-24 12:59:41,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 12:59:41,672 INFO L432 AbstractCegarLoop]: Abstraction has 374 states and 432 transitions. [2018-01-24 12:59:41,672 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-01-24 12:59:41,672 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states and 432 transitions. [2018-01-24 12:59:41,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-01-24 12:59:41,673 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 12:59:41,673 INFO L322 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1] [2018-01-24 12:59:41,673 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 12:59:41,673 INFO L82 PathProgramCache]: Analyzing trace with hash 1978446421, now seen corresponding path program 29 times [2018-01-24 12:59:41,673 INFO L67 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-01-24 12:59:41,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:41,674 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 12:59:41,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 12:59:41,674 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 12:59:41,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 12:59:41,682 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. Received shutdown request... [2018-01-24 12:59:41,702 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: Timeout exceeded at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.walkLeafNode(Interpolator.java:265) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.access$1(Interpolator.java:263) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator$ProofTreeWalker.walk(Interpolator.java:132) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:122) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:113) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.interpolate(Interpolator.java:220) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.getInterpolants(Interpolator.java:201) at de.uni_freiburg.informatik.ultimate.smtinterpol.smtlib2.SMTInterpol.getInterpolants(SMTInterpol.java:915) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.managedscript.ManagedScript.getInterpolants(ManagedScript.java:192) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.NestedInterpolantsBuilder.computeCraigInterpolants(NestedInterpolantsBuilder.java:279) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.NestedInterpolantsBuilder.(NestedInterpolantsBuilder.java:162) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.computeInterpolantsTree(InterpolatingTraceCheckCraig.java:263) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.computeInterpolants(InterpolatingTraceCheckCraig.java:199) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.(InterpolatingTraceCheckCraig.java:106) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructCraig(TraceCheckConstructor.java:222) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:179) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseTaipanRefinementStrategy.getTraceCheck(BaseTaipanRefinementStrategy.java:213) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:231) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:205) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:68) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:368) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:381) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:316) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:294) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:149) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:113) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:117) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:324) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.runToolchainDefault(DefaultToolchainJob.java:221) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.BasicToolchainJob.run(BasicToolchainJob.java:134) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) [2018-01-24 12:59:41,705 INFO L168 Benchmark]: Toolchain (without parser) took 52436.39 ms. Allocated memory was 304.1 MB in the beginning and 728.2 MB in the end (delta: 424.1 MB). Free memory was 265.1 MB in the beginning and 364.9 MB in the end (delta: -99.8 MB). Peak memory consumption was 324.4 MB. Max. memory is 5.3 GB. [2018-01-24 12:59:41,707 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 304.1 MB. Free memory is still 269.1 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 12:59:41,707 INFO L168 Benchmark]: CACSL2BoogieTranslator took 174.50 ms. Allocated memory is still 304.1 MB. Free memory was 263.1 MB in the beginning and 255.2 MB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 5.3 GB. [2018-01-24 12:59:41,707 INFO L168 Benchmark]: Boogie Preprocessor took 27.43 ms. Allocated memory is still 304.1 MB. Free memory is still 255.2 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 12:59:41,707 INFO L168 Benchmark]: RCFGBuilder took 180.54 ms. Allocated memory is still 304.1 MB. Free memory was 255.2 MB in the beginning and 242.6 MB in the end (delta: 12.6 MB). Peak memory consumption was 12.6 MB. Max. memory is 5.3 GB. [2018-01-24 12:59:41,708 INFO L168 Benchmark]: TraceAbstraction took 52046.57 ms. Allocated memory was 304.1 MB in the beginning and 728.2 MB in the end (delta: 424.1 MB). Free memory was 242.6 MB in the beginning and 364.9 MB in the end (delta: -122.3 MB). Peak memory consumption was 301.8 MB. Max. memory is 5.3 GB. [2018-01-24 12:59:41,710 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 304.1 MB. Free memory is still 269.1 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 174.50 ms. Allocated memory is still 304.1 MB. Free memory was 263.1 MB in the beginning and 255.2 MB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 27.43 ms. Allocated memory is still 304.1 MB. Free memory is still 255.2 MB. There was no memory consumed. Max. memory is 5.3 GB. * RCFGBuilder took 180.54 ms. Allocated memory is still 304.1 MB. Free memory was 255.2 MB in the beginning and 242.6 MB in the end (delta: 12.6 MB). Peak memory consumption was 12.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 52046.57 ms. Allocated memory was 304.1 MB in the beginning and 728.2 MB in the end (delta: 424.1 MB). Free memory was 242.6 MB in the beginning and 364.9 MB in the end (delta: -122.3 MB). Peak memory consumption was 301.8 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: Timeout exceeded de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: Timeout exceeded: de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.walkLeafNode(Interpolator.java:265) RESULT: Ultimate could not prove your program: Toolchain returned no result. Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_RubberTaipan+AI_EQ.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_12-59-41-718.csv Completed graceful shutdown