java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/memsafety/20051113-1.c_false-valid-memtrack.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 15:28:24,521 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 15:28:24,522 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 15:28:24,537 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 15:28:24,538 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 15:28:24,539 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 15:28:24,540 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 15:28:24,542 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 15:28:24,544 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 15:28:24,544 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 15:28:24,545 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 15:28:24,545 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 15:28:24,547 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 15:28:24,548 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 15:28:24,549 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 15:28:24,552 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 15:28:24,555 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 15:28:24,557 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 15:28:24,558 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 15:28:24,560 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 15:28:24,562 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-01-24 15:28:24,568 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 15:28:24,568 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 15:28:24,569 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf [2018-01-24 15:28:24,579 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 15:28:24,580 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 15:28:24,581 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 15:28:24,581 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 15:28:24,581 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 15:28:24,581 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 15:28:24,581 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 15:28:24,582 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 15:28:24,582 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 15:28:24,583 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 15:28:24,583 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 15:28:24,583 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 15:28:24,583 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 15:28:24,583 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 15:28:24,583 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 15:28:24,584 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 15:28:24,584 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 15:28:24,584 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 15:28:24,584 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 15:28:24,584 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 15:28:24,584 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 15:28:24,585 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 15:28:24,585 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 15:28:24,585 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 15:28:24,585 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 15:28:24,585 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 15:28:24,586 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 15:28:24,586 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 15:28:24,586 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 15:28:24,586 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 15:28:24,586 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 15:28:24,586 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 15:28:24,586 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 15:28:24,587 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 15:28:24,587 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 15:28:24,620 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 15:28:24,631 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 15:28:24,635 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 15:28:24,637 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 15:28:24,637 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 15:28:24,638 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/memsafety/20051113-1.c_false-valid-memtrack.i [2018-01-24 15:28:24,795 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 15:28:24,800 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 15:28:24,801 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 15:28:24,801 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 15:28:24,806 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 15:28:24,807 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 03:28:24" (1/1) ... [2018-01-24 15:28:24,810 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7856df24 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:28:24, skipping insertion in model container [2018-01-24 15:28:24,810 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 03:28:24" (1/1) ... [2018-01-24 15:28:24,824 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 15:28:24,865 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 15:28:24,994 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 15:28:25,019 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 15:28:25,028 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:28:25 WrapperNode [2018-01-24 15:28:25,029 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 15:28:25,029 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 15:28:25,030 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 15:28:25,030 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 15:28:25,046 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:28:25" (1/1) ... [2018-01-24 15:28:25,047 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:28:25" (1/1) ... [2018-01-24 15:28:25,056 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:28:25" (1/1) ... [2018-01-24 15:28:25,056 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:28:25" (1/1) ... [2018-01-24 15:28:25,062 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:28:25" (1/1) ... [2018-01-24 15:28:25,066 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:28:25" (1/1) ... [2018-01-24 15:28:25,068 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:28:25" (1/1) ... [2018-01-24 15:28:25,070 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 15:28:25,071 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 15:28:25,071 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 15:28:25,071 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 15:28:25,072 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:28:25" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 15:28:25,125 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 15:28:25,125 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 15:28:25,125 INFO L136 BoogieDeclarations]: Found implementation of procedure Sum [2018-01-24 15:28:25,125 INFO L136 BoogieDeclarations]: Found implementation of procedure Sum2 [2018-01-24 15:28:25,125 INFO L136 BoogieDeclarations]: Found implementation of procedure dummy_abort [2018-01-24 15:28:25,125 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 15:28:25,126 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 15:28:25,126 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 15:28:25,126 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 15:28:25,126 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 15:28:25,126 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 15:28:25,126 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-01-24 15:28:25,126 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-01-24 15:28:25,126 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-01-24 15:28:25,126 INFO L128 BoogieDeclarations]: Found specification of procedure Sum [2018-01-24 15:28:25,126 INFO L128 BoogieDeclarations]: Found specification of procedure Sum2 [2018-01-24 15:28:25,127 INFO L128 BoogieDeclarations]: Found specification of procedure dummy_abort [2018-01-24 15:28:25,127 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 15:28:25,127 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 15:28:25,127 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 15:28:25,304 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-01-24 15:28:25,536 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 15:28:25,537 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 03:28:25 BoogieIcfgContainer [2018-01-24 15:28:25,537 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 15:28:25,538 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 15:28:25,538 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 15:28:25,540 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 15:28:25,541 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 03:28:24" (1/3) ... [2018-01-24 15:28:25,542 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6a478c0d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 03:28:25, skipping insertion in model container [2018-01-24 15:28:25,542 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:28:25" (2/3) ... [2018-01-24 15:28:25,543 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6a478c0d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 03:28:25, skipping insertion in model container [2018-01-24 15:28:25,543 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 03:28:25" (3/3) ... [2018-01-24 15:28:25,545 INFO L105 eAbstractionObserver]: Analyzing ICFG 20051113-1.c_false-valid-memtrack.i [2018-01-24 15:28:25,555 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 15:28:25,564 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 25 error locations. [2018-01-24 15:28:25,620 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 15:28:25,620 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 15:28:25,621 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 15:28:25,621 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 15:28:25,621 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 15:28:25,621 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 15:28:25,621 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 15:28:25,621 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 15:28:25,622 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 15:28:25,648 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states. [2018-01-24 15:28:25,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 15:28:25,657 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:25,662 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:25,663 INFO L371 AbstractCegarLoop]: === Iteration 1 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:25,668 INFO L82 PathProgramCache]: Analyzing trace with hash -1274877597, now seen corresponding path program 1 times [2018-01-24 15:28:25,671 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:25,734 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:25,734 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:25,734 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:25,734 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:25,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:25,787 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:25,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:28:25,862 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:28:25,863 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 15:28:25,863 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:28:25,867 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 15:28:25,877 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 15:28:25,878 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 15:28:25,880 INFO L87 Difference]: Start difference. First operand 80 states. Second operand 4 states. [2018-01-24 15:28:26,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:26,126 INFO L93 Difference]: Finished difference Result 111 states and 123 transitions. [2018-01-24 15:28:26,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 15:28:26,229 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 8 [2018-01-24 15:28:26,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:26,237 INFO L225 Difference]: With dead ends: 111 [2018-01-24 15:28:26,237 INFO L226 Difference]: Without dead ends: 69 [2018-01-24 15:28:26,240 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 15:28:26,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-01-24 15:28:26,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2018-01-24 15:28:26,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-01-24 15:28:26,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 74 transitions. [2018-01-24 15:28:26,275 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 74 transitions. Word has length 8 [2018-01-24 15:28:26,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:26,275 INFO L432 AbstractCegarLoop]: Abstraction has 69 states and 74 transitions. [2018-01-24 15:28:26,275 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 15:28:26,275 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 74 transitions. [2018-01-24 15:28:26,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 15:28:26,275 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:26,276 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:26,276 INFO L371 AbstractCegarLoop]: === Iteration 2 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:26,276 INFO L82 PathProgramCache]: Analyzing trace with hash -1274877596, now seen corresponding path program 1 times [2018-01-24 15:28:26,276 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:26,277 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:26,278 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:26,278 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:26,278 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:26,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:26,294 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:26,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:28:26,359 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:28:26,359 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 15:28:26,360 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:28:26,361 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 15:28:26,361 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 15:28:26,361 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 15:28:26,362 INFO L87 Difference]: Start difference. First operand 69 states and 74 transitions. Second operand 4 states. [2018-01-24 15:28:26,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:26,489 INFO L93 Difference]: Finished difference Result 69 states and 74 transitions. [2018-01-24 15:28:26,490 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 15:28:26,490 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 8 [2018-01-24 15:28:26,491 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:26,492 INFO L225 Difference]: With dead ends: 69 [2018-01-24 15:28:26,492 INFO L226 Difference]: Without dead ends: 61 [2018-01-24 15:28:26,493 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 15:28:26,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-01-24 15:28:26,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2018-01-24 15:28:26,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-01-24 15:28:26,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 66 transitions. [2018-01-24 15:28:26,504 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 66 transitions. Word has length 8 [2018-01-24 15:28:26,504 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:26,504 INFO L432 AbstractCegarLoop]: Abstraction has 61 states and 66 transitions. [2018-01-24 15:28:26,504 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 15:28:26,505 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 66 transitions. [2018-01-24 15:28:26,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-24 15:28:26,506 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:26,506 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:26,506 INFO L371 AbstractCegarLoop]: === Iteration 3 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:26,506 INFO L82 PathProgramCache]: Analyzing trace with hash -1852712777, now seen corresponding path program 1 times [2018-01-24 15:28:26,507 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:26,508 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:26,508 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:26,508 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:26,508 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:26,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:26,533 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:26,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:28:26,604 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:28:26,604 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 15:28:26,604 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:28:26,605 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 15:28:26,605 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 15:28:26,605 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 15:28:26,605 INFO L87 Difference]: Start difference. First operand 61 states and 66 transitions. Second operand 5 states. [2018-01-24 15:28:26,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:26,719 INFO L93 Difference]: Finished difference Result 61 states and 66 transitions. [2018-01-24 15:28:26,719 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 15:28:26,719 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2018-01-24 15:28:26,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:26,721 INFO L225 Difference]: With dead ends: 61 [2018-01-24 15:28:26,721 INFO L226 Difference]: Without dead ends: 59 [2018-01-24 15:28:26,721 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:28:26,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-01-24 15:28:26,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2018-01-24 15:28:26,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2018-01-24 15:28:26,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 64 transitions. [2018-01-24 15:28:26,730 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 64 transitions. Word has length 25 [2018-01-24 15:28:26,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:26,731 INFO L432 AbstractCegarLoop]: Abstraction has 59 states and 64 transitions. [2018-01-24 15:28:26,731 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 15:28:26,731 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 64 transitions. [2018-01-24 15:28:26,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-24 15:28:26,732 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:26,732 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:26,732 INFO L371 AbstractCegarLoop]: === Iteration 4 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:26,733 INFO L82 PathProgramCache]: Analyzing trace with hash -1852712776, now seen corresponding path program 1 times [2018-01-24 15:28:26,733 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:26,734 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:26,734 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:26,734 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:26,734 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:26,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:26,757 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:26,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:28:26,906 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:28:26,906 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 15:28:26,907 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:28:26,907 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 15:28:26,907 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 15:28:26,908 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:28:26,908 INFO L87 Difference]: Start difference. First operand 59 states and 64 transitions. Second operand 6 states. [2018-01-24 15:28:27,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:27,035 INFO L93 Difference]: Finished difference Result 59 states and 64 transitions. [2018-01-24 15:28:27,035 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 15:28:27,035 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-01-24 15:28:27,035 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:27,036 INFO L225 Difference]: With dead ends: 59 [2018-01-24 15:28:27,036 INFO L226 Difference]: Without dead ends: 58 [2018-01-24 15:28:27,037 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-24 15:28:27,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-01-24 15:28:27,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 58. [2018-01-24 15:28:27,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-01-24 15:28:27,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 63 transitions. [2018-01-24 15:28:27,046 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 63 transitions. Word has length 25 [2018-01-24 15:28:27,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:27,046 INFO L432 AbstractCegarLoop]: Abstraction has 58 states and 63 transitions. [2018-01-24 15:28:27,046 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 15:28:27,046 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 63 transitions. [2018-01-24 15:28:27,047 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 15:28:27,047 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:27,048 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:27,048 INFO L371 AbstractCegarLoop]: === Iteration 5 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:27,048 INFO L82 PathProgramCache]: Analyzing trace with hash 1954449657, now seen corresponding path program 1 times [2018-01-24 15:28:27,048 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:27,049 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:27,049 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:27,050 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:27,050 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:27,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:27,076 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:27,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:28:27,470 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:28:27,470 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-01-24 15:28:27,470 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:28:27,471 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 15:28:27,471 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 15:28:27,471 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-01-24 15:28:27,471 INFO L87 Difference]: Start difference. First operand 58 states and 63 transitions. Second operand 9 states. [2018-01-24 15:28:27,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:27,759 INFO L93 Difference]: Finished difference Result 93 states and 102 transitions. [2018-01-24 15:28:27,760 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 15:28:27,760 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 27 [2018-01-24 15:28:27,760 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:27,761 INFO L225 Difference]: With dead ends: 93 [2018-01-24 15:28:27,761 INFO L226 Difference]: Without dead ends: 64 [2018-01-24 15:28:27,761 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 1 SyntacticMatches, 6 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-01-24 15:28:27,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-01-24 15:28:27,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 62. [2018-01-24 15:28:27,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-01-24 15:28:27,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 67 transitions. [2018-01-24 15:28:27,767 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 67 transitions. Word has length 27 [2018-01-24 15:28:27,767 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:27,768 INFO L432 AbstractCegarLoop]: Abstraction has 62 states and 67 transitions. [2018-01-24 15:28:27,768 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 15:28:27,768 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 67 transitions. [2018-01-24 15:28:27,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-01-24 15:28:27,768 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:27,768 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:27,769 INFO L371 AbstractCegarLoop]: === Iteration 6 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:27,769 INFO L82 PathProgramCache]: Analyzing trace with hash 1339860797, now seen corresponding path program 1 times [2018-01-24 15:28:27,769 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:27,770 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:27,770 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:27,770 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:27,770 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:27,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:27,790 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:27,940 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:28:27,940 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:27,940 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:27,941 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 34 with the following transitions: [2018-01-24 15:28:27,942 INFO L201 CegarAbsIntRunner]: [24], [25], [31], [32], [34], [38], [39], [46], [47], [49], [50], [52], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [105], [106], [110], [111], [112], [120], [121], [122] [2018-01-24 15:28:27,988 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:28:27,988 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:28:28,407 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:28:28,408 INFO L268 AbstractInterpreter]: Visited 30 different actions 37 times. Merged at 7 different actions 7 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 19 variables. [2018-01-24 15:28:28,422 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:28:28,422 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:28,422 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:28,475 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:28,476 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:28:28,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:28,510 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:28,587 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 15:28:28,587 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:28,755 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 15:28:28,777 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 15:28:28,777 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4, 4] imperfect sequences [6] total 11 [2018-01-24 15:28:28,777 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:28:28,778 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 15:28:28,778 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 15:28:28,778 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-01-24 15:28:28,778 INFO L87 Difference]: Start difference. First operand 62 states and 67 transitions. Second operand 4 states. [2018-01-24 15:28:28,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:28,834 INFO L93 Difference]: Finished difference Result 114 states and 124 transitions. [2018-01-24 15:28:28,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 15:28:28,835 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 33 [2018-01-24 15:28:28,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:28,836 INFO L225 Difference]: With dead ends: 114 [2018-01-24 15:28:28,837 INFO L226 Difference]: Without dead ends: 63 [2018-01-24 15:28:28,837 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 61 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2018-01-24 15:28:28,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-01-24 15:28:28,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2018-01-24 15:28:28,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-01-24 15:28:28,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-01-24 15:28:28,845 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 33 [2018-01-24 15:28:28,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:28,846 INFO L432 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-01-24 15:28:28,846 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 15:28:28,846 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-01-24 15:28:28,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-24 15:28:28,847 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:28,847 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:28,848 INFO L371 AbstractCegarLoop]: === Iteration 7 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:28,848 INFO L82 PathProgramCache]: Analyzing trace with hash 1619594826, now seen corresponding path program 1 times [2018-01-24 15:28:28,848 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:28,849 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:28,849 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:28,849 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:28,849 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:28,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:28,869 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:29,098 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-01-24 15:28:29,098 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:29,098 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:29,098 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 35 with the following transitions: [2018-01-24 15:28:29,099 INFO L201 CegarAbsIntRunner]: [24], [25], [29], [31], [32], [34], [38], [39], [46], [47], [49], [50], [52], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [105], [106], [110], [111], [112], [120], [121], [122] [2018-01-24 15:28:29,102 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:28:29,102 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:28:29,758 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:28:29,758 INFO L268 AbstractInterpreter]: Visited 31 different actions 46 times. Merged at 10 different actions 13 times. Never widened. Found 4 fixpoints after 3 different actions. Largest state had 19 variables. [2018-01-24 15:28:29,760 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:28:29,761 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:29,761 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:29,773 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:29,774 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:28:29,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:29,802 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:29,854 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 15:28:29,855 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:29,961 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 15:28:29,982 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:29,982 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 4 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:29,986 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:29,986 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:28:30,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:30,037 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:30,042 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 15:28:30,043 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:30,083 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 15:28:30,085 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:30,085 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5, 5, 5] total 13 [2018-01-24 15:28:30,085 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:30,086 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 15:28:30,086 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 15:28:30,086 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2018-01-24 15:28:30,086 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 10 states. [2018-01-24 15:28:30,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:30,273 INFO L93 Difference]: Finished difference Result 126 states and 138 transitions. [2018-01-24 15:28:30,274 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 15:28:30,274 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 34 [2018-01-24 15:28:30,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:30,276 INFO L225 Difference]: With dead ends: 126 [2018-01-24 15:28:30,276 INFO L226 Difference]: Without dead ends: 75 [2018-01-24 15:28:30,276 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 146 GetRequests, 128 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=53, Invalid=219, Unknown=0, NotChecked=0, Total=272 [2018-01-24 15:28:30,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-01-24 15:28:30,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 70. [2018-01-24 15:28:30,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-24 15:28:30,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 76 transitions. [2018-01-24 15:28:30,285 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 76 transitions. Word has length 34 [2018-01-24 15:28:30,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:30,285 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 76 transitions. [2018-01-24 15:28:30,285 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 15:28:30,285 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 76 transitions. [2018-01-24 15:28:30,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 15:28:30,287 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:30,287 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:30,287 INFO L371 AbstractCegarLoop]: === Iteration 8 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:30,287 INFO L82 PathProgramCache]: Analyzing trace with hash -341936469, now seen corresponding path program 1 times [2018-01-24 15:28:30,287 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:30,288 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:30,288 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:30,289 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:30,289 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:30,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:30,305 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:30,379 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 15:28:30,380 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:28:30,380 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 15:28:30,380 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:28:30,380 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 15:28:30,381 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 15:28:30,381 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 15:28:30,381 INFO L87 Difference]: Start difference. First operand 70 states and 76 transitions. Second operand 5 states. [2018-01-24 15:28:30,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:30,433 INFO L93 Difference]: Finished difference Result 70 states and 76 transitions. [2018-01-24 15:28:30,433 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 15:28:30,433 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2018-01-24 15:28:30,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:30,434 INFO L225 Difference]: With dead ends: 70 [2018-01-24 15:28:30,435 INFO L226 Difference]: Without dead ends: 68 [2018-01-24 15:28:30,435 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:28:30,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-01-24 15:28:30,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 68. [2018-01-24 15:28:30,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68 states. [2018-01-24 15:28:30,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 74 transitions. [2018-01-24 15:28:30,443 INFO L78 Accepts]: Start accepts. Automaton has 68 states and 74 transitions. Word has length 42 [2018-01-24 15:28:30,443 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:30,444 INFO L432 AbstractCegarLoop]: Abstraction has 68 states and 74 transitions. [2018-01-24 15:28:30,444 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 15:28:30,444 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 74 transitions. [2018-01-24 15:28:30,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 15:28:30,445 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:30,445 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:30,445 INFO L371 AbstractCegarLoop]: === Iteration 9 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:30,446 INFO L82 PathProgramCache]: Analyzing trace with hash -341936468, now seen corresponding path program 1 times [2018-01-24 15:28:30,446 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:30,447 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:30,447 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:30,447 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:30,447 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:30,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:30,465 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:30,542 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 15:28:30,543 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:28:30,543 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 15:28:30,543 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:28:30,543 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 15:28:30,543 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 15:28:30,544 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:28:30,544 INFO L87 Difference]: Start difference. First operand 68 states and 74 transitions. Second operand 6 states. [2018-01-24 15:28:30,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:30,680 INFO L93 Difference]: Finished difference Result 68 states and 74 transitions. [2018-01-24 15:28:30,680 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 15:28:30,680 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 42 [2018-01-24 15:28:30,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:30,682 INFO L225 Difference]: With dead ends: 68 [2018-01-24 15:28:30,682 INFO L226 Difference]: Without dead ends: 67 [2018-01-24 15:28:30,682 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-24 15:28:30,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-01-24 15:28:30,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2018-01-24 15:28:30,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-01-24 15:28:30,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 73 transitions. [2018-01-24 15:28:30,689 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 73 transitions. Word has length 42 [2018-01-24 15:28:30,690 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:30,690 INFO L432 AbstractCegarLoop]: Abstraction has 67 states and 73 transitions. [2018-01-24 15:28:30,690 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 15:28:30,690 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 73 transitions. [2018-01-24 15:28:30,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 15:28:30,691 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:30,692 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:30,692 INFO L371 AbstractCegarLoop]: === Iteration 10 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:30,692 INFO L82 PathProgramCache]: Analyzing trace with hash -614912991, now seen corresponding path program 2 times [2018-01-24 15:28:30,692 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:30,693 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:30,693 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:30,693 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:30,694 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:30,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:30,709 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:30,946 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 15:28:30,947 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:30,947 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:30,947 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:28:30,947 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:28:30,947 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:30,947 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:30,956 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:28:30,957 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:28:30,978 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:30,996 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:31,009 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:31,012 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:31,108 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 15:28:31,108 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:31,372 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 15:28:31,393 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:31,404 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:31,408 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:28:31,408 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:28:31,428 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:31,466 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:31,484 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:31,489 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:31,495 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 15:28:31,495 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:31,521 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 15:28:31,523 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:31,523 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6, 6, 6] total 16 [2018-01-24 15:28:31,523 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:31,524 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 15:28:31,524 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 15:28:31,524 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=189, Unknown=0, NotChecked=0, Total=240 [2018-01-24 15:28:31,524 INFO L87 Difference]: Start difference. First operand 67 states and 73 transitions. Second operand 12 states. [2018-01-24 15:28:31,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:31,832 INFO L93 Difference]: Finished difference Result 136 states and 150 transitions. [2018-01-24 15:28:31,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 15:28:31,832 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 41 [2018-01-24 15:28:31,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:31,833 INFO L225 Difference]: With dead ends: 136 [2018-01-24 15:28:31,834 INFO L226 Difference]: Without dead ends: 82 [2018-01-24 15:28:31,834 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 176 GetRequests, 154 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=75, Invalid=345, Unknown=0, NotChecked=0, Total=420 [2018-01-24 15:28:31,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-01-24 15:28:31,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 74. [2018-01-24 15:28:31,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-24 15:28:31,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 81 transitions. [2018-01-24 15:28:31,842 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 81 transitions. Word has length 41 [2018-01-24 15:28:31,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:31,842 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 81 transitions. [2018-01-24 15:28:31,843 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 15:28:31,843 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 81 transitions. [2018-01-24 15:28:31,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-01-24 15:28:31,844 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:31,844 INFO L322 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:31,844 INFO L371 AbstractCegarLoop]: === Iteration 11 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:31,845 INFO L82 PathProgramCache]: Analyzing trace with hash 1732121728, now seen corresponding path program 1 times [2018-01-24 15:28:31,845 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:31,845 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:31,846 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:28:31,846 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:31,846 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:31,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:31,863 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:32,202 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-01-24 15:28:32,202 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:32,202 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:32,202 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 46 with the following transitions: [2018-01-24 15:28:32,203 INFO L201 CegarAbsIntRunner]: [0], [4], [5], [12], [15], [24], [25], [29], [31], [32], [34], [38], [39], [44], [46], [47], [50], [52], [56], [57], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [91], [105], [106], [110], [111], [112], [113], [116], [120], [121], [122] [2018-01-24 15:28:32,204 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:28:32,205 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:28:32,734 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:28:32,734 INFO L268 AbstractInterpreter]: Visited 41 different actions 60 times. Merged at 13 different actions 16 times. Never widened. Found 5 fixpoints after 4 different actions. Largest state had 20 variables. [2018-01-24 15:28:32,746 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:28:32,746 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:32,746 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:32,756 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:32,756 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:28:32,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:32,789 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:32,862 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 15:28:32,862 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:32,964 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 15:28:32,985 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:32,985 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:32,988 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:32,988 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:28:33,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:33,026 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:33,033 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 15:28:33,033 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:33,055 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 15:28:33,057 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:33,057 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 7, 7, 7, 7] total 22 [2018-01-24 15:28:33,057 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:33,057 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 15:28:33,057 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 15:28:33,058 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=378, Unknown=0, NotChecked=0, Total=462 [2018-01-24 15:28:33,058 INFO L87 Difference]: Start difference. First operand 74 states and 81 transitions. Second operand 17 states. [2018-01-24 15:28:33,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:33,349 INFO L93 Difference]: Finished difference Result 144 states and 160 transitions. [2018-01-24 15:28:33,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 15:28:33,349 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 45 [2018-01-24 15:28:33,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:33,350 INFO L225 Difference]: With dead ends: 144 [2018-01-24 15:28:33,350 INFO L226 Difference]: Without dead ends: 84 [2018-01-24 15:28:33,351 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 168 SyntacticMatches, 10 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 108 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=116, Invalid=586, Unknown=0, NotChecked=0, Total=702 [2018-01-24 15:28:33,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-01-24 15:28:33,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 79. [2018-01-24 15:28:33,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-01-24 15:28:33,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 87 transitions. [2018-01-24 15:28:33,359 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 87 transitions. Word has length 45 [2018-01-24 15:28:33,359 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:33,359 INFO L432 AbstractCegarLoop]: Abstraction has 79 states and 87 transitions. [2018-01-24 15:28:33,359 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 15:28:33,359 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 87 transitions. [2018-01-24 15:28:33,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-01-24 15:28:33,361 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:33,361 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:33,361 INFO L371 AbstractCegarLoop]: === Iteration 12 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:33,361 INFO L82 PathProgramCache]: Analyzing trace with hash -117713403, now seen corresponding path program 3 times [2018-01-24 15:28:33,361 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:33,362 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:33,362 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:33,363 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:33,363 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:33,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:33,395 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:33,815 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 17 proven. 13 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 15:28:33,815 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:33,815 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:33,816 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:28:33,816 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:28:33,816 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:33,816 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:33,823 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:28:33,823 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:28:33,834 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:33,845 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:33,846 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:33,850 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:33,871 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 15:28:33,873 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:33,876 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:33,877 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-01-24 15:28:33,938 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 15:28:33,939 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 15:28:33,940 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:33,941 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:33,945 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:33,945 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:20, output treesize:16 [2018-01-24 15:28:33,971 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 15:28:33,973 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:33,974 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:33,975 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 15:28:33,975 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,000 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,005 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,006 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:29, output treesize:25 [2018-01-24 15:28:34,029 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 15:28:34,048 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,049 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,050 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,050 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,051 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,052 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,052 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 15:28:34,053 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,063 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,070 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,070 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:38, output treesize:34 [2018-01-24 15:28:34,108 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 15:28:34,111 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,111 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,112 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,113 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,113 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,114 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,115 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,115 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,116 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,117 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,117 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,118 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,119 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 15:28:34,119 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,139 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,147 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,147 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:47, output treesize:43 [2018-01-24 15:28:34,185 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 15:28:34,198 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,202 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,205 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,206 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,207 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,208 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,208 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,209 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,210 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,211 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,212 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,213 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,214 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,215 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,216 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,217 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,218 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 15:28:34,219 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,262 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,271 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,271 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:56, output treesize:52 [2018-01-24 15:28:34,320 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 15:28:34,325 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,326 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,327 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,328 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,329 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,330 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,340 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,341 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,342 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,343 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,344 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,345 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,346 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,349 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,357 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,358 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,359 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,365 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,367 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,368 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,381 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,382 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 15:28:34,384 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,441 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,452 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,452 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:65, output treesize:61 [2018-01-24 15:28:34,492 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 15:28:34,496 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,497 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,497 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,498 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,499 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,499 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,500 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,501 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,501 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,502 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,503 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,503 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,504 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,504 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,505 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,506 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,506 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,507 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,507 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,508 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,508 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,509 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,510 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,511 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,511 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,512 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,513 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,514 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 15:28:34,515 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,563 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,583 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,584 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-01-24 15:28:34,883 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 53 [2018-01-24 15:28:34,909 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,913 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,914 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,915 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,916 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,917 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,918 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,919 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,920 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,921 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,921 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,922 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,923 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,923 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,924 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,925 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,925 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,926 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,927 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,928 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,929 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,930 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,930 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,931 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,932 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,932 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,933 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:34,934 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 7 select indices, 7 select index equivalence classes, 27 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 160 [2018-01-24 15:28:34,935 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,961 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:34,968 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 15:28:34,968 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:90, output treesize:25 [2018-01-24 15:28:35,046 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 10 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 15:28:35,047 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:36,218 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 15:28:36,251 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:36,251 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:36,255 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:28:36,255 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:28:36,273 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:36,297 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:36,320 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:36,326 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:36,329 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 15:28:36,329 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,331 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,332 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-01-24 15:28:36,459 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 15:28:36,469 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 15:28:36,493 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,498 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,512 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,512 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:20, output treesize:16 [2018-01-24 15:28:36,587 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 15:28:36,590 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,590 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,591 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 15:28:36,591 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,603 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,607 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,608 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:29, output treesize:25 [2018-01-24 15:28:36,648 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 15:28:36,650 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,651 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,651 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,652 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,652 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,653 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,653 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 15:28:36,653 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,661 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,667 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,667 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:38, output treesize:34 [2018-01-24 15:28:36,705 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 15:28:36,707 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,708 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,708 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,709 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,709 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,710 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,710 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,711 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,711 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,712 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,713 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,718 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,719 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 15:28:36,719 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,735 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,741 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,741 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:47, output treesize:43 [2018-01-24 15:28:36,787 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 15:28:36,790 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,790 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,791 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,792 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,792 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,793 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,793 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,794 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,794 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,795 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,795 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,796 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,796 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,797 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,797 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,798 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,799 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 15:28:36,799 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,820 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,828 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,829 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:56, output treesize:52 [2018-01-24 15:28:36,879 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 15:28:36,881 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,882 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,883 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,883 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,884 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,885 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,886 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,886 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,887 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,888 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,888 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,889 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,890 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,890 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,891 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,892 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,892 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,893 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,894 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,894 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,895 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:36,896 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 15:28:36,896 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,928 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,937 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:36,937 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:65, output treesize:61 [2018-01-24 15:28:37,014 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 15:28:37,016 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,017 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,018 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,018 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,019 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,019 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,020 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,020 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,021 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,021 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,022 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,022 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,023 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,023 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,024 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,024 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,025 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,025 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,026 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,026 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,027 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,027 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,028 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,028 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,029 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,030 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,030 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,031 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 15:28:37,032 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:37,083 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:37,096 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:37,096 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-01-24 15:28:37,378 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 41 [2018-01-24 15:28:37,381 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,381 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,382 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,383 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,383 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,384 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:37,385 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 27 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 43 [2018-01-24 15:28:37,385 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:37,394 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:37,400 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 15:28:37,400 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:78, output treesize:25 [2018-01-24 15:28:37,497 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 10 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 15:28:37,497 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:38,221 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 15:28:38,223 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:38,223 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 17, 10, 17, 10] total 54 [2018-01-24 15:28:38,223 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:38,224 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 15:28:38,224 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 15:28:38,225 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=2520, Unknown=1, NotChecked=0, Total=2862 [2018-01-24 15:28:38,225 INFO L87 Difference]: Start difference. First operand 79 states and 87 transitions. Second operand 30 states. [2018-01-24 15:28:39,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:39,901 INFO L93 Difference]: Finished difference Result 113 states and 126 transitions. [2018-01-24 15:28:39,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 15:28:39,902 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 49 [2018-01-24 15:28:39,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:39,903 INFO L225 Difference]: With dead ends: 113 [2018-01-24 15:28:39,903 INFO L226 Difference]: Without dead ends: 77 [2018-01-24 15:28:39,904 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 235 GetRequests, 136 SyntacticMatches, 28 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2186 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=795, Invalid=4460, Unknown=1, NotChecked=0, Total=5256 [2018-01-24 15:28:39,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-01-24 15:28:39,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2018-01-24 15:28:39,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-01-24 15:28:39,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 84 transitions. [2018-01-24 15:28:39,912 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 84 transitions. Word has length 49 [2018-01-24 15:28:39,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:39,912 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 84 transitions. [2018-01-24 15:28:39,913 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 15:28:39,913 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 84 transitions. [2018-01-24 15:28:39,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 15:28:39,914 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:39,914 INFO L322 BasicCegarLoop]: trace histogram [4, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:39,914 INFO L371 AbstractCegarLoop]: === Iteration 13 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:39,915 INFO L82 PathProgramCache]: Analyzing trace with hash 2106198684, now seen corresponding path program 1 times [2018-01-24 15:28:39,915 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:39,915 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:39,916 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:28:39,916 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:39,916 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:39,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:39,928 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:39,978 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-01-24 15:28:39,978 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:28:39,978 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 15:28:39,978 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:28:39,979 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 15:28:39,979 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 15:28:39,979 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 15:28:39,979 INFO L87 Difference]: Start difference. First operand 77 states and 84 transitions. Second operand 5 states. [2018-01-24 15:28:40,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:40,006 INFO L93 Difference]: Finished difference Result 86 states and 93 transitions. [2018-01-24 15:28:40,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 15:28:40,006 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2018-01-24 15:28:40,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:40,007 INFO L225 Difference]: With dead ends: 86 [2018-01-24 15:28:40,007 INFO L226 Difference]: Without dead ends: 83 [2018-01-24 15:28:40,007 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:28:40,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-01-24 15:28:40,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 82. [2018-01-24 15:28:40,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-24 15:28:40,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 89 transitions. [2018-01-24 15:28:40,015 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 89 transitions. Word has length 52 [2018-01-24 15:28:40,015 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:40,015 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 89 transitions. [2018-01-24 15:28:40,016 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 15:28:40,016 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 89 transitions. [2018-01-24 15:28:40,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 15:28:40,017 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:40,017 INFO L322 BasicCegarLoop]: trace histogram [4, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:40,017 INFO L371 AbstractCegarLoop]: === Iteration 14 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:40,018 INFO L82 PathProgramCache]: Analyzing trace with hash 1604645521, now seen corresponding path program 1 times [2018-01-24 15:28:40,018 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:40,019 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:40,019 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:40,019 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:40,019 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:40,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:40,034 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:40,308 WARN L146 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 21 DAG size of output 14 [2018-01-24 15:28:40,626 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-01-24 15:28:40,634 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:40,634 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:40,635 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 53 with the following transitions: [2018-01-24 15:28:40,635 INFO L201 CegarAbsIntRunner]: [0], [4], [5], [12], [13], [15], [16], [18], [24], [25], [29], [31], [32], [34], [38], [39], [44], [46], [47], [50], [52], [56], [57], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [91], [105], [106], [110], [111], [112], [113], [116], [120], [121], [122] [2018-01-24 15:28:40,637 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:28:40,638 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:28:41,438 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:28:41,438 INFO L268 AbstractInterpreter]: Visited 44 different actions 70 times. Merged at 20 different actions 23 times. Never widened. Found 6 fixpoints after 5 different actions. Largest state had 20 variables. [2018-01-24 15:28:41,455 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:28:41,455 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:41,455 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:41,468 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:41,468 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:28:41,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:41,617 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:42,029 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 15:28:42,030 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:42,350 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 15:28:42,394 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:42,395 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) [2018-01-24 15:28:42,413 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:42,413 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:42,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:42,532 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:42,560 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 15:28:42,561 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:42,681 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 15:28:42,684 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:42,684 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8, 8, 8] total 25 [2018-01-24 15:28:42,685 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:42,685 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 15:28:42,685 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 15:28:42,686 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=490, Unknown=0, NotChecked=0, Total=600 [2018-01-24 15:28:42,686 INFO L87 Difference]: Start difference. First operand 82 states and 89 transitions. Second operand 19 states. [2018-01-24 15:28:43,279 WARN L146 SmtUtils]: Spent 134ms on a formula simplification. DAG size of input: 31 DAG size of output 30 [2018-01-24 15:28:43,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:43,481 INFO L93 Difference]: Finished difference Result 151 states and 166 transitions. [2018-01-24 15:28:43,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 15:28:43,482 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 52 [2018-01-24 15:28:43,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:43,483 INFO L225 Difference]: With dead ends: 151 [2018-01-24 15:28:43,483 INFO L226 Difference]: Without dead ends: 84 [2018-01-24 15:28:43,483 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 194 SyntacticMatches, 8 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 153 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=174, Invalid=882, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 15:28:43,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-01-24 15:28:43,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 81. [2018-01-24 15:28:43,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-01-24 15:28:43,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 88 transitions. [2018-01-24 15:28:43,490 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 88 transitions. Word has length 52 [2018-01-24 15:28:43,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:43,490 INFO L432 AbstractCegarLoop]: Abstraction has 81 states and 88 transitions. [2018-01-24 15:28:43,490 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 15:28:43,491 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 88 transitions. [2018-01-24 15:28:43,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-01-24 15:28:43,491 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:43,492 INFO L322 BasicCegarLoop]: trace histogram [5, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:43,492 INFO L371 AbstractCegarLoop]: === Iteration 15 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:43,492 INFO L82 PathProgramCache]: Analyzing trace with hash -544800124, now seen corresponding path program 1 times [2018-01-24 15:28:43,492 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:43,493 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:43,493 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:43,493 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:43,493 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:43,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:43,504 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:43,635 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-01-24 15:28:43,636 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:43,636 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:43,636 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 57 with the following transitions: [2018-01-24 15:28:43,636 INFO L201 CegarAbsIntRunner]: [0], [4], [5], [10], [22], [23], [24], [25], [29], [31], [32], [33], [34], [38], [39], [44], [46], [47], [50], [52], [56], [57], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [91], [94], [97], [102], [104], [105], [106], [110], [111], [112], [113], [116], [117], [118], [119], [120], [121], [122] [2018-01-24 15:28:43,638 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:28:43,638 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:28:43,984 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:28:43,984 INFO L268 AbstractInterpreter]: Visited 50 different actions 69 times. Merged at 13 different actions 16 times. Never widened. Found 5 fixpoints after 4 different actions. Largest state had 20 variables. [2018-01-24 15:28:43,990 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:28:43,990 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:43,990 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:44,005 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:44,005 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:28:44,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:44,038 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:44,156 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 15:28:44,156 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:44,295 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 15:28:44,315 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:44,315 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:44,319 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:44,319 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:28:44,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:44,365 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:44,371 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 15:28:44,371 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:44,420 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 15:28:44,422 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:44,422 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 23 [2018-01-24 15:28:44,423 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:44,423 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 15:28:44,423 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 15:28:44,424 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=124, Invalid=382, Unknown=0, NotChecked=0, Total=506 [2018-01-24 15:28:44,424 INFO L87 Difference]: Start difference. First operand 81 states and 88 transitions. Second operand 16 states. [2018-01-24 15:28:44,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:44,654 INFO L93 Difference]: Finished difference Result 148 states and 162 transitions. [2018-01-24 15:28:44,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 15:28:44,654 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 56 [2018-01-24 15:28:44,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:44,655 INFO L225 Difference]: With dead ends: 148 [2018-01-24 15:28:44,655 INFO L226 Difference]: Without dead ends: 80 [2018-01-24 15:28:44,656 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 242 GetRequests, 208 SyntacticMatches, 10 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=143, Invalid=507, Unknown=0, NotChecked=0, Total=650 [2018-01-24 15:28:44,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-24 15:28:44,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 77. [2018-01-24 15:28:44,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-01-24 15:28:44,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 83 transitions. [2018-01-24 15:28:44,662 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 83 transitions. Word has length 56 [2018-01-24 15:28:44,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:44,662 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 83 transitions. [2018-01-24 15:28:44,663 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 15:28:44,663 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 83 transitions. [2018-01-24 15:28:44,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-01-24 15:28:44,663 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:44,663 INFO L322 BasicCegarLoop]: trace histogram [6, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:44,663 INFO L371 AbstractCegarLoop]: === Iteration 16 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:44,664 INFO L82 PathProgramCache]: Analyzing trace with hash -1454707584, now seen corresponding path program 1 times [2018-01-24 15:28:44,664 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:44,664 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:44,664 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:44,664 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:44,664 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:44,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:44,682 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:44,910 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 15:28:44,910 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:44,911 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:44,911 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 61 with the following transitions: [2018-01-24 15:28:44,911 INFO L201 CegarAbsIntRunner]: [0], [4], [5], [10], [12], [13], [16], [18], [22], [23], [24], [25], [29], [31], [32], [34], [38], [39], [44], [46], [47], [50], [52], [56], [57], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [91], [94], [100], [102], [104], [105], [106], [110], [111], [112], [113], [116], [117], [120], [121], [122] [2018-01-24 15:28:44,912 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:28:44,913 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:28:45,394 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:28:45,394 INFO L268 AbstractInterpreter]: Visited 51 different actions 82 times. Merged at 24 different actions 27 times. Never widened. Found 6 fixpoints after 5 different actions. Largest state had 20 variables. [2018-01-24 15:28:45,410 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:28:45,410 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:45,410 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:45,423 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:45,423 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:28:45,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:45,456 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:45,597 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 15:28:45,598 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:45,757 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 15:28:45,790 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:45,790 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:45,794 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:45,794 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:28:45,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:45,845 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:45,852 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 15:28:45,852 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:45,903 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 15:28:45,904 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:45,904 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10, 10, 10, 10] total 25 [2018-01-24 15:28:45,905 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:45,905 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 15:28:45,905 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 15:28:45,906 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=440, Unknown=0, NotChecked=0, Total=600 [2018-01-24 15:28:45,906 INFO L87 Difference]: Start difference. First operand 77 states and 83 transitions. Second operand 17 states. [2018-01-24 15:28:46,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:46,188 INFO L93 Difference]: Finished difference Result 150 states and 163 transitions. [2018-01-24 15:28:46,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 15:28:46,188 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 60 [2018-01-24 15:28:46,188 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:46,189 INFO L225 Difference]: With dead ends: 150 [2018-01-24 15:28:46,189 INFO L226 Difference]: Without dead ends: 87 [2018-01-24 15:28:46,190 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 222 SyntacticMatches, 8 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 106 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=191, Invalid=621, Unknown=0, NotChecked=0, Total=812 [2018-01-24 15:28:46,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-01-24 15:28:46,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 84. [2018-01-24 15:28:46,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-01-24 15:28:46,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 90 transitions. [2018-01-24 15:28:46,196 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 90 transitions. Word has length 60 [2018-01-24 15:28:46,197 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:46,197 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 90 transitions. [2018-01-24 15:28:46,197 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 15:28:46,197 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 90 transitions. [2018-01-24 15:28:46,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-01-24 15:28:46,197 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:46,197 INFO L322 BasicCegarLoop]: trace histogram [7, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:46,198 INFO L371 AbstractCegarLoop]: === Iteration 17 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:46,198 INFO L82 PathProgramCache]: Analyzing trace with hash -374403177, now seen corresponding path program 2 times [2018-01-24 15:28:46,198 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:46,199 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:46,199 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:46,199 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:46,199 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:46,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:46,214 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:46,500 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 15:28:46,501 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:46,501 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:46,501 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:28:46,501 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:28:46,501 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:46,501 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:46,509 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:28:46,509 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:28:46,607 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:46,620 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:46,621 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:46,623 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:46,693 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 15:28:46,694 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:46,864 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 15:28:46,885 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:46,885 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:46,888 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:28:46,888 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:28:46,911 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:46,945 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:46,963 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:46,968 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:46,973 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 15:28:46,973 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:47,022 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 15:28:47,023 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:47,024 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 11, 11, 11] total 28 [2018-01-24 15:28:47,024 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:47,024 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 15:28:47,024 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 15:28:47,024 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=559, Unknown=0, NotChecked=0, Total=756 [2018-01-24 15:28:47,025 INFO L87 Difference]: Start difference. First operand 84 states and 90 transitions. Second operand 19 states. [2018-01-24 15:28:47,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:47,272 INFO L93 Difference]: Finished difference Result 154 states and 166 transitions. [2018-01-24 15:28:47,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 15:28:47,273 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 67 [2018-01-24 15:28:47,273 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:47,273 INFO L225 Difference]: With dead ends: 154 [2018-01-24 15:28:47,274 INFO L226 Difference]: Without dead ends: 85 [2018-01-24 15:28:47,274 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 288 GetRequests, 250 SyntacticMatches, 8 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 123 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=229, Invalid=763, Unknown=0, NotChecked=0, Total=992 [2018-01-24 15:28:47,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-01-24 15:28:47,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-01-24 15:28:47,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-01-24 15:28:47,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 90 transitions. [2018-01-24 15:28:47,281 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 90 transitions. Word has length 67 [2018-01-24 15:28:47,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:47,282 INFO L432 AbstractCegarLoop]: Abstraction has 85 states and 90 transitions. [2018-01-24 15:28:47,282 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 15:28:47,282 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 90 transitions. [2018-01-24 15:28:47,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-01-24 15:28:47,283 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:47,283 INFO L322 BasicCegarLoop]: trace histogram [8, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:47,283 INFO L371 AbstractCegarLoop]: === Iteration 18 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:47,283 INFO L82 PathProgramCache]: Analyzing trace with hash -1696068192, now seen corresponding path program 3 times [2018-01-24 15:28:47,284 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:47,284 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:47,284 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:28:47,285 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:47,285 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:47,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:47,302 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:47,567 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-01-24 15:28:47,568 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:47,568 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:47,568 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:28:47,568 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:28:47,568 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:47,568 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:47,578 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:28:47,578 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:28:47,596 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:47,610 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:47,622 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:47,624 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:47,628 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:47,670 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 15:28:47,672 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 15:28:47,672 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,674 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,677 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,677 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:15, output treesize:11 [2018-01-24 15:28:47,691 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 15:28:47,693 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,694 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,695 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 15:28:47,695 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,700 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,704 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,704 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:20 [2018-01-24 15:28:47,722 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 15:28:47,724 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,725 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,726 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,727 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,727 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,728 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,728 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 15:28:47,729 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,761 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,767 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,767 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:33, output treesize:29 [2018-01-24 15:28:47,790 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 15:28:47,793 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,794 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,795 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,796 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,796 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,797 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,798 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,798 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,799 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,800 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,800 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,801 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,802 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 15:28:47,802 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,821 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,828 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,828 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-01-24 15:28:47,859 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 15:28:47,863 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,864 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,865 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,866 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,866 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,867 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,868 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,874 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,875 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,876 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,877 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,877 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,878 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,879 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,879 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,883 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,884 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 15:28:47,885 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,913 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,922 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:47,922 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:51, output treesize:47 [2018-01-24 15:28:47,968 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 15:28:47,971 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,971 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,972 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,972 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,973 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,973 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,974 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,975 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,975 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,976 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,976 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,977 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,977 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,978 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,978 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,979 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,980 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,980 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,981 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,981 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,982 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:47,983 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 15:28:47,983 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,020 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,030 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,031 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:60, output treesize:56 [2018-01-24 15:28:48,086 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 15:28:48,089 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,089 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,090 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,091 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,091 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,092 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,092 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,093 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,094 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,094 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,095 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,096 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,096 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,097 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,097 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,098 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,099 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,099 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,100 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,100 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,101 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,102 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,102 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,103 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,104 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,104 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,105 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,106 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 15:28:48,106 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,154 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,166 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,166 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:69, output treesize:65 [2018-01-24 15:28:48,427 WARN L307 Elim1Store]: Array PQE input equivalent to false [2018-01-24 15:28:48,427 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,428 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,428 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:121, output treesize:1 [2018-01-24 15:28:48,442 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 15:28:48,442 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:48,626 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 15:28:48,647 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:48,647 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:48,654 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:28:48,654 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:28:48,683 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:48,714 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:48,798 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:48,837 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:48,844 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:48,854 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 15:28:48,856 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 15:28:48,856 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,857 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,859 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,859 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:15, output treesize:11 [2018-01-24 15:28:48,864 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 15:28:48,865 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,866 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,866 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 15:28:48,867 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,871 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,874 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,874 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:20 [2018-01-24 15:28:48,877 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 15:28:48,879 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,879 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,880 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,881 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,881 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,882 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,882 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 15:28:48,883 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,891 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,895 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,896 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:33, output treesize:29 [2018-01-24 15:28:48,899 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 15:28:48,901 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,902 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,902 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,903 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,903 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,904 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,904 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,905 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,906 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,906 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,907 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,907 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,908 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 15:28:48,908 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,932 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,937 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,938 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-01-24 15:28:48,941 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 15:28:48,942 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,943 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,944 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,944 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,945 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,945 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,946 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,946 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,947 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,948 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,949 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,950 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,950 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,951 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,952 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,952 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,953 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 15:28:48,954 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,980 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,987 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:48,987 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:51, output treesize:47 [2018-01-24 15:28:48,990 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 15:28:48,993 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,993 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,994 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,994 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,995 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,996 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,996 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,997 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,997 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,998 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,998 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:48,999 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,000 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,000 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,001 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,001 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,002 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,003 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,003 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,004 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,005 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,005 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 15:28:49,006 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:49,037 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:49,045 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:49,045 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:60, output treesize:56 [2018-01-24 15:28:49,048 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 15:28:49,051 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,051 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,052 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,053 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,053 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,054 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,054 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,055 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,056 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,056 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,057 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,057 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,058 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,058 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,059 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,059 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,060 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,061 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,061 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,062 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,062 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,063 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,064 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,064 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,065 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,065 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,066 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:28:49,067 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 15:28:49,067 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 15:28:49,108 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:49,118 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:28:49,118 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:69, output treesize:65 [2018-01-24 15:28:49,591 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 15:28:49,592 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:49,806 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 15:28:49,808 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:49,808 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 17, 8, 17, 8] total 42 [2018-01-24 15:28:49,808 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:49,808 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 15:28:49,809 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 15:28:49,809 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=213, Invalid=1509, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 15:28:49,810 INFO L87 Difference]: Start difference. First operand 85 states and 90 transitions. Second operand 28 states. [2018-01-24 15:28:50,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:50,930 INFO L93 Difference]: Finished difference Result 130 states and 139 transitions. [2018-01-24 15:28:50,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 15:28:50,931 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 74 [2018-01-24 15:28:50,931 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:50,932 INFO L225 Difference]: With dead ends: 130 [2018-01-24 15:28:50,932 INFO L226 Difference]: Without dead ends: 94 [2018-01-24 15:28:50,933 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 248 SyntacticMatches, 28 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1458 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=476, Invalid=3556, Unknown=0, NotChecked=0, Total=4032 [2018-01-24 15:28:50,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-01-24 15:28:50,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 91. [2018-01-24 15:28:50,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-01-24 15:28:50,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 95 transitions. [2018-01-24 15:28:50,952 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 95 transitions. Word has length 74 [2018-01-24 15:28:50,952 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:50,952 INFO L432 AbstractCegarLoop]: Abstraction has 91 states and 95 transitions. [2018-01-24 15:28:50,952 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 15:28:50,952 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 95 transitions. [2018-01-24 15:28:50,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-01-24 15:28:50,953 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:50,953 INFO L322 BasicCegarLoop]: trace histogram [8, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:50,953 INFO L371 AbstractCegarLoop]: === Iteration 19 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:50,953 INFO L82 PathProgramCache]: Analyzing trace with hash 1151371872, now seen corresponding path program 4 times [2018-01-24 15:28:50,953 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:50,954 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:50,954 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:28:50,954 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:50,954 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:50,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:50,967 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:51,106 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:51,106 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:51,107 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:51,107 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:28:51,107 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:28:51,107 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:51,107 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:51,116 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:28:51,116 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:28:51,172 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:51,175 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:51,250 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:51,250 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:51,495 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:51,516 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:51,516 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:51,530 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:28:51,531 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:28:51,630 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:51,636 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:51,645 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:51,645 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:51,697 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:51,698 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:51,699 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 32 [2018-01-24 15:28:51,699 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:51,699 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 15:28:51,699 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 15:28:51,700 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=357, Invalid=635, Unknown=0, NotChecked=0, Total=992 [2018-01-24 15:28:51,700 INFO L87 Difference]: Start difference. First operand 91 states and 95 transitions. Second operand 22 states. [2018-01-24 15:28:51,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:51,744 INFO L93 Difference]: Finished difference Result 164 states and 172 transitions. [2018-01-24 15:28:51,744 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 15:28:51,744 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 86 [2018-01-24 15:28:51,744 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:51,745 INFO L225 Difference]: With dead ends: 164 [2018-01-24 15:28:51,745 INFO L226 Difference]: Without dead ends: 92 [2018-01-24 15:28:51,745 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 355 GetRequests, 322 SyntacticMatches, 2 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 374 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=380, Invalid=676, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 15:28:51,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2018-01-24 15:28:51,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 92. [2018-01-24 15:28:51,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-01-24 15:28:51,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 96 transitions. [2018-01-24 15:28:51,751 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 96 transitions. Word has length 86 [2018-01-24 15:28:51,752 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:51,752 INFO L432 AbstractCegarLoop]: Abstraction has 92 states and 96 transitions. [2018-01-24 15:28:51,752 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 15:28:51,752 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 96 transitions. [2018-01-24 15:28:51,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 15:28:51,753 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:51,753 INFO L322 BasicCegarLoop]: trace histogram [9, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:51,753 INFO L371 AbstractCegarLoop]: === Iteration 20 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:51,753 INFO L82 PathProgramCache]: Analyzing trace with hash -1429474957, now seen corresponding path program 5 times [2018-01-24 15:28:51,753 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:51,754 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:51,754 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:28:51,754 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:51,755 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:51,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:51,773 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:51,897 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:51,898 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:51,898 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:51,898 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:28:51,898 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:28:51,898 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:51,898 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:51,904 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:28:51,904 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:28:51,913 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:51,917 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:51,921 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:51,927 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:51,934 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:51,949 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:51,952 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:51,955 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:52,064 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:52,065 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:52,475 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:52,496 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:52,496 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:52,499 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:28:52,499 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:28:52,507 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:52,510 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:52,519 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:52,541 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:52,641 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:53,140 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:53,167 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:53,174 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:53,180 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:53,180 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:53,230 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:53,232 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:53,232 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 35 [2018-01-24 15:28:53,232 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:53,233 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 15:28:53,233 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 15:28:53,233 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=426, Invalid=764, Unknown=0, NotChecked=0, Total=1190 [2018-01-24 15:28:53,233 INFO L87 Difference]: Start difference. First operand 92 states and 96 transitions. Second operand 24 states. [2018-01-24 15:28:53,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:53,273 INFO L93 Difference]: Finished difference Result 165 states and 173 transitions. [2018-01-24 15:28:53,274 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 15:28:53,274 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 87 [2018-01-24 15:28:53,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:53,275 INFO L225 Difference]: With dead ends: 165 [2018-01-24 15:28:53,275 INFO L226 Difference]: Without dead ends: 93 [2018-01-24 15:28:53,276 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 360 GetRequests, 324 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 457 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=451, Invalid=809, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 15:28:53,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-01-24 15:28:53,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2018-01-24 15:28:53,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-01-24 15:28:53,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 97 transitions. [2018-01-24 15:28:53,285 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 97 transitions. Word has length 87 [2018-01-24 15:28:53,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:53,286 INFO L432 AbstractCegarLoop]: Abstraction has 93 states and 97 transitions. [2018-01-24 15:28:53,286 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 15:28:53,286 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 97 transitions. [2018-01-24 15:28:53,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-24 15:28:53,287 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:53,287 INFO L322 BasicCegarLoop]: trace histogram [10, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:53,287 INFO L371 AbstractCegarLoop]: === Iteration 21 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:53,287 INFO L82 PathProgramCache]: Analyzing trace with hash 168651968, now seen corresponding path program 6 times [2018-01-24 15:28:53,287 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:53,288 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:53,289 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:28:53,289 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:53,289 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:53,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:53,306 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:53,830 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:53,830 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:53,830 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:53,831 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:28:53,831 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:28:53,831 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:53,831 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:53,852 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:28:53,852 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:28:53,873 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:28:53,892 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:28:53,908 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:28:53,938 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:28:53,986 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:28:54,117 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:28:54,118 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:54,121 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:54,198 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:54,198 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:54,421 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:54,456 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:54,456 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:54,462 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:28:54,462 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:28:54,490 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:28:54,528 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:28:54,579 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:28:54,854 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:28:55,553 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:28:57,338 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:28:57,370 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:57,376 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:57,386 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:57,386 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:57,448 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:57,449 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:57,450 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 38 [2018-01-24 15:28:57,450 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:57,450 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 15:28:57,450 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 15:28:57,450 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=501, Invalid=905, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 15:28:57,451 INFO L87 Difference]: Start difference. First operand 93 states and 97 transitions. Second operand 26 states. [2018-01-24 15:28:57,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:57,488 INFO L93 Difference]: Finished difference Result 166 states and 174 transitions. [2018-01-24 15:28:57,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 15:28:57,489 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 88 [2018-01-24 15:28:57,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:57,489 INFO L225 Difference]: With dead ends: 166 [2018-01-24 15:28:57,490 INFO L226 Difference]: Without dead ends: 94 [2018-01-24 15:28:57,490 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 365 GetRequests, 326 SyntacticMatches, 2 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 548 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=528, Invalid=954, Unknown=0, NotChecked=0, Total=1482 [2018-01-24 15:28:57,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-01-24 15:28:57,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 94. [2018-01-24 15:28:57,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-01-24 15:28:57,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 98 transitions. [2018-01-24 15:28:57,496 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 98 transitions. Word has length 88 [2018-01-24 15:28:57,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:57,497 INFO L432 AbstractCegarLoop]: Abstraction has 94 states and 98 transitions. [2018-01-24 15:28:57,497 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 15:28:57,497 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 98 transitions. [2018-01-24 15:28:57,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-01-24 15:28:57,497 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:57,497 INFO L322 BasicCegarLoop]: trace histogram [11, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:57,498 INFO L371 AbstractCegarLoop]: === Iteration 22 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:57,498 INFO L82 PathProgramCache]: Analyzing trace with hash -1829020909, now seen corresponding path program 7 times [2018-01-24 15:28:57,498 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:57,499 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:57,499 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:28:57,499 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:57,499 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:57,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:57,518 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:57,690 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:57,690 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:57,690 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:57,690 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:28:57,691 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:28:57,691 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:57,691 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:57,695 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:57,695 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:28:57,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:57,723 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:57,797 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:57,806 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:58,058 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:58,081 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:58,081 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:58,084 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:58,084 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:28:58,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:58,150 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:58,156 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:58,157 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:58,211 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:58,212 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:58,212 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 41 [2018-01-24 15:28:58,213 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:58,213 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 15:28:58,213 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 15:28:58,213 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=582, Invalid=1058, Unknown=0, NotChecked=0, Total=1640 [2018-01-24 15:28:58,214 INFO L87 Difference]: Start difference. First operand 94 states and 98 transitions. Second operand 28 states. [2018-01-24 15:28:58,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:58,257 INFO L93 Difference]: Finished difference Result 167 states and 175 transitions. [2018-01-24 15:28:58,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 15:28:58,257 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 89 [2018-01-24 15:28:58,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:58,258 INFO L225 Difference]: With dead ends: 167 [2018-01-24 15:28:58,258 INFO L226 Difference]: Without dead ends: 95 [2018-01-24 15:28:58,259 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 370 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 647 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=611, Invalid=1111, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 15:28:58,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2018-01-24 15:28:58,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2018-01-24 15:28:58,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-01-24 15:28:58,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 99 transitions. [2018-01-24 15:28:58,268 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 99 transitions. Word has length 89 [2018-01-24 15:28:58,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:58,268 INFO L432 AbstractCegarLoop]: Abstraction has 95 states and 99 transitions. [2018-01-24 15:28:58,269 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 15:28:58,269 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 99 transitions. [2018-01-24 15:28:58,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-01-24 15:28:58,270 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:58,270 INFO L322 BasicCegarLoop]: trace histogram [12, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:58,270 INFO L371 AbstractCegarLoop]: === Iteration 23 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:58,270 INFO L82 PathProgramCache]: Analyzing trace with hash 667629344, now seen corresponding path program 8 times [2018-01-24 15:28:58,270 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:58,271 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:58,271 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:28:58,271 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:58,271 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:58,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:58,290 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:58,473 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:58,474 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:58,474 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:58,474 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:28:58,474 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:28:58,474 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:58,474 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:58,480 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:28:58,480 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:28:58,494 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:58,509 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:58,511 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:58,514 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:58,596 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:58,596 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:58,851 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:58,871 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:58,871 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:28:58,874 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:28:58,874 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:28:58,897 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:58,937 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:28:58,959 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:58,965 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:58,971 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:58,971 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:28:59,031 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:59,032 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:28:59,032 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 44 [2018-01-24 15:28:59,032 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:28:59,032 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 15:28:59,033 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 15:28:59,033 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=669, Invalid=1223, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 15:28:59,033 INFO L87 Difference]: Start difference. First operand 95 states and 99 transitions. Second operand 30 states. [2018-01-24 15:28:59,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:28:59,077 INFO L93 Difference]: Finished difference Result 168 states and 176 transitions. [2018-01-24 15:28:59,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 15:28:59,078 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 90 [2018-01-24 15:28:59,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:28:59,078 INFO L225 Difference]: With dead ends: 168 [2018-01-24 15:28:59,078 INFO L226 Difference]: Without dead ends: 96 [2018-01-24 15:28:59,079 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 375 GetRequests, 330 SyntacticMatches, 2 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 754 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=700, Invalid=1280, Unknown=0, NotChecked=0, Total=1980 [2018-01-24 15:28:59,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-01-24 15:28:59,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 96. [2018-01-24 15:28:59,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-01-24 15:28:59,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 100 transitions. [2018-01-24 15:28:59,088 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 100 transitions. Word has length 90 [2018-01-24 15:28:59,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:28:59,088 INFO L432 AbstractCegarLoop]: Abstraction has 96 states and 100 transitions. [2018-01-24 15:28:59,088 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 15:28:59,088 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 100 transitions. [2018-01-24 15:28:59,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-01-24 15:28:59,089 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:28:59,089 INFO L322 BasicCegarLoop]: trace histogram [13, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:28:59,089 INFO L371 AbstractCegarLoop]: === Iteration 24 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 15:28:59,090 INFO L82 PathProgramCache]: Analyzing trace with hash 754375859, now seen corresponding path program 9 times [2018-01-24 15:28:59,090 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:28:59,091 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:59,091 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:28:59,091 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:28:59,091 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:28:59,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:28:59,111 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:28:59,386 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:59,387 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:59,387 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:28:59,387 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:28:59,387 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:28:59,387 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:28:59,387 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:28:59,393 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:28:59,393 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:28:59,418 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:59,439 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:59,467 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:59,492 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:59,542 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:59,602 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:59,802 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:59,884 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:28:59,885 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:28:59,889 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:28:59,985 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:28:59,985 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:29:00,268 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:29:00,289 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:29:00,289 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:29:00,292 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:29:00,293 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:29:00,322 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:29:00,351 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:29:00,424 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:29:00,585 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command Received shutdown request... [2018-01-24 15:29:12,599 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command Cannot interrupt operation gracefully because timeout expired. Forcing shutdown