java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test15_false-valid-memtrack.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 15:54:15,933 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 15:54:15,935 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 15:54:15,949 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 15:54:15,949 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 15:54:15,950 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 15:54:15,951 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 15:54:15,953 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 15:54:15,954 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 15:54:15,955 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 15:54:15,956 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 15:54:15,956 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 15:54:15,957 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 15:54:15,958 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 15:54:15,959 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 15:54:15,961 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 15:54:15,963 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 15:54:15,965 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 15:54:15,967 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 15:54:15,968 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 15:54:15,970 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 15:54:15,970 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 15:54:15,970 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 15:54:15,971 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 15:54:15,972 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 15:54:15,973 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 15:54:15,973 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 15:54:15,974 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 15:54:15,974 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 15:54:15,974 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 15:54:15,975 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 15:54:15,975 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf [2018-01-24 15:54:15,983 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 15:54:15,983 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 15:54:15,984 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 15:54:15,984 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 15:54:15,984 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 15:54:15,984 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 15:54:15,985 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 15:54:15,985 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 15:54:15,985 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 15:54:15,985 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 15:54:15,985 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 15:54:15,985 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 15:54:15,986 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 15:54:15,986 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 15:54:15,986 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 15:54:15,986 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 15:54:15,986 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 15:54:15,986 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 15:54:15,986 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 15:54:15,986 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 15:54:15,987 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 15:54:15,987 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 15:54:15,987 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 15:54:15,987 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 15:54:15,987 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 15:54:15,988 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 15:54:15,988 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 15:54:15,988 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 15:54:15,988 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 15:54:15,988 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 15:54:15,988 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 15:54:15,988 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 15:54:15,988 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 15:54:15,989 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 15:54:15,989 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 15:54:16,020 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 15:54:16,031 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 15:54:16,035 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 15:54:16,036 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 15:54:16,036 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 15:54:16,037 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test15_false-valid-memtrack.i [2018-01-24 15:54:16,219 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 15:54:16,224 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 15:54:16,225 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 15:54:16,225 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 15:54:16,230 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 15:54:16,231 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 03:54:16" (1/1) ... [2018-01-24 15:54:16,234 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@76fa0af6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:54:16, skipping insertion in model container [2018-01-24 15:54:16,234 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 03:54:16" (1/1) ... [2018-01-24 15:54:16,248 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 15:54:16,299 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 15:54:16,428 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 15:54:16,460 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 15:54:16,475 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:54:16 WrapperNode [2018-01-24 15:54:16,475 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 15:54:16,475 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 15:54:16,476 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 15:54:16,476 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 15:54:16,487 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:54:16" (1/1) ... [2018-01-24 15:54:16,487 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:54:16" (1/1) ... [2018-01-24 15:54:16,498 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:54:16" (1/1) ... [2018-01-24 15:54:16,499 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:54:16" (1/1) ... [2018-01-24 15:54:16,510 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:54:16" (1/1) ... [2018-01-24 15:54:16,514 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:54:16" (1/1) ... [2018-01-24 15:54:16,516 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:54:16" (1/1) ... [2018-01-24 15:54:16,520 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 15:54:16,520 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 15:54:16,521 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 15:54:16,521 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 15:54:16,522 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:54:16" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 15:54:16,569 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 15:54:16,569 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 15:54:16,569 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_nonpositive [2018-01-24 15:54:16,569 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-01-24 15:54:16,570 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-01-24 15:54:16,570 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-01-24 15:54:16,570 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_hid_get_drvdata [2018-01-24 15:54:16,570 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_hid_set_drvdata [2018-01-24 15:54:16,570 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_init_arvo_device_struct [2018-01-24 15:54:16,570 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_init_specials_unsafe [2018-01-24 15:54:16,571 INFO L136 BoogieDeclarations]: Found implementation of procedure lvd_arvo_remove_specials [2018-01-24 15:54:16,571 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_probe_unsafe [2018-01-24 15:54:16,571 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_remove [2018-01-24 15:54:16,571 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-01-24 15:54:16,571 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 15:54:16,571 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 15:54:16,572 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 15:54:16,572 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-01-24 15:54:16,572 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-01-24 15:54:16,572 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 15:54:16,572 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 15:54:16,572 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 15:54:16,573 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-01-24 15:54:16,573 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-01-24 15:54:16,573 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-01-24 15:54:16,573 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-01-24 15:54:16,573 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 15:54:16,574 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_nonpositive [2018-01-24 15:54:16,574 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-01-24 15:54:16,574 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-01-24 15:54:16,574 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-01-24 15:54:16,574 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_hid_get_drvdata [2018-01-24 15:54:16,574 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_hid_set_drvdata [2018-01-24 15:54:16,574 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_init_arvo_device_struct [2018-01-24 15:54:16,575 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_init_specials_unsafe [2018-01-24 15:54:16,575 INFO L128 BoogieDeclarations]: Found specification of procedure lvd_arvo_remove_specials [2018-01-24 15:54:16,575 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_probe_unsafe [2018-01-24 15:54:16,575 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_remove [2018-01-24 15:54:16,575 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-01-24 15:54:16,575 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 15:54:16,576 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 15:54:16,576 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 15:54:17,146 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 15:54:17,147 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 03:54:17 BoogieIcfgContainer [2018-01-24 15:54:17,147 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 15:54:17,148 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 15:54:17,148 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 15:54:17,151 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 15:54:17,151 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 03:54:16" (1/3) ... [2018-01-24 15:54:17,152 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@216181ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 03:54:17, skipping insertion in model container [2018-01-24 15:54:17,153 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:54:16" (2/3) ... [2018-01-24 15:54:17,153 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@216181ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 03:54:17, skipping insertion in model container [2018-01-24 15:54:17,153 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 03:54:17" (3/3) ... [2018-01-24 15:54:17,155 INFO L105 eAbstractionObserver]: Analyzing ICFG memleaks_test15_false-valid-memtrack.i [2018-01-24 15:54:17,164 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 15:54:17,171 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 45 error locations. [2018-01-24 15:54:17,227 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 15:54:17,227 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 15:54:17,227 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 15:54:17,228 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 15:54:17,228 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 15:54:17,228 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 15:54:17,228 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 15:54:17,228 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 15:54:17,229 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 15:54:17,256 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states. [2018-01-24 15:54:17,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-01-24 15:54:17,263 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:54:17,264 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:54:17,265 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-01-24 15:54:17,270 INFO L82 PathProgramCache]: Analyzing trace with hash 462743197, now seen corresponding path program 1 times [2018-01-24 15:54:17,273 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:54:17,326 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:17,326 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:54:17,326 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:17,327 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:54:17,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:17,398 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:54:17,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:54:17,609 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:54:17,610 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 15:54:17,610 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:54:17,612 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 15:54:17,622 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 15:54:17,623 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:54:17,625 INFO L87 Difference]: Start difference. First operand 165 states. Second operand 6 states. [2018-01-24 15:54:17,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:54:17,726 INFO L93 Difference]: Finished difference Result 172 states and 184 transitions. [2018-01-24 15:54:17,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 15:54:17,728 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-01-24 15:54:17,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:54:17,739 INFO L225 Difference]: With dead ends: 172 [2018-01-24 15:54:17,739 INFO L226 Difference]: Without dead ends: 162 [2018-01-24 15:54:17,742 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 15:54:17,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-01-24 15:54:17,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2018-01-24 15:54:17,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-01-24 15:54:17,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 174 transitions. [2018-01-24 15:54:17,791 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 174 transitions. Word has length 22 [2018-01-24 15:54:17,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:54:17,793 INFO L432 AbstractCegarLoop]: Abstraction has 162 states and 174 transitions. [2018-01-24 15:54:17,793 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 15:54:17,794 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 174 transitions. [2018-01-24 15:54:17,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-01-24 15:54:17,795 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:54:17,796 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:54:17,796 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-01-24 15:54:17,796 INFO L82 PathProgramCache]: Analyzing trace with hash -844495449, now seen corresponding path program 1 times [2018-01-24 15:54:17,796 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:54:17,798 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:17,798 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:54:17,798 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:17,799 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:54:17,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:17,827 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:54:17,923 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 15:54:17,923 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:54:17,923 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 15:54:17,923 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:54:17,924 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 15:54:17,925 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 15:54:17,925 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:54:17,925 INFO L87 Difference]: Start difference. First operand 162 states and 174 transitions. Second operand 6 states. [2018-01-24 15:54:18,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:54:18,070 INFO L93 Difference]: Finished difference Result 169 states and 180 transitions. [2018-01-24 15:54:18,070 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 15:54:18,070 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 33 [2018-01-24 15:54:18,071 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:54:18,072 INFO L225 Difference]: With dead ends: 169 [2018-01-24 15:54:18,073 INFO L226 Difference]: Without dead ends: 162 [2018-01-24 15:54:18,073 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-01-24 15:54:18,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-01-24 15:54:18,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2018-01-24 15:54:18,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-01-24 15:54:18,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 173 transitions. [2018-01-24 15:54:18,085 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 173 transitions. Word has length 33 [2018-01-24 15:54:18,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:54:18,086 INFO L432 AbstractCegarLoop]: Abstraction has 162 states and 173 transitions. [2018-01-24 15:54:18,086 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 15:54:18,086 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 173 transitions. [2018-01-24 15:54:18,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-24 15:54:18,087 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:54:18,087 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:54:18,087 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-01-24 15:54:18,087 INFO L82 PathProgramCache]: Analyzing trace with hash 902320110, now seen corresponding path program 1 times [2018-01-24 15:54:18,087 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:54:18,088 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:18,088 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:54:18,089 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:18,089 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:54:18,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:18,119 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:54:18,297 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 15:54:18,298 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:18,298 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:54:18,299 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 45 with the following transitions: [2018-01-24 15:54:18,300 INFO L201 CegarAbsIntRunner]: [72], [78], [79], [81], [86], [88], [93], [96], [147], [148], [154], [155], [157], [158], [194], [208], [209], [210], [211], [212], [213], [220], [221], [222], [223], [224] [2018-01-24 15:54:18,348 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:54:18,348 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:54:18,826 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:54:18,828 INFO L268 AbstractInterpreter]: Visited 26 different actions 44 times. Never merged. Never widened. Never found a fixpoint. Largest state had 18 variables. [2018-01-24 15:54:18,837 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:54:18,838 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:18,838 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:54:18,850 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:54:18,850 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:54:18,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:18,909 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:54:18,943 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 15:54:18,944 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 15:54:18,945 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:54:18,945 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-24 15:54:19,039 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:54:19,040 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 5 [2018-01-24 15:54:19,040 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 15:54:19,043 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 15:54:19,043 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:12, output treesize:5 [2018-01-24 15:54:19,088 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:54:19,090 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:54:19,091 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-01-24 15:54:19,092 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 15:54:19,100 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 15:54:19,101 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-01-24 15:54:19,128 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 20 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 15:54:19,128 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:54:19,490 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 4 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 15:54:19,523 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:19,523 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:54:19,527 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:54:19,528 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:54:19,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:19,599 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:54:19,604 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 15:54:19,604 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 15:54:19,610 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 15:54:19,610 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-24 15:54:19,654 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:54:19,655 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 5 [2018-01-24 15:54:19,655 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 15:54:19,658 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 15:54:19,658 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:12, output treesize:5 [2018-01-24 15:54:19,706 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:54:19,707 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 15:54:19,708 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-01-24 15:54:19,708 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 15:54:19,713 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 15:54:19,713 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-01-24 15:54:19,716 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 20 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 15:54:19,716 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:54:19,917 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 4 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 15:54:19,919 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:54:19,919 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 9, 8, 9, 8] total 17 [2018-01-24 15:54:19,919 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:54:19,920 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 15:54:19,920 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 15:54:19,920 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=249, Unknown=0, NotChecked=0, Total=306 [2018-01-24 15:54:19,920 INFO L87 Difference]: Start difference. First operand 162 states and 173 transitions. Second operand 12 states. [2018-01-24 15:54:20,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:54:20,689 INFO L93 Difference]: Finished difference Result 210 states and 228 transitions. [2018-01-24 15:54:20,690 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 15:54:20,690 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 44 [2018-01-24 15:54:20,691 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:54:20,694 INFO L225 Difference]: With dead ends: 210 [2018-01-24 15:54:20,694 INFO L226 Difference]: Without dead ends: 205 [2018-01-24 15:54:20,695 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 187 GetRequests, 155 SyntacticMatches, 13 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 144 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=86, Invalid=334, Unknown=0, NotChecked=0, Total=420 [2018-01-24 15:54:20,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-01-24 15:54:20,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 175. [2018-01-24 15:54:20,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2018-01-24 15:54:20,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 192 transitions. [2018-01-24 15:54:20,718 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 192 transitions. Word has length 44 [2018-01-24 15:54:20,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:54:20,718 INFO L432 AbstractCegarLoop]: Abstraction has 175 states and 192 transitions. [2018-01-24 15:54:20,718 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 15:54:20,718 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 192 transitions. [2018-01-24 15:54:20,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-24 15:54:20,720 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:54:20,720 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:54:20,720 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-01-24 15:54:20,720 INFO L82 PathProgramCache]: Analyzing trace with hash 902320111, now seen corresponding path program 1 times [2018-01-24 15:54:20,720 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:54:20,722 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:20,722 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:54:20,722 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:20,722 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:54:20,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:20,752 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:54:20,968 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 15:54:20,968 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:20,968 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:54:20,968 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 45 with the following transitions: [2018-01-24 15:54:20,968 INFO L201 CegarAbsIntRunner]: [72], [78], [79], [81], [86], [88], [93], [97], [147], [148], [154], [155], [157], [158], [194], [208], [209], [210], [211], [212], [213], [220], [221], [222], [223], [224] [2018-01-24 15:54:20,969 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:54:20,970 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:54:21,248 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:54:21,248 INFO L268 AbstractInterpreter]: Visited 26 different actions 44 times. Never merged. Never widened. Never found a fixpoint. Largest state had 18 variables. [2018-01-24 15:54:21,255 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:54:21,255 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:21,255 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:54:21,271 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:54:21,271 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:54:21,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:21,319 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:54:21,368 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 28 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-24 15:54:21,368 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:54:21,615 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 8 proven. 8 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 15:54:21,651 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-01-24 15:54:21,651 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [7, 6] total 13 [2018-01-24 15:54:21,651 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:54:21,652 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 15:54:21,652 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 15:54:21,652 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2018-01-24 15:54:21,653 INFO L87 Difference]: Start difference. First operand 175 states and 192 transitions. Second operand 6 states. [2018-01-24 15:54:21,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:54:21,797 INFO L93 Difference]: Finished difference Result 349 states and 390 transitions. [2018-01-24 15:54:21,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 15:54:21,798 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 44 [2018-01-24 15:54:21,798 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:54:21,800 INFO L225 Difference]: With dead ends: 349 [2018-01-24 15:54:21,800 INFO L226 Difference]: Without dead ends: 176 [2018-01-24 15:54:21,803 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 80 SyntacticMatches, 3 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=53, Invalid=157, Unknown=0, NotChecked=0, Total=210 [2018-01-24 15:54:21,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-01-24 15:54:21,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 176. [2018-01-24 15:54:21,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-01-24 15:54:21,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 193 transitions. [2018-01-24 15:54:21,827 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 193 transitions. Word has length 44 [2018-01-24 15:54:21,827 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:54:21,827 INFO L432 AbstractCegarLoop]: Abstraction has 176 states and 193 transitions. [2018-01-24 15:54:21,827 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 15:54:21,827 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 193 transitions. [2018-01-24 15:54:21,829 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-01-24 15:54:21,829 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:54:21,829 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:54:21,829 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-01-24 15:54:21,829 INFO L82 PathProgramCache]: Analyzing trace with hash -506792821, now seen corresponding path program 1 times [2018-01-24 15:54:21,829 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:54:21,831 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:21,831 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:54:21,831 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:21,831 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:54:21,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:21,862 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:54:22,048 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-01-24 15:54:22,048 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:22,048 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:54:22,048 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 48 with the following transitions: [2018-01-24 15:54:22,048 INFO L201 CegarAbsIntRunner]: [72], [76], [78], [79], [81], [86], [88], [93], [97], [147], [148], [154], [155], [157], [158], [194], [208], [209], [210], [211], [212], [213], [220], [221], [222], [223], [224] [2018-01-24 15:54:22,050 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:54:22,050 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:54:33,448 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:54:33,448 INFO L268 AbstractInterpreter]: Visited 27 different actions 71 times. Merged at 3 different actions 18 times. Never widened. Found 9 fixpoints after 2 different actions. Largest state had 24 variables. [2018-01-24 15:54:33,469 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:54:33,469 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:33,469 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:54:33,482 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:54:33,482 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:54:33,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:33,512 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:54:33,584 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 37 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 15:54:33,585 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:54:35,618 WARN L143 SmtUtils]: Spent 1778ms on a formula simplification that was a NOOP. DAG size: 40 [2018-01-24 15:54:35,653 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 11 proven. 12 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-01-24 15:54:35,676 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:35,676 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:54:35,679 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:54:35,679 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:54:35,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:35,740 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:54:35,755 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 26 proven. 1 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 15:54:35,755 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:54:35,964 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-01-24 15:54:35,967 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:54:35,967 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7, 7, 7] total 19 [2018-01-24 15:54:35,967 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:54:35,967 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 15:54:35,968 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 15:54:35,968 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=277, Unknown=0, NotChecked=0, Total=342 [2018-01-24 15:54:35,968 INFO L87 Difference]: Start difference. First operand 176 states and 193 transitions. Second operand 12 states. [2018-01-24 15:54:36,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:54:36,077 INFO L93 Difference]: Finished difference Result 351 states and 392 transitions. [2018-01-24 15:54:36,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 15:54:36,078 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 47 [2018-01-24 15:54:36,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:54:36,080 INFO L225 Difference]: With dead ends: 351 [2018-01-24 15:54:36,080 INFO L226 Difference]: Without dead ends: 177 [2018-01-24 15:54:36,081 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 170 SyntacticMatches, 7 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=85, Invalid=335, Unknown=0, NotChecked=0, Total=420 [2018-01-24 15:54:36,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-01-24 15:54:36,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 177. [2018-01-24 15:54:36,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-01-24 15:54:36,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 194 transitions. [2018-01-24 15:54:36,095 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 194 transitions. Word has length 47 [2018-01-24 15:54:36,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:54:36,096 INFO L432 AbstractCegarLoop]: Abstraction has 177 states and 194 transitions. [2018-01-24 15:54:36,096 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 15:54:36,096 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 194 transitions. [2018-01-24 15:54:36,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-01-24 15:54:36,096 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:54:36,097 INFO L322 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:54:36,097 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-01-24 15:54:36,097 INFO L82 PathProgramCache]: Analyzing trace with hash -1284083601, now seen corresponding path program 2 times [2018-01-24 15:54:36,097 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:54:36,098 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:36,098 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:54:36,098 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:36,098 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:54:36,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:36,123 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:54:36,315 WARN L146 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 23 DAG size of output 13 [2018-01-24 15:54:36,382 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-01-24 15:54:36,382 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:36,382 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:54:36,382 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:54:36,383 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:54:36,383 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:36,383 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:54:36,390 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:54:36,391 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:54:36,404 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:54:36,415 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:54:36,418 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:54:36,450 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:54:36,554 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 32 proven. 3 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-01-24 15:54:36,554 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:54:36,690 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 81 [2018-01-24 15:54:36,995 WARN L146 SmtUtils]: Spent 134ms on a formula simplification. DAG size of input: 56 DAG size of output 47 [2018-01-24 15:54:37,004 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:37,017 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:39,545 WARN L143 SmtUtils]: Spent 2477ms on a formula simplification that was a NOOP. DAG size: 49 [2018-01-24 15:54:39,553 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:39,713 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:41,850 WARN L143 SmtUtils]: Spent 2055ms on a formula simplification that was a NOOP. DAG size: 52 [2018-01-24 15:54:41,855 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:41,880 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 32 proven. 3 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-01-24 15:54:41,903 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:41,904 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:54:41,907 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:54:41,907 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:54:41,924 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:54:41,948 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:54:41,978 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:54:41,985 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:54:42,182 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 32 proven. 3 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-01-24 15:54:42,183 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:54:44,502 WARN L143 SmtUtils]: Spent 2033ms on a formula simplification that was a NOOP. DAG size: 41 [2018-01-24 15:54:44,646 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 32 proven. 3 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-01-24 15:54:44,648 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:54:44,648 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8, 8, 8] total 29 [2018-01-24 15:54:44,648 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:54:44,649 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 15:54:44,649 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 15:54:44,649 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=121, Invalid=691, Unknown=0, NotChecked=0, Total=812 [2018-01-24 15:54:44,649 INFO L87 Difference]: Start difference. First operand 177 states and 194 transitions. Second operand 14 states. [2018-01-24 15:54:44,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:54:44,880 INFO L93 Difference]: Finished difference Result 353 states and 394 transitions. [2018-01-24 15:54:44,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 15:54:44,881 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 50 [2018-01-24 15:54:44,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:54:44,883 INFO L225 Difference]: With dead ends: 353 [2018-01-24 15:54:44,883 INFO L226 Difference]: Without dead ends: 178 [2018-01-24 15:54:44,884 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 211 GetRequests, 174 SyntacticMatches, 6 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 208 ImplicationChecksByTransitivity, 7.9s TimeCoverageRelationStatistics Valid=161, Invalid=895, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 15:54:44,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2018-01-24 15:54:44,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2018-01-24 15:54:44,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2018-01-24 15:54:44,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 195 transitions. [2018-01-24 15:54:44,899 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 195 transitions. Word has length 50 [2018-01-24 15:54:44,899 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:54:44,899 INFO L432 AbstractCegarLoop]: Abstraction has 178 states and 195 transitions. [2018-01-24 15:54:44,899 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 15:54:44,899 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 195 transitions. [2018-01-24 15:54:44,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-01-24 15:54:44,900 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:54:44,901 INFO L322 BasicCegarLoop]: trace histogram [9, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:54:44,901 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-01-24 15:54:44,901 INFO L82 PathProgramCache]: Analyzing trace with hash -202175989, now seen corresponding path program 3 times [2018-01-24 15:54:44,901 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:54:44,902 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:44,902 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:54:44,902 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:44,902 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:54:44,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:44,929 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:54:45,131 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-01-24 15:54:45,132 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:45,132 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:54:45,132 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:54:45,132 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:54:45,132 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:45,132 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:54:45,141 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:54:45,141 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:54:45,163 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:54:45,172 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:54:45,185 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:54:45,188 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:54:45,192 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:54:45,355 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 46 proven. 6 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-01-24 15:54:45,355 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:54:45,537 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 81 [2018-01-24 15:54:45,815 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:45,827 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:47,856 WARN L143 SmtUtils]: Spent 1955ms on a formula simplification that was a NOOP. DAG size: 49 [2018-01-24 15:54:47,861 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:47,963 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:48,076 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:50,242 WARN L143 SmtUtils]: Spent 2057ms on a formula simplification that was a NOOP. DAG size: 52 [2018-01-24 15:54:50,249 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:50,292 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 46 proven. 6 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-01-24 15:54:50,325 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:50,325 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:54:50,341 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:54:50,341 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:54:50,363 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:54:50,378 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:54:50,419 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:54:50,446 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:54:50,452 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:54:50,613 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 46 proven. 6 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-01-24 15:54:50,614 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:54:52,949 WARN L143 SmtUtils]: Spent 2026ms on a formula simplification that was a NOOP. DAG size: 40 [2018-01-24 15:54:55,025 WARN L143 SmtUtils]: Spent 2030ms on a formula simplification that was a NOOP. DAG size: 42 [2018-01-24 15:54:55,233 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 46 proven. 6 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-01-24 15:54:55,235 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:54:55,235 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9, 9, 9] total 34 [2018-01-24 15:54:55,235 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:54:55,235 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 15:54:55,235 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 15:54:55,236 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=147, Invalid=975, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 15:54:55,236 INFO L87 Difference]: Start difference. First operand 178 states and 195 transitions. Second operand 16 states. [2018-01-24 15:54:55,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:54:55,492 INFO L93 Difference]: Finished difference Result 355 states and 396 transitions. [2018-01-24 15:54:55,492 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 15:54:55,492 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 53 [2018-01-24 15:54:55,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:54:55,494 INFO L225 Difference]: With dead ends: 355 [2018-01-24 15:54:55,494 INFO L226 Difference]: Without dead ends: 179 [2018-01-24 15:54:55,495 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 225 GetRequests, 182 SyntacticMatches, 8 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 281 ImplicationChecksByTransitivity, 9.5s TimeCoverageRelationStatistics Valid=181, Invalid=1151, Unknown=0, NotChecked=0, Total=1332 [2018-01-24 15:54:55,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-01-24 15:54:55,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2018-01-24 15:54:55,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2018-01-24 15:54:55,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 196 transitions. [2018-01-24 15:54:55,510 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 196 transitions. Word has length 53 [2018-01-24 15:54:55,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:54:55,510 INFO L432 AbstractCegarLoop]: Abstraction has 179 states and 196 transitions. [2018-01-24 15:54:55,510 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 15:54:55,510 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 196 transitions. [2018-01-24 15:54:55,511 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-01-24 15:54:55,511 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:54:55,512 INFO L322 BasicCegarLoop]: trace histogram [12, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:54:55,512 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-01-24 15:54:55,512 INFO L82 PathProgramCache]: Analyzing trace with hash -734121745, now seen corresponding path program 4 times [2018-01-24 15:54:55,512 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:54:55,513 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:55,513 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:54:55,514 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:54:55,514 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:54:55,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:54:55,545 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:54:55,736 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 64 proven. 10 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-01-24 15:54:55,736 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:55,736 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:54:55,736 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:54:55,736 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:54:55,736 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:55,737 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:54:55,745 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:54:55,746 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:54:56,622 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:54:56,626 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:54:56,746 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 64 proven. 10 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-01-24 15:54:56,746 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:54:57,004 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 81 [2018-01-24 15:54:57,214 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:57,221 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:57,305 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:57,386 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:57,558 WARN L143 SmtUtils]: Spent 123ms on a formula simplification that was a NOOP. DAG size: 52 [2018-01-24 15:54:57,562 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:57,654 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:57,839 WARN L143 SmtUtils]: Spent 127ms on a formula simplification that was a NOOP. DAG size: 52 [2018-01-24 15:54:57,843 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 27 [2018-01-24 15:54:57,864 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 64 proven. 10 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-01-24 15:54:57,886 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:54:57,886 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:54:57,889 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:54:57,890 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:54:58,057 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:54:58,070 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:54:58,231 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 68 proven. 10 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:54:58,231 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:55:00,649 WARN L143 SmtUtils]: Spent 2034ms on a formula simplification that was a NOOP. DAG size: 42 [2018-01-24 15:55:00,913 WARN L143 SmtUtils]: Spent 183ms on a formula simplification that was a NOOP. DAG size: 45 [2018-01-24 15:55:03,170 WARN L146 SmtUtils]: Spent 2095ms on a formula simplification. DAG size of input: 46 DAG size of output 45 [2018-01-24 15:55:03,182 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 74 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-01-24 15:55:03,184 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:55:03,184 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10, 10, 10] total 40 [2018-01-24 15:55:03,184 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:55:03,185 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 15:55:03,185 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 15:55:03,186 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=179, Invalid=1381, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 15:55:03,186 INFO L87 Difference]: Start difference. First operand 179 states and 196 transitions. Second operand 18 states. [2018-01-24 15:55:03,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:55:03,516 INFO L93 Difference]: Finished difference Result 357 states and 398 transitions. [2018-01-24 15:55:03,516 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 15:55:03,516 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 56 [2018-01-24 15:55:03,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:55:03,518 INFO L225 Difference]: With dead ends: 357 [2018-01-24 15:55:03,518 INFO L226 Difference]: Without dead ends: 180 [2018-01-24 15:55:03,520 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 239 GetRequests, 189 SyntacticMatches, 6 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 406 ImplicationChecksByTransitivity, 6.2s TimeCoverageRelationStatistics Valid=243, Invalid=1827, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 15:55:03,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-01-24 15:55:03,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 180. [2018-01-24 15:55:03,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-01-24 15:55:03,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 197 transitions. [2018-01-24 15:55:03,534 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 197 transitions. Word has length 56 [2018-01-24 15:55:03,534 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:55:03,534 INFO L432 AbstractCegarLoop]: Abstraction has 180 states and 197 transitions. [2018-01-24 15:55:03,534 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 15:55:03,534 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 197 transitions. [2018-01-24 15:55:03,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-01-24 15:55:03,535 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:55:03,535 INFO L322 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:55:03,536 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-01-24 15:55:03,536 INFO L82 PathProgramCache]: Analyzing trace with hash 1514307467, now seen corresponding path program 5 times [2018-01-24 15:55:03,536 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:55:03,537 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:55:03,537 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:55:03,537 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:55:03,537 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:55:03,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:55:03,572 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:55:04,110 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 50 proven. 58 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 15:55:04,110 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:55:04,110 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:55:04,110 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:55:04,110 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:55:04,110 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:55:04,110 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:55:04,115 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:55:04,116 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:55:04,126 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:55:04,128 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:55:04,135 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:55:04,566 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown