java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/array-examples/standard_strcpy_false-valid-deref_ground.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 15:25:03,460 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 15:25:03,462 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 15:25:03,477 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 15:25:03,478 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 15:25:03,479 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 15:25:03,480 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 15:25:03,481 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 15:25:03,484 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 15:25:03,485 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 15:25:03,486 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 15:25:03,486 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 15:25:03,487 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 15:25:03,488 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 15:25:03,489 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 15:25:03,492 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 15:25:03,494 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 15:25:03,496 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 15:25:03,497 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 15:25:03,499 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 15:25:03,501 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 15:25:03,501 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 15:25:03,501 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 15:25:03,502 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 15:25:03,503 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 15:25:03,504 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 15:25:03,504 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 15:25:03,505 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 15:25:03,505 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 15:25:03,505 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 15:25:03,506 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 15:25:03,507 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf [2018-01-24 15:25:03,515 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 15:25:03,515 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 15:25:03,516 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 15:25:03,516 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 15:25:03,516 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 15:25:03,516 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 15:25:03,516 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 15:25:03,517 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 15:25:03,517 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 15:25:03,517 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 15:25:03,517 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 15:25:03,517 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 15:25:03,518 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 15:25:03,518 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 15:25:03,518 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 15:25:03,518 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 15:25:03,518 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 15:25:03,518 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 15:25:03,518 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 15:25:03,518 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 15:25:03,519 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 15:25:03,519 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 15:25:03,519 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 15:25:03,519 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 15:25:03,519 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 15:25:03,520 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 15:25:03,520 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 15:25:03,520 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 15:25:03,520 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 15:25:03,520 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 15:25:03,520 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 15:25:03,520 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 15:25:03,520 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 15:25:03,521 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 15:25:03,521 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 15:25:03,554 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 15:25:03,565 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 15:25:03,568 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 15:25:03,570 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 15:25:03,570 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 15:25:03,571 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/standard_strcpy_false-valid-deref_ground.i [2018-01-24 15:25:03,686 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 15:25:03,692 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 15:25:03,692 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 15:25:03,693 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 15:25:03,698 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 15:25:03,699 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 03:25:03" (1/1) ... [2018-01-24 15:25:03,702 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4a7fa5d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:03, skipping insertion in model container [2018-01-24 15:25:03,702 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 03:25:03" (1/1) ... [2018-01-24 15:25:03,716 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 15:25:03,729 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 15:25:03,844 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 15:25:03,856 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 15:25:03,860 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:03 WrapperNode [2018-01-24 15:25:03,861 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 15:25:03,861 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 15:25:03,862 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 15:25:03,862 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 15:25:03,873 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:03" (1/1) ... [2018-01-24 15:25:03,873 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:03" (1/1) ... [2018-01-24 15:25:03,880 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:03" (1/1) ... [2018-01-24 15:25:03,880 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:03" (1/1) ... [2018-01-24 15:25:03,882 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:03" (1/1) ... [2018-01-24 15:25:03,885 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:03" (1/1) ... [2018-01-24 15:25:03,886 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:03" (1/1) ... [2018-01-24 15:25:03,887 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 15:25:03,887 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 15:25:03,887 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 15:25:03,888 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 15:25:03,888 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:03" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 15:25:03,938 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 15:25:03,938 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 15:25:03,938 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 15:25:03,939 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 15:25:03,939 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 15:25:03,939 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 15:25:03,939 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 15:25:03,939 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 15:25:03,939 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 15:25:04,052 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 15:25:04,053 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 03:25:04 BoogieIcfgContainer [2018-01-24 15:25:04,053 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 15:25:04,054 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 15:25:04,054 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 15:25:04,055 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 15:25:04,055 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 03:25:03" (1/3) ... [2018-01-24 15:25:04,056 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@338fbae1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 03:25:04, skipping insertion in model container [2018-01-24 15:25:04,056 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:03" (2/3) ... [2018-01-24 15:25:04,057 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@338fbae1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 03:25:04, skipping insertion in model container [2018-01-24 15:25:04,057 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 03:25:04" (3/3) ... [2018-01-24 15:25:04,059 INFO L105 eAbstractionObserver]: Analyzing ICFG standard_strcpy_false-valid-deref_ground.i [2018-01-24 15:25:04,065 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 15:25:04,071 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 5 error locations. [2018-01-24 15:25:04,109 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 15:25:04,109 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 15:25:04,110 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 15:25:04,110 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 15:25:04,110 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 15:25:04,110 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 15:25:04,110 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 15:25:04,111 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 15:25:04,111 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 15:25:04,131 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states. [2018-01-24 15:25:04,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2018-01-24 15:25:04,137 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:04,138 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:04,138 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:04,142 INFO L82 PathProgramCache]: Analyzing trace with hash -42218404, now seen corresponding path program 1 times [2018-01-24 15:25:04,144 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:04,183 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:04,184 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:04,184 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:04,184 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:04,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:04,221 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:04,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:04,275 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:25:04,276 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 15:25:04,276 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:25:04,278 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 15:25:04,290 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 15:25:04,291 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 15:25:04,293 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 3 states. [2018-01-24 15:25:04,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:04,427 INFO L93 Difference]: Finished difference Result 71 states and 84 transitions. [2018-01-24 15:25:04,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 15:25:04,429 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2018-01-24 15:25:04,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:04,439 INFO L225 Difference]: With dead ends: 71 [2018-01-24 15:25:04,440 INFO L226 Difference]: Without dead ends: 40 [2018-01-24 15:25:04,445 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 15:25:04,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-01-24 15:25:04,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 31. [2018-01-24 15:25:04,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-01-24 15:25:04,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 33 transitions. [2018-01-24 15:25:04,546 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 33 transitions. Word has length 7 [2018-01-24 15:25:04,546 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:04,546 INFO L432 AbstractCegarLoop]: Abstraction has 31 states and 33 transitions. [2018-01-24 15:25:04,546 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 15:25:04,546 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 33 transitions. [2018-01-24 15:25:04,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-01-24 15:25:04,547 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:04,547 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:04,547 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:04,547 INFO L82 PathProgramCache]: Analyzing trace with hash -207595369, now seen corresponding path program 1 times [2018-01-24 15:25:04,547 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:04,548 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:04,549 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:04,549 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:04,549 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:04,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:04,559 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:04,600 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:04,601 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:04,601 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:04,602 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 13 with the following transitions: [2018-01-24 15:25:04,604 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [10], [11], [16], [18], [20], [56], [57], [58] [2018-01-24 15:25:04,652 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:25:04,652 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:25:04,907 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:25:04,908 INFO L268 AbstractInterpreter]: Visited 11 different actions 23 times. Merged at 6 different actions 12 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 3 variables. [2018-01-24 15:25:04,917 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:25:04,917 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:04,917 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:04,928 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:04,928 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:04,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:04,952 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:04,979 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:04,979 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:05,046 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:05,068 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:05,068 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:05,071 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:05,072 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:05,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:05,082 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:05,088 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:05,089 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:05,117 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:05,119 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:05,119 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3, 3, 3] total 5 [2018-01-24 15:25:05,119 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:05,120 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 15:25:05,121 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 15:25:05,121 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:25:05,121 INFO L87 Difference]: Start difference. First operand 31 states and 33 transitions. Second operand 4 states. [2018-01-24 15:25:05,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:05,170 INFO L93 Difference]: Finished difference Result 57 states and 62 transitions. [2018-01-24 15:25:05,171 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 15:25:05,171 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-01-24 15:25:05,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:05,173 INFO L225 Difference]: With dead ends: 57 [2018-01-24 15:25:05,173 INFO L226 Difference]: Without dead ends: 54 [2018-01-24 15:25:05,174 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 43 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:25:05,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-24 15:25:05,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 36. [2018-01-24 15:25:05,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-01-24 15:25:05,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 39 transitions. [2018-01-24 15:25:05,181 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 39 transitions. Word has length 12 [2018-01-24 15:25:05,181 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:05,181 INFO L432 AbstractCegarLoop]: Abstraction has 36 states and 39 transitions. [2018-01-24 15:25:05,181 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 15:25:05,181 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 39 transitions. [2018-01-24 15:25:05,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-01-24 15:25:05,182 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:05,182 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:05,182 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:05,183 INFO L82 PathProgramCache]: Analyzing trace with hash -209255178, now seen corresponding path program 1 times [2018-01-24 15:25:05,183 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:05,184 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:05,184 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:05,184 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:05,184 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:05,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:05,190 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:05,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:05,238 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:25:05,238 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 15:25:05,238 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:25:05,238 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 15:25:05,238 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 15:25:05,239 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 15:25:05,239 INFO L87 Difference]: Start difference. First operand 36 states and 39 transitions. Second operand 4 states. [2018-01-24 15:25:05,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:05,265 INFO L93 Difference]: Finished difference Result 51 states and 54 transitions. [2018-01-24 15:25:05,266 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 15:25:05,266 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-01-24 15:25:05,266 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:05,267 INFO L225 Difference]: With dead ends: 51 [2018-01-24 15:25:05,267 INFO L226 Difference]: Without dead ends: 36 [2018-01-24 15:25:05,268 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 15:25:05,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2018-01-24 15:25:05,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2018-01-24 15:25:05,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-01-24 15:25:05,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 38 transitions. [2018-01-24 15:25:05,273 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 38 transitions. Word has length 12 [2018-01-24 15:25:05,273 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:05,274 INFO L432 AbstractCegarLoop]: Abstraction has 36 states and 38 transitions. [2018-01-24 15:25:05,274 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 15:25:05,274 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 38 transitions. [2018-01-24 15:25:05,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 15:25:05,274 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:05,274 INFO L322 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:05,275 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:05,275 INFO L82 PathProgramCache]: Analyzing trace with hash 2132883772, now seen corresponding path program 2 times [2018-01-24 15:25:05,275 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:05,276 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:05,276 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:05,276 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:05,277 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:05,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:05,285 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:05,378 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:05,378 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:05,378 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:05,378 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:05,379 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:05,379 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:05,379 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:05,387 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:05,387 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:05,396 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:05,400 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:05,401 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:05,402 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:05,410 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:05,411 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:05,508 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:05,532 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:05,532 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:05,535 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:05,535 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:05,540 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:05,543 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:05,547 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:05,550 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:05,573 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:05,573 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:05,582 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:05,583 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:05,584 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-01-24 15:25:05,584 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:05,584 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 15:25:05,584 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 15:25:05,584 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 15:25:05,585 INFO L87 Difference]: Start difference. First operand 36 states and 38 transitions. Second operand 5 states. [2018-01-24 15:25:05,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:05,684 INFO L93 Difference]: Finished difference Result 62 states and 67 transitions. [2018-01-24 15:25:05,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 15:25:05,684 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 15:25:05,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:05,685 INFO L225 Difference]: With dead ends: 62 [2018-01-24 15:25:05,686 INFO L226 Difference]: Without dead ends: 59 [2018-01-24 15:25:05,686 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 62 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 15:25:05,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-01-24 15:25:05,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 41. [2018-01-24 15:25:05,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-01-24 15:25:05,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 44 transitions. [2018-01-24 15:25:05,693 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 44 transitions. Word has length 17 [2018-01-24 15:25:05,693 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:05,693 INFO L432 AbstractCegarLoop]: Abstraction has 41 states and 44 transitions. [2018-01-24 15:25:05,693 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 15:25:05,693 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 44 transitions. [2018-01-24 15:25:05,694 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 15:25:05,694 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:05,694 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:05,695 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:05,695 INFO L82 PathProgramCache]: Analyzing trace with hash 2131223963, now seen corresponding path program 1 times [2018-01-24 15:25:05,695 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:05,696 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:05,696 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:05,696 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:05,696 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:05,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:05,702 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:05,753 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:05,753 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:05,753 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:05,754 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 18 with the following transitions: [2018-01-24 15:25:05,754 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [11], [14], [16], [18], [20], [24], [28], [33], [34], [56], [57], [58] [2018-01-24 15:25:05,755 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:25:05,755 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:25:05,927 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:25:05,927 INFO L268 AbstractInterpreter]: Visited 15 different actions 35 times. Merged at 10 different actions 20 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 4 variables. [2018-01-24 15:25:05,931 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:25:05,931 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:05,931 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:05,942 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:05,943 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:05,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:05,961 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:05,963 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 15:25:05,963 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:05,991 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 15:25:06,012 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 15:25:06,013 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2, 2] imperfect sequences [5] total 6 [2018-01-24 15:25:06,013 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:25:06,013 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 15:25:06,013 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 15:25:06,013 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 15:25:06,013 INFO L87 Difference]: Start difference. First operand 41 states and 44 transitions. Second operand 3 states. [2018-01-24 15:25:06,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:06,034 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2018-01-24 15:25:06,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 15:25:06,036 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 17 [2018-01-24 15:25:06,036 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:06,037 INFO L225 Difference]: With dead ends: 49 [2018-01-24 15:25:06,037 INFO L226 Difference]: Without dead ends: 47 [2018-01-24 15:25:06,038 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 15:25:06,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-01-24 15:25:06,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 45. [2018-01-24 15:25:06,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-01-24 15:25:06,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 48 transitions. [2018-01-24 15:25:06,045 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 48 transitions. Word has length 17 [2018-01-24 15:25:06,045 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:06,045 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 48 transitions. [2018-01-24 15:25:06,045 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 15:25:06,045 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 48 transitions. [2018-01-24 15:25:06,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-01-24 15:25:06,046 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:06,047 INFO L322 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:06,047 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:06,047 INFO L82 PathProgramCache]: Analyzing trace with hash 2059138999, now seen corresponding path program 3 times [2018-01-24 15:25:06,047 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:06,048 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:06,049 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:06,049 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:06,049 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:06,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:06,056 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:06,171 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:06,171 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:06,171 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:06,171 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:06,172 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:06,172 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:06,172 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:06,178 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:06,179 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:06,182 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:06,183 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:06,184 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:06,185 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:06,186 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:06,187 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:06,198 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:06,198 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:06,324 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:06,345 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:06,345 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:06,349 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:06,349 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:06,357 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:06,359 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:06,364 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:06,368 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:06,372 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:06,374 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:06,383 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:06,383 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:06,394 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:06,396 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:06,396 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 15:25:06,396 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:06,396 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 15:25:06,397 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 15:25:06,397 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 15:25:06,397 INFO L87 Difference]: Start difference. First operand 45 states and 48 transitions. Second operand 6 states. [2018-01-24 15:25:06,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:06,462 INFO L93 Difference]: Finished difference Result 92 states and 99 transitions. [2018-01-24 15:25:06,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 15:25:06,462 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-01-24 15:25:06,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:06,463 INFO L225 Difference]: With dead ends: 92 [2018-01-24 15:25:06,463 INFO L226 Difference]: Without dead ends: 89 [2018-01-24 15:25:06,463 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 81 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 15:25:06,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-01-24 15:25:06,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 50. [2018-01-24 15:25:06,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 15:25:06,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-01-24 15:25:06,470 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 22 [2018-01-24 15:25:06,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:06,470 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-01-24 15:25:06,471 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 15:25:06,471 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-01-24 15:25:06,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 15:25:06,472 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:06,472 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:06,472 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:06,472 INFO L82 PathProgramCache]: Analyzing trace with hash -6617899, now seen corresponding path program 1 times [2018-01-24 15:25:06,472 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:06,473 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:06,473 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:06,473 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:06,474 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:06,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:06,485 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:06,523 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:06,523 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:06,523 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:06,524 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 28 with the following transitions: [2018-01-24 15:25:06,524 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [11], [14], [16], [18], [20], [24], [28], [33], [34], [35], [37], [40], [46], [53], [55], [56], [57], [58], [60], [61] [2018-01-24 15:25:06,525 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:25:06,525 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:25:06,818 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:25:06,818 INFO L268 AbstractInterpreter]: Visited 23 different actions 81 times. Merged at 14 different actions 39 times. Never widened. Found 5 fixpoints after 3 different actions. Largest state had 5 variables. [2018-01-24 15:25:06,824 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:25:06,824 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:06,824 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:06,838 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:06,838 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:06,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:06,848 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:06,899 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:06,900 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:06,933 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:06,954 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:06,955 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:06,958 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:06,958 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:06,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:06,971 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:06,977 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:06,978 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:06,991 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:06,993 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:06,993 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 9 [2018-01-24 15:25:06,993 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:06,994 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 15:25:06,994 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 15:25:06,994 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-01-24 15:25:06,994 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 8 states. [2018-01-24 15:25:07,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:07,068 INFO L93 Difference]: Finished difference Result 71 states and 76 transitions. [2018-01-24 15:25:07,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 15:25:07,069 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27 [2018-01-24 15:25:07,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:07,070 INFO L225 Difference]: With dead ends: 71 [2018-01-24 15:25:07,070 INFO L226 Difference]: Without dead ends: 50 [2018-01-24 15:25:07,071 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 101 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-01-24 15:25:07,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-01-24 15:25:07,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2018-01-24 15:25:07,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 15:25:07,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 53 transitions. [2018-01-24 15:25:07,077 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 53 transitions. Word has length 27 [2018-01-24 15:25:07,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:07,077 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 53 transitions. [2018-01-24 15:25:07,077 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 15:25:07,077 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 53 transitions. [2018-01-24 15:25:07,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 15:25:07,078 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:07,078 INFO L322 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:07,078 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:07,078 INFO L82 PathProgramCache]: Analyzing trace with hash -1173615076, now seen corresponding path program 4 times [2018-01-24 15:25:07,079 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:07,079 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:07,080 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:07,080 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:07,080 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:07,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:07,088 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:07,406 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:07,406 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:07,406 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:07,406 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:07,407 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:07,407 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:07,407 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:07,416 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:07,417 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:07,427 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:07,429 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:07,436 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:07,437 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:07,540 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:07,561 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:07,561 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:07,564 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:07,565 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:07,580 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:07,584 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:07,591 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:07,591 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:07,630 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:07,633 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:07,633 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 15:25:07,633 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:07,634 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 15:25:07,634 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 15:25:07,634 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 15:25:07,634 INFO L87 Difference]: Start difference. First operand 50 states and 53 transitions. Second operand 7 states. [2018-01-24 15:25:07,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:07,763 INFO L93 Difference]: Finished difference Result 97 states and 104 transitions. [2018-01-24 15:25:07,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 15:25:07,764 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 27 [2018-01-24 15:25:07,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:07,764 INFO L225 Difference]: With dead ends: 97 [2018-01-24 15:25:07,765 INFO L226 Difference]: Without dead ends: 94 [2018-01-24 15:25:07,765 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 100 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 15:25:07,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-01-24 15:25:07,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 55. [2018-01-24 15:25:07,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-01-24 15:25:07,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 59 transitions. [2018-01-24 15:25:07,772 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 59 transitions. Word has length 27 [2018-01-24 15:25:07,772 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:07,772 INFO L432 AbstractCegarLoop]: Abstraction has 55 states and 59 transitions. [2018-01-24 15:25:07,772 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 15:25:07,772 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 59 transitions. [2018-01-24 15:25:07,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 15:25:07,773 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:07,773 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:07,774 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:07,774 INFO L82 PathProgramCache]: Analyzing trace with hash 155329936, now seen corresponding path program 2 times [2018-01-24 15:25:07,774 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:07,774 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:07,775 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:07,775 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:07,775 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:07,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:07,782 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:07,955 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:07,956 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:07,956 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:07,956 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:07,956 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:07,956 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:07,956 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:07,967 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:07,967 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:07,970 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:07,985 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:07,998 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:08,000 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:08,024 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,025 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:08,151 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,172 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:08,172 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:08,176 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:08,176 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:08,181 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,186 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,191 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:08,194 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:08,202 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,203 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:08,219 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,220 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:08,221 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 14 [2018-01-24 15:25:08,221 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:08,221 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 15:25:08,221 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 15:25:08,222 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2018-01-24 15:25:08,222 INFO L87 Difference]: Start difference. First operand 55 states and 59 transitions. Second operand 9 states. [2018-01-24 15:25:08,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:08,449 INFO L93 Difference]: Finished difference Result 72 states and 78 transitions. [2018-01-24 15:25:08,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 15:25:08,450 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 32 [2018-01-24 15:25:08,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:08,451 INFO L225 Difference]: With dead ends: 72 [2018-01-24 15:25:08,451 INFO L226 Difference]: Without dead ends: 55 [2018-01-24 15:25:08,451 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 120 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 15:25:08,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-01-24 15:25:08,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2018-01-24 15:25:08,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-01-24 15:25:08,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 58 transitions. [2018-01-24 15:25:08,457 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 58 transitions. Word has length 32 [2018-01-24 15:25:08,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:08,457 INFO L432 AbstractCegarLoop]: Abstraction has 55 states and 58 transitions. [2018-01-24 15:25:08,457 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 15:25:08,458 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 58 transitions. [2018-01-24 15:25:08,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 15:25:08,458 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:08,459 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:08,459 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:08,459 INFO L82 PathProgramCache]: Analyzing trace with hash -1011667241, now seen corresponding path program 5 times [2018-01-24 15:25:08,459 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:08,460 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:08,460 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:08,460 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:08,461 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:08,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:08,466 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:08,532 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,532 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:08,532 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:08,532 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:08,533 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:08,533 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:08,533 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:08,538 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:08,538 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:08,541 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,542 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,543 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,544 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,545 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,546 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,546 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:08,548 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:08,556 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,556 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:08,615 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,635 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:08,636 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:08,639 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:08,639 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:08,642 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,644 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,650 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,655 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,660 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,667 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:08,671 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:08,674 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:08,687 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,687 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:08,694 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,696 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:08,696 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 15:25:08,696 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:08,697 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 15:25:08,697 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 15:25:08,697 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 15:25:08,697 INFO L87 Difference]: Start difference. First operand 55 states and 58 transitions. Second operand 8 states. [2018-01-24 15:25:08,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:08,815 INFO L93 Difference]: Finished difference Result 102 states and 109 transitions. [2018-01-24 15:25:08,815 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 15:25:08,815 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 32 [2018-01-24 15:25:08,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:08,816 INFO L225 Difference]: With dead ends: 102 [2018-01-24 15:25:08,816 INFO L226 Difference]: Without dead ends: 99 [2018-01-24 15:25:08,817 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 119 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 15:25:08,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-01-24 15:25:08,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 60. [2018-01-24 15:25:08,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 15:25:08,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 64 transitions. [2018-01-24 15:25:08,823 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 64 transitions. Word has length 32 [2018-01-24 15:25:08,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:08,823 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 64 transitions. [2018-01-24 15:25:08,823 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 15:25:08,823 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 64 transitions. [2018-01-24 15:25:08,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 15:25:08,824 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:08,824 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:08,824 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:08,824 INFO L82 PathProgramCache]: Analyzing trace with hash -903265867, now seen corresponding path program 3 times [2018-01-24 15:25:08,824 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:08,825 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:08,825 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:08,825 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:08,825 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:08,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:08,832 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:08,969 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:08,969 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:08,970 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:08,970 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:08,970 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:08,970 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:08,970 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:08,982 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:08,982 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:08,986 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:08,989 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:08,990 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:08,992 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:09,010 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 15:25:09,010 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:09,043 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 15:25:09,067 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:09,067 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:09,070 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:09,070 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:09,074 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:09,077 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:09,081 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:09,084 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:09,087 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 15:25:09,087 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:09,094 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 15:25:09,096 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:09,096 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 3, 3, 3, 3] total 12 [2018-01-24 15:25:09,096 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:09,096 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 15:25:09,096 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 15:25:09,097 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2018-01-24 15:25:09,097 INFO L87 Difference]: Start difference. First operand 60 states and 64 transitions. Second operand 11 states. [2018-01-24 15:25:09,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:09,177 INFO L93 Difference]: Finished difference Result 97 states and 113 transitions. [2018-01-24 15:25:09,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 15:25:09,177 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2018-01-24 15:25:09,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:09,178 INFO L225 Difference]: With dead ends: 97 [2018-01-24 15:25:09,178 INFO L226 Difference]: Without dead ends: 74 [2018-01-24 15:25:09,178 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-01-24 15:25:09,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-01-24 15:25:09,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 72. [2018-01-24 15:25:09,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-01-24 15:25:09,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 77 transitions. [2018-01-24 15:25:09,183 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 77 transitions. Word has length 37 [2018-01-24 15:25:09,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:09,183 INFO L432 AbstractCegarLoop]: Abstraction has 72 states and 77 transitions. [2018-01-24 15:25:09,183 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 15:25:09,183 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 77 transitions. [2018-01-24 15:25:09,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 15:25:09,184 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:09,185 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:09,185 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:09,185 INFO L82 PathProgramCache]: Analyzing trace with hash -2070263044, now seen corresponding path program 6 times [2018-01-24 15:25:09,185 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:09,186 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:09,186 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:09,186 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:09,186 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:09,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:09,192 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:09,274 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:09,274 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:09,274 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:09,274 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:09,275 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:09,275 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:09,275 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:09,280 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:09,280 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:09,282 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,283 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,284 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,285 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,286 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,287 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,288 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,288 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:09,289 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:09,296 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:09,296 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:09,386 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:09,406 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:09,406 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:09,409 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:09,409 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:09,412 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,413 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,418 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,422 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,428 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,434 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,443 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:09,447 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:09,449 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:09,459 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:09,459 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:09,467 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:09,469 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:09,469 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 15:25:09,469 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:09,469 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 15:25:09,469 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 15:25:09,470 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 15:25:09,470 INFO L87 Difference]: Start difference. First operand 72 states and 77 transitions. Second operand 9 states. [2018-01-24 15:25:09,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:09,578 INFO L93 Difference]: Finished difference Result 155 states and 170 transitions. [2018-01-24 15:25:09,578 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 15:25:09,579 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 37 [2018-01-24 15:25:09,579 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:09,580 INFO L225 Difference]: With dead ends: 155 [2018-01-24 15:25:09,580 INFO L226 Difference]: Without dead ends: 152 [2018-01-24 15:25:09,580 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 138 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 15:25:09,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-24 15:25:09,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 77. [2018-01-24 15:25:09,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-01-24 15:25:09,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 83 transitions. [2018-01-24 15:25:09,588 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 83 transitions. Word has length 37 [2018-01-24 15:25:09,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:09,588 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 83 transitions. [2018-01-24 15:25:09,588 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 15:25:09,588 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 83 transitions. [2018-01-24 15:25:09,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 15:25:09,589 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:09,589 INFO L322 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:09,589 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:09,589 INFO L82 PathProgramCache]: Analyzing trace with hash 1122500087, now seen corresponding path program 7 times [2018-01-24 15:25:09,589 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:09,590 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:09,590 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:09,590 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:09,590 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:09,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:09,596 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:09,681 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:09,682 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:09,682 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:09,682 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:09,682 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:09,682 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:09,682 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:09,688 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:09,688 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:09,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:09,695 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:09,705 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:09,705 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:09,827 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:09,847 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:09,847 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:09,850 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:09,850 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:09,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:09,863 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:09,872 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:09,872 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:09,893 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:09,894 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:09,895 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 15:25:09,895 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:09,895 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 15:25:09,895 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 15:25:09,896 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 15:25:09,896 INFO L87 Difference]: Start difference. First operand 77 states and 83 transitions. Second operand 10 states. [2018-01-24 15:25:10,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:10,011 INFO L93 Difference]: Finished difference Result 185 states and 204 transitions. [2018-01-24 15:25:10,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 15:25:10,011 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-01-24 15:25:10,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:10,012 INFO L225 Difference]: With dead ends: 185 [2018-01-24 15:25:10,013 INFO L226 Difference]: Without dead ends: 182 [2018-01-24 15:25:10,013 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 157 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 15:25:10,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-01-24 15:25:10,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 82. [2018-01-24 15:25:10,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-24 15:25:10,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 89 transitions. [2018-01-24 15:25:10,023 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 89 transitions. Word has length 42 [2018-01-24 15:25:10,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:10,024 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 89 transitions. [2018-01-24 15:25:10,024 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 15:25:10,024 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 89 transitions. [2018-01-24 15:25:10,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-01-24 15:25:10,025 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:10,025 INFO L322 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:10,025 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:10,025 INFO L82 PathProgramCache]: Analyzing trace with hash -676728868, now seen corresponding path program 8 times [2018-01-24 15:25:10,026 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:10,026 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:10,027 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:10,027 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:10,027 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:10,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:10,034 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:10,181 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:10,181 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:10,181 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:10,181 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:10,182 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:10,182 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:10,182 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:10,188 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:10,189 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:10,193 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:10,198 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:10,206 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:10,208 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:10,229 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:10,230 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:10,367 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:10,387 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:10,387 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:10,390 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:10,390 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:10,393 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:10,399 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:10,405 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:10,407 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:10,415 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:10,415 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:10,428 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:10,429 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:10,429 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 15:25:10,429 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:10,429 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 15:25:10,429 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 15:25:10,430 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 15:25:10,430 INFO L87 Difference]: Start difference. First operand 82 states and 89 transitions. Second operand 11 states. [2018-01-24 15:25:10,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:10,583 INFO L93 Difference]: Finished difference Result 215 states and 238 transitions. [2018-01-24 15:25:10,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 15:25:10,584 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 47 [2018-01-24 15:25:10,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:10,585 INFO L225 Difference]: With dead ends: 215 [2018-01-24 15:25:10,586 INFO L226 Difference]: Without dead ends: 212 [2018-01-24 15:25:10,586 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 176 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 15:25:10,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states. [2018-01-24 15:25:10,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 87. [2018-01-24 15:25:10,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-01-24 15:25:10,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 95 transitions. [2018-01-24 15:25:10,597 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 95 transitions. Word has length 47 [2018-01-24 15:25:10,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:10,598 INFO L432 AbstractCegarLoop]: Abstraction has 87 states and 95 transitions. [2018-01-24 15:25:10,598 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 15:25:10,598 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 95 transitions. [2018-01-24 15:25:10,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 15:25:10,599 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:10,599 INFO L322 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:10,599 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:10,600 INFO L82 PathProgramCache]: Analyzing trace with hash -633576169, now seen corresponding path program 9 times [2018-01-24 15:25:10,600 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:10,601 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:10,601 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:10,601 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:10,601 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:10,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:10,608 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:10,734 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:10,734 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:10,735 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:10,735 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:10,735 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:10,735 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:10,735 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:10,741 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:10,741 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:10,744 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:10,745 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:10,746 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:10,747 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:10,748 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:10,750 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:10,751 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:10,752 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:10,754 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:10,756 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:10,756 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:10,758 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:10,778 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:10,778 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:10,954 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:10,986 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:10,986 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:10,989 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:10,989 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:10,993 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:10,994 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:10,998 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:11,003 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:11,009 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:11,017 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:11,024 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:11,034 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:11,045 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:11,062 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:11,068 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:11,071 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:11,092 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:11,093 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:11,113 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:11,115 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:11,115 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 15:25:11,115 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:11,116 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 15:25:11,116 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 15:25:11,116 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 15:25:11,116 INFO L87 Difference]: Start difference. First operand 87 states and 95 transitions. Second operand 12 states. [2018-01-24 15:25:11,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:11,350 INFO L93 Difference]: Finished difference Result 245 states and 272 transitions. [2018-01-24 15:25:11,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 15:25:11,351 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 52 [2018-01-24 15:25:11,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:11,353 INFO L225 Difference]: With dead ends: 245 [2018-01-24 15:25:11,353 INFO L226 Difference]: Without dead ends: 242 [2018-01-24 15:25:11,354 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 195 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 15:25:11,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states. [2018-01-24 15:25:11,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 92. [2018-01-24 15:25:11,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-01-24 15:25:11,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 101 transitions. [2018-01-24 15:25:11,366 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 101 transitions. Word has length 52 [2018-01-24 15:25:11,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:11,367 INFO L432 AbstractCegarLoop]: Abstraction has 92 states and 101 transitions. [2018-01-24 15:25:11,367 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 15:25:11,367 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 101 transitions. [2018-01-24 15:25:11,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-01-24 15:25:11,368 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:11,368 INFO L322 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:11,369 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:11,369 INFO L82 PathProgramCache]: Analyzing trace with hash -1365705540, now seen corresponding path program 10 times [2018-01-24 15:25:11,369 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:11,370 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:11,370 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:11,370 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:11,370 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:11,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:11,378 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:11,517 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:11,517 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:11,517 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:11,518 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:11,518 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:11,518 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:11,518 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:11,523 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:11,523 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:11,533 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:11,535 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:11,545 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:11,546 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:11,692 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:11,711 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:11,712 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:11,714 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:11,714 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:11,746 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:11,749 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:11,758 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:11,759 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:11,773 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:11,774 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:11,774 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 15:25:11,774 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:11,775 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 15:25:11,775 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 15:25:11,775 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 15:25:11,775 INFO L87 Difference]: Start difference. First operand 92 states and 101 transitions. Second operand 13 states. [2018-01-24 15:25:12,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:12,026 INFO L93 Difference]: Finished difference Result 275 states and 306 transitions. [2018-01-24 15:25:12,026 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 15:25:12,026 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2018-01-24 15:25:12,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:12,028 INFO L225 Difference]: With dead ends: 275 [2018-01-24 15:25:12,028 INFO L226 Difference]: Without dead ends: 272 [2018-01-24 15:25:12,028 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 214 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 15:25:12,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2018-01-24 15:25:12,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 97. [2018-01-24 15:25:12,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-01-24 15:25:12,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 107 transitions. [2018-01-24 15:25:12,043 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 107 transitions. Word has length 57 [2018-01-24 15:25:12,043 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:12,043 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 107 transitions. [2018-01-24 15:25:12,043 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 15:25:12,043 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 107 transitions. [2018-01-24 15:25:12,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 15:25:12,044 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:12,044 INFO L322 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:12,044 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:12,044 INFO L82 PathProgramCache]: Analyzing trace with hash -1933470172, now seen corresponding path program 4 times [2018-01-24 15:25:12,044 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:12,045 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:12,045 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:12,045 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:12,045 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:12,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:12,053 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:12,159 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 10 proven. 59 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-01-24 15:25:12,159 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:12,159 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:12,159 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:12,159 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:12,159 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:12,160 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:12,168 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:12,169 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:12,177 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:12,179 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:12,201 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:25:12,201 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:12,247 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:25:12,267 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:12,267 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:12,270 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:12,270 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:12,296 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:12,298 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:12,329 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:25:12,330 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:12,364 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 15:25:12,365 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:12,365 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 5, 5, 5, 5] total 18 [2018-01-24 15:25:12,366 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:12,366 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 15:25:12,366 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 15:25:12,366 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=269, Unknown=0, NotChecked=0, Total=342 [2018-01-24 15:25:12,367 INFO L87 Difference]: Start difference. First operand 97 states and 107 transitions. Second operand 15 states. [2018-01-24 15:25:12,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:12,560 INFO L93 Difference]: Finished difference Result 134 states and 152 transitions. [2018-01-24 15:25:12,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 15:25:12,560 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 62 [2018-01-24 15:25:12,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:12,562 INFO L225 Difference]: With dead ends: 134 [2018-01-24 15:25:12,562 INFO L226 Difference]: Without dead ends: 105 [2018-01-24 15:25:12,563 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 260 GetRequests, 238 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 112 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=103, Invalid=359, Unknown=0, NotChecked=0, Total=462 [2018-01-24 15:25:12,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-01-24 15:25:12,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 103. [2018-01-24 15:25:12,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-01-24 15:25:12,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 113 transitions. [2018-01-24 15:25:12,571 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 113 transitions. Word has length 62 [2018-01-24 15:25:12,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:12,571 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 113 transitions. [2018-01-24 15:25:12,571 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 15:25:12,571 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 113 transitions. [2018-01-24 15:25:12,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 15:25:12,572 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:12,572 INFO L322 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:12,572 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:12,572 INFO L82 PathProgramCache]: Analyzing trace with hash -116235209, now seen corresponding path program 11 times [2018-01-24 15:25:12,572 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:12,573 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:12,573 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:12,573 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:12,573 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:12,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:12,579 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:12,783 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:12,783 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:12,783 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:12,783 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:12,783 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:12,784 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:12,784 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:12,799 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:12,799 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:12,802 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,803 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,804 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,806 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,807 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,808 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,810 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,812 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,814 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,817 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,820 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,823 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:12,824 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:12,826 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:12,840 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:12,840 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:13,084 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:13,104 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:13,104 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:13,107 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:13,107 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:13,111 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:13,113 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:13,117 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:13,122 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:13,127 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:13,133 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:13,141 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:13,153 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:13,167 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:13,181 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:13,197 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:13,217 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:13,223 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:13,226 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:13,241 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:13,241 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:13,261 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:13,263 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:13,263 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 15:25:13,263 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:13,263 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 15:25:13,263 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 15:25:13,263 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 15:25:13,264 INFO L87 Difference]: Start difference. First operand 103 states and 113 transitions. Second operand 14 states. [2018-01-24 15:25:13,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:13,498 INFO L93 Difference]: Finished difference Result 328 states and 367 transitions. [2018-01-24 15:25:13,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 15:25:13,499 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 62 [2018-01-24 15:25:13,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:13,501 INFO L225 Difference]: With dead ends: 328 [2018-01-24 15:25:13,501 INFO L226 Difference]: Without dead ends: 325 [2018-01-24 15:25:13,501 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 233 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 15:25:13,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2018-01-24 15:25:13,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 108. [2018-01-24 15:25:13,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-01-24 15:25:13,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 119 transitions. [2018-01-24 15:25:13,517 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 119 transitions. Word has length 62 [2018-01-24 15:25:13,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:13,517 INFO L432 AbstractCegarLoop]: Abstraction has 108 states and 119 transitions. [2018-01-24 15:25:13,517 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 15:25:13,517 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 119 transitions. [2018-01-24 15:25:13,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-01-24 15:25:13,518 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:13,518 INFO L322 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:13,518 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:13,518 INFO L82 PathProgramCache]: Analyzing trace with hash -414879332, now seen corresponding path program 12 times [2018-01-24 15:25:13,518 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:13,519 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:13,519 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:13,519 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:13,520 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:13,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:13,528 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:13,705 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:13,705 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:13,705 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:13,705 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:13,705 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:13,705 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:13,705 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:13,710 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:13,710 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:13,713 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,714 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,715 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,715 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,716 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,717 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,718 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,719 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,720 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,721 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,723 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,724 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,726 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,726 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:13,727 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:13,737 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:13,737 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:13,928 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:13,948 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:13,948 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 34 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:13,951 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:13,951 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:13,955 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,956 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,959 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,963 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,968 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,973 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,981 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:13,992 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:14,005 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:14,021 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:14,037 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:14,060 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:14,087 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:14,093 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:14,097 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:14,110 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:14,111 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:14,137 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:14,139 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:14,139 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 15:25:14,139 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:14,139 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 15:25:14,139 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 15:25:14,140 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 15:25:14,140 INFO L87 Difference]: Start difference. First operand 108 states and 119 transitions. Second operand 15 states. [2018-01-24 15:25:14,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:14,424 INFO L93 Difference]: Finished difference Result 364 states and 408 transitions. [2018-01-24 15:25:14,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 15:25:14,424 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 67 [2018-01-24 15:25:14,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:14,426 INFO L225 Difference]: With dead ends: 364 [2018-01-24 15:25:14,426 INFO L226 Difference]: Without dead ends: 361 [2018-01-24 15:25:14,426 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 280 GetRequests, 252 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 15:25:14,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 361 states. [2018-01-24 15:25:14,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 361 to 113. [2018-01-24 15:25:14,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-01-24 15:25:14,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 125 transitions. [2018-01-24 15:25:14,438 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 125 transitions. Word has length 67 [2018-01-24 15:25:14,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:14,438 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 125 transitions. [2018-01-24 15:25:14,438 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 15:25:14,439 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 125 transitions. [2018-01-24 15:25:14,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-01-24 15:25:14,439 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:14,440 INFO L322 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:14,440 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:14,440 INFO L82 PathProgramCache]: Analyzing trace with hash -1135871145, now seen corresponding path program 13 times [2018-01-24 15:25:14,440 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:14,441 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:14,441 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:14,441 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:14,441 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:14,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:14,449 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:14,638 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:14,639 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:14,639 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:14,639 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:14,639 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:14,639 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:14,639 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:14,644 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:14,644 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:14,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:14,654 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:14,664 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:14,665 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:14,866 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:14,885 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:14,885 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 36 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:14,888 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:14,888 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:14,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:14,907 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:14,922 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:14,922 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:14,934 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:14,935 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:14,936 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 29 [2018-01-24 15:25:14,936 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:14,936 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 15:25:14,936 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 15:25:14,936 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 15:25:14,936 INFO L87 Difference]: Start difference. First operand 113 states and 125 transitions. Second operand 16 states. [2018-01-24 15:25:15,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:15,240 INFO L93 Difference]: Finished difference Result 400 states and 449 transitions. [2018-01-24 15:25:15,241 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 15:25:15,241 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2018-01-24 15:25:15,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:15,243 INFO L225 Difference]: With dead ends: 400 [2018-01-24 15:25:15,243 INFO L226 Difference]: Without dead ends: 397 [2018-01-24 15:25:15,243 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 301 GetRequests, 271 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 15:25:15,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 397 states. [2018-01-24 15:25:15,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 397 to 118. [2018-01-24 15:25:15,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-24 15:25:15,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 131 transitions. [2018-01-24 15:25:15,256 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 131 transitions. Word has length 72 [2018-01-24 15:25:15,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:15,256 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 131 transitions. [2018-01-24 15:25:15,256 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 15:25:15,256 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 131 transitions. [2018-01-24 15:25:15,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-01-24 15:25:15,257 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:15,258 INFO L322 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:15,258 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:15,258 INFO L82 PathProgramCache]: Analyzing trace with hash 1226682691, now seen corresponding path program 5 times [2018-01-24 15:25:15,258 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:15,259 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:15,259 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:15,259 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:15,259 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:15,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:15,268 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:15,392 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 24 proven. 89 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 15:25:15,392 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:15,392 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:15,392 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:15,392 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:15,392 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:15,392 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:15,397 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:15,397 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:15,401 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:15,403 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:15,405 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:15,407 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:15,409 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:15,412 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:15,412 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:15,414 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:15,476 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 15:25:15,476 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:15,588 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 15:25:15,609 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:15,609 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 38 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:15,614 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:15,614 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:15,618 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:15,621 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:15,629 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:15,638 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:15,649 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:15,668 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:15,676 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:15,679 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:15,689 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 15:25:15,689 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:15,700 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 15:25:15,701 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:15,701 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 6, 6, 6, 6] total 22 [2018-01-24 15:25:15,702 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:15,702 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 15:25:15,702 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 15:25:15,702 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=406, Unknown=0, NotChecked=0, Total=506 [2018-01-24 15:25:15,702 INFO L87 Difference]: Start difference. First operand 118 states and 131 transitions. Second operand 18 states. [2018-01-24 15:25:15,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:15,863 INFO L93 Difference]: Finished difference Result 161 states and 183 transitions. [2018-01-24 15:25:15,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 15:25:15,864 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 77 [2018-01-24 15:25:15,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:15,865 INFO L225 Difference]: With dead ends: 161 [2018-01-24 15:25:15,865 INFO L226 Difference]: Without dead ends: 126 [2018-01-24 15:25:15,865 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 323 GetRequests, 296 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 169 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=146, Invalid=556, Unknown=0, NotChecked=0, Total=702 [2018-01-24 15:25:15,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-01-24 15:25:15,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 124. [2018-01-24 15:25:15,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-01-24 15:25:15,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 137 transitions. [2018-01-24 15:25:15,881 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 137 transitions. Word has length 77 [2018-01-24 15:25:15,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:15,882 INFO L432 AbstractCegarLoop]: Abstraction has 124 states and 137 transitions. [2018-01-24 15:25:15,882 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 15:25:15,882 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 137 transitions. [2018-01-24 15:25:15,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-01-24 15:25:15,883 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:15,883 INFO L322 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:15,883 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:15,883 INFO L82 PathProgramCache]: Analyzing trace with hash 571297404, now seen corresponding path program 14 times [2018-01-24 15:25:15,883 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:15,884 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:15,884 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:15,884 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:15,884 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:15,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:15,892 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:16,111 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:16,112 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:16,112 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:16,112 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:16,112 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:16,112 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:16,112 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:16,118 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:16,118 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:16,122 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:16,131 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:16,133 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:16,135 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:16,154 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:16,154 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:16,435 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:16,455 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:16,455 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 40 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:16,458 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:16,458 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:16,462 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:16,472 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:16,479 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:16,483 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:16,496 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:16,496 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:16,515 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:16,517 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:16,517 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 31 [2018-01-24 15:25:16,517 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:16,517 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 15:25:16,518 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 15:25:16,518 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 15:25:16,518 INFO L87 Difference]: Start difference. First operand 124 states and 137 transitions. Second operand 17 states. [2018-01-24 15:25:16,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:16,909 INFO L93 Difference]: Finished difference Result 465 states and 524 transitions. [2018-01-24 15:25:16,909 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 15:25:16,909 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 77 [2018-01-24 15:25:16,910 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:16,912 INFO L225 Difference]: With dead ends: 465 [2018-01-24 15:25:16,912 INFO L226 Difference]: Without dead ends: 462 [2018-01-24 15:25:16,913 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 322 GetRequests, 290 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 15:25:16,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-01-24 15:25:16,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 129. [2018-01-24 15:25:16,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-01-24 15:25:16,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 143 transitions. [2018-01-24 15:25:16,933 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 143 transitions. Word has length 77 [2018-01-24 15:25:16,933 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:16,933 INFO L432 AbstractCegarLoop]: Abstraction has 129 states and 143 transitions. [2018-01-24 15:25:16,933 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 15:25:16,933 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 143 transitions. [2018-01-24 15:25:16,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-01-24 15:25:16,934 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:16,934 INFO L322 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:16,934 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:16,934 INFO L82 PathProgramCache]: Analyzing trace with hash 239807095, now seen corresponding path program 15 times [2018-01-24 15:25:16,934 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:16,935 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:16,935 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:16,935 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:16,935 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:16,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:16,943 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:17,120 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:17,120 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:17,120 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:17,120 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:17,120 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:17,120 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:17,121 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:17,126 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:17,126 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:17,129 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,132 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,132 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,133 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,134 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,135 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,136 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,138 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,139 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,141 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,143 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,145 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,147 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,149 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,152 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,153 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:17,154 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:17,171 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:17,172 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:17,444 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:17,465 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:17,465 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 42 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:17,471 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:17,472 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:17,476 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,477 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,481 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,485 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,491 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,498 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,506 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,514 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,526 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,542 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,561 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,581 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,605 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,635 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,675 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,722 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:17,732 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:17,735 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:17,751 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:17,751 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:17,771 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:17,772 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:17,772 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 33 [2018-01-24 15:25:17,772 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:17,772 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 15:25:17,773 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 15:25:17,773 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 15:25:17,773 INFO L87 Difference]: Start difference. First operand 129 states and 143 transitions. Second operand 18 states. [2018-01-24 15:25:18,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:18,263 INFO L93 Difference]: Finished difference Result 507 states and 572 transitions. [2018-01-24 15:25:18,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 15:25:18,263 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 82 [2018-01-24 15:25:18,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:18,266 INFO L225 Difference]: With dead ends: 507 [2018-01-24 15:25:18,266 INFO L226 Difference]: Without dead ends: 504 [2018-01-24 15:25:18,267 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 309 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 15:25:18,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states. [2018-01-24 15:25:18,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 134. [2018-01-24 15:25:18,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-24 15:25:18,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 149 transitions. [2018-01-24 15:25:18,290 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 149 transitions. Word has length 82 [2018-01-24 15:25:18,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:18,290 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 149 transitions. [2018-01-24 15:25:18,290 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 15:25:18,291 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 149 transitions. [2018-01-24 15:25:18,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 15:25:18,292 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:18,292 INFO L322 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:18,292 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:18,292 INFO L82 PathProgramCache]: Analyzing trace with hash -1580297380, now seen corresponding path program 16 times [2018-01-24 15:25:18,292 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:18,293 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:18,293 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:18,293 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:18,293 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:18,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:18,302 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:18,790 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:18,790 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:18,790 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:18,790 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:18,791 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:18,791 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:18,791 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:18,800 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:18,800 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:18,827 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:18,830 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:18,856 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:18,857 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:19,227 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,247 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:19,247 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 44 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:19,250 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:19,250 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:19,317 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:19,321 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:19,342 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,342 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:19,359 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,361 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:19,361 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 35 [2018-01-24 15:25:19,361 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:19,361 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 15:25:19,362 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 15:25:19,362 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 15:25:19,362 INFO L87 Difference]: Start difference. First operand 134 states and 149 transitions. Second operand 19 states. [2018-01-24 15:25:19,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:19,850 INFO L93 Difference]: Finished difference Result 549 states and 620 transitions. [2018-01-24 15:25:19,851 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 15:25:19,851 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 87 [2018-01-24 15:25:19,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:19,853 INFO L225 Difference]: With dead ends: 549 [2018-01-24 15:25:19,853 INFO L226 Difference]: Without dead ends: 546 [2018-01-24 15:25:19,854 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 364 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 15:25:19,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states. [2018-01-24 15:25:19,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 139. [2018-01-24 15:25:19,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-01-24 15:25:19,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 155 transitions. [2018-01-24 15:25:19,871 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 155 transitions. Word has length 87 [2018-01-24 15:25:19,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:19,871 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 155 transitions. [2018-01-24 15:25:19,872 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 15:25:19,872 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 155 transitions. [2018-01-24 15:25:19,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 15:25:19,873 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:19,873 INFO L322 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:19,873 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:19,873 INFO L82 PathProgramCache]: Analyzing trace with hash 677887160, now seen corresponding path program 6 times [2018-01-24 15:25:19,874 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:19,874 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:19,874 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:19,875 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:19,875 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:19,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:19,884 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:20,027 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 44 proven. 124 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-01-24 15:25:20,027 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:20,027 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:20,027 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:20,028 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:20,028 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:20,028 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:20,032 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:20,033 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:20,036 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,038 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,039 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,041 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,043 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,045 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,047 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,048 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:20,050 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:20,095 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 15:25:20,095 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:20,179 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 15:25:20,199 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:20,200 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 46 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:20,202 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:20,203 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:20,208 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,210 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,215 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,224 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,235 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,250 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,271 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,280 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:20,284 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:20,303 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 15:25:20,303 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:20,319 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 15:25:20,320 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:20,320 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 7, 7, 7, 7] total 26 [2018-01-24 15:25:20,320 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:20,321 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 15:25:20,321 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 15:25:20,321 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=571, Unknown=0, NotChecked=0, Total=702 [2018-01-24 15:25:20,321 INFO L87 Difference]: Start difference. First operand 139 states and 155 transitions. Second operand 21 states. [2018-01-24 15:25:20,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:20,503 INFO L93 Difference]: Finished difference Result 188 states and 214 transitions. [2018-01-24 15:25:20,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 15:25:20,503 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 92 [2018-01-24 15:25:20,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:20,504 INFO L225 Difference]: With dead ends: 188 [2018-01-24 15:25:20,504 INFO L226 Difference]: Without dead ends: 147 [2018-01-24 15:25:20,504 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 386 GetRequests, 354 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 238 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=196, Invalid=796, Unknown=0, NotChecked=0, Total=992 [2018-01-24 15:25:20,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-01-24 15:25:20,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 145. [2018-01-24 15:25:20,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-01-24 15:25:20,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 161 transitions. [2018-01-24 15:25:20,518 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 161 transitions. Word has length 92 [2018-01-24 15:25:20,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:20,518 INFO L432 AbstractCegarLoop]: Abstraction has 145 states and 161 transitions. [2018-01-24 15:25:20,518 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 15:25:20,518 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 161 transitions. [2018-01-24 15:25:20,519 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 15:25:20,519 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:20,519 INFO L322 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:20,519 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:20,519 INFO L82 PathProgramCache]: Analyzing trace with hash -957222505, now seen corresponding path program 17 times [2018-01-24 15:25:20,519 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:20,520 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:20,520 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:20,520 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:20,520 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:20,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:20,525 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:20,784 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:20,785 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:20,785 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:20,785 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:20,785 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:20,785 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:20,785 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:20,794 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:20,794 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:20,797 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,803 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,806 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,810 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,816 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,818 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,819 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,821 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,823 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,826 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,829 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,838 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,842 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,847 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,852 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,855 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,860 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,867 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,868 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:20,870 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:20,916 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:20,916 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:21,313 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:21,333 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:21,333 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 48 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:21,336 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:21,336 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:21,339 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,341 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,345 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,349 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,355 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,362 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,371 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,381 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,396 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,415 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,432 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,452 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,476 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,513 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,556 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,593 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,635 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,683 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:21,695 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:21,699 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:21,717 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:21,717 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:21,736 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:21,737 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:21,737 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 37 [2018-01-24 15:25:21,737 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:21,738 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 15:25:21,738 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 15:25:21,739 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 15:25:21,739 INFO L87 Difference]: Start difference. First operand 145 states and 161 transitions. Second operand 20 states. [2018-01-24 15:25:22,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:22,280 INFO L93 Difference]: Finished difference Result 626 states and 709 transitions. [2018-01-24 15:25:22,281 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 15:25:22,281 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 92 [2018-01-24 15:25:22,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:22,283 INFO L225 Difference]: With dead ends: 626 [2018-01-24 15:25:22,283 INFO L226 Difference]: Without dead ends: 623 [2018-01-24 15:25:22,284 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 385 GetRequests, 347 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 15:25:22,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 623 states. [2018-01-24 15:25:22,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 623 to 150. [2018-01-24 15:25:22,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-01-24 15:25:22,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 167 transitions. [2018-01-24 15:25:22,312 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 167 transitions. Word has length 92 [2018-01-24 15:25:22,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:22,312 INFO L432 AbstractCegarLoop]: Abstraction has 150 states and 167 transitions. [2018-01-24 15:25:22,312 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 15:25:22,312 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 167 transitions. [2018-01-24 15:25:22,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-01-24 15:25:22,313 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:22,313 INFO L322 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:22,313 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:22,313 INFO L82 PathProgramCache]: Analyzing trace with hash 736575548, now seen corresponding path program 18 times [2018-01-24 15:25:22,313 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:22,314 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:22,314 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:22,314 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:22,314 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:22,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:22,322 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:22,607 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:22,608 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:22,608 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:22,608 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:22,608 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:22,608 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:22,608 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:22,614 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:22,614 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:22,618 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,619 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,619 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,620 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,621 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,622 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,623 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,624 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,625 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,626 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,627 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,629 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,630 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,632 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,633 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,635 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,637 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,640 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,642 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:22,643 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:22,645 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:22,661 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:22,661 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:23,221 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:23,241 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:23,241 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 50 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:23,244 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:23,244 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:23,248 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,249 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,253 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,257 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,262 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,268 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,275 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,284 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,298 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,315 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,336 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,357 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,378 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,402 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,430 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,462 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,500 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,548 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,666 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:23,678 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:23,683 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:23,710 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:23,710 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:23,729 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:23,730 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:23,730 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 39 [2018-01-24 15:25:23,730 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:23,731 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 15:25:23,731 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 15:25:23,731 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 15:25:23,731 INFO L87 Difference]: Start difference. First operand 150 states and 167 transitions. Second operand 21 states. [2018-01-24 15:25:24,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:24,354 INFO L93 Difference]: Finished difference Result 674 states and 764 transitions. [2018-01-24 15:25:24,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 15:25:24,354 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 97 [2018-01-24 15:25:24,355 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:24,356 INFO L225 Difference]: With dead ends: 674 [2018-01-24 15:25:24,357 INFO L226 Difference]: Without dead ends: 671 [2018-01-24 15:25:24,357 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 406 GetRequests, 366 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 15:25:24,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 671 states. [2018-01-24 15:25:24,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 671 to 155. [2018-01-24 15:25:24,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 155 states. [2018-01-24 15:25:24,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 173 transitions. [2018-01-24 15:25:24,377 INFO L78 Accepts]: Start accepts. Automaton has 155 states and 173 transitions. Word has length 97 [2018-01-24 15:25:24,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:24,378 INFO L432 AbstractCegarLoop]: Abstraction has 155 states and 173 transitions. [2018-01-24 15:25:24,378 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 15:25:24,378 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 173 transitions. [2018-01-24 15:25:24,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-24 15:25:24,378 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:24,378 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:24,378 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:24,379 INFO L82 PathProgramCache]: Analyzing trace with hash -891985897, now seen corresponding path program 7 times [2018-01-24 15:25:24,379 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:24,379 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:24,379 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:24,379 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:24,379 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:24,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:24,386 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:24,639 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 70 proven. 164 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 15:25:24,639 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:24,639 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:24,639 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:24,639 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:24,639 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:24,639 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:24,645 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:24,645 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:24,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:24,662 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:24,831 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 15:25:24,832 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:25,002 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 15:25:25,022 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:25,022 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 52 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:25,025 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:25,025 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:25,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:25,060 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:25,121 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 15:25:25,121 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:25,160 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 15:25:25,161 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:25,162 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 8, 8, 8, 8] total 30 [2018-01-24 15:25:25,162 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:25,162 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 15:25:25,162 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 15:25:25,163 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=764, Unknown=0, NotChecked=0, Total=930 [2018-01-24 15:25:25,163 INFO L87 Difference]: Start difference. First operand 155 states and 173 transitions. Second operand 24 states. [2018-01-24 15:25:25,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:25,508 INFO L93 Difference]: Finished difference Result 210 states and 239 transitions. [2018-01-24 15:25:25,508 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 15:25:25,508 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 107 [2018-01-24 15:25:25,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:25,509 INFO L225 Difference]: With dead ends: 210 [2018-01-24 15:25:25,509 INFO L226 Difference]: Without dead ends: 163 [2018-01-24 15:25:25,510 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 449 GetRequests, 412 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 319 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=253, Invalid=1079, Unknown=0, NotChecked=0, Total=1332 [2018-01-24 15:25:25,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-01-24 15:25:25,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 161. [2018-01-24 15:25:25,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 161 states. [2018-01-24 15:25:25,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 179 transitions. [2018-01-24 15:25:25,528 INFO L78 Accepts]: Start accepts. Automaton has 161 states and 179 transitions. Word has length 107 [2018-01-24 15:25:25,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:25,528 INFO L432 AbstractCegarLoop]: Abstraction has 161 states and 179 transitions. [2018-01-24 15:25:25,528 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 15:25:25,528 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 179 transitions. [2018-01-24 15:25:25,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-24 15:25:25,529 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:25,529 INFO L322 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:25,529 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:25,529 INFO L82 PathProgramCache]: Analyzing trace with hash -878554953, now seen corresponding path program 19 times [2018-01-24 15:25:25,529 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:25,530 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:25,530 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:25,530 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:25,530 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:25,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:25,536 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:25,829 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:25,830 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:25,830 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:25,830 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:25,830 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:25,830 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:25,830 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:25,835 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:25,835 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:25,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:25,849 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:25,868 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:25,869 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:26,286 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:26,305 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:26,306 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 54 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:26,308 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:26,309 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:26,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:26,335 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:26,353 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:26,353 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:26,373 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:26,374 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:26,374 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 41 [2018-01-24 15:25:26,374 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:26,375 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 15:25:26,375 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 15:25:26,375 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 15:25:26,375 INFO L87 Difference]: Start difference. First operand 161 states and 179 transitions. Second operand 22 states. [2018-01-24 15:25:27,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:27,053 INFO L93 Difference]: Finished difference Result 757 states and 860 transitions. [2018-01-24 15:25:27,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 15:25:27,363 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 102 [2018-01-24 15:25:27,363 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:27,367 INFO L225 Difference]: With dead ends: 757 [2018-01-24 15:25:27,367 INFO L226 Difference]: Without dead ends: 754 [2018-01-24 15:25:27,369 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 427 GetRequests, 385 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 15:25:27,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 754 states. [2018-01-24 15:25:27,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 754 to 166. [2018-01-24 15:25:27,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-01-24 15:25:27,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 185 transitions. [2018-01-24 15:25:27,431 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 185 transitions. Word has length 102 [2018-01-24 15:25:27,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:27,432 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 185 transitions. [2018-01-24 15:25:27,432 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 15:25:27,432 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 185 transitions. [2018-01-24 15:25:27,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-24 15:25:27,433 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:27,434 INFO L322 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:27,434 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:27,434 INFO L82 PathProgramCache]: Analyzing trace with hash -399157988, now seen corresponding path program 20 times [2018-01-24 15:25:27,434 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:27,435 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:27,435 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:27,435 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:27,435 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:27,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:27,446 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:27,870 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:27,870 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:27,870 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:27,870 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:27,871 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:27,871 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:27,871 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:27,875 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:27,876 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:27,879 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:27,886 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:27,887 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:27,889 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:27,911 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:27,912 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:28,402 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:28,422 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:28,422 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 56 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:28,425 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:28,425 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:28,430 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:28,445 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:28,455 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:28,459 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:28,477 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:28,477 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:28,500 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:28,501 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:28,501 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 43 [2018-01-24 15:25:28,501 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:28,502 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 15:25:28,502 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 15:25:28,502 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 15:25:28,503 INFO L87 Difference]: Start difference. First operand 166 states and 185 transitions. Second operand 23 states. [2018-01-24 15:25:29,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:29,411 INFO L93 Difference]: Finished difference Result 811 states and 922 transitions. [2018-01-24 15:25:29,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 15:25:29,412 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 107 [2018-01-24 15:25:29,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:29,415 INFO L225 Difference]: With dead ends: 811 [2018-01-24 15:25:29,415 INFO L226 Difference]: Without dead ends: 808 [2018-01-24 15:25:29,416 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 404 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 15:25:29,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 808 states. [2018-01-24 15:25:29,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 808 to 171. [2018-01-24 15:25:29,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-01-24 15:25:29,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 191 transitions. [2018-01-24 15:25:29,461 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 191 transitions. Word has length 107 [2018-01-24 15:25:29,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:29,461 INFO L432 AbstractCegarLoop]: Abstraction has 171 states and 191 transitions. [2018-01-24 15:25:29,462 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 15:25:29,462 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 191 transitions. [2018-01-24 15:25:29,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-01-24 15:25:29,463 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:29,463 INFO L322 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:29,463 INFO L371 AbstractCegarLoop]: === Iteration 31 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:29,463 INFO L82 PathProgramCache]: Analyzing trace with hash 792610775, now seen corresponding path program 21 times [2018-01-24 15:25:29,463 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:29,464 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:29,464 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:29,464 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:29,464 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:29,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:29,472 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:29,876 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:29,876 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:29,876 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:29,876 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:29,876 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:29,876 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:29,876 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:29,881 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:29,881 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:29,885 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,886 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,887 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,888 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,889 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,890 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,892 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,893 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,895 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,896 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,898 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,900 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,902 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,905 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,907 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,910 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,913 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,916 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,920 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,924 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,928 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,932 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,933 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:29,936 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:29,971 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:29,971 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:30,535 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:30,555 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:30,555 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 58 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:30,558 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:30,558 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:30,562 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,564 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,567 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,571 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,577 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,584 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,591 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,600 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,611 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,626 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,644 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,664 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,687 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,715 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,753 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,798 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,843 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,895 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,956 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:31,041 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:31,137 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:31,231 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:31,245 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:31,249 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:31,272 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:31,272 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:31,296 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:31,298 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:31,298 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 45 [2018-01-24 15:25:31,298 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:31,298 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 15:25:31,299 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 15:25:31,299 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 15:25:31,299 INFO L87 Difference]: Start difference. First operand 171 states and 191 transitions. Second operand 24 states. [2018-01-24 15:25:32,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:32,200 INFO L93 Difference]: Finished difference Result 865 states and 984 transitions. [2018-01-24 15:25:32,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 15:25:32,255 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 112 [2018-01-24 15:25:32,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:32,258 INFO L225 Difference]: With dead ends: 865 [2018-01-24 15:25:32,258 INFO L226 Difference]: Without dead ends: 862 [2018-01-24 15:25:32,259 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 423 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 15:25:32,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 862 states. [2018-01-24 15:25:32,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 862 to 176. [2018-01-24 15:25:32,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-01-24 15:25:32,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 197 transitions. [2018-01-24 15:25:32,304 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 197 transitions. Word has length 112 [2018-01-24 15:25:32,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:32,305 INFO L432 AbstractCegarLoop]: Abstraction has 176 states and 197 transitions. [2018-01-24 15:25:32,305 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 15:25:32,305 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 197 transitions. [2018-01-24 15:25:32,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-24 15:25:32,306 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:32,306 INFO L322 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:32,306 INFO L371 AbstractCegarLoop]: === Iteration 32 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:32,307 INFO L82 PathProgramCache]: Analyzing trace with hash -600860340, now seen corresponding path program 8 times [2018-01-24 15:25:32,307 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:32,307 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:32,307 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:32,308 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:32,308 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:32,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:32,318 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:32,600 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 102 proven. 209 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-01-24 15:25:32,601 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:32,601 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:32,601 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:32,601 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:32,601 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:32,601 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:32,606 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:32,606 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:32,610 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,619 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,620 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:32,622 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:32,693 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 0 proven. 147 refuted. 0 times theorem prover too weak. 248 trivial. 0 not checked. [2018-01-24 15:25:32,693 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:32,831 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 0 proven. 147 refuted. 0 times theorem prover too weak. 248 trivial. 0 not checked. [2018-01-24 15:25:32,851 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:32,851 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 60 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:32,854 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:32,854 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:32,859 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,875 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,888 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:32,892 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:32,928 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 140 proven. 171 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-01-24 15:25:32,928 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:33,646 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 126 proven. 185 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-01-24 15:25:33,647 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:33,647 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 9, 9, 19, 19] total 52 [2018-01-24 15:25:33,648 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:33,648 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 15:25:33,648 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 15:25:33,649 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=550, Invalid=2206, Unknown=0, NotChecked=0, Total=2756 [2018-01-24 15:25:33,649 INFO L87 Difference]: Start difference. First operand 176 states and 197 transitions. Second operand 27 states. [2018-01-24 15:25:33,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:33,956 INFO L93 Difference]: Finished difference Result 237 states and 270 transitions. [2018-01-24 15:25:33,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 15:25:33,957 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 122 [2018-01-24 15:25:33,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:33,958 INFO L225 Difference]: With dead ends: 237 [2018-01-24 15:25:33,958 INFO L226 Difference]: Without dead ends: 184 [2018-01-24 15:25:33,959 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 512 GetRequests, 453 SyntacticMatches, 1 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 951 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=788, Invalid=2752, Unknown=0, NotChecked=0, Total=3540 [2018-01-24 15:25:33,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-01-24 15:25:33,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 182. [2018-01-24 15:25:33,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-24 15:25:33,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 203 transitions. [2018-01-24 15:25:33,987 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 203 transitions. Word has length 122 [2018-01-24 15:25:33,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:33,987 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 203 transitions. [2018-01-24 15:25:33,987 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 15:25:33,988 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 203 transitions. [2018-01-24 15:25:33,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-01-24 15:25:33,989 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:33,989 INFO L322 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:33,989 INFO L371 AbstractCegarLoop]: === Iteration 33 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:33,989 INFO L82 PathProgramCache]: Analyzing trace with hash 1092014588, now seen corresponding path program 22 times [2018-01-24 15:25:33,989 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:33,990 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:33,990 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:33,990 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:33,990 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:33,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:33,998 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:34,334 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:34,334 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:34,334 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:34,334 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:34,334 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:34,334 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:34,335 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:34,340 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:34,340 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:34,363 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:34,366 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:34,387 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:34,387 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:34,948 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:34,969 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:34,969 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 62 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:34,972 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:34,972 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:35,104 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:35,109 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:35,140 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:35,140 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:35,169 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:35,171 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:35,171 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 47 [2018-01-24 15:25:35,171 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:35,171 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 15:25:35,171 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 15:25:35,172 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 15:25:35,172 INFO L87 Difference]: Start difference. First operand 182 states and 203 transitions. Second operand 25 states. [2018-01-24 15:25:36,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:36,125 INFO L93 Difference]: Finished difference Result 960 states and 1094 transitions. [2018-01-24 15:25:36,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 15:25:36,125 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 117 [2018-01-24 15:25:36,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:36,128 INFO L225 Difference]: With dead ends: 960 [2018-01-24 15:25:36,128 INFO L226 Difference]: Without dead ends: 957 [2018-01-24 15:25:36,129 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 442 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 15:25:36,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957 states. [2018-01-24 15:25:36,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 957 to 187. [2018-01-24 15:25:36,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-01-24 15:25:36,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 209 transitions. [2018-01-24 15:25:36,161 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 209 transitions. Word has length 117 [2018-01-24 15:25:36,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:36,161 INFO L432 AbstractCegarLoop]: Abstraction has 187 states and 209 transitions. [2018-01-24 15:25:36,161 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 15:25:36,161 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 209 transitions. [2018-01-24 15:25:36,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-24 15:25:36,162 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:36,162 INFO L322 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:36,162 INFO L371 AbstractCegarLoop]: === Iteration 34 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:36,162 INFO L82 PathProgramCache]: Analyzing trace with hash 1378342647, now seen corresponding path program 23 times [2018-01-24 15:25:36,162 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:36,163 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:36,163 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:36,163 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:36,163 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:36,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:36,168 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:36,530 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:36,530 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:36,530 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:36,531 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:36,531 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:36,531 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:36,531 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:36,536 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:36,536 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:36,540 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,541 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,542 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,543 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,544 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,546 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,547 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,549 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,551 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,554 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,556 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,560 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,563 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,567 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,572 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,576 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,580 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,584 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,589 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,594 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,600 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,606 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,614 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,622 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:36,623 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:36,626 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:36,658 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:36,659 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:37,260 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:37,280 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:37,544 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 64 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:37,550 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:37,550 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:37,559 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,562 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,569 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,577 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,587 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,600 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,612 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,626 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,642 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,665 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,690 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,713 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,738 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,766 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,808 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,858 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,901 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:37,950 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:38,003 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:38,087 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:38,192 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:38,269 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:38,354 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:38,448 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:38,471 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:38,475 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:38,504 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:38,505 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:38,533 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:38,534 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:38,535 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 49 [2018-01-24 15:25:38,535 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:38,535 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 15:25:38,535 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 15:25:38,536 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 15:25:38,536 INFO L87 Difference]: Start difference. First operand 187 states and 209 transitions. Second operand 26 states. [2018-01-24 15:25:39,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:39,628 INFO L93 Difference]: Finished difference Result 1020 states and 1163 transitions. [2018-01-24 15:25:39,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 15:25:39,628 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 122 [2018-01-24 15:25:39,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:39,631 INFO L225 Difference]: With dead ends: 1020 [2018-01-24 15:25:39,631 INFO L226 Difference]: Without dead ends: 1017 [2018-01-24 15:25:39,632 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 511 GetRequests, 461 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 15:25:39,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1017 states. [2018-01-24 15:25:39,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1017 to 192. [2018-01-24 15:25:39,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192 states. [2018-01-24 15:25:39,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 215 transitions. [2018-01-24 15:25:39,670 INFO L78 Accepts]: Start accepts. Automaton has 192 states and 215 transitions. Word has length 122 [2018-01-24 15:25:39,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:39,670 INFO L432 AbstractCegarLoop]: Abstraction has 192 states and 215 transitions. [2018-01-24 15:25:39,670 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 15:25:39,670 INFO L276 IsEmpty]: Start isEmpty. Operand 192 states and 215 transitions. [2018-01-24 15:25:39,670 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-01-24 15:25:39,670 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:39,671 INFO L322 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:39,671 INFO L371 AbstractCegarLoop]: === Iteration 35 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:39,671 INFO L82 PathProgramCache]: Analyzing trace with hash -1016482084, now seen corresponding path program 24 times [2018-01-24 15:25:39,671 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:39,671 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:39,672 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:39,672 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:39,672 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:39,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:39,677 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:40,100 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:40,100 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:40,100 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:40,100 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:40,101 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:40,101 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:40,101 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:40,106 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:40,106 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:40,111 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,112 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,113 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,114 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,115 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,116 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,118 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,119 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,120 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,121 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,123 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,124 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,128 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,130 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,133 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,134 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,137 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,139 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,141 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,144 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,147 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,151 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,154 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,159 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,163 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:40,164 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:40,166 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:40,190 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:40,190 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:41,070 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:41,091 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:41,091 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 66 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:41,094 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:41,094 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:41,100 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,102 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,108 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,114 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,121 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,127 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,134 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,144 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,156 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,170 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,204 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,232 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,258 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,288 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,318 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,352 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,392 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,438 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,492 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,553 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,646 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:41,843 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:42,066 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:42,327 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:42,561 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:42,577 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:42,581 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:42,605 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:42,605 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:42,633 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:42,634 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:42,635 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 51 [2018-01-24 15:25:42,635 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:42,635 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 15:25:42,635 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 15:25:42,636 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 15:25:42,636 INFO L87 Difference]: Start difference. First operand 192 states and 215 transitions. Second operand 27 states. [2018-01-24 15:25:44,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:44,080 INFO L93 Difference]: Finished difference Result 1080 states and 1232 transitions. [2018-01-24 15:25:44,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 15:25:44,081 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 127 [2018-01-24 15:25:44,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:44,085 INFO L225 Difference]: With dead ends: 1080 [2018-01-24 15:25:44,085 INFO L226 Difference]: Without dead ends: 1077 [2018-01-24 15:25:44,086 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 532 GetRequests, 480 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 15:25:44,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1077 states. [2018-01-24 15:25:44,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1077 to 197. [2018-01-24 15:25:44,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-01-24 15:25:44,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 221 transitions. [2018-01-24 15:25:44,133 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 221 transitions. Word has length 127 [2018-01-24 15:25:44,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:44,133 INFO L432 AbstractCegarLoop]: Abstraction has 197 states and 221 transitions. [2018-01-24 15:25:44,133 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 15:25:44,133 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 221 transitions. [2018-01-24 15:25:44,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-01-24 15:25:44,134 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:44,134 INFO L322 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:44,134 INFO L371 AbstractCegarLoop]: === Iteration 36 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:44,134 INFO L82 PathProgramCache]: Analyzing trace with hash 795448555, now seen corresponding path program 9 times [2018-01-24 15:25:44,134 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:44,135 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:44,135 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:44,135 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:44,135 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:44,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:44,142 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:44,493 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 140 proven. 259 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-01-24 15:25:44,494 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:44,494 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:44,494 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:44,494 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:44,494 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:44,494 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:44,499 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:44,499 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:44,503 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,505 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,507 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,509 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,511 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,514 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,517 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,520 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,524 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,524 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:44,526 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:44,622 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 15:25:44,622 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:44,788 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 15:25:44,808 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:44,808 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 68 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:44,811 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:44,811 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:44,816 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,819 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,826 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,835 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,848 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,865 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,886 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,924 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,970 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:44,983 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:44,987 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:45,040 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 15:25:45,040 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:45,080 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 15:25:45,081 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:45,082 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 10, 10, 10, 10] total 38 [2018-01-24 15:25:45,082 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:45,082 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 15:25:45,083 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 15:25:45,083 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=248, Invalid=1234, Unknown=0, NotChecked=0, Total=1482 [2018-01-24 15:25:45,083 INFO L87 Difference]: Start difference. First operand 197 states and 221 transitions. Second operand 30 states. [2018-01-24 15:25:45,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:45,526 INFO L93 Difference]: Finished difference Result 264 states and 301 transitions. [2018-01-24 15:25:45,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-24 15:25:45,527 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 137 [2018-01-24 15:25:45,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:45,528 INFO L225 Difference]: With dead ends: 264 [2018-01-24 15:25:45,528 INFO L226 Difference]: Without dead ends: 205 [2018-01-24 15:25:45,529 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 575 GetRequests, 528 SyntacticMatches, 2 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 517 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=388, Invalid=1774, Unknown=0, NotChecked=0, Total=2162 [2018-01-24 15:25:45,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-01-24 15:25:45,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 203. [2018-01-24 15:25:45,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-01-24 15:25:45,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 227 transitions. [2018-01-24 15:25:45,566 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 227 transitions. Word has length 137 [2018-01-24 15:25:45,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:45,566 INFO L432 AbstractCegarLoop]: Abstraction has 203 states and 227 transitions. [2018-01-24 15:25:45,566 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 15:25:45,566 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 227 transitions. [2018-01-24 15:25:45,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-01-24 15:25:45,567 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:45,567 INFO L322 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:45,567 INFO L371 AbstractCegarLoop]: === Iteration 37 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:45,567 INFO L82 PathProgramCache]: Analyzing trace with hash 37813783, now seen corresponding path program 25 times [2018-01-24 15:25:45,567 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:45,568 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:45,568 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:45,568 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:45,568 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:45,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:45,576 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:46,059 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:46,060 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:46,060 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:46,060 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:46,060 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:46,060 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:46,060 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:46,065 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:46,065 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:46,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:46,082 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:46,107 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:46,107 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:46,813 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:46,832 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:46,832 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 70 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:46,835 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:46,835 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:46,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:46,870 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:46,935 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:46,936 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:46,985 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:46,987 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:46,987 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 53 [2018-01-24 15:25:46,987 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:46,987 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 15:25:46,988 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 15:25:46,988 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 15:25:46,988 INFO L87 Difference]: Start difference. First operand 203 states and 227 transitions. Second operand 28 states. [2018-01-24 15:25:48,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:48,412 INFO L93 Difference]: Finished difference Result 1187 states and 1356 transitions. [2018-01-24 15:25:48,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 15:25:48,413 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 132 [2018-01-24 15:25:48,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:48,416 INFO L225 Difference]: With dead ends: 1187 [2018-01-24 15:25:48,416 INFO L226 Difference]: Without dead ends: 1184 [2018-01-24 15:25:48,417 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 499 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 15:25:48,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1184 states. [2018-01-24 15:25:48,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1184 to 208. [2018-01-24 15:25:48,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 208 states. [2018-01-24 15:25:48,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208 states to 208 states and 233 transitions. [2018-01-24 15:25:48,460 INFO L78 Accepts]: Start accepts. Automaton has 208 states and 233 transitions. Word has length 132 [2018-01-24 15:25:48,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:48,461 INFO L432 AbstractCegarLoop]: Abstraction has 208 states and 233 transitions. [2018-01-24 15:25:48,461 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 15:25:48,461 INFO L276 IsEmpty]: Start isEmpty. Operand 208 states and 233 transitions. [2018-01-24 15:25:48,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-01-24 15:25:48,462 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:48,462 INFO L322 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:48,462 INFO L371 AbstractCegarLoop]: === Iteration 38 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:48,463 INFO L82 PathProgramCache]: Analyzing trace with hash -24378436, now seen corresponding path program 26 times [2018-01-24 15:25:48,463 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:48,463 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:48,463 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:48,463 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:48,463 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:48,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:48,469 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:48,938 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:48,938 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:48,939 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:48,939 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:48,939 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:48,939 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:48,939 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:48,944 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:48,944 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:48,949 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,961 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,962 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:48,965 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:48,991 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:48,992 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:49,716 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:49,736 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:49,736 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 72 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:49,738 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:49,739 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:49,743 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,760 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,773 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:49,776 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:49,806 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:49,806 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:49,838 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:49,839 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:49,840 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 55 [2018-01-24 15:25:49,840 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:49,840 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 15:25:49,840 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 15:25:49,840 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 15:25:49,841 INFO L87 Difference]: Start difference. First operand 208 states and 233 transitions. Second operand 29 states. [2018-01-24 15:25:51,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:51,388 INFO L93 Difference]: Finished difference Result 1253 states and 1432 transitions. [2018-01-24 15:25:51,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 15:25:51,389 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 137 [2018-01-24 15:25:51,389 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:51,392 INFO L225 Difference]: With dead ends: 1253 [2018-01-24 15:25:51,393 INFO L226 Difference]: Without dead ends: 1250 [2018-01-24 15:25:51,393 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 574 GetRequests, 518 SyntacticMatches, 2 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 15:25:51,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1250 states. [2018-01-24 15:25:51,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1250 to 213. [2018-01-24 15:25:51,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 213 states. [2018-01-24 15:25:51,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 239 transitions. [2018-01-24 15:25:51,444 INFO L78 Accepts]: Start accepts. Automaton has 213 states and 239 transitions. Word has length 137 [2018-01-24 15:25:51,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:51,445 INFO L432 AbstractCegarLoop]: Abstraction has 213 states and 239 transitions. [2018-01-24 15:25:51,445 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-24 15:25:51,445 INFO L276 IsEmpty]: Start isEmpty. Operand 213 states and 239 transitions. [2018-01-24 15:25:51,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-01-24 15:25:51,445 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:51,446 INFO L322 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:51,446 INFO L371 AbstractCegarLoop]: === Iteration 39 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:51,446 INFO L82 PathProgramCache]: Analyzing trace with hash -1695826633, now seen corresponding path program 27 times [2018-01-24 15:25:51,446 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:51,446 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:51,446 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:51,447 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:51,447 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:51,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:51,453 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. Received shutdown request... [2018-01-24 15:25:51,858 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 15:25:51,862 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 15:25:51,863 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 03:25:51 BoogieIcfgContainer [2018-01-24 15:25:51,863 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 15:25:51,864 INFO L168 Benchmark]: Toolchain (without parser) took 48176.91 ms. Allocated memory was 304.1 MB in the beginning and 744.5 MB in the end (delta: 440.4 MB). Free memory was 265.0 MB in the beginning and 566.3 MB in the end (delta: -301.3 MB). Peak memory consumption was 139.1 MB. Max. memory is 5.3 GB. [2018-01-24 15:25:51,864 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 304.1 MB. Free memory is still 270.0 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 15:25:51,865 INFO L168 Benchmark]: CACSL2BoogieTranslator took 168.72 ms. Allocated memory is still 304.1 MB. Free memory was 264.0 MB in the beginning and 256.8 MB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 5.3 GB. [2018-01-24 15:25:51,865 INFO L168 Benchmark]: Boogie Preprocessor took 25.62 ms. Allocated memory is still 304.1 MB. Free memory was 256.8 MB in the beginning and 254.8 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 15:25:51,865 INFO L168 Benchmark]: RCFGBuilder took 165.67 ms. Allocated memory is still 304.1 MB. Free memory was 254.8 MB in the beginning and 242.8 MB in the end (delta: 12.1 MB). Peak memory consumption was 12.1 MB. Max. memory is 5.3 GB. [2018-01-24 15:25:51,865 INFO L168 Benchmark]: TraceAbstraction took 47809.32 ms. Allocated memory was 304.1 MB in the beginning and 744.5 MB in the end (delta: 440.4 MB). Free memory was 242.8 MB in the beginning and 566.3 MB in the end (delta: -323.5 MB). Peak memory consumption was 116.9 MB. Max. memory is 5.3 GB. [2018-01-24 15:25:51,867 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 304.1 MB. Free memory is still 270.0 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 168.72 ms. Allocated memory is still 304.1 MB. Free memory was 264.0 MB in the beginning and 256.8 MB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 25.62 ms. Allocated memory is still 304.1 MB. Free memory was 256.8 MB in the beginning and 254.8 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 165.67 ms. Allocated memory is still 304.1 MB. Free memory was 254.8 MB in the beginning and 242.8 MB in the end (delta: 12.1 MB). Peak memory consumption was 12.1 MB. Max. memory is 5.3 GB. * TraceAbstraction took 47809.32 ms. Allocated memory was 304.1 MB in the beginning and 744.5 MB in the end (delta: 440.4 MB). Free memory was 242.8 MB in the beginning and 566.3 MB in the end (delta: -323.5 MB). Peak memory consumption was 116.9 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 10 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 0 LocStat_NO_SUPPORTING_DISEQUALITIES : 4 LocStat_NO_DISJUNCTIONS : -20 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 15 TransStat_MAX_WEQGRAPH_SIZE : 3 TransStat_MAX_SIZEOF_WEQEDGELABEL : 2 TransStat_NO_SUPPORTING_EQUALITIES : 5 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 16 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 6.336613 RENAME_VARIABLES(MILLISECONDS) : 0.570741 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 6.247653 PROJECTAWAY(MILLISECONDS) : 2.205060 ADD_WEAK_EQUALITY(MILLISECONDS) : 2.651736 DISJOIN(MILLISECONDS) : 0.234749 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.616344 ADD_EQUALITY(MILLISECONDS) : 3.863600 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.680037 #CONJOIN_DISJUNCTIVE : 36 #RENAME_VARIABLES : 82 #UNFREEZE : 0 #CONJOIN : 48 #PROJECTAWAY : 57 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 10 #RENAME_VARIABLES_DISJUNCTIVE : 77 #ADD_EQUALITY : 5 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 14 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 9 LocStat_NO_SUPPORTING_DISEQUALITIES : 4 LocStat_NO_DISJUNCTIONS : -28 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 19 TransStat_MAX_WEQGRAPH_SIZE : 3 TransStat_MAX_SIZEOF_WEQEDGELABEL : 2 TransStat_NO_SUPPORTING_EQUALITIES : 7 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 20 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.765938 RENAME_VARIABLES(MILLISECONDS) : 0.366913 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.284182 PROJECTAWAY(MILLISECONDS) : 0.051950 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.539920 DISJOIN(MILLISECONDS) : 0.188563 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.401038 ADD_EQUALITY(MILLISECONDS) : 0.047625 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.173664 #CONJOIN_DISJUNCTIVE : 56 #RENAME_VARIABLES : 122 #UNFREEZE : 0 #CONJOIN : 68 #PROJECTAWAY : 81 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 14 #RENAME_VARIABLES_DISJUNCTIVE : 117 #ADD_EQUALITY : 7 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 21 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 11 LocStat_NO_SUPPORTING_DISEQUALITIES : 7 LocStat_NO_DISJUNCTIONS : -42 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 29 TransStat_MAX_WEQGRAPH_SIZE : 3 TransStat_MAX_SIZEOF_WEQEDGELABEL : 2 TransStat_NO_SUPPORTING_EQUALITIES : 10 TransStat_NO_SUPPORTING_DISEQUALITIES : 2 TransStat_NO_DISJUNCTIONS : 30 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.098531 RENAME_VARIABLES(MILLISECONDS) : 0.088208 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.071312 PROJECTAWAY(MILLISECONDS) : 0.076404 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.230823 DISJOIN(MILLISECONDS) : 0.140351 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.103411 ADD_EQUALITY(MILLISECONDS) : 0.042104 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.010881 #CONJOIN_DISJUNCTIVE : 121 #RENAME_VARIABLES : 295 #UNFREEZE : 0 #CONJOIN : 184 #PROJECTAWAY : 191 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 26 #RENAME_VARIABLES_DISJUNCTIVE : 287 #ADD_EQUALITY : 10 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 2 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 7]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 7). Cancelled while BasicCegarLoop was analyzing trace of length 143 with TraceHistMax 28, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 27 known predicates. - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while BasicCegarLoop was analyzing trace of length 143 with TraceHistMax 28, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 27 known predicates. - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was analyzing trace of length 143 with TraceHistMax 28, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 27 known predicates. - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was analyzing trace of length 143 with TraceHistMax 28, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 27 known predicates. - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while BasicCegarLoop was analyzing trace of length 143 with TraceHistMax 28, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 27 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 32 locations, 5 error locations. TIMEOUT Result, 47.7s OverallTime, 39 OverallIterations, 28 TraceHistogramMax, 16.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4036 SDtfs, 2569 SDslu, 59587 SDs, 0 SdLazy, 30837 SolverSat, 230 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 11050 GetRequests, 9973 SyntacticMatches, 68 SemanticMatches, 1009 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2796 ImplicationChecksByTransitivity, 16.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=213occurred in iteration=38, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.7s AbstIntTime, 3 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.8s AutomataMinimizationTime, 38 MinimizatonAttempts, 10045 StatesRemovedByMinimization, 35 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 6.2s SatisfiabilityAnalysisTime, 20.9s InterpolantComputationTime, 7943 NumberOfCodeBlocks, 7913 NumberOfCodeBlocksAsserted, 501 NumberOfCheckSat, 13040 ConstructedInterpolants, 0 QuantifiedInterpolants, 7741836 SizeOfPredicates, 7 NumberOfNonLiveVariables, 7716 ConjunctsInSsa, 1767 ConjunctsInUnsatCore, 180 InterpolantComputations, 4 PerfectInterpolantSequences, 4895/85009 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_15-25-51-879.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_15-25-51-879.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_15-25-51-879.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-VPDomainBenchmark-1-2018-01-24_15-25-51-879.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-1-2018-01-24_15-25-51-879.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-VPDomainBenchmark-2-2018-01-24_15-25-51-879.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-2-2018-01-24_15-25-51-879.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_15-25-51-879.csv Completed graceful shutdown