java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf -i ../../../trunk/examples/svcomp/array-examples/standard_strcpy_original_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 15:25:17,022 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 15:25:17,024 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 15:25:17,066 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 15:25:17,067 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 15:25:17,067 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 15:25:17,068 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 15:25:17,069 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 15:25:17,071 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 15:25:17,072 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 15:25:17,073 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 15:25:17,073 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 15:25:17,074 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 15:25:17,075 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 15:25:17,076 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 15:25:17,079 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 15:25:17,081 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 15:25:17,083 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 15:25:17,084 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 15:25:17,085 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 15:25:17,087 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 15:25:17,088 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 15:25:17,088 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 15:25:17,089 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 15:25:17,090 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 15:25:17,091 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 15:25:17,091 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 15:25:17,092 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 15:25:17,092 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 15:25:17,092 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 15:25:17,093 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 15:25:17,093 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf [2018-01-24 15:25:17,103 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 15:25:17,103 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 15:25:17,104 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 15:25:17,104 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 15:25:17,104 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 15:25:17,105 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 15:25:17,105 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 15:25:17,105 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 15:25:17,106 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 15:25:17,106 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 15:25:17,106 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 15:25:17,106 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 15:25:17,106 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 15:25:17,107 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 15:25:17,107 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 15:25:17,107 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 15:25:17,107 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 15:25:17,107 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 15:25:17,107 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 15:25:17,108 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 15:25:17,108 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 15:25:17,108 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 15:25:17,108 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 15:25:17,108 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 15:25:17,109 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 15:25:17,109 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 15:25:17,109 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 15:25:17,109 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 15:25:17,109 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 15:25:17,110 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 15:25:17,110 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 15:25:17,110 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 15:25:17,110 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 15:25:17,111 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 15:25:17,111 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 15:25:17,146 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 15:25:17,156 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 15:25:17,159 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 15:25:17,160 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 15:25:17,160 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 15:25:17,161 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/standard_strcpy_original_false-valid-deref.i [2018-01-24 15:25:17,266 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 15:25:17,273 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 15:25:17,273 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 15:25:17,273 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 15:25:17,278 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 15:25:17,279 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 03:25:17" (1/1) ... [2018-01-24 15:25:17,281 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@87bddd7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:17, skipping insertion in model container [2018-01-24 15:25:17,281 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 03:25:17" (1/1) ... [2018-01-24 15:25:17,295 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 15:25:17,309 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 15:25:17,408 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 15:25:17,419 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 15:25:17,423 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:17 WrapperNode [2018-01-24 15:25:17,423 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 15:25:17,424 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 15:25:17,424 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 15:25:17,424 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 15:25:17,441 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:17" (1/1) ... [2018-01-24 15:25:17,441 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:17" (1/1) ... [2018-01-24 15:25:17,451 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:17" (1/1) ... [2018-01-24 15:25:17,451 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:17" (1/1) ... [2018-01-24 15:25:17,453 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:17" (1/1) ... [2018-01-24 15:25:17,457 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:17" (1/1) ... [2018-01-24 15:25:17,458 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:17" (1/1) ... [2018-01-24 15:25:17,459 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 15:25:17,460 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 15:25:17,460 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 15:25:17,460 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 15:25:17,462 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:17" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 15:25:17,523 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 15:25:17,524 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 15:25:17,524 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 15:25:17,524 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 15:25:17,524 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 15:25:17,524 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 15:25:17,524 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 15:25:17,524 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 15:25:17,525 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 15:25:17,698 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 15:25:17,698 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 03:25:17 BoogieIcfgContainer [2018-01-24 15:25:17,698 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 15:25:17,699 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 15:25:17,699 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 15:25:17,701 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 15:25:17,701 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 03:25:17" (1/3) ... [2018-01-24 15:25:17,702 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@71ce0606 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 03:25:17, skipping insertion in model container [2018-01-24 15:25:17,702 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 03:25:17" (2/3) ... [2018-01-24 15:25:17,702 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@71ce0606 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 03:25:17, skipping insertion in model container [2018-01-24 15:25:17,702 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 03:25:17" (3/3) ... [2018-01-24 15:25:17,704 INFO L105 eAbstractionObserver]: Analyzing ICFG standard_strcpy_original_false-valid-deref.i [2018-01-24 15:25:17,712 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 15:25:17,718 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2018-01-24 15:25:17,752 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 15:25:17,752 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 15:25:17,752 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 15:25:17,752 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 15:25:17,753 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 15:25:17,753 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 15:25:17,753 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 15:25:17,753 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 15:25:17,753 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 15:25:17,767 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states. [2018-01-24 15:25:17,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2018-01-24 15:25:17,772 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:17,773 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:17,773 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:17,777 INFO L82 PathProgramCache]: Analyzing trace with hash 1734695582, now seen corresponding path program 1 times [2018-01-24 15:25:17,779 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:17,839 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:17,840 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:17,840 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:17,840 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:17,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:17,881 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:17,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:17,958 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 15:25:17,958 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 15:25:17,959 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 15:25:17,961 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 15:25:17,971 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 15:25:17,972 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 15:25:17,974 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 3 states. [2018-01-24 15:25:18,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:18,065 INFO L93 Difference]: Finished difference Result 74 states and 90 transitions. [2018-01-24 15:25:18,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 15:25:18,066 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2018-01-24 15:25:18,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:18,075 INFO L225 Difference]: With dead ends: 74 [2018-01-24 15:25:18,076 INFO L226 Difference]: Without dead ends: 41 [2018-01-24 15:25:18,079 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 15:25:18,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2018-01-24 15:25:18,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 38. [2018-01-24 15:25:18,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-01-24 15:25:18,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 40 transitions. [2018-01-24 15:25:18,174 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 40 transitions. Word has length 7 [2018-01-24 15:25:18,175 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:18,175 INFO L432 AbstractCegarLoop]: Abstraction has 38 states and 40 transitions. [2018-01-24 15:25:18,175 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 15:25:18,175 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 40 transitions. [2018-01-24 15:25:18,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-01-24 15:25:18,175 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:18,176 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:18,176 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:18,176 INFO L82 PathProgramCache]: Analyzing trace with hash 337601429, now seen corresponding path program 1 times [2018-01-24 15:25:18,176 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:18,177 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:18,177 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:18,178 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:18,178 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:18,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:18,187 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:18,229 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:18,230 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:18,230 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:18,231 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 13 with the following transitions: [2018-01-24 15:25:18,233 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [10], [11], [16], [18], [20], [58], [59], [60] [2018-01-24 15:25:18,278 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 15:25:18,278 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 15:25:18,535 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 15:25:18,536 INFO L268 AbstractInterpreter]: Visited 11 different actions 23 times. Merged at 6 different actions 12 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 3 variables. [2018-01-24 15:25:18,551 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 15:25:18,551 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:18,551 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:18,566 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:18,566 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:18,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:18,587 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:18,598 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:18,598 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:18,636 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:18,671 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:18,671 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:18,675 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:18,675 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:18,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:18,684 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:18,692 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:18,692 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:18,702 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:18,703 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:18,703 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3, 3, 3] total 5 [2018-01-24 15:25:18,704 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:18,704 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 15:25:18,705 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 15:25:18,705 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:25:18,705 INFO L87 Difference]: Start difference. First operand 38 states and 40 transitions. Second operand 4 states. [2018-01-24 15:25:18,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:18,863 INFO L93 Difference]: Finished difference Result 60 states and 65 transitions. [2018-01-24 15:25:18,863 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 15:25:18,864 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-01-24 15:25:18,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:18,865 INFO L225 Difference]: With dead ends: 60 [2018-01-24 15:25:18,865 INFO L226 Difference]: Without dead ends: 54 [2018-01-24 15:25:18,866 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 43 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 15:25:18,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-24 15:25:18,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 50. [2018-01-24 15:25:18,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 15:25:18,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-01-24 15:25:18,875 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 12 [2018-01-24 15:25:18,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:18,875 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-01-24 15:25:18,875 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 15:25:18,875 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-01-24 15:25:18,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 15:25:18,876 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:18,877 INFO L322 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:18,877 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:18,877 INFO L82 PathProgramCache]: Analyzing trace with hash -1746445058, now seen corresponding path program 2 times [2018-01-24 15:25:18,877 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:18,878 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:18,878 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:18,879 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:18,879 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:18,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:18,887 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:19,002 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,002 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:19,002 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:19,002 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:19,002 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:19,003 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:19,003 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:19,011 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:19,011 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:19,017 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:19,020 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:19,021 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:19,022 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:19,040 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,040 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:19,148 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,168 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:19,169 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:19,172 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:19,173 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:19,177 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:19,180 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:19,183 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:19,186 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:19,219 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,219 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:19,255 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,256 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:19,257 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-01-24 15:25:19,257 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:19,257 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 15:25:19,257 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 15:25:19,257 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 15:25:19,258 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 5 states. [2018-01-24 15:25:19,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:19,353 INFO L93 Difference]: Finished difference Result 73 states and 80 transitions. [2018-01-24 15:25:19,353 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 15:25:19,353 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 15:25:19,353 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:19,355 INFO L225 Difference]: With dead ends: 73 [2018-01-24 15:25:19,355 INFO L226 Difference]: Without dead ends: 67 [2018-01-24 15:25:19,356 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 62 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 15:25:19,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-01-24 15:25:19,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 62. [2018-01-24 15:25:19,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-01-24 15:25:19,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 68 transitions. [2018-01-24 15:25:19,365 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 68 transitions. Word has length 17 [2018-01-24 15:25:19,365 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:19,365 INFO L432 AbstractCegarLoop]: Abstraction has 62 states and 68 transitions. [2018-01-24 15:25:19,365 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 15:25:19,366 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 68 transitions. [2018-01-24 15:25:19,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-01-24 15:25:19,366 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:19,366 INFO L322 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:19,366 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:19,367 INFO L82 PathProgramCache]: Analyzing trace with hash -228598475, now seen corresponding path program 3 times [2018-01-24 15:25:19,367 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:19,368 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:19,368 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:19,368 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:19,368 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:19,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:19,377 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:19,447 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,447 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:19,447 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:19,447 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:19,447 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:19,448 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:19,448 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:19,454 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:19,454 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:19,457 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:19,459 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:19,460 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:19,461 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:19,462 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:19,463 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:19,474 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,474 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:19,537 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,569 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:19,569 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:19,573 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:19,573 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:19,577 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:19,579 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:19,583 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:19,587 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:19,590 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:19,593 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:19,598 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,599 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:19,605 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,606 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:19,606 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 15:25:19,606 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:19,606 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 15:25:19,607 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 15:25:19,607 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 15:25:19,607 INFO L87 Difference]: Start difference. First operand 62 states and 68 transitions. Second operand 6 states. [2018-01-24 15:25:19,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:19,751 INFO L93 Difference]: Finished difference Result 86 states and 95 transitions. [2018-01-24 15:25:19,751 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 15:25:19,751 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-01-24 15:25:19,751 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:19,752 INFO L225 Difference]: With dead ends: 86 [2018-01-24 15:25:19,752 INFO L226 Difference]: Without dead ends: 80 [2018-01-24 15:25:19,753 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 81 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 15:25:19,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-24 15:25:19,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 74. [2018-01-24 15:25:19,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-24 15:25:19,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 82 transitions. [2018-01-24 15:25:19,762 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 82 transitions. Word has length 22 [2018-01-24 15:25:19,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:19,762 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 82 transitions. [2018-01-24 15:25:19,762 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 15:25:19,762 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 82 transitions. [2018-01-24 15:25:19,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 15:25:19,763 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:19,764 INFO L322 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:19,764 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:19,764 INFO L82 PathProgramCache]: Analyzing trace with hash 756148062, now seen corresponding path program 4 times [2018-01-24 15:25:19,764 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:19,765 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:19,766 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:19,766 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:19,766 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:19,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:19,774 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:19,831 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,831 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:19,831 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:19,832 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:19,832 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:19,832 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:19,832 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:19,843 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:19,844 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:19,851 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:19,853 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:19,860 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,861 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:19,928 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,949 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:19,949 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:19,953 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:19,953 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:19,968 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:19,971 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:19,978 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,978 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:19,990 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:19,991 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:19,992 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 15:25:19,992 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:19,992 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 15:25:19,993 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 15:25:19,993 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 15:25:19,993 INFO L87 Difference]: Start difference. First operand 74 states and 82 transitions. Second operand 7 states. [2018-01-24 15:25:20,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:20,150 INFO L93 Difference]: Finished difference Result 99 states and 110 transitions. [2018-01-24 15:25:20,150 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 15:25:20,150 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 27 [2018-01-24 15:25:20,151 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:20,151 INFO L225 Difference]: With dead ends: 99 [2018-01-24 15:25:20,151 INFO L226 Difference]: Without dead ends: 93 [2018-01-24 15:25:20,152 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 100 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 15:25:20,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-01-24 15:25:20,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 86. [2018-01-24 15:25:20,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-01-24 15:25:20,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 96 transitions. [2018-01-24 15:25:20,158 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 96 transitions. Word has length 27 [2018-01-24 15:25:20,159 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:20,159 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 96 transitions. [2018-01-24 15:25:20,159 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 15:25:20,159 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 96 transitions. [2018-01-24 15:25:20,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 15:25:20,160 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:20,160 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:20,160 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:20,160 INFO L82 PathProgramCache]: Analyzing trace with hash 671928021, now seen corresponding path program 5 times [2018-01-24 15:25:20,160 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:20,161 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:20,161 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:20,161 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:20,161 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:20,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:20,167 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:20,257 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:20,257 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:20,257 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:20,257 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:20,257 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:20,257 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:20,257 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:20,262 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:20,262 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:20,266 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,267 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,268 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,269 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,270 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,272 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,272 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:20,274 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:20,282 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:20,282 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:20,420 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:20,440 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:20,440 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:20,443 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:20,444 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:20,446 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,449 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,453 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,457 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,463 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,471 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:20,475 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:20,477 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:20,485 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:20,485 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:20,502 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:20,503 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:20,504 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 15:25:20,504 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:20,504 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 15:25:20,505 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 15:25:20,505 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 15:25:20,505 INFO L87 Difference]: Start difference. First operand 86 states and 96 transitions. Second operand 8 states. [2018-01-24 15:25:20,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:20,717 INFO L93 Difference]: Finished difference Result 112 states and 125 transitions. [2018-01-24 15:25:20,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 15:25:20,718 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 32 [2018-01-24 15:25:20,718 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:20,719 INFO L225 Difference]: With dead ends: 112 [2018-01-24 15:25:20,719 INFO L226 Difference]: Without dead ends: 106 [2018-01-24 15:25:20,719 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 119 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 15:25:20,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-01-24 15:25:20,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 98. [2018-01-24 15:25:20,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-01-24 15:25:20,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 110 transitions. [2018-01-24 15:25:20,730 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 110 transitions. Word has length 32 [2018-01-24 15:25:20,730 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:20,730 INFO L432 AbstractCegarLoop]: Abstraction has 98 states and 110 transitions. [2018-01-24 15:25:20,730 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 15:25:20,730 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 110 transitions. [2018-01-24 15:25:20,731 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 15:25:20,731 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:20,732 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:20,732 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:20,732 INFO L82 PathProgramCache]: Analyzing trace with hash -203753026, now seen corresponding path program 6 times [2018-01-24 15:25:20,732 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:20,732 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:20,733 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:20,733 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:20,733 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:20,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:20,743 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:20,862 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:20,862 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:20,862 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:20,862 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:20,862 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:20,863 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:20,863 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:20,872 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:20,873 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:20,876 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,877 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,879 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,880 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,881 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,882 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,883 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:20,887 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:20,890 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:20,902 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:20,903 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:21,090 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:21,113 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:21,113 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:21,117 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:21,117 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:21,120 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:21,122 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:21,126 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:21,130 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:21,136 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:21,143 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:21,152 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:21,156 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:21,159 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:21,168 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:21,168 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:21,177 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:21,178 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:21,178 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 15:25:21,178 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:21,179 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 15:25:21,179 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 15:25:21,179 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 15:25:21,179 INFO L87 Difference]: Start difference. First operand 98 states and 110 transitions. Second operand 9 states. [2018-01-24 15:25:21,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:21,357 INFO L93 Difference]: Finished difference Result 125 states and 140 transitions. [2018-01-24 15:25:21,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 15:25:21,357 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 37 [2018-01-24 15:25:21,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:21,358 INFO L225 Difference]: With dead ends: 125 [2018-01-24 15:25:21,358 INFO L226 Difference]: Without dead ends: 119 [2018-01-24 15:25:21,358 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 138 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 15:25:21,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-01-24 15:25:21,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 110. [2018-01-24 15:25:21,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-24 15:25:21,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 124 transitions. [2018-01-24 15:25:21,367 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 124 transitions. Word has length 37 [2018-01-24 15:25:21,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:21,367 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 124 transitions. [2018-01-24 15:25:21,367 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 15:25:21,367 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 124 transitions. [2018-01-24 15:25:21,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 15:25:21,368 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:21,368 INFO L322 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:21,369 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:21,369 INFO L82 PathProgramCache]: Analyzing trace with hash -1846527883, now seen corresponding path program 7 times [2018-01-24 15:25:21,369 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:21,370 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:21,370 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:21,370 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:21,370 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:21,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:21,379 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:21,495 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:21,495 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:21,496 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:21,496 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:21,496 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:21,496 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:21,496 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:21,506 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:21,506 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:21,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:21,515 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:21,530 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:21,531 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:21,635 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:21,655 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:21,655 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:21,658 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:21,659 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:21,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:21,672 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:21,679 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:21,680 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:21,688 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:21,689 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:21,689 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 15:25:21,690 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:21,690 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 15:25:21,690 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 15:25:21,690 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 15:25:21,690 INFO L87 Difference]: Start difference. First operand 110 states and 124 transitions. Second operand 10 states. [2018-01-24 15:25:21,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:21,895 INFO L93 Difference]: Finished difference Result 138 states and 155 transitions. [2018-01-24 15:25:21,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 15:25:21,895 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-01-24 15:25:21,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:21,896 INFO L225 Difference]: With dead ends: 138 [2018-01-24 15:25:21,896 INFO L226 Difference]: Without dead ends: 132 [2018-01-24 15:25:21,897 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 157 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 15:25:21,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-01-24 15:25:21,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 122. [2018-01-24 15:25:21,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-01-24 15:25:21,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 138 transitions. [2018-01-24 15:25:21,906 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 138 transitions. Word has length 42 [2018-01-24 15:25:21,907 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:21,907 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 138 transitions. [2018-01-24 15:25:21,907 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 15:25:21,907 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 138 transitions. [2018-01-24 15:25:21,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-01-24 15:25:21,909 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:21,909 INFO L322 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:21,909 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:21,909 INFO L82 PathProgramCache]: Analyzing trace with hash 2109248542, now seen corresponding path program 8 times [2018-01-24 15:25:21,909 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:21,910 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:21,910 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:21,910 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:21,910 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:21,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:21,919 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:22,021 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:22,021 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:22,021 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:22,021 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:22,021 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:22,022 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:22,022 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:22,028 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:22,028 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:22,031 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:22,034 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:22,035 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:22,037 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:22,048 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:22,048 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:22,214 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:22,234 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:22,234 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:22,237 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:22,237 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:22,240 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:22,248 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:22,256 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:22,260 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:22,271 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:22,271 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:22,283 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:22,285 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:22,285 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 15:25:22,285 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:22,286 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 15:25:22,286 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 15:25:22,286 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 15:25:22,287 INFO L87 Difference]: Start difference. First operand 122 states and 138 transitions. Second operand 11 states. [2018-01-24 15:25:22,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:22,636 INFO L93 Difference]: Finished difference Result 151 states and 170 transitions. [2018-01-24 15:25:22,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 15:25:22,636 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 47 [2018-01-24 15:25:22,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:22,638 INFO L225 Difference]: With dead ends: 151 [2018-01-24 15:25:22,638 INFO L226 Difference]: Without dead ends: 145 [2018-01-24 15:25:22,639 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 176 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 15:25:22,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-01-24 15:25:22,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 134. [2018-01-24 15:25:22,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-24 15:25:22,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 152 transitions. [2018-01-24 15:25:22,650 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 152 transitions. Word has length 47 [2018-01-24 15:25:22,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:22,650 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 152 transitions. [2018-01-24 15:25:22,650 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 15:25:22,651 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 152 transitions. [2018-01-24 15:25:22,652 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 15:25:22,652 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:22,653 INFO L322 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:22,653 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:22,653 INFO L82 PathProgramCache]: Analyzing trace with hash 408164885, now seen corresponding path program 9 times [2018-01-24 15:25:22,653 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:22,654 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:22,654 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:22,654 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:22,654 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:22,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:22,663 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:22,827 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:22,827 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:22,828 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:22,828 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:22,828 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:22,828 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:22,828 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:22,837 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:22,837 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:22,840 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:22,841 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:22,842 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:22,847 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:22,849 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:22,851 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:22,855 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:22,857 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:22,859 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:22,861 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:22,862 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:22,864 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:22,887 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:22,887 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:23,105 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:23,126 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:23,126 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:23,129 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:23,129 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:23,134 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:23,137 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:23,142 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:23,146 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:23,152 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:23,160 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:23,167 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:23,176 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:23,187 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:23,203 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:23,208 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:23,211 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:23,223 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:23,224 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:23,261 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:23,263 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:23,263 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 15:25:23,263 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:23,264 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 15:25:23,264 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 15:25:23,264 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 15:25:23,265 INFO L87 Difference]: Start difference. First operand 134 states and 152 transitions. Second operand 12 states. [2018-01-24 15:25:23,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:23,618 INFO L93 Difference]: Finished difference Result 164 states and 185 transitions. [2018-01-24 15:25:23,618 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 15:25:23,618 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 52 [2018-01-24 15:25:23,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:23,619 INFO L225 Difference]: With dead ends: 164 [2018-01-24 15:25:23,619 INFO L226 Difference]: Without dead ends: 158 [2018-01-24 15:25:23,620 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 195 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 15:25:23,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-01-24 15:25:23,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 146. [2018-01-24 15:25:23,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-01-24 15:25:23,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 166 transitions. [2018-01-24 15:25:23,630 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 166 transitions. Word has length 52 [2018-01-24 15:25:23,630 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:23,630 INFO L432 AbstractCegarLoop]: Abstraction has 146 states and 166 transitions. [2018-01-24 15:25:23,630 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 15:25:23,630 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 166 transitions. [2018-01-24 15:25:23,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-01-24 15:25:23,632 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:23,632 INFO L322 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:23,632 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:23,632 INFO L82 PathProgramCache]: Analyzing trace with hash -2136951170, now seen corresponding path program 10 times [2018-01-24 15:25:23,632 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:23,633 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:23,633 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:23,633 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:23,633 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:23,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:23,642 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:23,763 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:23,763 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:23,763 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:23,763 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:23,763 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:23,764 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:23,764 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:23,769 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:23,769 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:23,778 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:23,780 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:23,790 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:23,790 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:23,942 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:23,962 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:23,962 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:23,965 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:23,965 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:23,997 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:24,000 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:24,011 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:24,011 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:24,022 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:24,023 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:24,023 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 15:25:24,023 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:24,024 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 15:25:24,024 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 15:25:24,024 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 15:25:24,024 INFO L87 Difference]: Start difference. First operand 146 states and 166 transitions. Second operand 13 states. [2018-01-24 15:25:24,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:24,385 INFO L93 Difference]: Finished difference Result 177 states and 200 transitions. [2018-01-24 15:25:24,385 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 15:25:24,385 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2018-01-24 15:25:24,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:24,386 INFO L225 Difference]: With dead ends: 177 [2018-01-24 15:25:24,386 INFO L226 Difference]: Without dead ends: 171 [2018-01-24 15:25:24,387 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 214 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 15:25:24,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-01-24 15:25:24,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 158. [2018-01-24 15:25:24,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-01-24 15:25:24,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 180 transitions. [2018-01-24 15:25:24,395 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 180 transitions. Word has length 57 [2018-01-24 15:25:24,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:24,395 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 180 transitions. [2018-01-24 15:25:24,395 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 15:25:24,395 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 180 transitions. [2018-01-24 15:25:24,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 15:25:24,396 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:24,396 INFO L322 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:24,396 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:24,397 INFO L82 PathProgramCache]: Analyzing trace with hash 1325560757, now seen corresponding path program 11 times [2018-01-24 15:25:24,397 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:24,397 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:24,398 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:24,398 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:24,398 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:24,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:24,406 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:24,768 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:24,768 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:24,768 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:24,769 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:24,769 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:24,769 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:24,769 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:24,778 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:24,778 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:24,781 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:24,782 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:24,783 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:24,784 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:24,786 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:24,787 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:24,788 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:24,790 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:24,792 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:24,794 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:24,798 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:24,800 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:24,801 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:24,803 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:24,822 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:24,822 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:25,137 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:25,159 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:25,159 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:25,162 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:25,162 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:25,166 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:25,168 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:25,173 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:25,178 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:25,184 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:25,192 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:25,201 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:25,214 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:25,229 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:25,245 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:25,262 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:25,284 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:25,290 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:25,294 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:25,313 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:25,313 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:25,329 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:25,331 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:25,331 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 15:25:25,331 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:25,331 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 15:25:25,331 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 15:25:25,332 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 15:25:25,332 INFO L87 Difference]: Start difference. First operand 158 states and 180 transitions. Second operand 14 states. [2018-01-24 15:25:25,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:25,713 INFO L93 Difference]: Finished difference Result 190 states and 215 transitions. [2018-01-24 15:25:25,714 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 15:25:25,714 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 62 [2018-01-24 15:25:25,714 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:25,715 INFO L225 Difference]: With dead ends: 190 [2018-01-24 15:25:25,715 INFO L226 Difference]: Without dead ends: 184 [2018-01-24 15:25:25,716 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 233 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 15:25:25,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-01-24 15:25:25,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 170. [2018-01-24 15:25:25,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-01-24 15:25:25,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 194 transitions. [2018-01-24 15:25:25,722 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 194 transitions. Word has length 62 [2018-01-24 15:25:25,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:25,723 INFO L432 AbstractCegarLoop]: Abstraction has 170 states and 194 transitions. [2018-01-24 15:25:25,723 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 15:25:25,723 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 194 transitions. [2018-01-24 15:25:25,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-01-24 15:25:25,724 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:25,724 INFO L322 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:25,724 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:25,724 INFO L82 PathProgramCache]: Analyzing trace with hash 923361502, now seen corresponding path program 12 times [2018-01-24 15:25:25,724 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:25,725 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:25,725 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:25,725 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:25,725 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:25,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:25,734 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:25,947 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:25,947 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:25,947 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:25,947 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:25,947 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:25,947 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:25,947 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:25,952 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:25,952 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:25,955 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,956 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,957 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,958 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,959 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,960 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,961 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,962 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,963 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,964 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,965 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,967 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,969 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:25,969 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:25,971 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:25,990 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:25,990 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:26,186 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:26,206 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:26,207 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:26,209 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:26,210 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:26,213 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,214 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,218 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,222 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,226 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,231 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,239 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,252 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,269 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,291 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,309 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,330 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,358 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:26,364 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:26,368 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:26,380 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:26,380 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:26,396 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:26,398 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:26,398 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 15:25:26,398 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:26,398 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 15:25:26,399 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 15:25:26,399 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 15:25:26,399 INFO L87 Difference]: Start difference. First operand 170 states and 194 transitions. Second operand 15 states. [2018-01-24 15:25:26,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:26,848 INFO L93 Difference]: Finished difference Result 203 states and 230 transitions. [2018-01-24 15:25:26,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 15:25:26,848 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 67 [2018-01-24 15:25:26,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:26,850 INFO L225 Difference]: With dead ends: 203 [2018-01-24 15:25:26,850 INFO L226 Difference]: Without dead ends: 197 [2018-01-24 15:25:26,850 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 280 GetRequests, 252 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 15:25:26,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2018-01-24 15:25:26,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 182. [2018-01-24 15:25:26,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-24 15:25:26,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 208 transitions. [2018-01-24 15:25:26,859 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 208 transitions. Word has length 67 [2018-01-24 15:25:26,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:26,859 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 208 transitions. [2018-01-24 15:25:26,859 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 15:25:26,859 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 208 transitions. [2018-01-24 15:25:26,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-01-24 15:25:26,860 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:26,860 INFO L322 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:26,860 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:26,860 INFO L82 PathProgramCache]: Analyzing trace with hash 356861269, now seen corresponding path program 13 times [2018-01-24 15:25:26,860 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:26,861 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:26,861 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:26,861 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:26,861 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:26,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:26,868 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:27,040 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:27,040 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:27,040 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:27,041 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:27,041 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:27,041 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:27,041 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:27,045 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:27,046 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:27,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:27,365 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:27,389 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:27,390 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:27,668 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:27,689 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:27,689 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:27,692 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:27,692 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:27,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:27,712 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:27,724 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:27,724 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:27,740 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:27,742 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:27,742 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 29 [2018-01-24 15:25:27,742 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:27,742 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 15:25:27,743 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 15:25:27,743 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 15:25:27,743 INFO L87 Difference]: Start difference. First operand 182 states and 208 transitions. Second operand 16 states. [2018-01-24 15:25:28,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:28,271 INFO L93 Difference]: Finished difference Result 216 states and 245 transitions. [2018-01-24 15:25:28,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 15:25:28,272 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2018-01-24 15:25:28,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:28,273 INFO L225 Difference]: With dead ends: 216 [2018-01-24 15:25:28,273 INFO L226 Difference]: Without dead ends: 210 [2018-01-24 15:25:28,274 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 301 GetRequests, 271 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 15:25:28,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states. [2018-01-24 15:25:28,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 194. [2018-01-24 15:25:28,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-01-24 15:25:28,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 222 transitions. [2018-01-24 15:25:28,282 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 222 transitions. Word has length 72 [2018-01-24 15:25:28,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:28,282 INFO L432 AbstractCegarLoop]: Abstraction has 194 states and 222 transitions. [2018-01-24 15:25:28,282 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 15:25:28,282 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 222 transitions. [2018-01-24 15:25:28,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-01-24 15:25:28,283 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:28,283 INFO L322 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:28,283 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:28,284 INFO L82 PathProgramCache]: Analyzing trace with hash -1075276994, now seen corresponding path program 14 times [2018-01-24 15:25:28,284 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:28,284 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:28,285 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:28,285 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:28,285 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:28,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:28,293 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:28,494 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:28,494 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:28,494 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:28,494 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:28,495 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:28,495 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:28,495 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:28,500 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:28,500 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:28,503 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:28,509 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:28,510 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:28,511 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:28,530 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:28,530 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:28,791 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:28,811 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:28,812 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:28,815 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:28,815 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:28,819 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:28,829 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:28,837 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:28,840 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:28,854 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:28,854 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:28,871 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:28,872 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:28,872 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 31 [2018-01-24 15:25:28,872 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:28,872 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 15:25:28,872 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 15:25:28,873 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 15:25:28,873 INFO L87 Difference]: Start difference. First operand 194 states and 222 transitions. Second operand 17 states. [2018-01-24 15:25:29,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:29,438 INFO L93 Difference]: Finished difference Result 229 states and 260 transitions. [2018-01-24 15:25:29,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 15:25:29,438 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 77 [2018-01-24 15:25:29,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:29,440 INFO L225 Difference]: With dead ends: 229 [2018-01-24 15:25:29,440 INFO L226 Difference]: Without dead ends: 223 [2018-01-24 15:25:29,440 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 322 GetRequests, 290 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 15:25:29,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-01-24 15:25:29,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 206. [2018-01-24 15:25:29,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-01-24 15:25:29,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 236 transitions. [2018-01-24 15:25:29,454 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 236 transitions. Word has length 77 [2018-01-24 15:25:29,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:29,454 INFO L432 AbstractCegarLoop]: Abstraction has 206 states and 236 transitions. [2018-01-24 15:25:29,454 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 15:25:29,454 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 236 transitions. [2018-01-24 15:25:29,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-01-24 15:25:29,455 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:29,455 INFO L322 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:29,455 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:29,455 INFO L82 PathProgramCache]: Analyzing trace with hash 904302325, now seen corresponding path program 15 times [2018-01-24 15:25:29,455 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:29,456 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:29,456 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:29,456 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:29,456 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:29,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:29,464 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:29,822 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:29,823 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:29,823 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:29,823 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:29,823 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:29,823 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:29,823 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:29,828 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:29,828 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:29,831 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,832 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,833 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,834 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,835 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,836 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,837 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,838 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,840 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,841 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,843 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,845 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,846 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,849 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,851 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,854 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:29,854 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:29,856 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:29,870 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:29,870 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:30,236 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:30,271 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:30,271 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:30,274 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:30,274 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:30,280 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,282 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,286 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,290 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,296 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,304 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,311 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,321 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,332 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,348 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,367 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,387 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,410 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,437 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,476 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,521 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:30,530 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:30,533 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:30,552 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:30,552 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:30,569 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:30,570 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:30,570 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 33 [2018-01-24 15:25:30,571 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:30,571 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 15:25:30,571 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 15:25:30,571 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 15:25:30,571 INFO L87 Difference]: Start difference. First operand 206 states and 236 transitions. Second operand 18 states. [2018-01-24 15:25:31,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:31,176 INFO L93 Difference]: Finished difference Result 242 states and 275 transitions. [2018-01-24 15:25:31,176 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 15:25:31,176 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 82 [2018-01-24 15:25:31,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:31,177 INFO L225 Difference]: With dead ends: 242 [2018-01-24 15:25:31,177 INFO L226 Difference]: Without dead ends: 236 [2018-01-24 15:25:31,178 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 309 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 15:25:31,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-01-24 15:25:31,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 218. [2018-01-24 15:25:31,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2018-01-24 15:25:31,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 250 transitions. [2018-01-24 15:25:31,186 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 250 transitions. Word has length 82 [2018-01-24 15:25:31,187 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:31,187 INFO L432 AbstractCegarLoop]: Abstraction has 218 states and 250 transitions. [2018-01-24 15:25:31,187 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 15:25:31,187 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 250 transitions. [2018-01-24 15:25:31,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 15:25:31,188 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:31,188 INFO L322 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:31,188 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:31,188 INFO L82 PathProgramCache]: Analyzing trace with hash 2125745566, now seen corresponding path program 16 times [2018-01-24 15:25:31,188 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:31,189 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:31,189 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:31,189 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:31,189 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:31,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:31,196 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:31,432 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:31,433 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:31,433 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:31,433 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:31,433 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:31,433 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:31,433 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:31,438 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:31,438 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:31,453 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:31,455 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:31,472 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:31,472 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:31,812 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:31,832 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:31,832 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:31,835 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:31,835 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:31,905 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:31,908 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:31,926 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:31,926 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:31,949 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:31,951 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:31,951 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 35 [2018-01-24 15:25:31,951 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:31,951 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 15:25:31,952 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 15:25:31,952 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 15:25:31,952 INFO L87 Difference]: Start difference. First operand 218 states and 250 transitions. Second operand 19 states. [2018-01-24 15:25:32,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:32,745 INFO L93 Difference]: Finished difference Result 255 states and 290 transitions. [2018-01-24 15:25:32,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 15:25:32,746 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 87 [2018-01-24 15:25:32,746 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:32,747 INFO L225 Difference]: With dead ends: 255 [2018-01-24 15:25:32,747 INFO L226 Difference]: Without dead ends: 249 [2018-01-24 15:25:32,748 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 364 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 15:25:32,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states. [2018-01-24 15:25:32,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 230. [2018-01-24 15:25:32,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-01-24 15:25:32,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 264 transitions. [2018-01-24 15:25:32,759 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 264 transitions. Word has length 87 [2018-01-24 15:25:32,760 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:32,760 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 264 transitions. [2018-01-24 15:25:32,760 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 15:25:32,760 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 264 transitions. [2018-01-24 15:25:32,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 15:25:32,761 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:32,761 INFO L322 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:32,761 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:32,762 INFO L82 PathProgramCache]: Analyzing trace with hash 120606869, now seen corresponding path program 17 times [2018-01-24 15:25:32,762 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:32,762 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:32,763 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:32,763 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:32,763 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:32,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:32,772 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:32,967 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:32,967 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:32,968 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:32,968 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:32,968 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:32,968 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:32,968 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:32,973 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:32,974 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:32,977 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,978 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,979 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,980 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,981 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,982 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,983 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,984 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,986 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,988 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,989 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,992 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,994 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:32,997 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,000 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,004 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,007 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,012 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,013 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:33,015 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:33,030 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:33,030 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:33,386 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:33,406 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:33,406 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:33,409 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:33,409 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:33,413 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,415 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,419 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,425 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,431 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,438 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,447 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,457 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,472 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,490 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,506 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,526 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,550 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,587 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,629 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,665 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,707 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,755 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:33,766 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:33,769 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:33,786 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:33,786 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:33,806 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:33,808 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:33,808 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 37 [2018-01-24 15:25:33,808 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:33,808 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 15:25:33,808 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 15:25:33,809 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 15:25:33,809 INFO L87 Difference]: Start difference. First operand 230 states and 264 transitions. Second operand 20 states. [2018-01-24 15:25:34,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:34,606 INFO L93 Difference]: Finished difference Result 268 states and 305 transitions. [2018-01-24 15:25:34,606 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 15:25:34,606 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 92 [2018-01-24 15:25:34,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:34,608 INFO L225 Difference]: With dead ends: 268 [2018-01-24 15:25:34,608 INFO L226 Difference]: Without dead ends: 262 [2018-01-24 15:25:34,609 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 385 GetRequests, 347 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 15:25:34,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262 states. [2018-01-24 15:25:34,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262 to 242. [2018-01-24 15:25:34,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242 states. [2018-01-24 15:25:34,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 278 transitions. [2018-01-24 15:25:34,619 INFO L78 Accepts]: Start accepts. Automaton has 242 states and 278 transitions. Word has length 92 [2018-01-24 15:25:34,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:34,619 INFO L432 AbstractCegarLoop]: Abstraction has 242 states and 278 transitions. [2018-01-24 15:25:34,619 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 15:25:34,619 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 278 transitions. [2018-01-24 15:25:34,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-01-24 15:25:34,620 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:34,621 INFO L322 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:34,621 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:34,621 INFO L82 PathProgramCache]: Analyzing trace with hash 2070056958, now seen corresponding path program 18 times [2018-01-24 15:25:34,621 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:34,622 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:34,622 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:34,622 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:34,622 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:34,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:34,632 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:34,964 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:34,964 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:34,964 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:34,965 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:34,965 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:34,965 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:34,965 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:34,970 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:34,970 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:34,974 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,975 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,976 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,977 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,978 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,979 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,980 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,981 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,983 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,984 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,986 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,988 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,990 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,991 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,993 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,995 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:34,998 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,000 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,003 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,003 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:35,005 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:35,022 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:35,022 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:35,551 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:35,571 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:35,571 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:35,574 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:35,574 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:35,579 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,581 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,584 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,588 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,593 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,598 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,605 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,615 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,631 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,653 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,675 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,698 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,722 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,749 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,783 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,822 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,868 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:35,940 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:36,051 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:36,062 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:36,066 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:36,083 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:36,083 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:36,103 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:36,104 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:36,104 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 39 [2018-01-24 15:25:36,104 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:36,105 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 15:25:36,105 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 15:25:36,105 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 15:25:36,105 INFO L87 Difference]: Start difference. First operand 242 states and 278 transitions. Second operand 21 states. [2018-01-24 15:25:36,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:36,986 INFO L93 Difference]: Finished difference Result 281 states and 320 transitions. [2018-01-24 15:25:36,986 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 15:25:36,986 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 97 [2018-01-24 15:25:36,987 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:36,987 INFO L225 Difference]: With dead ends: 281 [2018-01-24 15:25:36,988 INFO L226 Difference]: Without dead ends: 275 [2018-01-24 15:25:36,988 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 406 GetRequests, 366 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 15:25:36,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 275 states. [2018-01-24 15:25:36,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 275 to 254. [2018-01-24 15:25:36,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 254 states. [2018-01-24 15:25:36,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254 states to 254 states and 292 transitions. [2018-01-24 15:25:37,000 INFO L78 Accepts]: Start accepts. Automaton has 254 states and 292 transitions. Word has length 97 [2018-01-24 15:25:37,000 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:37,000 INFO L432 AbstractCegarLoop]: Abstraction has 254 states and 292 transitions. [2018-01-24 15:25:37,000 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 15:25:37,000 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 292 transitions. [2018-01-24 15:25:37,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-24 15:25:37,001 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:37,001 INFO L322 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:37,001 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:37,002 INFO L82 PathProgramCache]: Analyzing trace with hash 183274037, now seen corresponding path program 19 times [2018-01-24 15:25:37,002 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:37,003 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:37,003 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:37,003 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:37,003 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:37,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:37,012 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:37,303 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:37,544 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:37,544 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:37,545 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:37,545 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:37,545 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:37,545 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:37,554 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:37,555 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:37,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:37,581 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:37,610 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:37,610 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:38,108 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:38,127 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:38,128 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:38,130 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:38,131 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:38,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:38,156 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:38,173 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:38,173 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:38,195 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:38,196 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:38,196 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 41 [2018-01-24 15:25:38,196 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:38,196 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 15:25:38,196 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 15:25:38,197 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 15:25:38,197 INFO L87 Difference]: Start difference. First operand 254 states and 292 transitions. Second operand 22 states. [2018-01-24 15:25:39,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:39,129 INFO L93 Difference]: Finished difference Result 294 states and 335 transitions. [2018-01-24 15:25:39,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 15:25:39,130 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 102 [2018-01-24 15:25:39,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:39,131 INFO L225 Difference]: With dead ends: 294 [2018-01-24 15:25:39,131 INFO L226 Difference]: Without dead ends: 288 [2018-01-24 15:25:39,131 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 427 GetRequests, 385 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 15:25:39,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2018-01-24 15:25:39,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 266. [2018-01-24 15:25:39,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 266 states. [2018-01-24 15:25:39,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 266 states to 266 states and 306 transitions. [2018-01-24 15:25:39,139 INFO L78 Accepts]: Start accepts. Automaton has 266 states and 306 transitions. Word has length 102 [2018-01-24 15:25:39,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:39,140 INFO L432 AbstractCegarLoop]: Abstraction has 266 states and 306 transitions. [2018-01-24 15:25:39,140 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 15:25:39,140 INFO L276 IsEmpty]: Start isEmpty. Operand 266 states and 306 transitions. [2018-01-24 15:25:39,140 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-24 15:25:39,141 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:39,141 INFO L322 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:39,141 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:39,141 INFO L82 PathProgramCache]: Analyzing trace with hash -1033282978, now seen corresponding path program 20 times [2018-01-24 15:25:39,141 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:39,141 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:39,142 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:39,142 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:39,142 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:39,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:39,148 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:40,255 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:40,255 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:40,255 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:40,256 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:40,256 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:40,256 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:40,256 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:40,262 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:40,262 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:40,266 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:40,279 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:40,282 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:40,285 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:40,306 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:40,307 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:40,905 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:40,925 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:40,926 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:40,929 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:40,929 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:40,934 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:40,951 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:40,968 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:40,973 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:41,015 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:41,015 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:41,049 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:41,051 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:41,051 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 43 [2018-01-24 15:25:41,051 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:41,051 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 15:25:41,052 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 15:25:41,052 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 15:25:41,052 INFO L87 Difference]: Start difference. First operand 266 states and 306 transitions. Second operand 23 states. [2018-01-24 15:25:42,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:42,124 INFO L93 Difference]: Finished difference Result 307 states and 350 transitions. [2018-01-24 15:25:42,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 15:25:42,125 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 107 [2018-01-24 15:25:42,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:42,126 INFO L225 Difference]: With dead ends: 307 [2018-01-24 15:25:42,126 INFO L226 Difference]: Without dead ends: 301 [2018-01-24 15:25:42,126 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 404 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 15:25:42,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states. [2018-01-24 15:25:42,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 278. [2018-01-24 15:25:42,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 278 states. [2018-01-24 15:25:42,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 278 states to 278 states and 320 transitions. [2018-01-24 15:25:42,135 INFO L78 Accepts]: Start accepts. Automaton has 278 states and 320 transitions. Word has length 107 [2018-01-24 15:25:42,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:42,135 INFO L432 AbstractCegarLoop]: Abstraction has 278 states and 320 transitions. [2018-01-24 15:25:42,136 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 15:25:42,136 INFO L276 IsEmpty]: Start isEmpty. Operand 278 states and 320 transitions. [2018-01-24 15:25:42,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-01-24 15:25:42,136 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:42,137 INFO L322 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:42,137 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:42,137 INFO L82 PathProgramCache]: Analyzing trace with hash -1905968171, now seen corresponding path program 21 times [2018-01-24 15:25:42,137 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:42,138 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:42,138 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:42,138 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:42,138 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:42,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:42,147 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:42,487 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:42,487 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:42,487 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:42,488 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:42,488 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:42,488 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:42,488 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:42,492 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:42,493 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:42,496 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,497 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,498 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,498 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,499 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,500 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,501 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,502 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,503 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,505 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,506 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,508 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,510 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,512 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,514 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,517 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,519 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,522 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,525 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,529 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,533 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,537 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:42,538 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:42,540 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:42,560 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:42,560 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:43,067 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:43,087 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:43,087 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:43,090 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:25:43,090 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:25:43,095 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,096 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,100 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,103 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,109 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,115 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,122 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,141 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,157 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,175 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,194 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,217 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,244 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,282 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,327 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,371 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,423 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,484 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,571 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,670 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,766 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:25:43,781 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:43,788 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:43,816 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:43,816 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:43,850 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:43,852 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:43,852 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 45 [2018-01-24 15:25:43,852 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:43,852 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 15:25:43,852 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 15:25:43,853 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 15:25:43,853 INFO L87 Difference]: Start difference. First operand 278 states and 320 transitions. Second operand 24 states. [2018-01-24 15:25:45,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:45,111 INFO L93 Difference]: Finished difference Result 320 states and 365 transitions. [2018-01-24 15:25:45,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 15:25:45,112 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 112 [2018-01-24 15:25:45,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:45,114 INFO L225 Difference]: With dead ends: 320 [2018-01-24 15:25:45,114 INFO L226 Difference]: Without dead ends: 314 [2018-01-24 15:25:45,115 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 423 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 15:25:45,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states. [2018-01-24 15:25:45,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 290. [2018-01-24 15:25:45,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 290 states. [2018-01-24 15:25:45,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290 states to 290 states and 334 transitions. [2018-01-24 15:25:45,126 INFO L78 Accepts]: Start accepts. Automaton has 290 states and 334 transitions. Word has length 112 [2018-01-24 15:25:45,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:45,126 INFO L432 AbstractCegarLoop]: Abstraction has 290 states and 334 transitions. [2018-01-24 15:25:45,127 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 15:25:45,127 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states and 334 transitions. [2018-01-24 15:25:45,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-01-24 15:25:45,128 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:45,128 INFO L322 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:45,128 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:45,128 INFO L82 PathProgramCache]: Analyzing trace with hash -994136898, now seen corresponding path program 22 times [2018-01-24 15:25:45,128 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:45,129 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:45,129 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:45,129 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:45,129 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:45,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:45,138 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:45,612 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:45,612 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:45,612 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:45,612 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:45,612 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:45,612 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:45,612 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:45,620 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:45,620 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:45,651 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:45,655 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:45,687 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:45,688 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:46,276 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:46,295 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:46,295 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:46,298 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:25:46,298 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:25:46,418 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:46,422 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:46,462 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:46,462 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:46,507 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:46,508 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:46,508 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 47 [2018-01-24 15:25:46,509 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:46,509 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 15:25:46,509 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 15:25:46,510 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 15:25:46,510 INFO L87 Difference]: Start difference. First operand 290 states and 334 transitions. Second operand 25 states. [2018-01-24 15:25:47,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:47,765 INFO L93 Difference]: Finished difference Result 333 states and 380 transitions. [2018-01-24 15:25:47,765 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 15:25:47,765 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 117 [2018-01-24 15:25:47,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:47,766 INFO L225 Difference]: With dead ends: 333 [2018-01-24 15:25:47,766 INFO L226 Difference]: Without dead ends: 327 [2018-01-24 15:25:47,767 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 442 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 15:25:47,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states. [2018-01-24 15:25:47,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 302. [2018-01-24 15:25:47,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 302 states. [2018-01-24 15:25:47,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 348 transitions. [2018-01-24 15:25:47,774 INFO L78 Accepts]: Start accepts. Automaton has 302 states and 348 transitions. Word has length 117 [2018-01-24 15:25:47,775 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:47,775 INFO L432 AbstractCegarLoop]: Abstraction has 302 states and 348 transitions. [2018-01-24 15:25:47,775 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 15:25:47,775 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 348 transitions. [2018-01-24 15:25:47,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-24 15:25:47,776 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:47,777 INFO L322 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:47,777 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:47,777 INFO L82 PathProgramCache]: Analyzing trace with hash 1248093557, now seen corresponding path program 23 times [2018-01-24 15:25:47,777 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:47,778 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:47,778 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:47,778 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:47,778 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:47,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:47,787 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:48,138 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:48,139 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:48,139 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:48,139 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:48,139 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:48,139 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:48,139 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:48,144 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:48,144 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:48,148 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,149 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,150 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,151 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,152 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,154 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,155 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,156 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,158 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,159 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,161 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,163 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,166 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,168 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,171 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,174 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,178 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,182 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,186 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,191 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,196 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,202 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,209 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,217 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,218 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:48,220 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:48,243 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:48,243 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:48,841 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:48,861 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:48,861 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:48,864 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 15:25:48,864 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:48,869 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,871 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,874 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,879 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,886 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,894 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,902 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,912 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,925 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,943 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,966 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:48,987 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,012 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,038 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,079 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,128 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,170 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,219 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,272 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,356 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,460 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,538 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,623 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,718 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:49,739 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:49,744 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:49,775 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:49,776 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:49,804 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:49,806 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:49,806 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 49 [2018-01-24 15:25:49,806 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:49,806 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 15:25:49,806 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 15:25:49,807 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 15:25:49,807 INFO L87 Difference]: Start difference. First operand 302 states and 348 transitions. Second operand 26 states. [2018-01-24 15:25:51,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:51,175 INFO L93 Difference]: Finished difference Result 346 states and 395 transitions. [2018-01-24 15:25:51,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 15:25:51,175 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 122 [2018-01-24 15:25:51,175 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:51,176 INFO L225 Difference]: With dead ends: 346 [2018-01-24 15:25:51,176 INFO L226 Difference]: Without dead ends: 340 [2018-01-24 15:25:51,177 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 511 GetRequests, 461 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 15:25:51,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states. [2018-01-24 15:25:51,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 314. [2018-01-24 15:25:51,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 314 states. [2018-01-24 15:25:51,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 314 states to 314 states and 362 transitions. [2018-01-24 15:25:51,184 INFO L78 Accepts]: Start accepts. Automaton has 314 states and 362 transitions. Word has length 122 [2018-01-24 15:25:51,184 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:51,185 INFO L432 AbstractCegarLoop]: Abstraction has 314 states and 362 transitions. [2018-01-24 15:25:51,185 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 15:25:51,185 INFO L276 IsEmpty]: Start isEmpty. Operand 314 states and 362 transitions. [2018-01-24 15:25:51,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-01-24 15:25:51,185 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:51,185 INFO L322 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:51,186 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:51,186 INFO L82 PathProgramCache]: Analyzing trace with hash -1210546402, now seen corresponding path program 24 times [2018-01-24 15:25:51,186 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:51,186 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:51,186 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:51,186 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:51,186 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:51,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:51,192 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:51,603 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:51,603 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:51,603 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:51,603 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:51,603 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:51,604 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:51,604 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:51,608 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:51,609 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:51,613 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,613 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,614 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,615 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,616 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,617 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,618 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,619 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,620 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,621 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,622 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,624 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,625 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,627 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,628 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,630 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,632 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,634 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,636 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,638 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,641 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,645 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,648 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,652 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,656 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:51,657 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:51,660 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:51,720 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:51,720 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:52,630 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:52,672 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:52,672 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:52,675 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 15:25:52,676 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 15:25:52,681 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,682 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,687 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,692 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,699 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,704 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,709 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,718 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,729 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,743 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,763 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,786 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,813 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,846 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,878 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,917 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:52,964 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:53,025 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:53,098 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:53,189 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:53,309 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:53,506 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:53,736 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:54,003 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:54,241 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 15:25:54,257 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:54,262 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:54,287 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:54,287 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:54,328 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:54,330 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:54,330 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 51 [2018-01-24 15:25:54,330 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:54,331 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 15:25:54,331 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 15:25:54,332 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 15:25:54,332 INFO L87 Difference]: Start difference. First operand 314 states and 362 transitions. Second operand 27 states. [2018-01-24 15:25:55,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:55,857 INFO L93 Difference]: Finished difference Result 359 states and 410 transitions. [2018-01-24 15:25:55,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 15:25:55,858 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 127 [2018-01-24 15:25:55,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:55,859 INFO L225 Difference]: With dead ends: 359 [2018-01-24 15:25:55,859 INFO L226 Difference]: Without dead ends: 353 [2018-01-24 15:25:55,860 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 532 GetRequests, 480 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 15:25:55,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353 states. [2018-01-24 15:25:55,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353 to 326. [2018-01-24 15:25:55,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 326 states. [2018-01-24 15:25:55,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 376 transitions. [2018-01-24 15:25:55,868 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 376 transitions. Word has length 127 [2018-01-24 15:25:55,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:55,868 INFO L432 AbstractCegarLoop]: Abstraction has 326 states and 376 transitions. [2018-01-24 15:25:55,869 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 15:25:55,869 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 376 transitions. [2018-01-24 15:25:55,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-01-24 15:25:55,869 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:55,870 INFO L322 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:55,870 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:55,870 INFO L82 PathProgramCache]: Analyzing trace with hash 53741333, now seen corresponding path program 25 times [2018-01-24 15:25:55,870 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:55,871 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:55,871 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:25:55,871 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:55,871 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:55,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:55,877 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:56,368 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:56,368 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:56,369 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:56,369 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:56,369 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:56,369 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:56,369 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:56,375 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:56,375 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:56,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:56,403 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:56,472 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:56,473 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:57,477 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:57,497 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:57,498 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:25:57,500 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:57,501 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 15:25:57,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:57,536 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:57,566 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:57,566 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:25:57,606 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:57,607 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:25:57,608 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 53 [2018-01-24 15:25:57,608 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:25:57,608 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 15:25:57,608 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 15:25:57,609 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 15:25:57,609 INFO L87 Difference]: Start difference. First operand 326 states and 376 transitions. Second operand 28 states. [2018-01-24 15:25:59,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:25:59,160 INFO L93 Difference]: Finished difference Result 372 states and 425 transitions. [2018-01-24 15:25:59,160 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 15:25:59,160 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 132 [2018-01-24 15:25:59,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:25:59,161 INFO L225 Difference]: With dead ends: 372 [2018-01-24 15:25:59,162 INFO L226 Difference]: Without dead ends: 366 [2018-01-24 15:25:59,162 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 499 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 15:25:59,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states. [2018-01-24 15:25:59,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 338. [2018-01-24 15:25:59,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 338 states. [2018-01-24 15:25:59,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 338 states to 338 states and 390 transitions. [2018-01-24 15:25:59,174 INFO L78 Accepts]: Start accepts. Automaton has 338 states and 390 transitions. Word has length 132 [2018-01-24 15:25:59,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:25:59,175 INFO L432 AbstractCegarLoop]: Abstraction has 338 states and 390 transitions. [2018-01-24 15:25:59,175 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 15:25:59,175 INFO L276 IsEmpty]: Start isEmpty. Operand 338 states and 390 transitions. [2018-01-24 15:25:59,176 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-01-24 15:25:59,176 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:25:59,176 INFO L322 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1] [2018-01-24 15:25:59,176 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:25:59,176 INFO L82 PathProgramCache]: Analyzing trace with hash -173217410, now seen corresponding path program 26 times [2018-01-24 15:25:59,176 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:25:59,177 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:59,177 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 15:25:59,177 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:25:59,177 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:25:59,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:25:59,185 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:25:59,768 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:59,769 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:59,769 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:25:59,769 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:25:59,769 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:25:59,769 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:25:59,769 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:25:59,774 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:25:59,775 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:25:59,779 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:59,793 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:25:59,794 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:25:59,797 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:25:59,828 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:25:59,829 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:26:00,607 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:00,627 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:26:00,627 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:26:00,630 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 15:26:00,630 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 15:26:00,635 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:26:00,651 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 15:26:00,666 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:26:00,672 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:26:00,705 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:00,705 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:26:00,741 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:00,742 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:26:00,742 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 55 [2018-01-24 15:26:00,742 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:26:00,743 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 15:26:00,743 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 15:26:00,743 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 15:26:00,744 INFO L87 Difference]: Start difference. First operand 338 states and 390 transitions. Second operand 29 states. [2018-01-24 15:26:02,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:26:02,436 INFO L93 Difference]: Finished difference Result 385 states and 440 transitions. [2018-01-24 15:26:02,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 15:26:02,436 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 137 [2018-01-24 15:26:02,436 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:26:02,437 INFO L225 Difference]: With dead ends: 385 [2018-01-24 15:26:02,437 INFO L226 Difference]: Without dead ends: 379 [2018-01-24 15:26:02,438 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 574 GetRequests, 518 SyntacticMatches, 2 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 15:26:02,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379 states. [2018-01-24 15:26:02,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379 to 350. [2018-01-24 15:26:02,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 350 states. [2018-01-24 15:26:02,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 350 states to 350 states and 404 transitions. [2018-01-24 15:26:02,451 INFO L78 Accepts]: Start accepts. Automaton has 350 states and 404 transitions. Word has length 137 [2018-01-24 15:26:02,451 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:26:02,451 INFO L432 AbstractCegarLoop]: Abstraction has 350 states and 404 transitions. [2018-01-24 15:26:02,451 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-24 15:26:02,451 INFO L276 IsEmpty]: Start isEmpty. Operand 350 states and 404 transitions. [2018-01-24 15:26:02,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-01-24 15:26:02,453 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:26:02,453 INFO L322 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1] [2018-01-24 15:26:02,453 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:26:02,453 INFO L82 PathProgramCache]: Analyzing trace with hash 681451701, now seen corresponding path program 27 times [2018-01-24 15:26:02,454 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:26:02,454 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:26:02,454 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:26:02,454 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:26:02,455 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:26:02,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:26:02,465 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:26:03,026 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:03,026 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:26:03,026 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:26:03,026 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:26:03,026 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:26:03,026 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:26:03,027 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:26:03,031 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:26:03,032 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:26:03,037 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,038 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,040 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,041 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,043 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,045 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,046 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,048 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,050 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,053 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,055 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,058 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,061 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,065 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,068 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,071 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,079 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,093 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,096 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,101 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,105 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,109 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,114 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,119 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,125 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,137 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,144 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:03,145 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:26:03,147 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:26:03,177 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:03,177 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:26:04,000 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:04,021 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:26:04,021 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:26:04,024 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 15:26:04,024 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 15:26:04,029 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,030 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,034 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,038 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,044 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,051 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,058 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,068 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,079 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,095 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,114 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,134 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,158 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,186 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,226 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,272 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,318 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,371 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,433 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,525 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,625 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,723 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,833 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:04,956 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:05,130 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:05,315 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:05,491 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:05,693 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 15:26:05,721 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:26:05,728 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:26:05,773 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:05,773 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:26:05,830 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:05,832 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:26:05,832 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 57 [2018-01-24 15:26:05,832 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:26:05,833 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 15:26:05,833 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 15:26:05,834 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=897, Invalid=2409, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 15:26:05,834 INFO L87 Difference]: Start difference. First operand 350 states and 404 transitions. Second operand 30 states. [2018-01-24 15:26:07,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 15:26:07,669 INFO L93 Difference]: Finished difference Result 398 states and 455 transitions. [2018-01-24 15:26:07,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-24 15:26:07,669 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 142 [2018-01-24 15:26:07,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 15:26:07,671 INFO L225 Difference]: With dead ends: 398 [2018-01-24 15:26:07,671 INFO L226 Difference]: Without dead ends: 392 [2018-01-24 15:26:07,671 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 595 GetRequests, 537 SyntacticMatches, 2 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=897, Invalid=2409, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 15:26:07,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states. [2018-01-24 15:26:07,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 362. [2018-01-24 15:26:07,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 362 states. [2018-01-24 15:26:07,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 362 states to 362 states and 418 transitions. [2018-01-24 15:26:07,683 INFO L78 Accepts]: Start accepts. Automaton has 362 states and 418 transitions. Word has length 142 [2018-01-24 15:26:07,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 15:26:07,684 INFO L432 AbstractCegarLoop]: Abstraction has 362 states and 418 transitions. [2018-01-24 15:26:07,684 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 15:26:07,684 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states and 418 transitions. [2018-01-24 15:26:07,685 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2018-01-24 15:26:07,685 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 15:26:07,686 INFO L322 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1] [2018-01-24 15:26:07,686 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 15:26:07,686 INFO L82 PathProgramCache]: Analyzing trace with hash 1555157982, now seen corresponding path program 28 times [2018-01-24 15:26:07,686 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 15:26:07,687 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:26:07,687 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 15:26:07,687 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 15:26:07,687 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 15:26:07,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 15:26:07,697 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 15:26:08,297 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:08,298 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:26:08,298 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 15:26:08,298 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 15:26:08,298 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 15:26:08,298 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:26:08,298 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 15:26:08,303 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:26:08,303 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:26:08,341 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:26:08,344 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:26:08,375 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:08,375 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:26:09,256 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:09,277 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 15:26:09,277 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 15:26:09,280 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 15:26:09,280 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 15:26:09,495 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 15:26:09,501 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 15:26:09,532 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:09,532 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 15:26:09,571 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 15:26:09,573 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 15:26:09,573 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 59 [2018-01-24 15:26:09,573 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 15:26:09,573 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-24 15:26:09,574 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-24 15:26:09,574 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=958, Invalid=2582, Unknown=0, NotChecked=0, Total=3540 [2018-01-24 15:26:09,574 INFO L87 Difference]: Start difference. First operand 362 states and 418 transitions. Second operand 31 states. Received shutdown request... [2018-01-24 15:26:10,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 15:26:10,334 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 15:26:10,338 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 15:26:10,339 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 03:26:10 BoogieIcfgContainer [2018-01-24 15:26:10,339 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 15:26:10,340 INFO L168 Benchmark]: Toolchain (without parser) took 53073.15 ms. Allocated memory was 308.8 MB in the beginning and 685.2 MB in the end (delta: 376.4 MB). Free memory was 269.7 MB in the beginning and 488.9 MB in the end (delta: -219.2 MB). Peak memory consumption was 157.3 MB. Max. memory is 5.3 GB. [2018-01-24 15:26:10,340 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 308.8 MB. Free memory is still 274.7 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 15:26:10,340 INFO L168 Benchmark]: CACSL2BoogieTranslator took 150.35 ms. Allocated memory is still 308.8 MB. Free memory was 268.7 MB in the beginning and 261.5 MB in the end (delta: 7.2 MB). Peak memory consumption was 7.2 MB. Max. memory is 5.3 GB. [2018-01-24 15:26:10,341 INFO L168 Benchmark]: Boogie Preprocessor took 35.64 ms. Allocated memory is still 308.8 MB. Free memory was 261.5 MB in the beginning and 259.5 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 15:26:10,341 INFO L168 Benchmark]: RCFGBuilder took 238.44 ms. Allocated memory is still 308.8 MB. Free memory was 259.5 MB in the beginning and 247.5 MB in the end (delta: 12.0 MB). Peak memory consumption was 12.0 MB. Max. memory is 5.3 GB. [2018-01-24 15:26:10,341 INFO L168 Benchmark]: TraceAbstraction took 52639.93 ms. Allocated memory was 308.8 MB in the beginning and 685.2 MB in the end (delta: 376.4 MB). Free memory was 247.5 MB in the beginning and 488.9 MB in the end (delta: -241.4 MB). Peak memory consumption was 135.0 MB. Max. memory is 5.3 GB. [2018-01-24 15:26:10,343 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 308.8 MB. Free memory is still 274.7 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 150.35 ms. Allocated memory is still 308.8 MB. Free memory was 268.7 MB in the beginning and 261.5 MB in the end (delta: 7.2 MB). Peak memory consumption was 7.2 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 35.64 ms. Allocated memory is still 308.8 MB. Free memory was 261.5 MB in the beginning and 259.5 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 238.44 ms. Allocated memory is still 308.8 MB. Free memory was 259.5 MB in the beginning and 247.5 MB in the end (delta: 12.0 MB). Peak memory consumption was 12.0 MB. Max. memory is 5.3 GB. * TraceAbstraction took 52639.93 ms. Allocated memory was 308.8 MB in the beginning and 685.2 MB in the end (delta: 376.4 MB). Free memory was 247.5 MB in the beginning and 488.9 MB in the end (delta: -241.4 MB). Peak memory consumption was 135.0 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 10 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 0 LocStat_NO_SUPPORTING_DISEQUALITIES : 4 LocStat_NO_DISJUNCTIONS : -20 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 15 TransStat_MAX_WEQGRAPH_SIZE : 3 TransStat_MAX_SIZEOF_WEQEDGELABEL : 2 TransStat_NO_SUPPORTING_EQUALITIES : 5 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 16 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 5.821957 RENAME_VARIABLES(MILLISECONDS) : 0.617777 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 5.742879 PROJECTAWAY(MILLISECONDS) : 1.944137 ADD_WEAK_EQUALITY(MILLISECONDS) : 3.509643 DISJOIN(MILLISECONDS) : 0.209246 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.663739 ADD_EQUALITY(MILLISECONDS) : 0.084607 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.766021 #CONJOIN_DISJUNCTIVE : 36 #RENAME_VARIABLES : 82 #UNFREEZE : 0 #CONJOIN : 48 #PROJECTAWAY : 57 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 10 #RENAME_VARIABLES_DISJUNCTIVE : 77 #ADD_EQUALITY : 5 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 7]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 7). Cancelled while BasicCegarLoop was constructing difference of abstraction (362states) and interpolant automaton (currently 22 states, 31 states before enhancement), while ReachableStatesComputation was computing reachable states (142 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while BasicCegarLoop was constructing difference of abstraction (362states) and interpolant automaton (currently 22 states, 31 states before enhancement), while ReachableStatesComputation was computing reachable states (142 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was constructing difference of abstraction (362states) and interpolant automaton (currently 22 states, 31 states before enhancement), while ReachableStatesComputation was computing reachable states (142 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was constructing difference of abstraction (362states) and interpolant automaton (currently 22 states, 31 states before enhancement), while ReachableStatesComputation was computing reachable states (142 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 12]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 12). Cancelled while BasicCegarLoop was constructing difference of abstraction (362states) and interpolant automaton (currently 22 states, 31 states before enhancement), while ReachableStatesComputation was computing reachable states (142 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while BasicCegarLoop was constructing difference of abstraction (362states) and interpolant automaton (currently 22 states, 31 states before enhancement), while ReachableStatesComputation was computing reachable states (142 states constructedinput type IntersectNwa). - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 34 locations, 6 error locations. TIMEOUT Result, 52.5s OverallTime, 29 OverallIterations, 29 TraceHistogramMax, 20.6s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4584 SDtfs, 2553 SDslu, 64295 SDs, 0 SdLazy, 58475 SolverSat, 973 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 16.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 9312 GetRequests, 8387 SyntacticMatches, 56 SemanticMatches, 869 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 434 ImplicationChecksByTransitivity, 17.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=362occurred in iteration=28, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.3s AbstIntTime, 1 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.3s AutomataMinimizationTime, 28 MinimizatonAttempts, 462 StatesRemovedByMinimization, 28 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 8.1s SatisfiabilityAnalysisTime, 21.2s InterpolantComputationTime, 6685 NumberOfCodeBlocks, 6685 NumberOfCodeBlocksAsserted, 487 NumberOfCheckSat, 10996 ConstructedInterpolants, 0 QuantifiedInterpolants, 8194098 SizeOfPredicates, 0 NumberOfNonLiveVariables, 6468 ConjunctsInSsa, 1792 ConjunctsInUnsatCore, 141 InterpolantComputations, 1 PerfectInterpolantSequences, 0/95410 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_15-26-10-354.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_15-26-10-354.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_15-26-10-354.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_15-26-10-354.csv Completed graceful shutdown