java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf -i ../../../trunk/examples/svcomp/memsafety/20051113-1.c_false-valid-memtrack.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 16:57:00,423 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 16:57:00,425 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 16:57:00,438 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 16:57:00,438 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 16:57:00,439 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 16:57:00,440 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 16:57:00,442 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 16:57:00,444 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 16:57:00,445 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 16:57:00,445 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 16:57:00,445 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 16:57:00,446 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 16:57:00,447 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 16:57:00,448 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 16:57:00,450 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 16:57:00,452 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 16:57:00,454 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 16:57:00,456 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 16:57:00,457 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 16:57:00,459 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-01-24 16:57:00,465 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 16:57:00,465 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 16:57:00,466 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf [2018-01-24 16:57:00,475 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 16:57:00,476 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 16:57:00,477 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 16:57:00,477 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 16:57:00,477 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 16:57:00,477 INFO L133 SettingsManager]: * Deactivate Weak Equivalences=true [2018-01-24 16:57:00,478 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 16:57:00,478 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 16:57:00,478 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 16:57:00,479 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 16:57:00,479 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 16:57:00,479 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 16:57:00,479 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 16:57:00,479 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 16:57:00,480 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 16:57:00,480 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 16:57:00,480 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 16:57:00,480 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 16:57:00,480 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 16:57:00,481 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 16:57:00,481 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 16:57:00,481 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 16:57:00,481 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 16:57:00,481 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 16:57:00,482 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 16:57:00,482 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 16:57:00,482 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 16:57:00,482 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 16:57:00,482 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 16:57:00,483 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 16:57:00,483 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 16:57:00,483 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 16:57:00,483 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 16:57:00,483 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 16:57:00,484 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 16:57:00,485 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 16:57:00,519 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 16:57:00,530 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 16:57:00,533 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 16:57:00,534 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 16:57:00,535 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 16:57:00,535 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/memsafety/20051113-1.c_false-valid-memtrack.i [2018-01-24 16:57:00,696 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 16:57:00,702 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 16:57:00,703 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 16:57:00,703 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 16:57:00,709 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 16:57:00,710 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 04:57:00" (1/1) ... [2018-01-24 16:57:00,712 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@715f1c11 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:57:00, skipping insertion in model container [2018-01-24 16:57:00,713 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 04:57:00" (1/1) ... [2018-01-24 16:57:00,727 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 16:57:00,768 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 16:57:00,900 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 16:57:00,921 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 16:57:00,931 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:57:00 WrapperNode [2018-01-24 16:57:00,931 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 16:57:00,932 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 16:57:00,932 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 16:57:00,932 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 16:57:00,949 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:57:00" (1/1) ... [2018-01-24 16:57:00,949 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:57:00" (1/1) ... [2018-01-24 16:57:00,959 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:57:00" (1/1) ... [2018-01-24 16:57:00,959 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:57:00" (1/1) ... [2018-01-24 16:57:00,964 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:57:00" (1/1) ... [2018-01-24 16:57:00,968 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:57:00" (1/1) ... [2018-01-24 16:57:00,970 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:57:00" (1/1) ... [2018-01-24 16:57:00,973 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 16:57:00,973 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 16:57:00,973 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 16:57:00,974 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 16:57:00,975 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:57:00" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 16:57:01,025 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 16:57:01,025 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 16:57:01,025 INFO L136 BoogieDeclarations]: Found implementation of procedure Sum [2018-01-24 16:57:01,025 INFO L136 BoogieDeclarations]: Found implementation of procedure Sum2 [2018-01-24 16:57:01,025 INFO L136 BoogieDeclarations]: Found implementation of procedure dummy_abort [2018-01-24 16:57:01,025 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 16:57:01,026 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 16:57:01,026 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 16:57:01,026 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 16:57:01,026 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 16:57:01,026 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 16:57:01,026 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-01-24 16:57:01,026 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-01-24 16:57:01,026 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-01-24 16:57:01,026 INFO L128 BoogieDeclarations]: Found specification of procedure Sum [2018-01-24 16:57:01,027 INFO L128 BoogieDeclarations]: Found specification of procedure Sum2 [2018-01-24 16:57:01,027 INFO L128 BoogieDeclarations]: Found specification of procedure dummy_abort [2018-01-24 16:57:01,027 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 16:57:01,027 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 16:57:01,027 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 16:57:01,157 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-01-24 16:57:01,311 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 16:57:01,311 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 04:57:01 BoogieIcfgContainer [2018-01-24 16:57:01,311 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 16:57:01,312 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 16:57:01,312 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 16:57:01,314 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 16:57:01,314 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 04:57:00" (1/3) ... [2018-01-24 16:57:01,315 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31624e92 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 04:57:01, skipping insertion in model container [2018-01-24 16:57:01,315 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:57:00" (2/3) ... [2018-01-24 16:57:01,315 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31624e92 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 04:57:01, skipping insertion in model container [2018-01-24 16:57:01,315 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 04:57:01" (3/3) ... [2018-01-24 16:57:01,317 INFO L105 eAbstractionObserver]: Analyzing ICFG 20051113-1.c_false-valid-memtrack.i [2018-01-24 16:57:01,327 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 16:57:01,337 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 25 error locations. [2018-01-24 16:57:01,387 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 16:57:01,388 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 16:57:01,388 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 16:57:01,388 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 16:57:01,388 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 16:57:01,388 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 16:57:01,388 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 16:57:01,388 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 16:57:01,389 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 16:57:01,405 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states. [2018-01-24 16:57:01,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 16:57:01,430 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:01,431 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:01,432 INFO L371 AbstractCegarLoop]: === Iteration 1 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:01,435 INFO L82 PathProgramCache]: Analyzing trace with hash -1274877597, now seen corresponding path program 1 times [2018-01-24 16:57:01,437 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:01,480 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:01,481 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:01,481 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:01,481 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:01,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:01,525 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:01,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:57:01,609 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:57:01,609 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 16:57:01,609 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:57:01,612 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 16:57:01,623 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 16:57:01,623 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 16:57:01,625 INFO L87 Difference]: Start difference. First operand 80 states. Second operand 4 states. [2018-01-24 16:57:02,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:02,004 INFO L93 Difference]: Finished difference Result 111 states and 123 transitions. [2018-01-24 16:57:02,004 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 16:57:02,006 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 8 [2018-01-24 16:57:02,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:02,018 INFO L225 Difference]: With dead ends: 111 [2018-01-24 16:57:02,018 INFO L226 Difference]: Without dead ends: 69 [2018-01-24 16:57:02,022 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 16:57:02,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-01-24 16:57:02,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2018-01-24 16:57:02,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-01-24 16:57:02,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 74 transitions. [2018-01-24 16:57:02,074 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 74 transitions. Word has length 8 [2018-01-24 16:57:02,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:02,075 INFO L432 AbstractCegarLoop]: Abstraction has 69 states and 74 transitions. [2018-01-24 16:57:02,075 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 16:57:02,075 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 74 transitions. [2018-01-24 16:57:02,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 16:57:02,076 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:02,076 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:02,076 INFO L371 AbstractCegarLoop]: === Iteration 2 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:02,076 INFO L82 PathProgramCache]: Analyzing trace with hash -1274877596, now seen corresponding path program 1 times [2018-01-24 16:57:02,077 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:02,078 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:02,078 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:02,078 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:02,079 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:02,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:02,098 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:02,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:57:02,204 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:57:02,205 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 16:57:02,205 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:57:02,207 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 16:57:02,207 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 16:57:02,207 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 16:57:02,207 INFO L87 Difference]: Start difference. First operand 69 states and 74 transitions. Second operand 4 states. [2018-01-24 16:57:02,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:02,342 INFO L93 Difference]: Finished difference Result 69 states and 74 transitions. [2018-01-24 16:57:02,342 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 16:57:02,343 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 8 [2018-01-24 16:57:02,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:02,344 INFO L225 Difference]: With dead ends: 69 [2018-01-24 16:57:02,344 INFO L226 Difference]: Without dead ends: 61 [2018-01-24 16:57:02,345 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 16:57:02,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-01-24 16:57:02,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2018-01-24 16:57:02,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-01-24 16:57:02,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 66 transitions. [2018-01-24 16:57:02,356 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 66 transitions. Word has length 8 [2018-01-24 16:57:02,356 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:02,356 INFO L432 AbstractCegarLoop]: Abstraction has 61 states and 66 transitions. [2018-01-24 16:57:02,356 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 16:57:02,357 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 66 transitions. [2018-01-24 16:57:02,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-24 16:57:02,357 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:02,358 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:02,358 INFO L371 AbstractCegarLoop]: === Iteration 3 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:02,358 INFO L82 PathProgramCache]: Analyzing trace with hash -1852712777, now seen corresponding path program 1 times [2018-01-24 16:57:02,358 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:02,359 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:02,360 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:02,360 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:02,360 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:02,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:02,387 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:02,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:57:02,463 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:57:02,463 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 16:57:02,463 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:57:02,464 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 16:57:02,464 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 16:57:02,464 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 16:57:02,465 INFO L87 Difference]: Start difference. First operand 61 states and 66 transitions. Second operand 5 states. [2018-01-24 16:57:02,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:02,587 INFO L93 Difference]: Finished difference Result 61 states and 66 transitions. [2018-01-24 16:57:02,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 16:57:02,588 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 25 [2018-01-24 16:57:02,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:02,589 INFO L225 Difference]: With dead ends: 61 [2018-01-24 16:57:02,589 INFO L226 Difference]: Without dead ends: 59 [2018-01-24 16:57:02,590 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 16:57:02,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-01-24 16:57:02,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2018-01-24 16:57:02,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2018-01-24 16:57:02,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 64 transitions. [2018-01-24 16:57:02,599 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 64 transitions. Word has length 25 [2018-01-24 16:57:02,600 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:02,600 INFO L432 AbstractCegarLoop]: Abstraction has 59 states and 64 transitions. [2018-01-24 16:57:02,600 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 16:57:02,600 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 64 transitions. [2018-01-24 16:57:02,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-24 16:57:02,601 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:02,601 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:02,601 INFO L371 AbstractCegarLoop]: === Iteration 4 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:02,601 INFO L82 PathProgramCache]: Analyzing trace with hash -1852712776, now seen corresponding path program 1 times [2018-01-24 16:57:02,602 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:02,603 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:02,603 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:02,603 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:02,603 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:02,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:02,628 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:02,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:57:02,738 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:57:02,738 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 16:57:02,738 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:57:02,739 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 16:57:02,739 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 16:57:02,739 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 16:57:02,740 INFO L87 Difference]: Start difference. First operand 59 states and 64 transitions. Second operand 6 states. [2018-01-24 16:57:02,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:02,899 INFO L93 Difference]: Finished difference Result 59 states and 64 transitions. [2018-01-24 16:57:02,899 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 16:57:02,900 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-01-24 16:57:02,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:02,901 INFO L225 Difference]: With dead ends: 59 [2018-01-24 16:57:02,901 INFO L226 Difference]: Without dead ends: 58 [2018-01-24 16:57:02,901 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-24 16:57:02,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-01-24 16:57:02,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 58. [2018-01-24 16:57:02,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-01-24 16:57:02,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 63 transitions. [2018-01-24 16:57:02,910 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 63 transitions. Word has length 25 [2018-01-24 16:57:02,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:02,910 INFO L432 AbstractCegarLoop]: Abstraction has 58 states and 63 transitions. [2018-01-24 16:57:02,910 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 16:57:02,911 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 63 transitions. [2018-01-24 16:57:02,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 16:57:02,911 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:02,912 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:02,912 INFO L371 AbstractCegarLoop]: === Iteration 5 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:02,912 INFO L82 PathProgramCache]: Analyzing trace with hash 1954449657, now seen corresponding path program 1 times [2018-01-24 16:57:02,912 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:02,913 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:02,913 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:02,913 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:02,913 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:02,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:02,942 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:03,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:57:03,267 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:57:03,267 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-01-24 16:57:03,267 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:57:03,267 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 16:57:03,268 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 16:57:03,268 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-01-24 16:57:03,268 INFO L87 Difference]: Start difference. First operand 58 states and 63 transitions. Second operand 9 states. [2018-01-24 16:57:03,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:03,518 INFO L93 Difference]: Finished difference Result 93 states and 102 transitions. [2018-01-24 16:57:03,518 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 16:57:03,519 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 27 [2018-01-24 16:57:03,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:03,520 INFO L225 Difference]: With dead ends: 93 [2018-01-24 16:57:03,520 INFO L226 Difference]: Without dead ends: 64 [2018-01-24 16:57:03,520 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 1 SyntacticMatches, 6 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-01-24 16:57:03,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-01-24 16:57:03,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 62. [2018-01-24 16:57:03,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-01-24 16:57:03,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 67 transitions. [2018-01-24 16:57:03,526 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 67 transitions. Word has length 27 [2018-01-24 16:57:03,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:03,527 INFO L432 AbstractCegarLoop]: Abstraction has 62 states and 67 transitions. [2018-01-24 16:57:03,527 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 16:57:03,527 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 67 transitions. [2018-01-24 16:57:03,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-01-24 16:57:03,527 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:03,528 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:03,528 INFO L371 AbstractCegarLoop]: === Iteration 6 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:03,528 INFO L82 PathProgramCache]: Analyzing trace with hash 1339860797, now seen corresponding path program 1 times [2018-01-24 16:57:03,528 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:03,529 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:03,529 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:03,529 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:03,529 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:03,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:03,547 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:03,730 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:57:03,731 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:03,731 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:03,732 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 34 with the following transitions: [2018-01-24 16:57:03,733 INFO L201 CegarAbsIntRunner]: [24], [25], [31], [32], [34], [38], [39], [46], [47], [49], [50], [52], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [105], [106], [110], [111], [112], [120], [121], [122] [2018-01-24 16:57:03,777 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 16:57:03,777 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 16:57:03,992 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 16:57:03,994 INFO L268 AbstractInterpreter]: Visited 30 different actions 37 times. Merged at 7 different actions 7 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 19 variables. [2018-01-24 16:57:04,005 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 16:57:04,006 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:04,006 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:04,019 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:04,019 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:04,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:04,064 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:04,107 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 16:57:04,107 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:04,173 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 16:57:04,194 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 16:57:04,194 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4, 4] imperfect sequences [6] total 11 [2018-01-24 16:57:04,194 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:57:04,195 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 16:57:04,195 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 16:57:04,195 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-01-24 16:57:04,195 INFO L87 Difference]: Start difference. First operand 62 states and 67 transitions. Second operand 4 states. [2018-01-24 16:57:04,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:04,224 INFO L93 Difference]: Finished difference Result 114 states and 124 transitions. [2018-01-24 16:57:04,225 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 16:57:04,225 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 33 [2018-01-24 16:57:04,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:04,227 INFO L225 Difference]: With dead ends: 114 [2018-01-24 16:57:04,227 INFO L226 Difference]: Without dead ends: 63 [2018-01-24 16:57:04,228 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 61 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2018-01-24 16:57:04,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-01-24 16:57:04,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2018-01-24 16:57:04,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-01-24 16:57:04,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-01-24 16:57:04,236 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 33 [2018-01-24 16:57:04,236 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:04,236 INFO L432 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-01-24 16:57:04,237 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 16:57:04,237 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-01-24 16:57:04,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-24 16:57:04,238 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:04,238 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:04,238 INFO L371 AbstractCegarLoop]: === Iteration 7 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:04,238 INFO L82 PathProgramCache]: Analyzing trace with hash 1619594826, now seen corresponding path program 1 times [2018-01-24 16:57:04,238 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:04,239 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:04,239 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:04,240 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:04,240 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:04,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:04,263 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:04,464 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-01-24 16:57:04,464 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:04,464 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:04,465 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 35 with the following transitions: [2018-01-24 16:57:04,465 INFO L201 CegarAbsIntRunner]: [24], [25], [29], [31], [32], [34], [38], [39], [46], [47], [49], [50], [52], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [105], [106], [110], [111], [112], [120], [121], [122] [2018-01-24 16:57:04,467 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 16:57:04,467 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 16:57:04,574 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 16:57:04,574 INFO L268 AbstractInterpreter]: Visited 31 different actions 42 times. Merged at 10 different actions 10 times. Never widened. Found 3 fixpoints after 3 different actions. Largest state had 19 variables. [2018-01-24 16:57:04,576 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 16:57:04,576 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:04,576 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:04,591 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:04,591 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:04,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:04,621 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:04,676 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 16:57:04,677 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:04,789 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 16:57:04,822 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:04,822 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 4 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:04,830 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:04,830 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:04,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:04,882 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:04,887 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 16:57:04,887 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:04,962 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-01-24 16:57:04,963 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:04,963 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5, 5, 5] total 13 [2018-01-24 16:57:04,963 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:04,964 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 16:57:04,964 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 16:57:04,964 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2018-01-24 16:57:04,964 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 10 states. [2018-01-24 16:57:05,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:05,157 INFO L93 Difference]: Finished difference Result 126 states and 138 transitions. [2018-01-24 16:57:05,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 16:57:05,158 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 34 [2018-01-24 16:57:05,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:05,160 INFO L225 Difference]: With dead ends: 126 [2018-01-24 16:57:05,160 INFO L226 Difference]: Without dead ends: 75 [2018-01-24 16:57:05,161 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 146 GetRequests, 128 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=219, Unknown=0, NotChecked=0, Total=272 [2018-01-24 16:57:05,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-01-24 16:57:05,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 70. [2018-01-24 16:57:05,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-24 16:57:05,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 76 transitions. [2018-01-24 16:57:05,170 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 76 transitions. Word has length 34 [2018-01-24 16:57:05,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:05,170 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 76 transitions. [2018-01-24 16:57:05,170 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 16:57:05,171 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 76 transitions. [2018-01-24 16:57:05,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 16:57:05,172 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:05,172 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:05,172 INFO L371 AbstractCegarLoop]: === Iteration 8 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:05,172 INFO L82 PathProgramCache]: Analyzing trace with hash -341936469, now seen corresponding path program 1 times [2018-01-24 16:57:05,173 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:05,173 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:05,174 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:05,174 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:05,174 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:05,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:05,191 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:05,247 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 16:57:05,248 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:57:05,248 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 16:57:05,248 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:57:05,248 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 16:57:05,249 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 16:57:05,249 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 16:57:05,249 INFO L87 Difference]: Start difference. First operand 70 states and 76 transitions. Second operand 5 states. [2018-01-24 16:57:05,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:05,339 INFO L93 Difference]: Finished difference Result 70 states and 76 transitions. [2018-01-24 16:57:05,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 16:57:05,339 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 42 [2018-01-24 16:57:05,340 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:05,340 INFO L225 Difference]: With dead ends: 70 [2018-01-24 16:57:05,341 INFO L226 Difference]: Without dead ends: 68 [2018-01-24 16:57:05,341 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 16:57:05,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-01-24 16:57:05,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 68. [2018-01-24 16:57:05,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68 states. [2018-01-24 16:57:05,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 74 transitions. [2018-01-24 16:57:05,349 INFO L78 Accepts]: Start accepts. Automaton has 68 states and 74 transitions. Word has length 42 [2018-01-24 16:57:05,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:05,350 INFO L432 AbstractCegarLoop]: Abstraction has 68 states and 74 transitions. [2018-01-24 16:57:05,350 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 16:57:05,350 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 74 transitions. [2018-01-24 16:57:05,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 16:57:05,351 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:05,351 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:05,352 INFO L371 AbstractCegarLoop]: === Iteration 9 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:05,352 INFO L82 PathProgramCache]: Analyzing trace with hash -341936468, now seen corresponding path program 1 times [2018-01-24 16:57:05,352 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:05,353 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:05,353 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:05,353 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:05,353 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:05,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:05,369 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:05,543 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 16:57:05,543 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:57:05,543 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 16:57:05,543 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:57:05,543 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 16:57:05,544 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 16:57:05,544 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-01-24 16:57:05,544 INFO L87 Difference]: Start difference. First operand 68 states and 74 transitions. Second operand 6 states. [2018-01-24 16:57:05,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:05,643 INFO L93 Difference]: Finished difference Result 68 states and 74 transitions. [2018-01-24 16:57:05,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 16:57:05,643 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 42 [2018-01-24 16:57:05,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:05,645 INFO L225 Difference]: With dead ends: 68 [2018-01-24 16:57:05,645 INFO L226 Difference]: Without dead ends: 67 [2018-01-24 16:57:05,646 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-01-24 16:57:05,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-01-24 16:57:05,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2018-01-24 16:57:05,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-01-24 16:57:05,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 73 transitions. [2018-01-24 16:57:05,654 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 73 transitions. Word has length 42 [2018-01-24 16:57:05,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:05,655 INFO L432 AbstractCegarLoop]: Abstraction has 67 states and 73 transitions. [2018-01-24 16:57:05,655 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 16:57:05,655 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 73 transitions. [2018-01-24 16:57:05,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-01-24 16:57:05,657 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:05,657 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:05,657 INFO L371 AbstractCegarLoop]: === Iteration 10 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:05,657 INFO L82 PathProgramCache]: Analyzing trace with hash -614912991, now seen corresponding path program 2 times [2018-01-24 16:57:05,657 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:05,658 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:05,659 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:05,659 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:05,659 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:05,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:05,678 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:05,916 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 16:57:05,917 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:05,917 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:05,917 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:57:05,917 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:57:05,917 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:05,917 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:05,928 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:57:05,928 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:57:05,947 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:05,966 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:05,978 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:05,982 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:06,033 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 16:57:06,034 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:06,168 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 16:57:06,189 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:06,189 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:06,192 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:57:06,193 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:57:06,216 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:06,241 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:06,252 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:06,256 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:06,264 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 16:57:06,264 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:06,296 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-01-24 16:57:06,301 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:06,302 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6, 6, 6] total 16 [2018-01-24 16:57:06,302 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:06,302 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 16:57:06,302 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 16:57:06,303 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=189, Unknown=0, NotChecked=0, Total=240 [2018-01-24 16:57:06,303 INFO L87 Difference]: Start difference. First operand 67 states and 73 transitions. Second operand 12 states. [2018-01-24 16:57:06,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:06,711 INFO L93 Difference]: Finished difference Result 136 states and 150 transitions. [2018-01-24 16:57:06,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 16:57:06,711 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 41 [2018-01-24 16:57:06,712 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:06,712 INFO L225 Difference]: With dead ends: 136 [2018-01-24 16:57:06,712 INFO L226 Difference]: Without dead ends: 82 [2018-01-24 16:57:06,713 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 176 GetRequests, 154 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=75, Invalid=345, Unknown=0, NotChecked=0, Total=420 [2018-01-24 16:57:06,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-01-24 16:57:06,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 74. [2018-01-24 16:57:06,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-24 16:57:06,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 81 transitions. [2018-01-24 16:57:06,721 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 81 transitions. Word has length 41 [2018-01-24 16:57:06,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:06,722 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 81 transitions. [2018-01-24 16:57:06,722 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 16:57:06,722 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 81 transitions. [2018-01-24 16:57:06,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-01-24 16:57:06,723 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:06,723 INFO L322 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:06,724 INFO L371 AbstractCegarLoop]: === Iteration 11 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:06,724 INFO L82 PathProgramCache]: Analyzing trace with hash 1732121728, now seen corresponding path program 1 times [2018-01-24 16:57:06,724 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:06,725 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:06,725 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:57:06,725 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:06,725 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:06,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:06,742 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:07,083 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-01-24 16:57:07,083 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:07,083 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:07,084 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 46 with the following transitions: [2018-01-24 16:57:07,084 INFO L201 CegarAbsIntRunner]: [0], [4], [5], [12], [15], [24], [25], [29], [31], [32], [34], [38], [39], [44], [46], [47], [50], [52], [56], [57], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [91], [105], [106], [110], [111], [112], [113], [116], [120], [121], [122] [2018-01-24 16:57:07,087 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 16:57:07,087 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 16:57:07,230 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 16:57:07,230 INFO L268 AbstractInterpreter]: Visited 41 different actions 56 times. Merged at 13 different actions 13 times. Never widened. Found 4 fixpoints after 4 different actions. Largest state had 20 variables. [2018-01-24 16:57:07,232 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 16:57:07,232 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:07,232 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:07,246 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:07,246 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:07,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:07,277 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:07,353 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 16:57:07,354 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:07,479 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 16:57:07,500 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:07,501 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:07,508 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:07,508 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:07,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:07,557 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:07,563 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 16:57:07,563 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:07,614 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 16:57:07,615 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:07,615 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 7, 7, 7, 7] total 22 [2018-01-24 16:57:07,615 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:07,616 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 16:57:07,616 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 16:57:07,616 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=378, Unknown=0, NotChecked=0, Total=462 [2018-01-24 16:57:07,616 INFO L87 Difference]: Start difference. First operand 74 states and 81 transitions. Second operand 17 states. [2018-01-24 16:57:07,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:07,900 INFO L93 Difference]: Finished difference Result 144 states and 160 transitions. [2018-01-24 16:57:07,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 16:57:07,901 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 45 [2018-01-24 16:57:07,901 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:07,901 INFO L225 Difference]: With dead ends: 144 [2018-01-24 16:57:07,902 INFO L226 Difference]: Without dead ends: 84 [2018-01-24 16:57:07,902 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 168 SyntacticMatches, 10 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 108 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=116, Invalid=586, Unknown=0, NotChecked=0, Total=702 [2018-01-24 16:57:07,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-01-24 16:57:07,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 79. [2018-01-24 16:57:07,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-01-24 16:57:07,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 87 transitions. [2018-01-24 16:57:07,910 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 87 transitions. Word has length 45 [2018-01-24 16:57:07,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:07,910 INFO L432 AbstractCegarLoop]: Abstraction has 79 states and 87 transitions. [2018-01-24 16:57:07,910 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 16:57:07,910 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 87 transitions. [2018-01-24 16:57:07,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-01-24 16:57:07,912 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:07,912 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:07,912 INFO L371 AbstractCegarLoop]: === Iteration 12 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:07,913 INFO L82 PathProgramCache]: Analyzing trace with hash -117713403, now seen corresponding path program 3 times [2018-01-24 16:57:07,913 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:07,914 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:07,914 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:07,914 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:07,914 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:07,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:07,933 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:08,355 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 17 proven. 13 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 16:57:08,355 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:08,355 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:08,355 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:57:08,355 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:57:08,356 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:08,356 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:08,367 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:57:08,367 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:57:08,379 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:08,390 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:08,391 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:08,394 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:08,411 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 16:57:08,413 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,416 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,416 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-01-24 16:57:08,509 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 16:57:08,511 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:57:08,511 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,512 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,515 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,515 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:20, output treesize:16 [2018-01-24 16:57:08,541 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 16:57:08,544 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,545 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,546 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 16:57:08,547 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,555 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,562 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,562 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:29, output treesize:25 [2018-01-24 16:57:08,592 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 16:57:08,595 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,595 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,596 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,597 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,598 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,598 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,599 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 16:57:08,600 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,614 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,621 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,621 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:38, output treesize:34 [2018-01-24 16:57:08,658 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 16:57:08,673 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,674 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,676 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,677 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,682 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,684 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,690 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,692 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,695 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,696 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,697 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,698 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,699 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 16:57:08,700 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,725 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,733 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,733 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:47, output treesize:43 [2018-01-24 16:57:08,774 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 16:57:08,779 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,780 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,780 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,781 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,782 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,782 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,783 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,784 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,784 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,785 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,790 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,791 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,791 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,792 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,793 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,794 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,795 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 16:57:08,796 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,824 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,833 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,833 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:56, output treesize:52 [2018-01-24 16:57:08,864 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 16:57:08,874 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,875 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,876 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,877 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,877 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,878 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,879 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,879 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,880 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,880 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,881 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,882 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,882 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,883 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,884 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,884 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,885 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,886 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,886 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,887 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,888 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:08,889 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 16:57:08,890 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,931 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,948 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:08,948 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:65, output treesize:61 [2018-01-24 16:57:09,010 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 16:57:09,014 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,015 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,015 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,016 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,017 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,018 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,018 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,019 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,020 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,021 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,021 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,022 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,023 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,023 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,024 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,025 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,025 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,026 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,027 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,027 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,028 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,029 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,030 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,030 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,031 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,032 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,032 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,035 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 16:57:09,036 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:09,094 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:09,105 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:09,105 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-01-24 16:57:09,371 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 53 [2018-01-24 16:57:09,376 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,377 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,378 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,379 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,380 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,381 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,382 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,383 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,384 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,385 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,386 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,386 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,387 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,388 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,389 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,389 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,390 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,391 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,391 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,392 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,393 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,394 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,395 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,395 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,396 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,397 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,398 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:09,399 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 7 select indices, 7 select index equivalence classes, 27 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 160 [2018-01-24 16:57:09,400 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:09,424 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:09,431 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 16:57:09,432 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:90, output treesize:25 [2018-01-24 16:57:09,534 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 10 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 16:57:09,534 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:10,495 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 16:57:10,515 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:10,515 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:10,518 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:57:10,518 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:57:10,538 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:10,561 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:10,584 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:10,590 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:10,597 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 16:57:10,598 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,624 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,625 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-01-24 16:57:10,748 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 16:57:10,750 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:57:10,750 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,753 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,758 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,759 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:20, output treesize:16 [2018-01-24 16:57:10,810 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 16:57:10,812 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,813 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,814 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 16:57:10,814 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,819 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,824 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,825 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:29, output treesize:25 [2018-01-24 16:57:10,868 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 16:57:10,871 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,871 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,872 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,872 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,873 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,874 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,874 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 16:57:10,875 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,884 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,890 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,891 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:38, output treesize:34 [2018-01-24 16:57:10,930 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 16:57:10,932 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,932 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,933 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,933 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,934 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,934 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,935 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,936 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,936 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,937 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,937 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,938 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:10,939 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 16:57:10,939 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,957 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,963 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:10,963 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:47, output treesize:43 [2018-01-24 16:57:11,007 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 16:57:11,012 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,013 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,013 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,014 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,014 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,015 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,016 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,016 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,017 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,017 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,018 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,019 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,020 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,020 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,021 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,022 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,022 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 16:57:11,023 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:11,049 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:11,059 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:11,059 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:56, output treesize:52 [2018-01-24 16:57:11,123 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 16:57:11,125 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,126 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,126 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,127 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,127 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,128 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,128 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,129 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,129 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,130 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,130 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,131 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,132 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,132 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,133 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,133 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,134 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,135 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,135 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,136 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,136 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,137 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 16:57:11,138 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:11,167 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:11,176 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:11,176 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:65, output treesize:61 [2018-01-24 16:57:11,249 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 16:57:11,252 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,252 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,253 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,253 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,254 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,254 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,255 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,255 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,256 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,256 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,257 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,257 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,258 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,259 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,259 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,260 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,260 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,261 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,261 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,262 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,262 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,263 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,264 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,264 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,265 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,265 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,266 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,267 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 16:57:11,268 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:11,308 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:11,319 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:11,319 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:74, output treesize:70 [2018-01-24 16:57:11,617 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 41 [2018-01-24 16:57:11,620 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,621 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,621 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,622 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,622 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,623 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:11,624 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 27 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 43 [2018-01-24 16:57:11,624 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:11,639 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:11,645 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 16:57:11,645 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:78, output treesize:25 [2018-01-24 16:57:11,745 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 10 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 16:57:11,745 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:12,562 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 16:57:12,564 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:12,564 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 17, 10, 17, 10] total 54 [2018-01-24 16:57:12,564 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:12,565 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 16:57:12,565 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 16:57:12,566 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=2521, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 16:57:12,566 INFO L87 Difference]: Start difference. First operand 79 states and 87 transitions. Second operand 30 states. [2018-01-24 16:57:14,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:14,243 INFO L93 Difference]: Finished difference Result 113 states and 126 transitions. [2018-01-24 16:57:14,243 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 16:57:14,243 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 49 [2018-01-24 16:57:14,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:14,244 INFO L225 Difference]: With dead ends: 113 [2018-01-24 16:57:14,245 INFO L226 Difference]: Without dead ends: 77 [2018-01-24 16:57:14,246 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 235 GetRequests, 136 SyntacticMatches, 28 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2186 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=795, Invalid=4461, Unknown=0, NotChecked=0, Total=5256 [2018-01-24 16:57:14,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-01-24 16:57:14,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2018-01-24 16:57:14,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-01-24 16:57:14,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 84 transitions. [2018-01-24 16:57:14,265 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 84 transitions. Word has length 49 [2018-01-24 16:57:14,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:14,265 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 84 transitions. [2018-01-24 16:57:14,265 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 16:57:14,265 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 84 transitions. [2018-01-24 16:57:14,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 16:57:14,267 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:14,267 INFO L322 BasicCegarLoop]: trace histogram [4, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:14,267 INFO L371 AbstractCegarLoop]: === Iteration 13 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:14,267 INFO L82 PathProgramCache]: Analyzing trace with hash 2106198684, now seen corresponding path program 1 times [2018-01-24 16:57:14,267 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:14,268 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:14,268 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:57:14,268 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:14,269 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:14,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:14,280 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:14,355 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-01-24 16:57:14,355 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:57:14,355 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 16:57:14,355 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:57:14,355 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 16:57:14,356 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 16:57:14,356 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 16:57:14,356 INFO L87 Difference]: Start difference. First operand 77 states and 84 transitions. Second operand 5 states. [2018-01-24 16:57:14,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:14,396 INFO L93 Difference]: Finished difference Result 86 states and 93 transitions. [2018-01-24 16:57:14,396 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 16:57:14,396 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2018-01-24 16:57:14,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:14,397 INFO L225 Difference]: With dead ends: 86 [2018-01-24 16:57:14,397 INFO L226 Difference]: Without dead ends: 83 [2018-01-24 16:57:14,398 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 16:57:14,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-01-24 16:57:14,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 82. [2018-01-24 16:57:14,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-24 16:57:14,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 89 transitions. [2018-01-24 16:57:14,404 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 89 transitions. Word has length 52 [2018-01-24 16:57:14,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:14,405 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 89 transitions. [2018-01-24 16:57:14,405 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 16:57:14,405 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 89 transitions. [2018-01-24 16:57:14,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 16:57:14,406 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:14,406 INFO L322 BasicCegarLoop]: trace histogram [4, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:14,406 INFO L371 AbstractCegarLoop]: === Iteration 14 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:14,406 INFO L82 PathProgramCache]: Analyzing trace with hash 1604645521, now seen corresponding path program 1 times [2018-01-24 16:57:14,406 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:14,407 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:14,407 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:14,407 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:14,407 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:14,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:14,420 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:14,678 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-01-24 16:57:14,679 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:14,679 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:14,679 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 53 with the following transitions: [2018-01-24 16:57:14,679 INFO L201 CegarAbsIntRunner]: [0], [4], [5], [12], [13], [15], [16], [18], [24], [25], [29], [31], [32], [34], [38], [39], [44], [46], [47], [50], [52], [56], [57], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [91], [105], [106], [110], [111], [112], [113], [116], [120], [121], [122] [2018-01-24 16:57:14,681 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 16:57:14,681 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 16:57:14,817 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 16:57:14,817 INFO L268 AbstractInterpreter]: Visited 44 different actions 66 times. Merged at 20 different actions 20 times. Never widened. Found 5 fixpoints after 5 different actions. Largest state had 20 variables. [2018-01-24 16:57:14,831 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 16:57:14,831 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:14,831 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:14,842 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:14,842 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:14,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:14,871 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:14,932 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 16:57:14,933 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:15,039 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 16:57:15,059 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:15,059 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:15,063 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:15,064 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:15,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:15,104 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:15,108 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 16:57:15,108 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:15,129 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-01-24 16:57:15,131 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:15,131 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8, 8, 8] total 25 [2018-01-24 16:57:15,131 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:15,131 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 16:57:15,131 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 16:57:15,132 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=490, Unknown=0, NotChecked=0, Total=600 [2018-01-24 16:57:15,132 INFO L87 Difference]: Start difference. First operand 82 states and 89 transitions. Second operand 19 states. [2018-01-24 16:57:15,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:15,465 INFO L93 Difference]: Finished difference Result 151 states and 166 transitions. [2018-01-24 16:57:15,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 16:57:15,465 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 52 [2018-01-24 16:57:15,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:15,466 INFO L225 Difference]: With dead ends: 151 [2018-01-24 16:57:15,466 INFO L226 Difference]: Without dead ends: 84 [2018-01-24 16:57:15,467 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 194 SyntacticMatches, 8 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 153 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=174, Invalid=882, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 16:57:15,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-01-24 16:57:15,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 81. [2018-01-24 16:57:15,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-01-24 16:57:15,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 88 transitions. [2018-01-24 16:57:15,472 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 88 transitions. Word has length 52 [2018-01-24 16:57:15,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:15,472 INFO L432 AbstractCegarLoop]: Abstraction has 81 states and 88 transitions. [2018-01-24 16:57:15,472 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 16:57:15,472 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 88 transitions. [2018-01-24 16:57:15,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-01-24 16:57:15,473 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:15,473 INFO L322 BasicCegarLoop]: trace histogram [5, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:15,474 INFO L371 AbstractCegarLoop]: === Iteration 15 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:15,474 INFO L82 PathProgramCache]: Analyzing trace with hash -544800124, now seen corresponding path program 1 times [2018-01-24 16:57:15,474 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:15,475 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:15,475 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:15,475 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:15,475 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:15,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:15,485 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:15,694 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-01-24 16:57:15,694 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:15,694 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:15,694 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 57 with the following transitions: [2018-01-24 16:57:15,694 INFO L201 CegarAbsIntRunner]: [0], [4], [5], [10], [22], [23], [24], [25], [29], [31], [32], [33], [34], [38], [39], [44], [46], [47], [50], [52], [56], [57], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [91], [94], [97], [102], [104], [105], [106], [110], [111], [112], [113], [116], [117], [118], [119], [120], [121], [122] [2018-01-24 16:57:15,696 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 16:57:15,696 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 16:57:15,792 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 16:57:15,793 INFO L268 AbstractInterpreter]: Visited 50 different actions 65 times. Merged at 13 different actions 13 times. Never widened. Found 4 fixpoints after 4 different actions. Largest state had 20 variables. [2018-01-24 16:57:15,797 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 16:57:15,797 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:15,797 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:15,812 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:15,812 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:15,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:15,846 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:15,991 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 16:57:15,991 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:16,109 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 16:57:16,130 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:16,130 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:16,133 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:16,133 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:16,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:16,175 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:16,182 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 16:57:16,182 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:16,214 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 16:57:16,215 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:16,215 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 23 [2018-01-24 16:57:16,215 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:16,216 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 16:57:16,216 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 16:57:16,216 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=124, Invalid=382, Unknown=0, NotChecked=0, Total=506 [2018-01-24 16:57:16,216 INFO L87 Difference]: Start difference. First operand 81 states and 88 transitions. Second operand 16 states. [2018-01-24 16:57:16,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:16,386 INFO L93 Difference]: Finished difference Result 148 states and 162 transitions. [2018-01-24 16:57:16,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 16:57:16,386 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 56 [2018-01-24 16:57:16,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:16,387 INFO L225 Difference]: With dead ends: 148 [2018-01-24 16:57:16,387 INFO L226 Difference]: Without dead ends: 80 [2018-01-24 16:57:16,388 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 242 GetRequests, 208 SyntacticMatches, 10 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=143, Invalid=507, Unknown=0, NotChecked=0, Total=650 [2018-01-24 16:57:16,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-24 16:57:16,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 77. [2018-01-24 16:57:16,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-01-24 16:57:16,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 83 transitions. [2018-01-24 16:57:16,398 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 83 transitions. Word has length 56 [2018-01-24 16:57:16,398 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:16,398 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 83 transitions. [2018-01-24 16:57:16,398 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 16:57:16,398 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 83 transitions. [2018-01-24 16:57:16,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-01-24 16:57:16,400 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:16,400 INFO L322 BasicCegarLoop]: trace histogram [6, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:16,400 INFO L371 AbstractCegarLoop]: === Iteration 16 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:16,401 INFO L82 PathProgramCache]: Analyzing trace with hash -1454707584, now seen corresponding path program 1 times [2018-01-24 16:57:16,401 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:16,401 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:16,402 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:16,402 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:16,402 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:16,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:16,420 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:16,713 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 16:57:16,713 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:16,713 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:16,714 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 61 with the following transitions: [2018-01-24 16:57:16,714 INFO L201 CegarAbsIntRunner]: [0], [4], [5], [10], [12], [13], [16], [18], [22], [23], [24], [25], [29], [31], [32], [34], [38], [39], [44], [46], [47], [50], [52], [56], [57], [58], [59], [63], [64], [67], [70], [73], [76], [79], [82], [91], [94], [100], [102], [104], [105], [106], [110], [111], [112], [113], [116], [117], [120], [121], [122] [2018-01-24 16:57:16,716 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 16:57:16,716 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 16:57:16,845 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 16:57:16,846 INFO L268 AbstractInterpreter]: Visited 51 different actions 78 times. Merged at 24 different actions 24 times. Never widened. Found 5 fixpoints after 5 different actions. Largest state had 20 variables. [2018-01-24 16:57:16,847 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 16:57:16,847 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:16,847 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:16,856 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:16,856 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:16,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:16,881 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:16,946 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 16:57:16,946 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:17,090 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 16:57:17,110 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:17,110 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:17,113 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:17,113 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:17,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:17,157 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:17,161 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 16:57:17,161 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:17,191 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-01-24 16:57:17,193 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:17,193 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10, 10, 10, 10] total 25 [2018-01-24 16:57:17,193 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:17,193 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 16:57:17,194 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 16:57:17,194 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=440, Unknown=0, NotChecked=0, Total=600 [2018-01-24 16:57:17,194 INFO L87 Difference]: Start difference. First operand 77 states and 83 transitions. Second operand 17 states. [2018-01-24 16:57:17,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:17,380 INFO L93 Difference]: Finished difference Result 150 states and 163 transitions. [2018-01-24 16:57:17,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 16:57:17,380 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 60 [2018-01-24 16:57:17,380 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:17,381 INFO L225 Difference]: With dead ends: 150 [2018-01-24 16:57:17,381 INFO L226 Difference]: Without dead ends: 87 [2018-01-24 16:57:17,381 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 222 SyntacticMatches, 8 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 106 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=191, Invalid=621, Unknown=0, NotChecked=0, Total=812 [2018-01-24 16:57:17,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-01-24 16:57:17,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 84. [2018-01-24 16:57:17,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-01-24 16:57:17,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 90 transitions. [2018-01-24 16:57:17,390 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 90 transitions. Word has length 60 [2018-01-24 16:57:17,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:17,390 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 90 transitions. [2018-01-24 16:57:17,390 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 16:57:17,390 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 90 transitions. [2018-01-24 16:57:17,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-01-24 16:57:17,391 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:17,391 INFO L322 BasicCegarLoop]: trace histogram [7, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:17,391 INFO L371 AbstractCegarLoop]: === Iteration 17 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:17,392 INFO L82 PathProgramCache]: Analyzing trace with hash -374403177, now seen corresponding path program 2 times [2018-01-24 16:57:17,392 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:17,393 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:17,393 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:17,393 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:17,393 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:17,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:17,410 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:17,685 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 16:57:17,686 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:17,686 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:17,686 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:57:17,686 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:57:17,686 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:17,686 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:17,691 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:57:17,691 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:57:17,706 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:17,723 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:17,725 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:17,728 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:17,865 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 16:57:17,866 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:18,033 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 16:57:18,053 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:18,053 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:18,056 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:57:18,056 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:57:18,078 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:18,110 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:18,127 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:18,131 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:18,136 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 16:57:18,136 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:18,174 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-01-24 16:57:18,175 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:18,175 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 11, 11, 11] total 28 [2018-01-24 16:57:18,175 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:18,176 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 16:57:18,176 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 16:57:18,176 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=559, Unknown=0, NotChecked=0, Total=756 [2018-01-24 16:57:18,176 INFO L87 Difference]: Start difference. First operand 84 states and 90 transitions. Second operand 19 states. [2018-01-24 16:57:18,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:18,376 INFO L93 Difference]: Finished difference Result 154 states and 166 transitions. [2018-01-24 16:57:18,376 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 16:57:18,376 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 67 [2018-01-24 16:57:18,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:18,376 INFO L225 Difference]: With dead ends: 154 [2018-01-24 16:57:18,377 INFO L226 Difference]: Without dead ends: 85 [2018-01-24 16:57:18,377 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 288 GetRequests, 250 SyntacticMatches, 8 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 123 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=229, Invalid=763, Unknown=0, NotChecked=0, Total=992 [2018-01-24 16:57:18,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-01-24 16:57:18,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-01-24 16:57:18,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-01-24 16:57:18,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 90 transitions. [2018-01-24 16:57:18,383 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 90 transitions. Word has length 67 [2018-01-24 16:57:18,383 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:18,383 INFO L432 AbstractCegarLoop]: Abstraction has 85 states and 90 transitions. [2018-01-24 16:57:18,383 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 16:57:18,383 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 90 transitions. [2018-01-24 16:57:18,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-01-24 16:57:18,384 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:18,384 INFO L322 BasicCegarLoop]: trace histogram [8, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:18,384 INFO L371 AbstractCegarLoop]: === Iteration 18 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:18,384 INFO L82 PathProgramCache]: Analyzing trace with hash -1696068192, now seen corresponding path program 3 times [2018-01-24 16:57:18,384 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:18,385 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:18,385 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:57:18,385 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:18,385 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:18,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:18,398 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:18,618 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-01-24 16:57:18,619 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:18,619 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:18,619 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:57:18,619 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:57:18,619 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:18,619 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:18,624 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:57:18,624 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:57:18,639 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:18,652 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:18,663 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:18,664 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:18,667 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:18,684 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 16:57:18,685 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:57:18,686 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,687 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,689 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,689 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:15, output treesize:11 [2018-01-24 16:57:18,701 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 16:57:18,702 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,703 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,703 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 16:57:18,704 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,707 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,711 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,711 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:20 [2018-01-24 16:57:18,725 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 16:57:18,727 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,728 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,729 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,729 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,730 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,731 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,732 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 16:57:18,732 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,747 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,752 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,752 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:33, output treesize:29 [2018-01-24 16:57:18,770 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 16:57:18,772 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,773 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,773 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,774 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,775 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,775 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,776 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,776 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,777 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,777 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,778 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,778 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,779 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 16:57:18,779 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,793 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,799 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,799 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-01-24 16:57:18,819 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 16:57:18,822 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,822 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,823 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,824 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,824 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,824 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,825 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,825 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,826 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,827 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,827 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,828 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,828 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,829 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,829 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,830 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,831 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 16:57:18,831 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,852 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,858 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,859 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:51, output treesize:47 [2018-01-24 16:57:18,883 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 16:57:18,885 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,886 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,887 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,887 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,888 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,888 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,889 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,889 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,890 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,891 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,891 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,892 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,892 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,893 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,893 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,894 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,895 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,895 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,896 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,896 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,897 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,898 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 16:57:18,899 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,929 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,937 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:18,938 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:60, output treesize:56 [2018-01-24 16:57:18,967 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 16:57:18,970 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,970 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,971 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,972 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,972 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,973 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,973 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,974 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,975 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,975 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,976 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,976 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,977 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,977 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,978 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,978 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,979 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,979 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,980 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,980 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,981 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,981 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,982 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,982 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,983 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,984 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,984 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:18,985 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 16:57:18,985 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:19,024 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:19,033 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:19,034 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:69, output treesize:65 [2018-01-24 16:57:19,302 WARN L307 Elim1Store]: Array PQE input equivalent to false [2018-01-24 16:57:19,302 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:19,303 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:19,303 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:121, output treesize:1 [2018-01-24 16:57:19,317 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 16:57:19,318 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:20,120 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 16:57:20,150 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:20,151 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:20,156 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:57:20,156 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:57:20,181 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:20,211 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:20,293 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:20,330 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:20,336 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:20,344 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-01-24 16:57:20,345 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:57:20,345 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,346 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,348 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,349 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:15, output treesize:11 [2018-01-24 16:57:20,351 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-01-24 16:57:20,353 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,354 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,354 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 31 [2018-01-24 16:57:20,354 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,358 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,361 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,361 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:20 [2018-01-24 16:57:20,364 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 23 [2018-01-24 16:57:20,365 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,366 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,366 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,367 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,367 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,368 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,368 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 6 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 78 [2018-01-24 16:57:20,368 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,376 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,381 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,381 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:33, output treesize:29 [2018-01-24 16:57:20,383 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2018-01-24 16:57:20,385 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,385 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,386 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,386 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,387 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,387 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,388 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,389 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,389 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,390 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,390 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,391 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,391 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 12 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 149 [2018-01-24 16:57:20,392 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,409 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,414 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,414 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-01-24 16:57:20,417 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2018-01-24 16:57:20,419 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,419 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,420 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,420 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,421 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,421 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,422 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,422 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,423 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,423 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,424 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,424 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,425 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,425 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,426 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,426 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,427 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 16 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 206 [2018-01-24 16:57:20,428 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,451 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,458 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,458 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:51, output treesize:47 [2018-01-24 16:57:20,461 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 44 [2018-01-24 16:57:20,463 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,464 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,464 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,465 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,465 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,466 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,466 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,467 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,468 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,468 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,469 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,469 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,470 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,470 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,471 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,471 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,472 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,472 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,473 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,474 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,474 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,475 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 21 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 253 [2018-01-24 16:57:20,475 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,503 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,511 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,511 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:60, output treesize:56 [2018-01-24 16:57:20,514 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 51 [2018-01-24 16:57:20,516 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,517 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,517 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,518 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,518 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,519 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,519 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,520 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,520 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,521 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,521 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,522 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,522 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,523 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,523 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,524 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,524 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,525 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,525 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,526 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,526 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,527 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,528 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,528 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,529 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,530 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,530 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:57:20,531 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 27 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 308 [2018-01-24 16:57:20,532 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,570 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,579 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:57:20,580 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:69, output treesize:65 [2018-01-24 16:57:20,901 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 16:57:20,901 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:21,067 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-01-24 16:57:21,068 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:21,069 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 17, 8, 17, 8] total 42 [2018-01-24 16:57:21,069 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:21,069 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 16:57:21,069 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 16:57:21,069 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=213, Invalid=1509, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 16:57:21,070 INFO L87 Difference]: Start difference. First operand 85 states and 90 transitions. Second operand 28 states. [2018-01-24 16:57:22,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:22,040 INFO L93 Difference]: Finished difference Result 130 states and 139 transitions. [2018-01-24 16:57:22,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 16:57:22,066 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 74 [2018-01-24 16:57:22,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:22,067 INFO L225 Difference]: With dead ends: 130 [2018-01-24 16:57:22,067 INFO L226 Difference]: Without dead ends: 94 [2018-01-24 16:57:22,068 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 248 SyntacticMatches, 28 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1458 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=476, Invalid=3556, Unknown=0, NotChecked=0, Total=4032 [2018-01-24 16:57:22,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-01-24 16:57:22,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 91. [2018-01-24 16:57:22,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-01-24 16:57:22,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 95 transitions. [2018-01-24 16:57:22,077 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 95 transitions. Word has length 74 [2018-01-24 16:57:22,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:22,077 INFO L432 AbstractCegarLoop]: Abstraction has 91 states and 95 transitions. [2018-01-24 16:57:22,077 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 16:57:22,077 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 95 transitions. [2018-01-24 16:57:22,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-01-24 16:57:22,077 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:22,078 INFO L322 BasicCegarLoop]: trace histogram [8, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:22,078 INFO L371 AbstractCegarLoop]: === Iteration 19 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:22,078 INFO L82 PathProgramCache]: Analyzing trace with hash 1151371872, now seen corresponding path program 4 times [2018-01-24 16:57:22,078 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:22,078 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:22,078 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:57:22,079 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:22,079 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:22,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:22,092 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:22,311 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:22,312 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:22,312 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:22,312 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:57:22,312 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:57:22,312 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:22,312 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:22,319 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 16:57:22,319 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 16:57:22,367 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:22,370 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:22,432 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:22,432 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:22,600 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:22,620 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:22,620 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:22,624 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 16:57:22,624 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 16:57:22,711 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:22,716 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:22,722 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:22,722 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:22,767 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:22,768 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:22,769 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 32 [2018-01-24 16:57:22,769 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:22,769 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 16:57:22,769 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 16:57:22,770 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=357, Invalid=635, Unknown=0, NotChecked=0, Total=992 [2018-01-24 16:57:22,770 INFO L87 Difference]: Start difference. First operand 91 states and 95 transitions. Second operand 22 states. [2018-01-24 16:57:22,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:22,811 INFO L93 Difference]: Finished difference Result 164 states and 172 transitions. [2018-01-24 16:57:22,812 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 16:57:22,812 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 86 [2018-01-24 16:57:22,812 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:22,813 INFO L225 Difference]: With dead ends: 164 [2018-01-24 16:57:22,813 INFO L226 Difference]: Without dead ends: 92 [2018-01-24 16:57:22,813 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 355 GetRequests, 322 SyntacticMatches, 2 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 374 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=380, Invalid=676, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 16:57:22,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2018-01-24 16:57:22,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 92. [2018-01-24 16:57:22,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-01-24 16:57:22,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 96 transitions. [2018-01-24 16:57:22,820 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 96 transitions. Word has length 86 [2018-01-24 16:57:22,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:22,820 INFO L432 AbstractCegarLoop]: Abstraction has 92 states and 96 transitions. [2018-01-24 16:57:22,820 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 16:57:22,820 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 96 transitions. [2018-01-24 16:57:22,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 16:57:22,821 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:22,821 INFO L322 BasicCegarLoop]: trace histogram [9, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:22,821 INFO L371 AbstractCegarLoop]: === Iteration 20 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:22,821 INFO L82 PathProgramCache]: Analyzing trace with hash -1429474957, now seen corresponding path program 5 times [2018-01-24 16:57:22,822 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:22,822 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:22,822 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:57:22,822 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:22,822 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:22,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:22,839 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:23,238 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:23,239 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:23,239 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:23,239 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:57:23,239 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:57:23,239 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:23,239 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:23,244 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 16:57:23,244 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:57:23,251 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:23,252 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:23,255 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:23,260 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:23,267 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:23,280 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:23,282 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:23,284 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:23,344 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:23,344 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:23,579 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:23,599 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:23,599 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:23,602 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 16:57:23,602 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:57:23,609 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:23,612 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:23,621 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:23,641 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:23,731 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:24,188 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:24,212 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:24,217 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:24,223 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:24,224 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:24,261 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:24,263 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:24,263 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 35 [2018-01-24 16:57:24,263 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:24,264 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 16:57:24,264 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 16:57:24,265 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=426, Invalid=764, Unknown=0, NotChecked=0, Total=1190 [2018-01-24 16:57:24,265 INFO L87 Difference]: Start difference. First operand 92 states and 96 transitions. Second operand 24 states. [2018-01-24 16:57:24,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:24,325 INFO L93 Difference]: Finished difference Result 165 states and 173 transitions. [2018-01-24 16:57:24,325 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 16:57:24,325 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 87 [2018-01-24 16:57:24,326 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:24,326 INFO L225 Difference]: With dead ends: 165 [2018-01-24 16:57:24,326 INFO L226 Difference]: Without dead ends: 93 [2018-01-24 16:57:24,327 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 360 GetRequests, 324 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 457 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=451, Invalid=809, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 16:57:24,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-01-24 16:57:24,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2018-01-24 16:57:24,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-01-24 16:57:24,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 97 transitions. [2018-01-24 16:57:24,332 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 97 transitions. Word has length 87 [2018-01-24 16:57:24,333 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:24,333 INFO L432 AbstractCegarLoop]: Abstraction has 93 states and 97 transitions. [2018-01-24 16:57:24,333 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 16:57:24,333 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 97 transitions. [2018-01-24 16:57:24,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-24 16:57:24,333 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:24,334 INFO L322 BasicCegarLoop]: trace histogram [10, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:24,334 INFO L371 AbstractCegarLoop]: === Iteration 21 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:24,334 INFO L82 PathProgramCache]: Analyzing trace with hash 168651968, now seen corresponding path program 6 times [2018-01-24 16:57:24,334 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:24,334 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:24,334 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:57:24,335 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:24,335 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:24,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:24,348 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:24,510 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:24,510 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:24,510 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:24,510 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:57:24,510 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:57:24,511 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:24,511 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:24,515 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 16:57:24,515 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 16:57:24,532 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:57:24,543 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:57:24,553 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:57:24,580 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:57:24,620 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:57:24,736 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:57:24,737 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:24,740 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:24,814 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:24,814 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:25,028 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:25,059 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:25,059 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:25,062 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 16:57:25,062 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 16:57:25,089 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:57:25,116 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:57:25,163 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:57:25,429 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:57:26,055 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:57:27,644 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:57:27,675 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:27,683 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:27,689 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:27,689 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:27,732 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:27,734 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:27,734 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 38 [2018-01-24 16:57:27,734 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:27,735 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 16:57:27,735 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 16:57:27,735 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=501, Invalid=905, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 16:57:27,735 INFO L87 Difference]: Start difference. First operand 93 states and 97 transitions. Second operand 26 states. [2018-01-24 16:57:27,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:27,771 INFO L93 Difference]: Finished difference Result 166 states and 174 transitions. [2018-01-24 16:57:27,771 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 16:57:27,771 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 88 [2018-01-24 16:57:27,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:27,772 INFO L225 Difference]: With dead ends: 166 [2018-01-24 16:57:27,772 INFO L226 Difference]: Without dead ends: 94 [2018-01-24 16:57:27,773 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 365 GetRequests, 326 SyntacticMatches, 2 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 548 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=528, Invalid=954, Unknown=0, NotChecked=0, Total=1482 [2018-01-24 16:57:27,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-01-24 16:57:27,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 94. [2018-01-24 16:57:27,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-01-24 16:57:27,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 98 transitions. [2018-01-24 16:57:27,783 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 98 transitions. Word has length 88 [2018-01-24 16:57:27,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:27,784 INFO L432 AbstractCegarLoop]: Abstraction has 94 states and 98 transitions. [2018-01-24 16:57:27,784 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 16:57:27,784 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 98 transitions. [2018-01-24 16:57:27,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-01-24 16:57:27,785 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:27,785 INFO L322 BasicCegarLoop]: trace histogram [11, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:27,785 INFO L371 AbstractCegarLoop]: === Iteration 22 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:27,785 INFO L82 PathProgramCache]: Analyzing trace with hash -1829020909, now seen corresponding path program 7 times [2018-01-24 16:57:27,785 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:27,786 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:27,786 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:57:27,786 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:27,786 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:27,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:27,806 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:27,989 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:27,990 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:27,990 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:27,990 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:57:27,990 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:57:27,990 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:27,990 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:27,995 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:27,995 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:28,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:28,024 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:28,100 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:28,100 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:28,323 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:28,343 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:28,343 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:28,346 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:28,347 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:57:28,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:28,411 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:28,425 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:28,425 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:28,490 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:28,491 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:28,491 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 41 [2018-01-24 16:57:28,491 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:28,492 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 16:57:28,492 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 16:57:28,492 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=582, Invalid=1058, Unknown=0, NotChecked=0, Total=1640 [2018-01-24 16:57:28,492 INFO L87 Difference]: Start difference. First operand 94 states and 98 transitions. Second operand 28 states. [2018-01-24 16:57:28,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:28,564 INFO L93 Difference]: Finished difference Result 167 states and 175 transitions. [2018-01-24 16:57:28,564 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 16:57:28,564 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 89 [2018-01-24 16:57:28,565 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:28,565 INFO L225 Difference]: With dead ends: 167 [2018-01-24 16:57:28,565 INFO L226 Difference]: Without dead ends: 95 [2018-01-24 16:57:28,566 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 370 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 647 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=611, Invalid=1111, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 16:57:28,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2018-01-24 16:57:28,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2018-01-24 16:57:28,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-01-24 16:57:28,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 99 transitions. [2018-01-24 16:57:28,574 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 99 transitions. Word has length 89 [2018-01-24 16:57:28,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:28,574 INFO L432 AbstractCegarLoop]: Abstraction has 95 states and 99 transitions. [2018-01-24 16:57:28,574 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 16:57:28,574 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 99 transitions. [2018-01-24 16:57:28,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-01-24 16:57:28,575 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:28,575 INFO L322 BasicCegarLoop]: trace histogram [12, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:28,576 INFO L371 AbstractCegarLoop]: === Iteration 23 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:28,576 INFO L82 PathProgramCache]: Analyzing trace with hash 667629344, now seen corresponding path program 8 times [2018-01-24 16:57:28,576 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:28,576 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:28,577 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:57:28,577 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:28,577 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:28,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:28,596 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:28,733 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:28,733 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:28,733 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:28,733 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:57:28,733 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:57:28,734 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:28,734 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:28,739 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:57:28,739 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:57:28,753 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:28,768 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:28,770 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:28,773 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:28,853 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:28,853 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:29,126 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:29,147 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:29,147 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:29,150 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:57:29,151 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:57:29,173 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:29,215 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:57:29,238 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:29,243 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:29,250 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:29,250 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:29,306 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:29,308 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:57:29,308 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 44 [2018-01-24 16:57:29,308 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:57:29,308 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 16:57:29,308 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 16:57:29,309 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=669, Invalid=1223, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 16:57:29,309 INFO L87 Difference]: Start difference. First operand 95 states and 99 transitions. Second operand 30 states. [2018-01-24 16:57:29,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:57:29,373 INFO L93 Difference]: Finished difference Result 168 states and 176 transitions. [2018-01-24 16:57:29,373 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 16:57:29,373 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 90 [2018-01-24 16:57:29,373 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:57:29,374 INFO L225 Difference]: With dead ends: 168 [2018-01-24 16:57:29,374 INFO L226 Difference]: Without dead ends: 96 [2018-01-24 16:57:29,374 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 375 GetRequests, 330 SyntacticMatches, 2 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 754 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=700, Invalid=1280, Unknown=0, NotChecked=0, Total=1980 [2018-01-24 16:57:29,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-01-24 16:57:29,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 96. [2018-01-24 16:57:29,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-01-24 16:57:29,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 100 transitions. [2018-01-24 16:57:29,382 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 100 transitions. Word has length 90 [2018-01-24 16:57:29,382 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:57:29,382 INFO L432 AbstractCegarLoop]: Abstraction has 96 states and 100 transitions. [2018-01-24 16:57:29,382 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 16:57:29,383 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 100 transitions. [2018-01-24 16:57:29,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-01-24 16:57:29,383 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:57:29,383 INFO L322 BasicCegarLoop]: trace histogram [13, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:57:29,383 INFO L371 AbstractCegarLoop]: === Iteration 24 === [Sum2Err2RequiresViolation, Sum2Err0RequiresViolation, Sum2Err1RequiresViolation, Sum2Err3RequiresViolation, SumErr2RequiresViolation, SumErr3RequiresViolation, SumErr1RequiresViolation, SumErr0RequiresViolation, mainErr5RequiresViolation, mainErr13RequiresViolation, mainErr1RequiresViolation, mainErr16EnsuresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr15RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr12RequiresViolation, mainErr6RequiresViolation, mainErr14RequiresViolation]=== [2018-01-24 16:57:29,383 INFO L82 PathProgramCache]: Analyzing trace with hash 754375859, now seen corresponding path program 9 times [2018-01-24 16:57:29,383 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:57:29,384 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:29,384 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:57:29,384 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:57:29,384 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:57:29,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:57:29,403 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:57:29,656 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:29,656 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:29,656 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:57:29,656 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:57:29,656 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:57:29,657 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:29,657 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:57:29,666 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:57:29,667 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:57:29,685 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:29,699 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:29,716 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:29,732 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:29,763 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:29,799 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:29,981 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:30,073 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:30,075 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:57:30,078 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:57:30,455 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:30,455 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:57:30,811 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 16:57:30,844 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:57:30,844 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:57:30,847 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:57:30,848 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:57:30,875 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:30,906 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:30,979 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:31,138 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:57:43,153 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command Received shutdown request... [2018-01-24 16:57:55,202 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command Cannot interrupt operation gracefully because timeout expired. Forcing shutdown