java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf -i ../../../trunk/examples/svcomp/memsafety/960521-1_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 16:55:00,111 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 16:55:00,113 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 16:55:00,126 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 16:55:00,126 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 16:55:00,127 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 16:55:00,128 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 16:55:00,130 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 16:55:00,132 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 16:55:00,133 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 16:55:00,134 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 16:55:00,134 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 16:55:00,135 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 16:55:00,137 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 16:55:00,138 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 16:55:00,140 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 16:55:00,142 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 16:55:00,144 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 16:55:00,145 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 16:55:00,146 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 16:55:00,149 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 16:55:00,149 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 16:55:00,149 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 16:55:00,150 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 16:55:00,151 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 16:55:00,152 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 16:55:00,153 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 16:55:00,153 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 16:55:00,154 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 16:55:00,154 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 16:55:00,155 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 16:55:00,155 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf [2018-01-24 16:55:00,165 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 16:55:00,165 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 16:55:00,166 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 16:55:00,166 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 16:55:00,166 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 16:55:00,167 INFO L133 SettingsManager]: * Deactivate Weak Equivalences=true [2018-01-24 16:55:00,167 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 16:55:00,167 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 16:55:00,168 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 16:55:00,168 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 16:55:00,168 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 16:55:00,168 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 16:55:00,169 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 16:55:00,169 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 16:55:00,169 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 16:55:00,169 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 16:55:00,169 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 16:55:00,170 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 16:55:00,170 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 16:55:00,170 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 16:55:00,170 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 16:55:00,170 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 16:55:00,171 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 16:55:00,171 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 16:55:00,171 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 16:55:00,171 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 16:55:00,171 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 16:55:00,172 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 16:55:00,172 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 16:55:00,172 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 16:55:00,172 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 16:55:00,172 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 16:55:00,173 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 16:55:00,173 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 16:55:00,174 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 16:55:00,174 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 16:55:00,207 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 16:55:00,216 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 16:55:00,219 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 16:55:00,220 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 16:55:00,220 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 16:55:00,221 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/memsafety/960521-1_false-valid-deref.i [2018-01-24 16:55:00,374 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 16:55:00,381 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 16:55:00,381 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 16:55:00,381 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 16:55:00,387 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 16:55:00,388 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 04:55:00" (1/1) ... [2018-01-24 16:55:00,390 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7ef7ce9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:55:00, skipping insertion in model container [2018-01-24 16:55:00,390 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 04:55:00" (1/1) ... [2018-01-24 16:55:00,409 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 16:55:00,450 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 16:55:00,569 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 16:55:00,584 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 16:55:00,590 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:55:00 WrapperNode [2018-01-24 16:55:00,590 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 16:55:00,591 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 16:55:00,591 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 16:55:00,591 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 16:55:00,606 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:55:00" (1/1) ... [2018-01-24 16:55:00,606 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:55:00" (1/1) ... [2018-01-24 16:55:00,616 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:55:00" (1/1) ... [2018-01-24 16:55:00,617 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:55:00" (1/1) ... [2018-01-24 16:55:00,621 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:55:00" (1/1) ... [2018-01-24 16:55:00,624 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:55:00" (1/1) ... [2018-01-24 16:55:00,625 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:55:00" (1/1) ... [2018-01-24 16:55:00,626 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 16:55:00,627 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 16:55:00,627 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 16:55:00,627 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 16:55:00,628 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:55:00" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 16:55:00,679 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 16:55:00,679 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 16:55:00,679 INFO L136 BoogieDeclarations]: Found implementation of procedure foo [2018-01-24 16:55:00,679 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 16:55:00,679 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 16:55:00,679 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 16:55:00,679 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 16:55:00,679 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 16:55:00,680 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 16:55:00,680 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-01-24 16:55:00,680 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-01-24 16:55:00,680 INFO L128 BoogieDeclarations]: Found specification of procedure foo [2018-01-24 16:55:00,680 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 16:55:00,680 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 16:55:00,680 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 16:55:00,926 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 16:55:00,927 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 04:55:00 BoogieIcfgContainer [2018-01-24 16:55:00,928 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 16:55:00,928 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 16:55:00,928 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 16:55:00,930 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 16:55:00,930 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 04:55:00" (1/3) ... [2018-01-24 16:55:00,931 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5c157966 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 04:55:00, skipping insertion in model container [2018-01-24 16:55:00,931 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:55:00" (2/3) ... [2018-01-24 16:55:00,932 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5c157966 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 04:55:00, skipping insertion in model container [2018-01-24 16:55:00,932 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 04:55:00" (3/3) ... [2018-01-24 16:55:00,934 INFO L105 eAbstractionObserver]: Analyzing ICFG 960521-1_false-valid-deref.i [2018-01-24 16:55:00,940 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 16:55:00,946 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 17 error locations. [2018-01-24 16:55:00,981 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 16:55:00,981 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 16:55:00,981 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 16:55:00,981 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 16:55:00,981 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 16:55:00,981 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 16:55:00,982 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 16:55:00,982 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 16:55:00,983 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 16:55:01,004 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states. [2018-01-24 16:55:01,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-01-24 16:55:01,011 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:01,012 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:01,012 INFO L371 AbstractCegarLoop]: === Iteration 1 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:01,016 INFO L82 PathProgramCache]: Analyzing trace with hash 1993989713, now seen corresponding path program 1 times [2018-01-24 16:55:01,017 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:01,058 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:01,059 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:01,059 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:01,059 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:01,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:01,122 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:01,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:01,212 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:55:01,212 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 16:55:01,212 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:55:01,215 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 16:55:01,230 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 16:55:01,231 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 16:55:01,233 INFO L87 Difference]: Start difference. First operand 53 states. Second operand 4 states. [2018-01-24 16:55:01,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:01,499 INFO L93 Difference]: Finished difference Result 84 states and 90 transitions. [2018-01-24 16:55:01,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 16:55:01,501 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2018-01-24 16:55:01,501 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:01,512 INFO L225 Difference]: With dead ends: 84 [2018-01-24 16:55:01,512 INFO L226 Difference]: Without dead ends: 49 [2018-01-24 16:55:01,516 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 16:55:01,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-01-24 16:55:01,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2018-01-24 16:55:01,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-01-24 16:55:01,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 51 transitions. [2018-01-24 16:55:01,545 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 51 transitions. Word has length 11 [2018-01-24 16:55:01,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:01,546 INFO L432 AbstractCegarLoop]: Abstraction has 49 states and 51 transitions. [2018-01-24 16:55:01,546 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 16:55:01,546 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 51 transitions. [2018-01-24 16:55:01,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-01-24 16:55:01,546 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:01,546 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:01,546 INFO L371 AbstractCegarLoop]: === Iteration 2 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:01,547 INFO L82 PathProgramCache]: Analyzing trace with hash 1993989714, now seen corresponding path program 1 times [2018-01-24 16:55:01,547 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:01,548 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:01,548 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:01,548 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:01,548 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:01,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:01,570 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:01,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:01,643 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:55:01,643 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 16:55:01,643 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:55:01,645 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 16:55:01,645 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 16:55:01,645 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 16:55:01,646 INFO L87 Difference]: Start difference. First operand 49 states and 51 transitions. Second operand 5 states. [2018-01-24 16:55:01,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:01,755 INFO L93 Difference]: Finished difference Result 49 states and 51 transitions. [2018-01-24 16:55:01,755 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 16:55:01,755 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 11 [2018-01-24 16:55:01,756 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:01,757 INFO L225 Difference]: With dead ends: 49 [2018-01-24 16:55:01,757 INFO L226 Difference]: Without dead ends: 48 [2018-01-24 16:55:01,758 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-01-24 16:55:01,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-01-24 16:55:01,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2018-01-24 16:55:01,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-01-24 16:55:01,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 50 transitions. [2018-01-24 16:55:01,765 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 50 transitions. Word has length 11 [2018-01-24 16:55:01,765 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:01,765 INFO L432 AbstractCegarLoop]: Abstraction has 48 states and 50 transitions. [2018-01-24 16:55:01,766 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 16:55:01,766 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 50 transitions. [2018-01-24 16:55:01,766 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 16:55:01,766 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:01,767 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:01,767 INFO L371 AbstractCegarLoop]: === Iteration 3 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:01,767 INFO L82 PathProgramCache]: Analyzing trace with hash -1188525484, now seen corresponding path program 1 times [2018-01-24 16:55:01,767 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:01,768 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:01,768 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:01,769 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:01,769 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:01,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:01,787 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:01,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:01,848 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:55:01,848 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 16:55:01,848 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:55:01,849 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 16:55:01,849 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 16:55:01,849 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 16:55:01,849 INFO L87 Difference]: Start difference. First operand 48 states and 50 transitions. Second operand 6 states. [2018-01-24 16:55:01,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:01,955 INFO L93 Difference]: Finished difference Result 48 states and 50 transitions. [2018-01-24 16:55:01,955 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 16:55:01,955 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-01-24 16:55:01,955 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:01,956 INFO L225 Difference]: With dead ends: 48 [2018-01-24 16:55:01,956 INFO L226 Difference]: Without dead ends: 45 [2018-01-24 16:55:01,956 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-01-24 16:55:01,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-01-24 16:55:01,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-01-24 16:55:01,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-01-24 16:55:01,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 47 transitions. [2018-01-24 16:55:01,963 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 47 transitions. Word has length 17 [2018-01-24 16:55:01,963 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:01,963 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 47 transitions. [2018-01-24 16:55:01,963 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 16:55:01,963 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 47 transitions. [2018-01-24 16:55:01,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 16:55:01,964 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:01,964 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:01,965 INFO L371 AbstractCegarLoop]: === Iteration 4 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:01,965 INFO L82 PathProgramCache]: Analyzing trace with hash -1188525483, now seen corresponding path program 1 times [2018-01-24 16:55:01,965 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:01,966 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:01,966 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:01,966 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:01,966 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:01,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:01,986 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:02,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:02,159 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:55:02,159 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 16:55:02,160 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:55:02,160 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 16:55:02,160 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 16:55:02,160 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 16:55:02,160 INFO L87 Difference]: Start difference. First operand 45 states and 47 transitions. Second operand 7 states. [2018-01-24 16:55:02,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:02,282 INFO L93 Difference]: Finished difference Result 80 states and 87 transitions. [2018-01-24 16:55:02,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 16:55:02,283 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 17 [2018-01-24 16:55:02,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:02,284 INFO L225 Difference]: With dead ends: 80 [2018-01-24 16:55:02,284 INFO L226 Difference]: Without dead ends: 53 [2018-01-24 16:55:02,285 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-01-24 16:55:02,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-01-24 16:55:02,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 48. [2018-01-24 16:55:02,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-01-24 16:55:02,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 50 transitions. [2018-01-24 16:55:02,292 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 50 transitions. Word has length 17 [2018-01-24 16:55:02,293 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:02,293 INFO L432 AbstractCegarLoop]: Abstraction has 48 states and 50 transitions. [2018-01-24 16:55:02,293 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 16:55:02,293 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 50 transitions. [2018-01-24 16:55:02,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-01-24 16:55:02,294 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:02,294 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:02,294 INFO L371 AbstractCegarLoop]: === Iteration 5 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:02,294 INFO L82 PathProgramCache]: Analyzing trace with hash -2106816852, now seen corresponding path program 1 times [2018-01-24 16:55:02,295 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:02,296 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:02,296 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:02,296 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:02,296 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:02,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:02,315 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:02,505 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:02,505 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:02,505 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:02,506 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 22 with the following transitions: [2018-01-24 16:55:02,508 INFO L201 CegarAbsIntRunner]: [0], [1], [2], [6], [11], [12], [14], [16], [42], [43], [44], [45], [46], [47], [50], [76], [77], [78], [80] [2018-01-24 16:55:02,558 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 16:55:02,558 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 16:55:02,743 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 16:55:02,744 INFO L268 AbstractInterpreter]: Visited 19 different actions 24 times. Merged at 5 different actions 5 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 26 variables. [2018-01-24 16:55:02,764 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 16:55:02,764 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:02,765 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:02,770 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:02,770 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:55:02,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:02,805 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:02,838 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:55:02,839 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:02,844 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:02,844 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:15, output treesize:14 [2018-01-24 16:55:02,865 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-01-24 16:55:02,866 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:02,878 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 16:55:02,878 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:22, output treesize:21 [2018-01-24 16:55:02,999 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:02,999 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:03,432 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 16:55:03,447 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-01-24 16:55:03,447 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:03,449 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:03,451 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:03,451 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:15, output treesize:5 [2018-01-24 16:55:03,489 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:03,518 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:03,518 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:03,522 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:03,522 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:55:03,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:03,560 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:03,565 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:55:03,565 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:03,574 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 16:55:03,574 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:03,579 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:03,579 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-01-24 16:55:03,626 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:55:03,627 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 16:55:03,627 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:03,672 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:55:03,673 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:55:03,674 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 16:55:03,674 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:03,692 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 16:55:03,692 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:32, output treesize:25 [2018-01-24 16:55:03,848 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:03,848 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:03,968 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-01-24 16:55:03,969 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:03,972 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 16:55:03,983 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 1 [2018-01-24 16:55:03,983 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:03,985 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:03,987 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:03,988 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:25, output treesize:5 [2018-01-24 16:55:03,992 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:03,993 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:03,993 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8, 7, 7, 7] total 24 [2018-01-24 16:55:03,993 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:03,994 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 16:55:03,994 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 16:55:03,994 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=477, Unknown=1, NotChecked=0, Total=600 [2018-01-24 16:55:03,995 INFO L87 Difference]: Start difference. First operand 48 states and 50 transitions. Second operand 12 states. [2018-01-24 16:55:04,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:04,264 INFO L93 Difference]: Finished difference Result 90 states and 95 transitions. [2018-01-24 16:55:04,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 16:55:04,264 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 21 [2018-01-24 16:55:04,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:04,265 INFO L225 Difference]: With dead ends: 90 [2018-01-24 16:55:04,265 INFO L226 Difference]: Without dead ends: 63 [2018-01-24 16:55:04,266 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 64 SyntacticMatches, 4 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 232 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=162, Invalid=593, Unknown=1, NotChecked=0, Total=756 [2018-01-24 16:55:04,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-01-24 16:55:04,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 56. [2018-01-24 16:55:04,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2018-01-24 16:55:04,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 60 transitions. [2018-01-24 16:55:04,272 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 60 transitions. Word has length 21 [2018-01-24 16:55:04,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:04,272 INFO L432 AbstractCegarLoop]: Abstraction has 56 states and 60 transitions. [2018-01-24 16:55:04,272 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 16:55:04,272 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 60 transitions. [2018-01-24 16:55:04,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-24 16:55:04,273 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:04,273 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:04,273 INFO L371 AbstractCegarLoop]: === Iteration 6 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:04,273 INFO L82 PathProgramCache]: Analyzing trace with hash -702775421, now seen corresponding path program 2 times [2018-01-24 16:55:04,273 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:04,274 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:04,274 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:04,274 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:04,274 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:04,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:04,289 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:04,485 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:04,485 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:04,486 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:04,486 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:04,486 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:04,486 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:04,486 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:04,491 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:55:04,491 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:55:04,507 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:04,512 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:04,514 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:04,516 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:04,520 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 16:55:04,521 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:04,527 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:55:04,527 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:04,533 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:04,533 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-01-24 16:55:04,567 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:55:04,568 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:55:04,568 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 16:55:04,568 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:04,580 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 16:55:04,580 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:04,586 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 16:55:04,586 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:32, output treesize:25 [2018-01-24 16:55:04,873 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:04,873 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:05,016 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-01-24 16:55:05,016 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,020 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 16:55:05,031 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 1 [2018-01-24 16:55:05,031 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,032 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,034 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,035 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:25, output treesize:5 [2018-01-24 16:55:05,055 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:05,076 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:05,076 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:05,079 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:55:05,079 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:55:05,101 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:05,135 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:05,147 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:05,151 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:05,159 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:55:05,160 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,180 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 16:55:05,180 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,197 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,197 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-01-24 16:55:05,208 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:55:05,209 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 16:55:05,209 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,221 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:55:05,222 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:55:05,223 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 16:55:05,223 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,233 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 16:55:05,234 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:32, output treesize:25 [2018-01-24 16:55:05,278 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:05,278 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:05,346 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-01-24 16:55:05,346 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,350 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 16:55:05,361 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-01-24 16:55:05,361 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,362 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,365 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:05,365 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:25, output treesize:5 [2018-01-24 16:55:05,371 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:05,372 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:05,372 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8, 8, 8] total 23 [2018-01-24 16:55:05,373 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:05,373 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 16:55:05,373 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 16:55:05,374 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=442, Unknown=0, NotChecked=0, Total=552 [2018-01-24 16:55:05,374 INFO L87 Difference]: Start difference. First operand 56 states and 60 transitions. Second operand 17 states. [2018-01-24 16:55:05,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:05,895 INFO L93 Difference]: Finished difference Result 104 states and 111 transitions. [2018-01-24 16:55:05,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 16:55:05,895 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 25 [2018-01-24 16:55:05,896 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:05,896 INFO L225 Difference]: With dead ends: 104 [2018-01-24 16:55:05,896 INFO L226 Difference]: Without dead ends: 73 [2018-01-24 16:55:05,897 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 83 SyntacticMatches, 3 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 257 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=208, Invalid=722, Unknown=0, NotChecked=0, Total=930 [2018-01-24 16:55:05,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-01-24 16:55:05,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 64. [2018-01-24 16:55:05,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-01-24 16:55:05,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 70 transitions. [2018-01-24 16:55:05,906 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 70 transitions. Word has length 25 [2018-01-24 16:55:05,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:05,906 INFO L432 AbstractCegarLoop]: Abstraction has 64 states and 70 transitions. [2018-01-24 16:55:05,906 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 16:55:05,907 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 70 transitions. [2018-01-24 16:55:05,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-01-24 16:55:05,907 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:05,908 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:05,908 INFO L371 AbstractCegarLoop]: === Iteration 7 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:05,908 INFO L82 PathProgramCache]: Analyzing trace with hash 1827026138, now seen corresponding path program 3 times [2018-01-24 16:55:05,908 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:05,909 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:05,909 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:55:05,909 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:05,909 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:05,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:05,925 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:06,136 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:06,136 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:06,136 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:06,136 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:06,136 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:06,136 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:06,137 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:06,142 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:55:06,142 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:55:06,153 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:06,156 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:06,157 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:06,158 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:06,163 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:55:06,164 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:06,173 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 16:55:06,173 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:06,177 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:06,177 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-01-24 16:55:06,207 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:55:06,208 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:55:06,208 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 16:55:06,208 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:06,215 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 16:55:06,216 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:06,221 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:06,221 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:29, output treesize:22 [2018-01-24 16:55:06,338 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 16:55:06,338 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:07,108 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 16:55:07,128 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:07,128 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:07,131 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:55:07,131 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:55:07,148 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:07,176 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:07,187 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:07,191 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:07,195 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 16:55:07,195 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:07,200 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:55:07,200 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:07,203 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:07,203 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-01-24 16:55:07,243 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:55:07,252 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:55:07,253 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 16:55:07,253 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:07,259 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 16:55:07,259 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:07,264 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 16:55:07,265 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:29, output treesize:22 [2018-01-24 16:55:07,424 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 16:55:07,424 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:07,592 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 16:55:07,594 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:07,594 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 7, 7, 7] total 29 [2018-01-24 16:55:07,594 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:07,595 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 16:55:07,595 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 16:55:07,595 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=730, Unknown=0, NotChecked=0, Total=870 [2018-01-24 16:55:07,596 INFO L87 Difference]: Start difference. First operand 64 states and 70 transitions. Second operand 18 states. [2018-01-24 16:55:08,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:08,416 INFO L93 Difference]: Finished difference Result 125 states and 137 transitions. [2018-01-24 16:55:08,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 16:55:08,417 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2018-01-24 16:55:08,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:08,419 INFO L225 Difference]: With dead ends: 125 [2018-01-24 16:55:08,419 INFO L226 Difference]: Without dead ends: 90 [2018-01-24 16:55:08,420 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 92 SyntacticMatches, 5 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 461 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=338, Invalid=1302, Unknown=0, NotChecked=0, Total=1640 [2018-01-24 16:55:08,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-01-24 16:55:08,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 70. [2018-01-24 16:55:08,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-24 16:55:08,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 76 transitions. [2018-01-24 16:55:08,432 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 76 transitions. Word has length 29 [2018-01-24 16:55:08,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:08,432 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 76 transitions. [2018-01-24 16:55:08,432 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 16:55:08,432 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 76 transitions. [2018-01-24 16:55:08,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-01-24 16:55:08,433 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:08,433 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:08,433 INFO L371 AbstractCegarLoop]: === Iteration 8 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:08,433 INFO L82 PathProgramCache]: Analyzing trace with hash -645884181, now seen corresponding path program 1 times [2018-01-24 16:55:08,433 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:08,434 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:08,434 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:55:08,434 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:08,434 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:08,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:08,449 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:08,574 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:08,575 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:08,575 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:08,575 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 41 with the following transitions: [2018-01-24 16:55:08,575 INFO L201 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [12], [16], [20], [24], [29], [32], [42], [43], [44], [45], [46], [47], [50], [76], [77], [78], [80] [2018-01-24 16:55:08,577 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 16:55:08,577 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 16:55:08,691 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 16:55:08,691 INFO L268 AbstractInterpreter]: Visited 23 different actions 32 times. Merged at 9 different actions 9 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 26 variables. [2018-01-24 16:55:08,693 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 16:55:08,693 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:08,693 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:08,700 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:08,700 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:55:08,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:08,728 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:08,864 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:08,864 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:09,063 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:09,096 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:09,096 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:09,101 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:09,102 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:55:09,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:09,159 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:09,167 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:09,168 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:09,179 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:09,181 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:09,182 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 22 [2018-01-24 16:55:09,182 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:09,182 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 16:55:09,183 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 16:55:09,183 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=199, Invalid=263, Unknown=0, NotChecked=0, Total=462 [2018-01-24 16:55:09,183 INFO L87 Difference]: Start difference. First operand 70 states and 76 transitions. Second operand 15 states. [2018-01-24 16:55:09,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:09,300 INFO L93 Difference]: Finished difference Result 136 states and 147 transitions. [2018-01-24 16:55:09,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 16:55:09,300 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 40 [2018-01-24 16:55:09,300 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:09,301 INFO L225 Difference]: With dead ends: 136 [2018-01-24 16:55:09,301 INFO L226 Difference]: Without dead ends: 102 [2018-01-24 16:55:09,301 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 167 GetRequests, 147 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 164 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=199, Invalid=263, Unknown=0, NotChecked=0, Total=462 [2018-01-24 16:55:09,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-01-24 16:55:09,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 86. [2018-01-24 16:55:09,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-01-24 16:55:09,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 98 transitions. [2018-01-24 16:55:09,315 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 98 transitions. Word has length 40 [2018-01-24 16:55:09,315 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:09,315 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 98 transitions. [2018-01-24 16:55:09,315 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 16:55:09,316 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 98 transitions. [2018-01-24 16:55:09,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-24 16:55:09,317 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:09,317 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:09,317 INFO L371 AbstractCegarLoop]: === Iteration 9 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:09,317 INFO L82 PathProgramCache]: Analyzing trace with hash -2113361740, now seen corresponding path program 2 times [2018-01-24 16:55:09,317 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:09,318 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:09,318 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:09,318 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:09,319 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:09,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:09,333 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:09,450 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:09,450 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:09,451 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:09,451 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:09,451 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:09,451 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:09,451 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:09,459 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:55:09,459 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:55:09,476 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:09,479 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:09,482 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:09,496 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:55:09,496 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:09,501 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 16:55:09,501 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:15, output treesize:14 [2018-01-24 16:55:09,613 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:55:09,613 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:09,836 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:55:09,856 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 16:55:09,856 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [10] total 20 [2018-01-24 16:55:09,856 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:55:09,856 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 16:55:09,857 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 16:55:09,857 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=305, Unknown=0, NotChecked=0, Total=380 [2018-01-24 16:55:09,857 INFO L87 Difference]: Start difference. First operand 86 states and 98 transitions. Second operand 8 states. [2018-01-24 16:55:10,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:10,063 INFO L93 Difference]: Finished difference Result 86 states and 98 transitions. [2018-01-24 16:55:10,094 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 16:55:10,094 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 44 [2018-01-24 16:55:10,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:10,095 INFO L225 Difference]: With dead ends: 86 [2018-01-24 16:55:10,095 INFO L226 Difference]: Without dead ends: 73 [2018-01-24 16:55:10,096 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 120 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=138, Invalid=564, Unknown=0, NotChecked=0, Total=702 [2018-01-24 16:55:10,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-01-24 16:55:10,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2018-01-24 16:55:10,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-01-24 16:55:10,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 79 transitions. [2018-01-24 16:55:10,111 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 79 transitions. Word has length 44 [2018-01-24 16:55:10,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:10,112 INFO L432 AbstractCegarLoop]: Abstraction has 73 states and 79 transitions. [2018-01-24 16:55:10,112 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 16:55:10,112 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 79 transitions. [2018-01-24 16:55:10,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-24 16:55:10,113 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:10,113 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:10,113 INFO L371 AbstractCegarLoop]: === Iteration 10 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:10,113 INFO L82 PathProgramCache]: Analyzing trace with hash -2113361741, now seen corresponding path program 1 times [2018-01-24 16:55:10,114 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:10,114 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:10,115 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:55:10,115 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:10,115 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:10,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:10,126 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:10,175 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:55:10,176 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:55:10,176 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 16:55:10,176 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:55:10,176 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 16:55:10,176 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 16:55:10,176 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 16:55:10,177 INFO L87 Difference]: Start difference. First operand 73 states and 79 transitions. Second operand 4 states. [2018-01-24 16:55:10,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:10,216 INFO L93 Difference]: Finished difference Result 73 states and 79 transitions. [2018-01-24 16:55:10,216 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 16:55:10,216 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 44 [2018-01-24 16:55:10,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:10,218 INFO L225 Difference]: With dead ends: 73 [2018-01-24 16:55:10,218 INFO L226 Difference]: Without dead ends: 71 [2018-01-24 16:55:10,218 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 16:55:10,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-01-24 16:55:10,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2018-01-24 16:55:10,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-01-24 16:55:10,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 72 transitions. [2018-01-24 16:55:10,231 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 72 transitions. Word has length 44 [2018-01-24 16:55:10,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:10,231 INFO L432 AbstractCegarLoop]: Abstraction has 71 states and 72 transitions. [2018-01-24 16:55:10,231 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 16:55:10,231 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 72 transitions. [2018-01-24 16:55:10,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-01-24 16:55:10,233 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:10,233 INFO L322 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:10,233 INFO L371 AbstractCegarLoop]: === Iteration 11 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:10,233 INFO L82 PathProgramCache]: Analyzing trace with hash -747893621, now seen corresponding path program 1 times [2018-01-24 16:55:10,233 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:10,234 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:10,234 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:10,234 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:10,235 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:10,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:10,253 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:10,427 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:55:10,427 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:10,427 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:10,427 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 71 with the following transitions: [2018-01-24 16:55:10,428 INFO L201 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [12], [16], [20], [24], [27], [29], [30], [34], [38], [42], [43], [44], [45], [46], [47], [50], [54], [76], [77], [78], [80], [81] [2018-01-24 16:55:10,429 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 16:55:10,430 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 16:55:10,546 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 16:55:10,546 INFO L268 AbstractInterpreter]: Visited 28 different actions 42 times. Merged at 13 different actions 13 times. Never widened. Found 3 fixpoints after 3 different actions. Largest state had 26 variables. [2018-01-24 16:55:10,548 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 16:55:10,548 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:10,548 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:10,557 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:10,557 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:55:10,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:10,592 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:10,750 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:55:10,750 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:10,909 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:55:10,931 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:10,931 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:10,934 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:10,934 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:55:10,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:10,980 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:10,990 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:55:10,990 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:11,056 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:55:11,058 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:11,059 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 11, 10, 11] total 26 [2018-01-24 16:55:11,059 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:11,059 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 16:55:11,060 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 16:55:11,060 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=238, Invalid=412, Unknown=0, NotChecked=0, Total=650 [2018-01-24 16:55:11,060 INFO L87 Difference]: Start difference. First operand 71 states and 72 transitions. Second operand 18 states. [2018-01-24 16:55:11,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:11,232 INFO L93 Difference]: Finished difference Result 114 states and 117 transitions. [2018-01-24 16:55:11,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 16:55:11,232 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 70 [2018-01-24 16:55:11,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:11,233 INFO L225 Difference]: With dead ends: 114 [2018-01-24 16:55:11,233 INFO L226 Difference]: Without dead ends: 83 [2018-01-24 16:55:11,234 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 290 GetRequests, 261 SyntacticMatches, 4 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 227 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=263, Invalid=439, Unknown=0, NotChecked=0, Total=702 [2018-01-24 16:55:11,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-01-24 16:55:11,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 79. [2018-01-24 16:55:11,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-01-24 16:55:11,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 80 transitions. [2018-01-24 16:55:11,247 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 80 transitions. Word has length 70 [2018-01-24 16:55:11,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:11,248 INFO L432 AbstractCegarLoop]: Abstraction has 79 states and 80 transitions. [2018-01-24 16:55:11,248 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 16:55:11,248 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 80 transitions. [2018-01-24 16:55:11,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-24 16:55:11,250 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:11,250 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:11,250 INFO L371 AbstractCegarLoop]: === Iteration 12 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:11,250 INFO L82 PathProgramCache]: Analyzing trace with hash 1885472427, now seen corresponding path program 2 times [2018-01-24 16:55:11,250 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:11,251 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:11,251 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:11,251 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:11,251 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:11,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:11,271 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:11,422 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 16:55:11,422 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:11,422 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:11,422 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:11,422 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:11,422 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:11,422 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:11,432 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:55:11,432 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:55:11,447 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:11,459 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:11,461 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:11,464 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:11,567 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 16:55:11,567 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:11,711 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 16:55:11,731 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:11,731 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:11,734 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:55:11,734 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:55:11,753 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:11,793 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:11,811 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:11,815 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:11,825 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 16:55:11,825 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:11,884 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 16:55:11,886 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:11,886 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 12, 11, 12] total 29 [2018-01-24 16:55:11,886 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:11,887 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 16:55:11,887 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 16:55:11,887 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=299, Invalid=513, Unknown=0, NotChecked=0, Total=812 [2018-01-24 16:55:11,887 INFO L87 Difference]: Start difference. First operand 79 states and 80 transitions. Second operand 20 states. [2018-01-24 16:55:12,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:12,008 INFO L93 Difference]: Finished difference Result 126 states and 129 transitions. [2018-01-24 16:55:12,008 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 16:55:12,008 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 78 [2018-01-24 16:55:12,008 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:12,009 INFO L225 Difference]: With dead ends: 126 [2018-01-24 16:55:12,009 INFO L226 Difference]: Without dead ends: 91 [2018-01-24 16:55:12,009 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 323 GetRequests, 291 SyntacticMatches, 4 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 296 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=327, Invalid=543, Unknown=0, NotChecked=0, Total=870 [2018-01-24 16:55:12,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-01-24 16:55:12,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 87. [2018-01-24 16:55:12,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-01-24 16:55:12,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 88 transitions. [2018-01-24 16:55:12,018 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 88 transitions. Word has length 78 [2018-01-24 16:55:12,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:12,018 INFO L432 AbstractCegarLoop]: Abstraction has 87 states and 88 transitions. [2018-01-24 16:55:12,018 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 16:55:12,018 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 88 transitions. [2018-01-24 16:55:12,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-01-24 16:55:12,019 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:12,019 INFO L322 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:12,019 INFO L371 AbstractCegarLoop]: === Iteration 13 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:12,019 INFO L82 PathProgramCache]: Analyzing trace with hash 2069780427, now seen corresponding path program 3 times [2018-01-24 16:55:12,019 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:12,020 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:12,020 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:55:12,020 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:12,020 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:12,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:12,039 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:12,170 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 16:55:12,171 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:12,171 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:12,171 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:12,171 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:12,171 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:12,171 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:12,177 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:55:12,177 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:55:12,190 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,193 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,196 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,200 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,205 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,214 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,229 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,250 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,267 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,268 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:12,270 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:12,398 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 16:55:12,398 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:12,672 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 158 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 16:55:12,693 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:12,693 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:12,696 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:55:12,696 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:55:12,713 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,742 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,775 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,813 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,863 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:12,925 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:13,014 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:13,133 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:13,259 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:13,277 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:13,282 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:13,292 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 16:55:13,292 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:13,352 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 16:55:13,354 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:13,354 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14, 15, 12, 13] total 36 [2018-01-24 16:55:13,354 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:13,354 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 16:55:13,355 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 16:55:13,355 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=418, Invalid=842, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 16:55:13,355 INFO L87 Difference]: Start difference. First operand 87 states and 88 transitions. Second operand 24 states. [2018-01-24 16:55:13,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:13,533 INFO L93 Difference]: Finished difference Result 138 states and 141 transitions. [2018-01-24 16:55:13,533 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 16:55:13,533 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 86 [2018-01-24 16:55:13,534 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:13,534 INFO L225 Difference]: With dead ends: 138 [2018-01-24 16:55:13,534 INFO L226 Difference]: Without dead ends: 99 [2018-01-24 16:55:13,535 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 317 SyntacticMatches, 4 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 498 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=457, Invalid=949, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 16:55:13,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-01-24 16:55:13,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 95. [2018-01-24 16:55:13,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-01-24 16:55:13,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 96 transitions. [2018-01-24 16:55:13,545 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 96 transitions. Word has length 86 [2018-01-24 16:55:13,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:13,545 INFO L432 AbstractCegarLoop]: Abstraction has 95 states and 96 transitions. [2018-01-24 16:55:13,545 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 16:55:13,545 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 96 transitions. [2018-01-24 16:55:13,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-01-24 16:55:13,546 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:13,547 INFO L322 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:13,547 INFO L371 AbstractCegarLoop]: === Iteration 14 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:13,547 INFO L82 PathProgramCache]: Analyzing trace with hash 67534827, now seen corresponding path program 4 times [2018-01-24 16:55:13,547 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:13,548 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:13,548 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:55:13,548 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:13,548 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:13,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:13,567 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:13,732 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 162 trivial. 0 not checked. [2018-01-24 16:55:13,732 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:13,732 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:13,733 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:13,733 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:13,733 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:13,733 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:13,737 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 16:55:13,738 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 16:55:13,761 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:13,763 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:13,766 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:55:13,767 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:13,768 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:13,768 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:8, output treesize:7 [2018-01-24 16:55:14,091 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 162 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:14,091 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:14,427 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:14,498 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:14,527 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:14,565 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:55:14,728 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:55:15,018 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:15,054 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:15,098 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:15,272 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:55:15,326 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:15,328 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:15,329 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:15,832 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 162 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:15,852 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:15,852 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:15,856 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 16:55:15,856 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 16:55:15,926 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:15,931 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:15,935 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:55:15,936 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:15,939 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:15,939 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-01-24 16:55:15,992 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 162 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:15,992 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:16,170 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:16,199 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:16,230 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:16,260 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:55:16,566 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:55:16,616 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:16,618 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:16,620 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:16,622 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:55:16,909 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:16,911 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:16,913 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:17,042 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 162 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:17,044 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:17,044 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 25, 28, 24, 25] total 65 [2018-01-24 16:55:17,044 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:17,044 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-01-24 16:55:17,044 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-01-24 16:55:17,045 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=822, Invalid=3338, Unknown=0, NotChecked=0, Total=4160 [2018-01-24 16:55:17,045 INFO L87 Difference]: Start difference. First operand 95 states and 96 transitions. Second operand 37 states. [2018-01-24 16:55:17,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:17,703 INFO L93 Difference]: Finished difference Result 150 states and 153 transitions. [2018-01-24 16:55:17,703 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 16:55:17,703 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 94 [2018-01-24 16:55:17,703 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:17,704 INFO L225 Difference]: With dead ends: 150 [2018-01-24 16:55:17,704 INFO L226 Difference]: Without dead ends: 107 [2018-01-24 16:55:17,706 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 404 GetRequests, 291 SyntacticMatches, 35 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 2 DeprecatedPredicates, 4371 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=1218, Invalid=5102, Unknown=0, NotChecked=0, Total=6320 [2018-01-24 16:55:17,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-01-24 16:55:17,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 103. [2018-01-24 16:55:17,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-01-24 16:55:17,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 104 transitions. [2018-01-24 16:55:17,716 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 104 transitions. Word has length 94 [2018-01-24 16:55:17,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:17,716 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 104 transitions. [2018-01-24 16:55:17,716 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-01-24 16:55:17,716 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 104 transitions. [2018-01-24 16:55:17,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-24 16:55:17,717 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:17,717 INFO L322 BasicCegarLoop]: trace histogram [11, 11, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:17,717 INFO L371 AbstractCegarLoop]: === Iteration 15 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:17,718 INFO L82 PathProgramCache]: Analyzing trace with hash 306183947, now seen corresponding path program 5 times [2018-01-24 16:55:17,718 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:17,718 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:17,718 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:55:17,718 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:17,718 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:17,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:17,737 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:17,949 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 16:55:17,949 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:17,949 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:17,949 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:17,950 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:17,950 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:17,950 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:17,954 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 16:55:17,955 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:55:17,963 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:17,965 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:17,968 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:17,971 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:17,977 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:17,993 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:18,020 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:18,052 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:18,250 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:18,293 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:18,928 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:18,930 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:18,934 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:18,946 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 16:55:18,946 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:19,081 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 16:55:19,101 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:19,102 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:19,104 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 16:55:19,105 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:55:19,115 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:19,120 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:19,130 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:19,143 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:19,171 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:19,208 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:19,261 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:19,331 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:19,541 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:19,845 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:20,300 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:20,337 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:20,344 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:20,352 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 16:55:20,352 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:20,372 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 16:55:20,374 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:20,374 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 13, 13, 13, 13] total 27 [2018-01-24 16:55:20,374 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:20,375 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 16:55:20,375 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 16:55:20,375 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=304, Invalid=398, Unknown=0, NotChecked=0, Total=702 [2018-01-24 16:55:20,375 INFO L87 Difference]: Start difference. First operand 103 states and 104 transitions. Second operand 16 states. [2018-01-24 16:55:20,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:20,622 INFO L93 Difference]: Finished difference Result 162 states and 165 transitions. [2018-01-24 16:55:20,623 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 16:55:20,623 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 102 [2018-01-24 16:55:20,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:20,623 INFO L225 Difference]: With dead ends: 162 [2018-01-24 16:55:20,623 INFO L226 Difference]: Without dead ends: 115 [2018-01-24 16:55:20,624 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 443 GetRequests, 407 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 114 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=580, Invalid=826, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 16:55:20,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-01-24 16:55:20,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 111. [2018-01-24 16:55:20,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-01-24 16:55:20,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 112 transitions. [2018-01-24 16:55:20,636 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 112 transitions. Word has length 102 [2018-01-24 16:55:20,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:20,636 INFO L432 AbstractCegarLoop]: Abstraction has 111 states and 112 transitions. [2018-01-24 16:55:20,636 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 16:55:20,636 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 112 transitions. [2018-01-24 16:55:20,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-01-24 16:55:20,637 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:20,637 INFO L322 BasicCegarLoop]: trace histogram [12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:20,637 INFO L371 AbstractCegarLoop]: === Iteration 16 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:20,637 INFO L82 PathProgramCache]: Analyzing trace with hash -2043652821, now seen corresponding path program 6 times [2018-01-24 16:55:20,637 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:20,637 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:20,638 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:55:20,638 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:20,638 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:20,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:20,652 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:20,823 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 16:55:20,823 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:20,823 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:20,823 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:20,823 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:20,823 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:20,823 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:20,830 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 16:55:20,830 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 16:55:20,844 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:20,849 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:20,853 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:20,860 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:20,875 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:20,888 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:20,912 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:20,983 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,022 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,049 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,113 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,163 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,164 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:21,168 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:21,181 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 16:55:21,181 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:21,358 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 16:55:21,379 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:21,379 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:21,382 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 16:55:21,382 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 16:55:21,402 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,432 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,467 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,514 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,582 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,643 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,719 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,820 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:21,925 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:22,112 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:22,279 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:22,491 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:55:22,517 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:22,523 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:22,538 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 16:55:22,538 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:22,555 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 16:55:22,557 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:22,557 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 14, 14, 14, 14] total 29 [2018-01-24 16:55:22,557 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:22,558 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 16:55:22,558 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 16:55:22,558 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=355, Invalid=457, Unknown=0, NotChecked=0, Total=812 [2018-01-24 16:55:22,558 INFO L87 Difference]: Start difference. First operand 111 states and 112 transitions. Second operand 17 states. [2018-01-24 16:55:22,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:22,722 INFO L93 Difference]: Finished difference Result 174 states and 177 transitions. [2018-01-24 16:55:22,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 16:55:22,722 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 110 [2018-01-24 16:55:22,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:22,723 INFO L225 Difference]: With dead ends: 174 [2018-01-24 16:55:22,723 INFO L226 Difference]: Without dead ends: 123 [2018-01-24 16:55:22,723 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 478 GetRequests, 439 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 131 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=680, Invalid=960, Unknown=0, NotChecked=0, Total=1640 [2018-01-24 16:55:22,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2018-01-24 16:55:22,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 119. [2018-01-24 16:55:22,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-01-24 16:55:22,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 120 transitions. [2018-01-24 16:55:22,735 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 120 transitions. Word has length 110 [2018-01-24 16:55:22,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:22,735 INFO L432 AbstractCegarLoop]: Abstraction has 119 states and 120 transitions. [2018-01-24 16:55:22,735 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 16:55:22,735 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 120 transitions. [2018-01-24 16:55:22,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-01-24 16:55:22,736 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:22,737 INFO L322 BasicCegarLoop]: trace histogram [13, 13, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:22,737 INFO L371 AbstractCegarLoop]: === Iteration 17 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:22,737 INFO L82 PathProgramCache]: Analyzing trace with hash -130219445, now seen corresponding path program 7 times [2018-01-24 16:55:22,737 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:22,738 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:22,738 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:55:22,738 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:22,738 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:22,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:22,758 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:22,924 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 16:55:22,924 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:22,924 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:22,925 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:22,925 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:22,925 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:22,925 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:22,929 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:22,930 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:55:22,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:22,964 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:23,091 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 16:55:23,091 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:23,362 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 16:55:23,381 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:23,381 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:23,385 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:23,385 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:55:23,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:23,456 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:23,481 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 16:55:23,481 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:23,575 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 16:55:23,576 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:23,576 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16, 17, 16, 17] total 44 [2018-01-24 16:55:23,576 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:23,577 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 16:55:23,577 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 16:55:23,577 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=709, Invalid=1183, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 16:55:23,577 INFO L87 Difference]: Start difference. First operand 119 states and 120 transitions. Second operand 30 states. [2018-01-24 16:55:23,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:23,711 INFO L93 Difference]: Finished difference Result 186 states and 189 transitions. [2018-01-24 16:55:23,712 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 16:55:23,712 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 118 [2018-01-24 16:55:23,712 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:23,712 INFO L225 Difference]: With dead ends: 186 [2018-01-24 16:55:23,712 INFO L226 Difference]: Without dead ends: 131 [2018-01-24 16:55:23,713 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 488 GetRequests, 441 SyntacticMatches, 4 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 776 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=752, Invalid=1228, Unknown=0, NotChecked=0, Total=1980 [2018-01-24 16:55:23,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2018-01-24 16:55:23,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 127. [2018-01-24 16:55:23,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127 states. [2018-01-24 16:55:23,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 128 transitions. [2018-01-24 16:55:23,723 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 128 transitions. Word has length 118 [2018-01-24 16:55:23,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:23,724 INFO L432 AbstractCegarLoop]: Abstraction has 127 states and 128 transitions. [2018-01-24 16:55:23,724 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 16:55:23,724 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 128 transitions. [2018-01-24 16:55:23,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-01-24 16:55:23,724 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:23,725 INFO L322 BasicCegarLoop]: trace histogram [14, 14, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:23,725 INFO L371 AbstractCegarLoop]: === Iteration 18 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:23,725 INFO L82 PathProgramCache]: Analyzing trace with hash -1727297941, now seen corresponding path program 8 times [2018-01-24 16:55:23,725 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:23,725 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:23,726 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:55:23,726 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:23,726 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:23,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:23,742 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:23,955 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 16:55:23,956 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:23,956 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:23,956 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:23,956 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:23,956 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:23,956 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:23,962 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:55:23,963 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:55:23,976 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:23,994 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:23,997 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:24,000 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:24,212 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 16:55:24,212 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:24,519 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 16:55:24,539 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:24,540 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:24,542 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:55:24,543 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:55:24,562 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:24,613 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:24,638 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:24,644 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:24,661 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 16:55:24,661 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:24,766 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 16:55:24,768 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:24,768 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 18, 17, 18] total 47 [2018-01-24 16:55:24,768 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:24,769 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-01-24 16:55:24,769 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-01-24 16:55:24,770 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=812, Invalid=1350, Unknown=0, NotChecked=0, Total=2162 [2018-01-24 16:55:24,770 INFO L87 Difference]: Start difference. First operand 127 states and 128 transitions. Second operand 32 states. [2018-01-24 16:55:24,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:24,966 INFO L93 Difference]: Finished difference Result 198 states and 201 transitions. [2018-01-24 16:55:24,966 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 16:55:24,966 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 126 [2018-01-24 16:55:24,967 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:24,967 INFO L225 Difference]: With dead ends: 198 [2018-01-24 16:55:24,967 INFO L226 Difference]: Without dead ends: 139 [2018-01-24 16:55:24,968 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 521 GetRequests, 471 SyntacticMatches, 4 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 899 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=858, Invalid=1398, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 16:55:24,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-01-24 16:55:24,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 135. [2018-01-24 16:55:24,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-24 16:55:24,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 136 transitions. [2018-01-24 16:55:24,987 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 136 transitions. Word has length 126 [2018-01-24 16:55:24,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:24,987 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 136 transitions. [2018-01-24 16:55:24,988 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-01-24 16:55:24,988 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 136 transitions. [2018-01-24 16:55:24,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-01-24 16:55:24,989 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:24,989 INFO L322 BasicCegarLoop]: trace histogram [15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:24,989 INFO L371 AbstractCegarLoop]: === Iteration 19 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:24,989 INFO L82 PathProgramCache]: Analyzing trace with hash 293691787, now seen corresponding path program 9 times [2018-01-24 16:55:24,989 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:24,990 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:24,990 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:55:24,990 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:24,990 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:25,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:25,011 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:25,261 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 16:55:25,261 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:25,294 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:25,294 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:25,294 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:25,295 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:25,295 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:25,301 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:55:25,301 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:55:25,318 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,322 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,326 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,332 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,339 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,354 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,366 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,389 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,412 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,432 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,486 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,629 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,708 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:25,771 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:26,129 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:26,131 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:26,136 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:26,159 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 16:55:26,159 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:26,378 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 16:55:26,399 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:26,400 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:26,402 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:55:26,403 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:55:26,434 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:26,485 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:26,544 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:26,614 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:26,685 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:26,751 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:26,848 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:26,982 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:27,121 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:27,302 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:27,547 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:27,858 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:28,199 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:28,603 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:29,115 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:55:29,154 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:29,161 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:29,339 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 16:55:29,339 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:29,700 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 16:55:29,702 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:29,703 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 17, 17, 18, 19] total 66 [2018-01-24 16:55:29,703 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:29,703 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 16:55:29,703 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 16:55:29,704 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1555, Invalid=2735, Unknown=0, NotChecked=0, Total=4290 [2018-01-24 16:55:29,704 INFO L87 Difference]: Start difference. First operand 135 states and 136 transitions. Second operand 20 states. [2018-01-24 16:55:29,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:29,823 INFO L93 Difference]: Finished difference Result 210 states and 213 transitions. [2018-01-24 16:55:29,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 16:55:29,824 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 134 [2018-01-24 16:55:29,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:29,824 INFO L225 Difference]: With dead ends: 210 [2018-01-24 16:55:29,824 INFO L226 Difference]: Without dead ends: 147 [2018-01-24 16:55:29,825 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 583 GetRequests, 516 SyntacticMatches, 2 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2061 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1620, Invalid=2802, Unknown=0, NotChecked=0, Total=4422 [2018-01-24 16:55:29,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-01-24 16:55:29,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 143. [2018-01-24 16:55:29,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-01-24 16:55:29,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 144 transitions. [2018-01-24 16:55:29,838 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 144 transitions. Word has length 134 [2018-01-24 16:55:29,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:29,838 INFO L432 AbstractCegarLoop]: Abstraction has 143 states and 144 transitions. [2018-01-24 16:55:29,838 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 16:55:29,838 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 144 transitions. [2018-01-24 16:55:29,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-01-24 16:55:29,839 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:29,839 INFO L322 BasicCegarLoop]: trace histogram [16, 16, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:29,839 INFO L371 AbstractCegarLoop]: === Iteration 20 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:29,839 INFO L82 PathProgramCache]: Analyzing trace with hash 1657017259, now seen corresponding path program 10 times [2018-01-24 16:55:29,839 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:29,840 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:29,840 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:55:29,840 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:29,841 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:29,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:29,857 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:30,339 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 450 trivial. 0 not checked. [2018-01-24 16:55:30,340 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:30,372 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:30,373 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:30,373 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:30,373 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:30,373 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:30,378 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 16:55:30,378 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 16:55:30,417 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:30,421 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:30,436 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:55:30,437 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:30,446 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:30,447 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:8, output treesize:7 [2018-01-24 16:55:31,458 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 450 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:31,459 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:31,931 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:31,987 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:31,989 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:32,114 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:32,161 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:32,212 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:32,728 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:32,781 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:32,830 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:55:32,899 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:32,901 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:32,903 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:33,459 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:33,520 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:33,579 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:55:34,523 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 450 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:34,544 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:34,544 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:34,548 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 16:55:34,548 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 16:55:34,628 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:34,637 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:34,640 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:55:34,640 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:55:34,663 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:55:34,663 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-01-24 16:55:34,796 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 450 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:34,796 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:35,124 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:35,126 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:35,128 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:35,130 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:55:35,186 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:35,232 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:35,278 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:35,527 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:55:35,577 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:35,624 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:35,672 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:36,287 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:36,341 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:36,400 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:55:36,666 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 450 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:55:36,667 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:55:36,667 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 37, 41, 36, 37] total 97 [2018-01-24 16:55:36,668 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:55:36,668 INFO L409 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-01-24 16:55:36,668 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-01-24 16:55:36,670 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1876, Invalid=7436, Unknown=0, NotChecked=0, Total=9312 [2018-01-24 16:55:36,670 INFO L87 Difference]: Start difference. First operand 143 states and 144 transitions. Second operand 55 states. [2018-01-24 16:55:37,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:55:37,592 INFO L93 Difference]: Finished difference Result 222 states and 225 transitions. [2018-01-24 16:55:37,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 16:55:37,592 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 142 [2018-01-24 16:55:37,592 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:55:37,593 INFO L225 Difference]: With dead ends: 222 [2018-01-24 16:55:37,593 INFO L226 Difference]: Without dead ends: 155 [2018-01-24 16:55:37,596 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 608 GetRequests, 447 SyntacticMatches, 45 SemanticMatches, 116 ConstructedPredicates, 0 IntricatePredicates, 4 DeprecatedPredicates, 10078 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=2719, Invalid=11087, Unknown=0, NotChecked=0, Total=13806 [2018-01-24 16:55:37,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-01-24 16:55:37,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 151. [2018-01-24 16:55:37,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-01-24 16:55:37,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 152 transitions. [2018-01-24 16:55:37,611 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 152 transitions. Word has length 142 [2018-01-24 16:55:37,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:55:37,611 INFO L432 AbstractCegarLoop]: Abstraction has 151 states and 152 transitions. [2018-01-24 16:55:37,611 INFO L433 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-01-24 16:55:37,611 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 152 transitions. [2018-01-24 16:55:37,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-01-24 16:55:37,612 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:55:37,612 INFO L322 BasicCegarLoop]: trace histogram [17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:55:37,612 INFO L371 AbstractCegarLoop]: === Iteration 21 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:55:37,612 INFO L82 PathProgramCache]: Analyzing trace with hash -969335605, now seen corresponding path program 11 times [2018-01-24 16:55:37,612 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:55:37,613 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:37,613 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:55:37,613 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:55:37,613 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:55:37,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:55:37,634 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:55:37,884 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 16:55:37,885 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:37,885 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:55:37,885 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:55:37,885 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:55:37,885 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:37,885 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:55:37,890 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 16:55:37,890 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:55:37,899 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:37,901 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:37,904 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:37,907 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:37,912 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:37,927 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:37,992 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:38,025 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:38,062 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:38,077 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:38,182 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:38,217 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:38,240 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:38,283 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:38,322 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:38,356 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:43,504 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:43,517 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:43,524 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:43,542 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 16:55:43,542 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:55:43,815 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 16:55:43,848 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:55:43,848 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:55:43,851 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 16:55:43,851 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:55:43,867 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:43,875 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:43,891 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:43,914 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:43,941 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:43,973 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:44,042 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:44,132 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:44,251 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:44,408 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:44,952 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:45,670 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:46,582 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:47,681 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:50,661 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:54,644 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command Received shutdown request... [2018-01-24 16:55:57,400 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:55:57,470 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:55:57,478 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:55:57,482 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-01-24 16:55:57,482 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 16:55:57,486 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 16:55:57,486 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 04:55:57 BoogieIcfgContainer [2018-01-24 16:55:57,486 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 16:55:57,487 INFO L168 Benchmark]: Toolchain (without parser) took 57112.38 ms. Allocated memory was 300.4 MB in the beginning and 718.8 MB in the end (delta: 418.4 MB). Free memory was 260.5 MB in the beginning and 539.7 MB in the end (delta: -279.2 MB). Peak memory consumption was 139.2 MB. Max. memory is 5.3 GB. [2018-01-24 16:55:57,488 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 300.4 MB. Free memory is still 266.4 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 16:55:57,488 INFO L168 Benchmark]: CACSL2BoogieTranslator took 209.56 ms. Allocated memory is still 300.4 MB. Free memory was 259.5 MB in the beginning and 249.3 MB in the end (delta: 10.2 MB). Peak memory consumption was 10.2 MB. Max. memory is 5.3 GB. [2018-01-24 16:55:57,489 INFO L168 Benchmark]: Boogie Preprocessor took 35.14 ms. Allocated memory is still 300.4 MB. Free memory was 249.3 MB in the beginning and 247.3 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 16:55:57,489 INFO L168 Benchmark]: RCFGBuilder took 301.10 ms. Allocated memory is still 300.4 MB. Free memory was 247.3 MB in the beginning and 229.7 MB in the end (delta: 17.6 MB). Peak memory consumption was 17.6 MB. Max. memory is 5.3 GB. [2018-01-24 16:55:57,489 INFO L168 Benchmark]: TraceAbstraction took 56558.42 ms. Allocated memory was 300.4 MB in the beginning and 718.8 MB in the end (delta: 418.4 MB). Free memory was 229.7 MB in the beginning and 539.7 MB in the end (delta: -310.0 MB). Peak memory consumption was 108.4 MB. Max. memory is 5.3 GB. [2018-01-24 16:55:57,491 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 300.4 MB. Free memory is still 266.4 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 209.56 ms. Allocated memory is still 300.4 MB. Free memory was 259.5 MB in the beginning and 249.3 MB in the end (delta: 10.2 MB). Peak memory consumption was 10.2 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 35.14 ms. Allocated memory is still 300.4 MB. Free memory was 249.3 MB in the beginning and 247.3 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 301.10 ms. Allocated memory is still 300.4 MB. Free memory was 247.3 MB in the beginning and 229.7 MB in the end (delta: 17.6 MB). Peak memory consumption was 17.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 56558.42 ms. Allocated memory was 300.4 MB in the beginning and 718.8 MB in the end (delta: 418.4 MB). Free memory was 229.7 MB in the beginning and 539.7 MB in the end (delta: -310.0 MB). Peak memory consumption was 108.4 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 18 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 226 LocStat_NO_SUPPORTING_DISEQUALITIES : 34 LocStat_NO_DISJUNCTIONS : -36 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 25 TransStat_MAX_WEQGRAPH_SIZE : 0 TransStat_MAX_SIZEOF_WEQEDGELABEL : 0 TransStat_NO_SUPPORTING_EQUALITIES : 65 TransStat_NO_SUPPORTING_DISEQUALITIES : 4 TransStat_NO_DISJUNCTIONS : 26 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 1.063151 RENAME_VARIABLES(MILLISECONDS) : 0.664964 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 1.001750 PROJECTAWAY(MILLISECONDS) : 0.382776 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.001094 DISJOIN(MILLISECONDS) : 0.664208 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.715772 ADD_EQUALITY(MILLISECONDS) : 0.045489 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.017493 #CONJOIN_DISJUNCTIVE : 39 #RENAME_VARIABLES : 68 #UNFREEZE : 0 #CONJOIN : 96 #PROJECTAWAY : 61 #ADD_WEAK_EQUALITY : 9 #DISJOIN : 6 #RENAME_VARIABLES_DISJUNCTIVE : 65 #ADD_EQUALITY : 67 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 2 - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 22 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 259 LocStat_NO_SUPPORTING_DISEQUALITIES : 46 LocStat_NO_DISJUNCTIONS : -44 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 29 TransStat_MAX_WEQGRAPH_SIZE : 0 TransStat_MAX_SIZEOF_WEQEDGELABEL : 0 TransStat_NO_SUPPORTING_EQUALITIES : 67 TransStat_NO_SUPPORTING_DISEQUALITIES : 4 TransStat_NO_DISJUNCTIONS : 30 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.895189 RENAME_VARIABLES(MILLISECONDS) : 0.261611 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.411635 PROJECTAWAY(MILLISECONDS) : 0.063808 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.001089 DISJOIN(MILLISECONDS) : 0.567781 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.295501 ADD_EQUALITY(MILLISECONDS) : 0.025421 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.013804 #CONJOIN_DISJUNCTIVE : 51 #RENAME_VARIABLES : 92 #UNFREEZE : 0 #CONJOIN : 108 #PROJECTAWAY : 77 #ADD_WEAK_EQUALITY : 9 #DISJOIN : 10 #RENAME_VARIABLES_DISJUNCTIVE : 89 #ADD_EQUALITY : 69 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 2 - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 26 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 296 LocStat_NO_SUPPORTING_DISEQUALITIES : 58 LocStat_NO_DISJUNCTIONS : -52 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 34 TransStat_MAX_WEQGRAPH_SIZE : 0 TransStat_MAX_SIZEOF_WEQEDGELABEL : 0 TransStat_NO_SUPPORTING_EQUALITIES : 71 TransStat_NO_SUPPORTING_DISEQUALITIES : 4 TransStat_NO_DISJUNCTIONS : 35 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.757363 RENAME_VARIABLES(MILLISECONDS) : 0.207542 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.324375 PROJECTAWAY(MILLISECONDS) : 0.049437 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.001300 DISJOIN(MILLISECONDS) : 0.404340 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.239513 ADD_EQUALITY(MILLISECONDS) : 0.022220 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.014909 #CONJOIN_DISJUNCTIVE : 59 #RENAME_VARIABLES : 111 #UNFREEZE : 0 #CONJOIN : 126 #PROJECTAWAY : 96 #ADD_WEAK_EQUALITY : 11 #DISJOIN : 5 #RENAME_VARIABLES_DISJUNCTIVE : 109 #ADD_EQUALITY : 74 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 2 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 625). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 625). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 627). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 627). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 637). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 634). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 639). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 634). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 636). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 637). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 639). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 639). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 639). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 636). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 637). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 637). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 629]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 629). Cancelled while BasicCegarLoop was analyzing trace of length 151 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 53 locations, 17 error locations. TIMEOUT Result, 56.5s OverallTime, 21 OverallIterations, 17 TraceHistogramMax, 5.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 481 SDtfs, 2920 SDslu, 2858 SDs, 0 SdLazy, 3318 SolverSat, 717 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 5140 GetRequests, 4351 SyntacticMatches, 116 SemanticMatches, 673 ConstructedPredicates, 0 IntricatePredicates, 6 DeprecatedPredicates, 20688 ImplicationChecksByTransitivity, 17.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=151occurred in iteration=20, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.4s AbstIntTime, 3 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 20 MinimizatonAttempts, 97 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 8.9s SatisfiabilityAnalysisTime, 20.2s InterpolantComputationTime, 3713 NumberOfCodeBlocks, 3617 NumberOfCodeBlocksAsserted, 143 NumberOfCheckSat, 6029 ConstructedInterpolants, 636 QuantifiedInterpolants, 4365963 SizeOfPredicates, 102 NumberOfNonLiveVariables, 7465 ConjunctsInSsa, 493 ConjunctsInUnsatCore, 78 InterpolantComputations, 7 PerfectInterpolantSequences, 12092/24408 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_16-55-57-502.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_16-55-57-502.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_16-55-57-502.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-1-2018-01-24_16-55-57-502.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-1-2018-01-24_16-55-57-502.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-2-2018-01-24_16-55-57-502.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-2-2018-01-24_16-55-57-502.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_16-55-57-502.csv Completed graceful shutdown