java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf -i ../../../trunk/examples/svcomp/memsafety/960521-1_false-valid-free.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 16:55:59,926 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 16:55:59,927 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 16:55:59,942 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 16:55:59,942 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 16:55:59,943 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 16:55:59,944 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 16:55:59,946 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 16:55:59,948 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 16:55:59,949 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 16:55:59,950 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 16:55:59,950 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 16:55:59,951 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 16:55:59,952 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 16:55:59,953 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 16:55:59,956 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 16:55:59,958 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 16:55:59,960 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 16:55:59,961 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 16:55:59,963 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 16:55:59,965 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 16:55:59,965 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 16:55:59,965 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 16:55:59,967 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 16:55:59,967 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 16:55:59,969 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 16:55:59,969 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 16:55:59,969 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 16:55:59,970 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 16:55:59,970 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 16:55:59,970 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 16:55:59,971 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf [2018-01-24 16:55:59,979 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 16:55:59,979 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 16:55:59,979 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 16:55:59,979 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 16:55:59,980 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 16:55:59,980 INFO L133 SettingsManager]: * Deactivate Weak Equivalences=true [2018-01-24 16:55:59,980 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 16:55:59,980 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 16:55:59,980 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 16:55:59,980 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 16:55:59,981 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 16:55:59,981 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 16:55:59,981 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 16:55:59,981 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 16:55:59,981 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 16:55:59,981 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 16:55:59,981 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 16:55:59,981 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 16:55:59,982 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 16:55:59,982 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 16:55:59,982 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 16:55:59,982 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 16:55:59,982 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 16:55:59,982 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 16:55:59,983 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 16:55:59,983 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 16:55:59,983 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 16:55:59,983 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 16:55:59,983 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 16:55:59,983 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 16:55:59,983 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 16:55:59,984 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 16:55:59,984 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 16:55:59,984 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 16:55:59,984 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 16:55:59,985 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 16:56:00,017 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 16:56:00,028 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 16:56:00,031 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 16:56:00,032 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 16:56:00,032 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 16:56:00,033 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/memsafety/960521-1_false-valid-free.i [2018-01-24 16:56:00,177 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 16:56:00,182 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 16:56:00,183 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 16:56:00,183 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 16:56:00,188 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 16:56:00,189 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 04:56:00" (1/1) ... [2018-01-24 16:56:00,192 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7ef7ce9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:56:00, skipping insertion in model container [2018-01-24 16:56:00,192 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 04:56:00" (1/1) ... [2018-01-24 16:56:00,210 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 16:56:00,250 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 16:56:00,364 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 16:56:00,379 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 16:56:00,390 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:56:00 WrapperNode [2018-01-24 16:56:00,391 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 16:56:00,391 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 16:56:00,391 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 16:56:00,391 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 16:56:00,410 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:56:00" (1/1) ... [2018-01-24 16:56:00,410 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:56:00" (1/1) ... [2018-01-24 16:56:00,422 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:56:00" (1/1) ... [2018-01-24 16:56:00,422 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:56:00" (1/1) ... [2018-01-24 16:56:00,427 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:56:00" (1/1) ... [2018-01-24 16:56:00,431 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:56:00" (1/1) ... [2018-01-24 16:56:00,432 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:56:00" (1/1) ... [2018-01-24 16:56:00,434 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 16:56:00,435 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 16:56:00,438 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 16:56:00,438 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 16:56:00,439 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:56:00" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 16:56:00,499 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 16:56:00,499 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 16:56:00,499 INFO L136 BoogieDeclarations]: Found implementation of procedure foo [2018-01-24 16:56:00,499 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 16:56:00,499 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-24 16:56:00,500 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-24 16:56:00,500 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-24 16:56:00,502 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-24 16:56:00,502 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-24 16:56:00,502 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-01-24 16:56:00,502 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-01-24 16:56:00,502 INFO L128 BoogieDeclarations]: Found specification of procedure foo [2018-01-24 16:56:00,503 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 16:56:00,503 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 16:56:00,503 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 16:56:00,752 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 16:56:00,753 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 04:56:00 BoogieIcfgContainer [2018-01-24 16:56:00,753 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 16:56:00,753 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 16:56:00,753 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 16:56:00,755 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 16:56:00,755 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 04:56:00" (1/3) ... [2018-01-24 16:56:00,756 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5c157966 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 04:56:00, skipping insertion in model container [2018-01-24 16:56:00,757 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 04:56:00" (2/3) ... [2018-01-24 16:56:00,757 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5c157966 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 04:56:00, skipping insertion in model container [2018-01-24 16:56:00,757 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 04:56:00" (3/3) ... [2018-01-24 16:56:00,758 INFO L105 eAbstractionObserver]: Analyzing ICFG 960521-1_false-valid-free.i [2018-01-24 16:56:00,765 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 16:56:00,772 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 17 error locations. [2018-01-24 16:56:00,816 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 16:56:00,816 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 16:56:00,816 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 16:56:00,816 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 16:56:00,816 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 16:56:00,816 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 16:56:00,816 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 16:56:00,817 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 16:56:00,817 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 16:56:00,838 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states. [2018-01-24 16:56:00,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-01-24 16:56:00,844 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:00,845 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:00,845 INFO L371 AbstractCegarLoop]: === Iteration 1 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:00,849 INFO L82 PathProgramCache]: Analyzing trace with hash 1993989713, now seen corresponding path program 1 times [2018-01-24 16:56:00,851 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:00,894 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:00,894 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:00,894 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:00,895 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:00,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:00,959 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:01,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:01,053 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:56:01,053 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 16:56:01,053 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:56:01,055 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 16:56:01,066 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 16:56:01,067 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 16:56:01,069 INFO L87 Difference]: Start difference. First operand 53 states. Second operand 4 states. [2018-01-24 16:56:01,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:01,316 INFO L93 Difference]: Finished difference Result 84 states and 90 transitions. [2018-01-24 16:56:01,316 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 16:56:01,318 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 11 [2018-01-24 16:56:01,319 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:01,330 INFO L225 Difference]: With dead ends: 84 [2018-01-24 16:56:01,331 INFO L226 Difference]: Without dead ends: 49 [2018-01-24 16:56:01,335 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 16:56:01,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-01-24 16:56:01,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2018-01-24 16:56:01,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-01-24 16:56:01,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 51 transitions. [2018-01-24 16:56:01,372 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 51 transitions. Word has length 11 [2018-01-24 16:56:01,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:01,372 INFO L432 AbstractCegarLoop]: Abstraction has 49 states and 51 transitions. [2018-01-24 16:56:01,372 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 16:56:01,372 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 51 transitions. [2018-01-24 16:56:01,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-01-24 16:56:01,373 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:01,373 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:01,373 INFO L371 AbstractCegarLoop]: === Iteration 2 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:01,373 INFO L82 PathProgramCache]: Analyzing trace with hash 1993989714, now seen corresponding path program 1 times [2018-01-24 16:56:01,373 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:01,375 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:01,375 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:01,375 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:01,375 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:01,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:01,395 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:01,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:01,463 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:56:01,463 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 16:56:01,463 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:56:01,465 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 16:56:01,465 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 16:56:01,466 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-01-24 16:56:01,466 INFO L87 Difference]: Start difference. First operand 49 states and 51 transitions. Second operand 5 states. [2018-01-24 16:56:01,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:01,582 INFO L93 Difference]: Finished difference Result 49 states and 51 transitions. [2018-01-24 16:56:01,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 16:56:01,583 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 11 [2018-01-24 16:56:01,583 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:01,584 INFO L225 Difference]: With dead ends: 49 [2018-01-24 16:56:01,584 INFO L226 Difference]: Without dead ends: 48 [2018-01-24 16:56:01,585 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-01-24 16:56:01,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-01-24 16:56:01,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2018-01-24 16:56:01,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-01-24 16:56:01,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 50 transitions. [2018-01-24 16:56:01,592 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 50 transitions. Word has length 11 [2018-01-24 16:56:01,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:01,593 INFO L432 AbstractCegarLoop]: Abstraction has 48 states and 50 transitions. [2018-01-24 16:56:01,593 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 16:56:01,593 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 50 transitions. [2018-01-24 16:56:01,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 16:56:01,594 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:01,594 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:01,594 INFO L371 AbstractCegarLoop]: === Iteration 3 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:01,594 INFO L82 PathProgramCache]: Analyzing trace with hash -1188525484, now seen corresponding path program 1 times [2018-01-24 16:56:01,595 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:01,596 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:01,596 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:01,596 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:01,596 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:01,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:01,619 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:01,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:01,692 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:56:01,692 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 16:56:01,692 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:56:01,692 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 16:56:01,693 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 16:56:01,693 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-01-24 16:56:01,693 INFO L87 Difference]: Start difference. First operand 48 states and 50 transitions. Second operand 6 states. [2018-01-24 16:56:01,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:01,795 INFO L93 Difference]: Finished difference Result 48 states and 50 transitions. [2018-01-24 16:56:01,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 16:56:01,796 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-01-24 16:56:01,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:01,797 INFO L225 Difference]: With dead ends: 48 [2018-01-24 16:56:01,797 INFO L226 Difference]: Without dead ends: 45 [2018-01-24 16:56:01,798 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-01-24 16:56:01,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-01-24 16:56:01,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-01-24 16:56:01,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-01-24 16:56:01,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 47 transitions. [2018-01-24 16:56:01,804 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 47 transitions. Word has length 17 [2018-01-24 16:56:01,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:01,805 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 47 transitions. [2018-01-24 16:56:01,805 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 16:56:01,805 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 47 transitions. [2018-01-24 16:56:01,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 16:56:01,806 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:01,806 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:01,806 INFO L371 AbstractCegarLoop]: === Iteration 4 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:01,807 INFO L82 PathProgramCache]: Analyzing trace with hash -1188525483, now seen corresponding path program 1 times [2018-01-24 16:56:01,807 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:01,808 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:01,808 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:01,808 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:01,808 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:01,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:01,828 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:01,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:01,986 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:56:01,986 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-01-24 16:56:01,986 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:56:01,987 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 16:56:01,987 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 16:56:01,987 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 16:56:01,988 INFO L87 Difference]: Start difference. First operand 45 states and 47 transitions. Second operand 7 states. [2018-01-24 16:56:02,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:02,115 INFO L93 Difference]: Finished difference Result 80 states and 87 transitions. [2018-01-24 16:56:02,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 16:56:02,116 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 17 [2018-01-24 16:56:02,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:02,117 INFO L225 Difference]: With dead ends: 80 [2018-01-24 16:56:02,117 INFO L226 Difference]: Without dead ends: 53 [2018-01-24 16:56:02,118 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-01-24 16:56:02,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-01-24 16:56:02,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 48. [2018-01-24 16:56:02,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-01-24 16:56:02,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 50 transitions. [2018-01-24 16:56:02,126 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 50 transitions. Word has length 17 [2018-01-24 16:56:02,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:02,126 INFO L432 AbstractCegarLoop]: Abstraction has 48 states and 50 transitions. [2018-01-24 16:56:02,126 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 16:56:02,127 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 50 transitions. [2018-01-24 16:56:02,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-01-24 16:56:02,127 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:02,128 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:02,128 INFO L371 AbstractCegarLoop]: === Iteration 5 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:02,128 INFO L82 PathProgramCache]: Analyzing trace with hash -2106816852, now seen corresponding path program 1 times [2018-01-24 16:56:02,128 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:02,129 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:02,129 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:02,130 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:02,130 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:02,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:02,150 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:02,321 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:02,322 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:02,322 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:02,323 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 22 with the following transitions: [2018-01-24 16:56:02,325 INFO L201 CegarAbsIntRunner]: [0], [1], [2], [6], [11], [12], [14], [16], [42], [43], [44], [45], [46], [47], [50], [76], [77], [78], [80] [2018-01-24 16:56:02,371 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 16:56:02,371 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 16:56:02,565 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 16:56:02,567 INFO L268 AbstractInterpreter]: Visited 19 different actions 24 times. Merged at 5 different actions 5 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 26 variables. [2018-01-24 16:56:02,580 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 16:56:02,580 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:02,580 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:02,588 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:02,589 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:56:02,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:02,631 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:02,664 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:56:02,666 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:02,686 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:02,686 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:15, output treesize:14 [2018-01-24 16:56:02,717 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-01-24 16:56:02,718 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:02,737 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 16:56:02,737 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:22, output treesize:21 [2018-01-24 16:56:02,868 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:02,869 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:03,910 WARN L143 SmtUtils]: Spent 311ms on a formula simplification that was a NOOP. DAG size: 17 [2018-01-24 16:56:03,914 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 16:56:03,927 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-01-24 16:56:03,927 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:03,928 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:03,929 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:03,929 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:15, output treesize:5 [2018-01-24 16:56:03,950 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:03,985 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:03,985 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:03,988 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:03,989 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:56:04,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:04,023 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:04,029 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:56:04,029 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,037 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 16:56:04,037 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,042 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,042 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-01-24 16:56:04,078 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:56:04,080 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 16:56:04,080 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,095 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:56:04,096 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:56:04,097 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 16:56:04,097 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,105 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 16:56:04,106 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:32, output treesize:25 [2018-01-24 16:56:04,230 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:04,231 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:04,325 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-01-24 16:56:04,326 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,329 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 16:56:04,339 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 1 [2018-01-24 16:56:04,339 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,340 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,343 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,343 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:25, output treesize:5 [2018-01-24 16:56:04,347 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:04,349 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:04,349 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8, 7, 7, 7] total 24 [2018-01-24 16:56:04,349 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:04,349 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 16:56:04,349 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 16:56:04,350 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=476, Unknown=2, NotChecked=0, Total=600 [2018-01-24 16:56:04,350 INFO L87 Difference]: Start difference. First operand 48 states and 50 transitions. Second operand 12 states. [2018-01-24 16:56:04,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:04,624 INFO L93 Difference]: Finished difference Result 90 states and 95 transitions. [2018-01-24 16:56:04,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 16:56:04,624 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 21 [2018-01-24 16:56:04,625 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:04,626 INFO L225 Difference]: With dead ends: 90 [2018-01-24 16:56:04,626 INFO L226 Difference]: Without dead ends: 63 [2018-01-24 16:56:04,627 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 64 SyntacticMatches, 4 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 232 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=162, Invalid=592, Unknown=2, NotChecked=0, Total=756 [2018-01-24 16:56:04,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-01-24 16:56:04,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 56. [2018-01-24 16:56:04,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2018-01-24 16:56:04,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 60 transitions. [2018-01-24 16:56:04,635 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 60 transitions. Word has length 21 [2018-01-24 16:56:04,635 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:04,636 INFO L432 AbstractCegarLoop]: Abstraction has 56 states and 60 transitions. [2018-01-24 16:56:04,636 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 16:56:04,636 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 60 transitions. [2018-01-24 16:56:04,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-24 16:56:04,637 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:04,637 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:04,637 INFO L371 AbstractCegarLoop]: === Iteration 6 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:04,637 INFO L82 PathProgramCache]: Analyzing trace with hash -702775421, now seen corresponding path program 2 times [2018-01-24 16:56:04,637 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:04,638 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:04,639 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:04,639 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:04,639 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:04,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:04,658 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:04,846 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:04,846 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:04,846 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:04,847 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:04,847 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:04,847 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:04,847 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:04,854 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:56:04,854 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:56:04,869 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:04,873 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:04,874 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:04,876 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:04,880 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 16:56:04,881 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,887 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:56:04,888 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,892 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,893 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-01-24 16:56:04,918 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:56:04,919 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:56:04,920 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 16:56:04,920 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,928 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 16:56:04,928 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:04,935 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 16:56:04,935 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:32, output treesize:25 [2018-01-24 16:56:05,137 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:05,137 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:05,273 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-01-24 16:56:05,273 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,278 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 16:56:05,288 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 1 [2018-01-24 16:56:05,288 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,290 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,293 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,293 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:25, output treesize:5 [2018-01-24 16:56:05,310 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:05,331 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:05,331 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:05,334 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:56:05,334 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:56:05,353 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:05,384 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:05,396 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:05,423 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:05,427 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:56:05,427 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,446 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 16:56:05,446 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,452 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,452 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-01-24 16:56:05,456 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:56:05,457 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 16:56:05,457 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,470 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:56:05,471 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:56:05,472 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 16:56:05,472 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,484 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 16:56:05,485 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:32, output treesize:25 [2018-01-24 16:56:05,538 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:05,538 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:05,581 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-01-24 16:56:05,581 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,585 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-01-24 16:56:05,596 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-01-24 16:56:05,596 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,597 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,600 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:05,600 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:25, output treesize:5 [2018-01-24 16:56:05,605 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:05,606 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:05,607 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8, 8, 8] total 23 [2018-01-24 16:56:05,607 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:05,607 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 16:56:05,608 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 16:56:05,608 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=442, Unknown=0, NotChecked=0, Total=552 [2018-01-24 16:56:05,608 INFO L87 Difference]: Start difference. First operand 56 states and 60 transitions. Second operand 17 states. [2018-01-24 16:56:06,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:06,100 INFO L93 Difference]: Finished difference Result 104 states and 111 transitions. [2018-01-24 16:56:06,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 16:56:06,101 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 25 [2018-01-24 16:56:06,101 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:06,101 INFO L225 Difference]: With dead ends: 104 [2018-01-24 16:56:06,102 INFO L226 Difference]: Without dead ends: 73 [2018-01-24 16:56:06,103 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 83 SyntacticMatches, 3 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 257 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=208, Invalid=722, Unknown=0, NotChecked=0, Total=930 [2018-01-24 16:56:06,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-01-24 16:56:06,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 64. [2018-01-24 16:56:06,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-01-24 16:56:06,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 70 transitions. [2018-01-24 16:56:06,111 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 70 transitions. Word has length 25 [2018-01-24 16:56:06,112 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:06,112 INFO L432 AbstractCegarLoop]: Abstraction has 64 states and 70 transitions. [2018-01-24 16:56:06,112 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 16:56:06,112 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 70 transitions. [2018-01-24 16:56:06,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-01-24 16:56:06,113 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:06,113 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:06,113 INFO L371 AbstractCegarLoop]: === Iteration 7 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:06,113 INFO L82 PathProgramCache]: Analyzing trace with hash 1827026138, now seen corresponding path program 3 times [2018-01-24 16:56:06,114 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:06,114 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:06,115 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:56:06,115 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:06,115 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:06,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:06,130 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:06,399 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:06,399 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:06,399 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:06,399 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:06,400 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:06,400 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:06,400 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:06,407 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:56:06,408 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:56:06,419 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:06,422 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:06,423 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:06,425 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:06,428 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:56:06,428 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:06,434 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 16:56:06,434 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:06,438 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:06,438 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-01-24 16:56:06,461 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:56:06,462 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:56:06,463 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 16:56:06,463 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:06,470 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 16:56:06,470 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:06,475 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:06,475 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:29, output treesize:22 [2018-01-24 16:56:06,598 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 16:56:06,599 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:07,190 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 16:56:07,210 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:07,210 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:07,213 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:56:07,213 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:56:07,235 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:07,265 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:07,276 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:07,281 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:07,284 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-24 16:56:07,284 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:07,289 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:56:07,289 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:07,293 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:07,293 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-01-24 16:56:07,335 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:56:07,336 INFO L700 Elim1Store]: detected not equals via solver [2018-01-24 16:56:07,336 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-01-24 16:56:07,336 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:07,344 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-01-24 16:56:07,344 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:07,350 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 16:56:07,350 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:29, output treesize:22 [2018-01-24 16:56:07,535 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 16:56:07,536 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:07,984 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-24 16:56:07,986 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:07,986 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 7, 7, 7] total 29 [2018-01-24 16:56:07,986 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:07,986 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 16:56:07,987 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 16:56:07,987 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=730, Unknown=0, NotChecked=0, Total=870 [2018-01-24 16:56:07,987 INFO L87 Difference]: Start difference. First operand 64 states and 70 transitions. Second operand 18 states. [2018-01-24 16:56:08,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:08,906 INFO L93 Difference]: Finished difference Result 125 states and 137 transitions. [2018-01-24 16:56:08,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 16:56:08,906 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 29 [2018-01-24 16:56:08,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:08,909 INFO L225 Difference]: With dead ends: 125 [2018-01-24 16:56:08,910 INFO L226 Difference]: Without dead ends: 90 [2018-01-24 16:56:08,911 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 92 SyntacticMatches, 5 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 460 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=338, Invalid=1302, Unknown=0, NotChecked=0, Total=1640 [2018-01-24 16:56:08,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-01-24 16:56:08,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 70. [2018-01-24 16:56:08,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-24 16:56:08,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 76 transitions. [2018-01-24 16:56:08,930 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 76 transitions. Word has length 29 [2018-01-24 16:56:08,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:08,931 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 76 transitions. [2018-01-24 16:56:08,931 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 16:56:08,931 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 76 transitions. [2018-01-24 16:56:08,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-01-24 16:56:08,932 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:08,932 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:08,932 INFO L371 AbstractCegarLoop]: === Iteration 8 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:08,932 INFO L82 PathProgramCache]: Analyzing trace with hash -645884181, now seen corresponding path program 1 times [2018-01-24 16:56:08,932 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:08,933 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:08,933 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:56:08,934 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:08,934 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:08,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:08,948 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:09,051 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:09,051 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:09,051 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:09,051 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 41 with the following transitions: [2018-01-24 16:56:09,051 INFO L201 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [12], [16], [20], [24], [29], [32], [42], [43], [44], [45], [46], [47], [50], [76], [77], [78], [80] [2018-01-24 16:56:09,053 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 16:56:09,053 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 16:56:09,158 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 16:56:09,158 INFO L268 AbstractInterpreter]: Visited 23 different actions 32 times. Merged at 9 different actions 9 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 26 variables. [2018-01-24 16:56:09,161 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 16:56:09,161 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:09,161 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:09,174 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:09,174 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:56:09,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:09,205 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:09,314 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:09,314 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:09,495 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:09,528 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:09,528 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:09,534 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:09,534 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:56:09,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:09,580 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:09,589 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:09,589 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:09,607 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:09,609 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:09,609 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 22 [2018-01-24 16:56:09,609 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:09,610 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 16:56:09,610 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 16:56:09,610 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=199, Invalid=263, Unknown=0, NotChecked=0, Total=462 [2018-01-24 16:56:09,610 INFO L87 Difference]: Start difference. First operand 70 states and 76 transitions. Second operand 15 states. [2018-01-24 16:56:09,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:09,747 INFO L93 Difference]: Finished difference Result 136 states and 147 transitions. [2018-01-24 16:56:09,747 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 16:56:09,747 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 40 [2018-01-24 16:56:09,748 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:09,748 INFO L225 Difference]: With dead ends: 136 [2018-01-24 16:56:09,749 INFO L226 Difference]: Without dead ends: 102 [2018-01-24 16:56:09,749 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 167 GetRequests, 147 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 164 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=199, Invalid=263, Unknown=0, NotChecked=0, Total=462 [2018-01-24 16:56:09,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-01-24 16:56:09,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 86. [2018-01-24 16:56:09,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-01-24 16:56:09,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 98 transitions. [2018-01-24 16:56:09,763 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 98 transitions. Word has length 40 [2018-01-24 16:56:09,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:09,763 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 98 transitions. [2018-01-24 16:56:09,763 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 16:56:09,763 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 98 transitions. [2018-01-24 16:56:09,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-24 16:56:09,764 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:09,764 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:09,764 INFO L371 AbstractCegarLoop]: === Iteration 9 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:09,765 INFO L82 PathProgramCache]: Analyzing trace with hash -2113361740, now seen corresponding path program 2 times [2018-01-24 16:56:09,765 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:09,765 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:09,765 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:09,765 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:09,766 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:09,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:09,780 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:09,905 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:09,906 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:09,906 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:09,906 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:09,906 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:09,906 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:09,906 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:09,913 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:56:09,913 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:56:09,927 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:09,935 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:09,938 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:09,952 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:56:09,952 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:09,985 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-01-24 16:56:09,985 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:15, output treesize:14 [2018-01-24 16:56:10,169 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:56:10,170 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:10,420 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:56:10,445 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 16:56:10,445 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [10] total 20 [2018-01-24 16:56:10,445 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:56:10,445 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 16:56:10,445 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 16:56:10,446 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=305, Unknown=0, NotChecked=0, Total=380 [2018-01-24 16:56:10,446 INFO L87 Difference]: Start difference. First operand 86 states and 98 transitions. Second operand 8 states. [2018-01-24 16:56:10,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:10,653 INFO L93 Difference]: Finished difference Result 86 states and 98 transitions. [2018-01-24 16:56:10,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 16:56:10,653 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 44 [2018-01-24 16:56:10,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:10,655 INFO L225 Difference]: With dead ends: 86 [2018-01-24 16:56:10,656 INFO L226 Difference]: Without dead ends: 81 [2018-01-24 16:56:10,656 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 120 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=138, Invalid=564, Unknown=0, NotChecked=0, Total=702 [2018-01-24 16:56:10,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-01-24 16:56:10,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2018-01-24 16:56:10,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-01-24 16:56:10,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 87 transitions. [2018-01-24 16:56:10,672 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 87 transitions. Word has length 44 [2018-01-24 16:56:10,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:10,672 INFO L432 AbstractCegarLoop]: Abstraction has 81 states and 87 transitions. [2018-01-24 16:56:10,672 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 16:56:10,672 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 87 transitions. [2018-01-24 16:56:10,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-24 16:56:10,674 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:10,674 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:10,674 INFO L371 AbstractCegarLoop]: === Iteration 10 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:10,674 INFO L82 PathProgramCache]: Analyzing trace with hash -2113361741, now seen corresponding path program 1 times [2018-01-24 16:56:10,674 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:10,675 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:10,675 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:56:10,675 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:10,676 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:10,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:10,688 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:10,728 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:56:10,729 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 16:56:10,729 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 16:56:10,729 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 16:56:10,729 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 16:56:10,729 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 16:56:10,730 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-01-24 16:56:10,730 INFO L87 Difference]: Start difference. First operand 81 states and 87 transitions. Second operand 4 states. [2018-01-24 16:56:10,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:10,788 INFO L93 Difference]: Finished difference Result 81 states and 87 transitions. [2018-01-24 16:56:10,789 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 16:56:10,789 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 44 [2018-01-24 16:56:10,789 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:10,790 INFO L225 Difference]: With dead ends: 81 [2018-01-24 16:56:10,790 INFO L226 Difference]: Without dead ends: 79 [2018-01-24 16:56:10,791 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-01-24 16:56:10,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-01-24 16:56:10,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 79. [2018-01-24 16:56:10,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-01-24 16:56:10,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 80 transitions. [2018-01-24 16:56:10,803 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 80 transitions. Word has length 44 [2018-01-24 16:56:10,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:10,803 INFO L432 AbstractCegarLoop]: Abstraction has 79 states and 80 transitions. [2018-01-24 16:56:10,803 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 16:56:10,803 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 80 transitions. [2018-01-24 16:56:10,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-01-24 16:56:10,805 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:10,805 INFO L322 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:10,805 INFO L371 AbstractCegarLoop]: === Iteration 11 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:10,805 INFO L82 PathProgramCache]: Analyzing trace with hash 1791473436, now seen corresponding path program 1 times [2018-01-24 16:56:10,805 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:10,806 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:10,806 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:10,807 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:10,807 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:10,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:10,824 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:10,962 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:56:10,962 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:10,963 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:10,963 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 74 with the following transitions: [2018-01-24 16:56:10,963 INFO L201 CegarAbsIntRunner]: [0], [1], [2], [6], [9], [11], [12], [16], [20], [24], [27], [29], [30], [34], [38], [42], [43], [44], [45], [46], [47], [50], [52], [65], [66], [70], [76], [77], [78], [80], [81] [2018-01-24 16:56:10,965 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 16:56:10,965 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 16:56:11,110 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 16:56:11,111 INFO L268 AbstractInterpreter]: Visited 31 different actions 48 times. Merged at 16 different actions 16 times. Never widened. Found 3 fixpoints after 3 different actions. Largest state had 27 variables. [2018-01-24 16:56:11,114 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 16:56:11,114 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:11,114 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:11,127 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:11,127 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:56:11,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:11,164 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:11,297 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:56:11,298 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:11,470 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:56:11,490 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:11,490 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:11,493 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:11,493 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:56:11,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:11,542 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:11,553 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:56:11,553 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:11,625 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-01-24 16:56:11,627 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:11,627 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 11, 10, 11] total 26 [2018-01-24 16:56:11,627 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:11,628 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 16:56:11,628 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 16:56:11,629 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=238, Invalid=412, Unknown=0, NotChecked=0, Total=650 [2018-01-24 16:56:11,629 INFO L87 Difference]: Start difference. First operand 79 states and 80 transitions. Second operand 18 states. [2018-01-24 16:56:11,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:11,750 INFO L93 Difference]: Finished difference Result 130 states and 133 transitions. [2018-01-24 16:56:11,751 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 16:56:11,751 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 73 [2018-01-24 16:56:11,751 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:11,752 INFO L225 Difference]: With dead ends: 130 [2018-01-24 16:56:11,752 INFO L226 Difference]: Without dead ends: 91 [2018-01-24 16:56:11,752 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 302 GetRequests, 273 SyntacticMatches, 4 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 227 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=263, Invalid=439, Unknown=0, NotChecked=0, Total=702 [2018-01-24 16:56:11,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-01-24 16:56:11,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 87. [2018-01-24 16:56:11,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-01-24 16:56:11,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 88 transitions. [2018-01-24 16:56:11,766 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 88 transitions. Word has length 73 [2018-01-24 16:56:11,766 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:11,766 INFO L432 AbstractCegarLoop]: Abstraction has 87 states and 88 transitions. [2018-01-24 16:56:11,766 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 16:56:11,766 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 88 transitions. [2018-01-24 16:56:11,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-01-24 16:56:11,768 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:11,768 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:11,768 INFO L371 AbstractCegarLoop]: === Iteration 12 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:11,768 INFO L82 PathProgramCache]: Analyzing trace with hash 526780668, now seen corresponding path program 2 times [2018-01-24 16:56:11,768 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:11,769 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:11,769 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:11,769 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:11,770 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:11,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:11,789 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:11,986 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 16:56:11,986 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:11,987 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:11,987 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:11,987 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:11,987 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:11,987 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:11,994 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:56:11,995 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:56:12,015 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:12,031 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:12,035 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:12,038 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:12,146 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 16:56:12,147 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:12,362 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 16:56:12,385 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:12,385 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:12,389 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:56:12,389 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:56:12,419 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:12,474 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:12,493 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:12,498 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:12,508 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 16:56:12,508 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:12,568 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 16:56:12,569 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:12,570 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 12, 11, 12] total 29 [2018-01-24 16:56:12,570 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:12,570 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 16:56:12,570 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 16:56:12,571 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=299, Invalid=513, Unknown=0, NotChecked=0, Total=812 [2018-01-24 16:56:12,571 INFO L87 Difference]: Start difference. First operand 87 states and 88 transitions. Second operand 20 states. [2018-01-24 16:56:12,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:12,731 INFO L93 Difference]: Finished difference Result 142 states and 145 transitions. [2018-01-24 16:56:12,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 16:56:12,731 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 81 [2018-01-24 16:56:12,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:12,732 INFO L225 Difference]: With dead ends: 142 [2018-01-24 16:56:12,732 INFO L226 Difference]: Without dead ends: 99 [2018-01-24 16:56:12,733 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 335 GetRequests, 303 SyntacticMatches, 4 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 296 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=327, Invalid=543, Unknown=0, NotChecked=0, Total=870 [2018-01-24 16:56:12,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-01-24 16:56:12,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 95. [2018-01-24 16:56:12,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-01-24 16:56:12,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 96 transitions. [2018-01-24 16:56:12,744 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 96 transitions. Word has length 81 [2018-01-24 16:56:12,744 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:12,744 INFO L432 AbstractCegarLoop]: Abstraction has 95 states and 96 transitions. [2018-01-24 16:56:12,745 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 16:56:12,745 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 96 transitions. [2018-01-24 16:56:12,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-01-24 16:56:12,746 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:12,746 INFO L322 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:12,747 INFO L371 AbstractCegarLoop]: === Iteration 13 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:12,747 INFO L82 PathProgramCache]: Analyzing trace with hash -2016762916, now seen corresponding path program 3 times [2018-01-24 16:56:12,747 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:12,748 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:12,748 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:56:12,748 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:12,748 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:12,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:12,765 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:12,898 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 16:56:12,898 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:12,898 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:12,899 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:12,899 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:12,899 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:12,899 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:12,908 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:56:12,908 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:56:12,924 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:12,931 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:12,936 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:12,942 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:12,953 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:12,964 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:12,983 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:13,016 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:13,025 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:13,026 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:13,029 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:13,096 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 16:56:13,096 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:13,262 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 16:56:13,283 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:13,283 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:13,286 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:56:13,287 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:56:13,314 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:13,357 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:13,410 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:13,472 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:13,554 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:13,659 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:13,791 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:13,960 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:14,183 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:14,206 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:14,212 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:14,229 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 16:56:14,230 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:14,304 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-01-24 16:56:14,306 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:14,306 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 13, 12, 13] total 32 [2018-01-24 16:56:14,306 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:14,307 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 16:56:14,307 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 16:56:14,307 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=367, Invalid=625, Unknown=0, NotChecked=0, Total=992 [2018-01-24 16:56:14,307 INFO L87 Difference]: Start difference. First operand 95 states and 96 transitions. Second operand 22 states. [2018-01-24 16:56:14,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:14,480 INFO L93 Difference]: Finished difference Result 154 states and 157 transitions. [2018-01-24 16:56:14,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 16:56:14,480 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 89 [2018-01-24 16:56:14,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:14,482 INFO L225 Difference]: With dead ends: 154 [2018-01-24 16:56:14,482 INFO L226 Difference]: Without dead ends: 107 [2018-01-24 16:56:14,483 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 368 GetRequests, 333 SyntacticMatches, 4 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 374 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=398, Invalid=658, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 16:56:14,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-01-24 16:56:14,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 103. [2018-01-24 16:56:14,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-01-24 16:56:14,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 104 transitions. [2018-01-24 16:56:14,499 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 104 transitions. Word has length 89 [2018-01-24 16:56:14,499 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:14,499 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 104 transitions. [2018-01-24 16:56:14,499 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 16:56:14,499 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 104 transitions. [2018-01-24 16:56:14,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-01-24 16:56:14,501 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:14,501 INFO L322 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:14,501 INFO L371 AbstractCegarLoop]: === Iteration 14 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:14,501 INFO L82 PathProgramCache]: Analyzing trace with hash 1885341628, now seen corresponding path program 4 times [2018-01-24 16:56:14,501 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:14,502 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:14,502 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:56:14,503 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:14,503 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:14,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:14,524 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:14,672 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 162 trivial. 0 not checked. [2018-01-24 16:56:14,672 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:14,673 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:14,673 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:14,673 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:14,673 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:14,673 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:14,678 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 16:56:14,678 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 16:56:14,703 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:14,706 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:14,708 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:56:14,708 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:14,709 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:14,709 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:8, output treesize:7 [2018-01-24 16:56:15,002 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 10 [2018-01-24 16:56:15,003 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:15,006 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 16:56:15,006 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:24, output treesize:17 [2018-01-24 16:56:15,054 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 136 proven. 188 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:15,054 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:15,374 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:15,420 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:15,464 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:15,509 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:15,512 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:15,514 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:15,622 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:15,657 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:15,695 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:16,368 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 136 proven. 188 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:16,388 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:16,388 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:16,391 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 16:56:16,391 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 16:56:16,445 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:16,450 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:16,452 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:56:16,453 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:16,455 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:16,456 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:8, output treesize:7 [2018-01-24 16:56:16,468 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 10 [2018-01-24 16:56:16,468 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:16,476 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 16:56:16,476 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:24, output treesize:17 [2018-01-24 16:56:16,493 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 136 proven. 188 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:16,494 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:16,680 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:16,717 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:16,751 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:16,793 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:16,833 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:16,836 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:16,839 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:16,917 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:16,920 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:16,923 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:16,926 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:17,201 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 136 proven. 188 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:17,203 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:17,203 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 26, 28, 26, 26] total 64 [2018-01-24 16:56:17,203 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:17,203 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-01-24 16:56:17,204 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-01-24 16:56:17,204 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=784, Invalid=3248, Unknown=0, NotChecked=0, Total=4032 [2018-01-24 16:56:17,204 INFO L87 Difference]: Start difference. First operand 103 states and 104 transitions. Second operand 38 states. [2018-01-24 16:56:17,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:17,712 INFO L93 Difference]: Finished difference Result 166 states and 169 transitions. [2018-01-24 16:56:17,712 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 16:56:17,712 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 97 [2018-01-24 16:56:17,712 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:17,713 INFO L225 Difference]: With dead ends: 166 [2018-01-24 16:56:17,713 INFO L226 Difference]: Without dead ends: 115 [2018-01-24 16:56:17,715 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 416 GetRequests, 322 SyntacticMatches, 17 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 2 DeprecatedPredicates, 3416 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1159, Invalid=5003, Unknown=0, NotChecked=0, Total=6162 [2018-01-24 16:56:17,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-01-24 16:56:17,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 111. [2018-01-24 16:56:17,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-01-24 16:56:17,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 112 transitions. [2018-01-24 16:56:17,726 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 112 transitions. Word has length 97 [2018-01-24 16:56:17,726 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:17,726 INFO L432 AbstractCegarLoop]: Abstraction has 111 states and 112 transitions. [2018-01-24 16:56:17,726 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-01-24 16:56:17,726 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 112 transitions. [2018-01-24 16:56:17,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-01-24 16:56:17,727 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:17,727 INFO L322 BasicCegarLoop]: trace histogram [11, 11, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:17,727 INFO L371 AbstractCegarLoop]: === Iteration 15 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:17,727 INFO L82 PathProgramCache]: Analyzing trace with hash -984566628, now seen corresponding path program 5 times [2018-01-24 16:56:17,728 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:17,728 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:17,728 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:56:17,728 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:17,728 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:17,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:17,749 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:17,932 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 16:56:17,932 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:17,932 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:17,932 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:17,932 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:17,933 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:17,933 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:17,938 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 16:56:17,938 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:56:17,951 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:17,954 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:17,958 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:17,963 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:17,972 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:17,997 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:18,027 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:18,063 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:18,272 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:18,317 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:19,028 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:19,032 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:19,037 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:19,067 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 16:56:19,067 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:19,198 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 16:56:19,220 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:19,220 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:19,223 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 16:56:19,223 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:56:19,233 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:19,238 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:19,248 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:19,261 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:19,289 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:19,327 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:19,380 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:19,452 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:19,667 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:19,960 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:20,431 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:20,470 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:20,476 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:20,484 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 16:56:20,484 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:20,500 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 16:56:20,501 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:20,502 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 13, 13, 13, 13] total 27 [2018-01-24 16:56:20,502 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:20,502 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 16:56:20,502 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 16:56:20,502 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=304, Invalid=398, Unknown=0, NotChecked=0, Total=702 [2018-01-24 16:56:20,502 INFO L87 Difference]: Start difference. First operand 111 states and 112 transitions. Second operand 16 states. [2018-01-24 16:56:20,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:20,675 INFO L93 Difference]: Finished difference Result 178 states and 181 transitions. [2018-01-24 16:56:20,675 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 16:56:20,675 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 105 [2018-01-24 16:56:20,676 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:20,676 INFO L225 Difference]: With dead ends: 178 [2018-01-24 16:56:20,676 INFO L226 Difference]: Without dead ends: 123 [2018-01-24 16:56:20,677 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 455 GetRequests, 419 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 114 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=580, Invalid=826, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 16:56:20,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2018-01-24 16:56:20,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 119. [2018-01-24 16:56:20,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-01-24 16:56:20,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 120 transitions. [2018-01-24 16:56:20,689 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 120 transitions. Word has length 105 [2018-01-24 16:56:20,689 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:20,689 INFO L432 AbstractCegarLoop]: Abstraction has 119 states and 120 transitions. [2018-01-24 16:56:20,689 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 16:56:20,690 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 120 transitions. [2018-01-24 16:56:20,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-01-24 16:56:20,690 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:20,690 INFO L322 BasicCegarLoop]: trace histogram [12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:20,690 INFO L371 AbstractCegarLoop]: === Iteration 16 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:20,691 INFO L82 PathProgramCache]: Analyzing trace with hash -1299764612, now seen corresponding path program 6 times [2018-01-24 16:56:20,691 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:20,691 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:20,691 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:56:20,692 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:20,692 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:20,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:20,707 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:20,950 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 16:56:20,951 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:20,951 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:20,951 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:20,951 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:20,951 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:20,951 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:20,956 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 16:56:20,956 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 16:56:20,969 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:20,972 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:20,976 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:20,980 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:20,989 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:21,010 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:21,049 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:21,110 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:21,190 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:21,341 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:21,474 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:21,712 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:21,714 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:21,717 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:21,733 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 16:56:21,733 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:21,933 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 16:56:21,955 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:21,955 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:21,962 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 16:56:21,962 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 16:56:21,989 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:22,033 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:22,083 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:22,154 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:22,235 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:22,331 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:22,436 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:22,548 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:22,700 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:22,948 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:23,192 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:23,490 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 16:56:23,527 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:23,534 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:23,543 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 16:56:23,543 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:23,563 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2018-01-24 16:56:23,565 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:23,565 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 14, 14, 14, 14] total 29 [2018-01-24 16:56:23,565 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:23,565 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 16:56:23,565 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 16:56:23,566 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=355, Invalid=457, Unknown=0, NotChecked=0, Total=812 [2018-01-24 16:56:23,566 INFO L87 Difference]: Start difference. First operand 119 states and 120 transitions. Second operand 17 states. [2018-01-24 16:56:23,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:23,752 INFO L93 Difference]: Finished difference Result 190 states and 193 transitions. [2018-01-24 16:56:23,752 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 16:56:23,752 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 113 [2018-01-24 16:56:23,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:23,753 INFO L225 Difference]: With dead ends: 190 [2018-01-24 16:56:23,753 INFO L226 Difference]: Without dead ends: 131 [2018-01-24 16:56:23,754 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 451 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 131 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=680, Invalid=960, Unknown=0, NotChecked=0, Total=1640 [2018-01-24 16:56:23,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2018-01-24 16:56:23,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 127. [2018-01-24 16:56:23,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127 states. [2018-01-24 16:56:23,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 128 transitions. [2018-01-24 16:56:23,767 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 128 transitions. Word has length 113 [2018-01-24 16:56:23,767 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:23,767 INFO L432 AbstractCegarLoop]: Abstraction has 127 states and 128 transitions. [2018-01-24 16:56:23,767 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 16:56:23,767 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 128 transitions. [2018-01-24 16:56:23,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-01-24 16:56:23,768 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:23,768 INFO L322 BasicCegarLoop]: trace histogram [13, 13, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:23,768 INFO L371 AbstractCegarLoop]: === Iteration 17 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:23,769 INFO L82 PathProgramCache]: Analyzing trace with hash -1012012708, now seen corresponding path program 7 times [2018-01-24 16:56:23,769 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:23,769 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:23,769 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:56:23,769 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:23,769 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:23,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:23,791 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:23,994 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 16:56:23,995 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:23,995 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:23,995 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:23,995 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:23,995 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:23,995 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:24,000 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:24,000 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:56:24,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:24,029 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:24,149 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 16:56:24,149 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:24,438 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 16:56:24,457 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:24,458 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:24,460 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:24,460 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 16:56:24,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:24,530 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:24,546 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 16:56:24,546 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:24,641 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-01-24 16:56:24,643 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:24,643 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16, 17, 16, 17] total 44 [2018-01-24 16:56:24,643 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:24,643 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 16:56:24,643 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 16:56:24,644 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=709, Invalid=1183, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 16:56:24,644 INFO L87 Difference]: Start difference. First operand 127 states and 128 transitions. Second operand 30 states. [2018-01-24 16:56:24,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:24,801 INFO L93 Difference]: Finished difference Result 202 states and 205 transitions. [2018-01-24 16:56:24,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 16:56:24,802 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 121 [2018-01-24 16:56:24,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:24,802 INFO L225 Difference]: With dead ends: 202 [2018-01-24 16:56:24,802 INFO L226 Difference]: Without dead ends: 139 [2018-01-24 16:56:24,803 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 500 GetRequests, 453 SyntacticMatches, 4 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 776 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=752, Invalid=1228, Unknown=0, NotChecked=0, Total=1980 [2018-01-24 16:56:24,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-01-24 16:56:24,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 135. [2018-01-24 16:56:24,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-24 16:56:24,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 136 transitions. [2018-01-24 16:56:24,815 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 136 transitions. Word has length 121 [2018-01-24 16:56:24,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:24,816 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 136 transitions. [2018-01-24 16:56:24,816 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 16:56:24,816 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 136 transitions. [2018-01-24 16:56:24,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2018-01-24 16:56:24,816 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:24,817 INFO L322 BasicCegarLoop]: trace histogram [14, 14, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:24,817 INFO L371 AbstractCegarLoop]: === Iteration 18 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:24,817 INFO L82 PathProgramCache]: Analyzing trace with hash 70218044, now seen corresponding path program 8 times [2018-01-24 16:56:24,817 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:24,818 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:24,818 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 16:56:24,818 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:24,818 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:24,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:24,841 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:25,062 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 16:56:25,063 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:25,063 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:25,063 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:25,063 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:25,063 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:25,063 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:25,069 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:56:25,069 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:56:25,085 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:25,103 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:25,106 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:25,110 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:25,258 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 16:56:25,258 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:25,582 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 16:56:25,602 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:25,602 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:25,605 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 16:56:25,606 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:56:25,626 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:25,691 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:25,717 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:25,723 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:25,742 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 16:56:25,742 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:25,849 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 16:56:25,850 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:25,850 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 18, 17, 18] total 47 [2018-01-24 16:56:25,850 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:25,851 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-01-24 16:56:25,851 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-01-24 16:56:25,851 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=812, Invalid=1350, Unknown=0, NotChecked=0, Total=2162 [2018-01-24 16:56:25,852 INFO L87 Difference]: Start difference. First operand 135 states and 136 transitions. Second operand 32 states. [2018-01-24 16:56:26,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:26,033 INFO L93 Difference]: Finished difference Result 214 states and 217 transitions. [2018-01-24 16:56:26,033 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 16:56:26,033 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 129 [2018-01-24 16:56:26,033 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:26,034 INFO L225 Difference]: With dead ends: 214 [2018-01-24 16:56:26,034 INFO L226 Difference]: Without dead ends: 147 [2018-01-24 16:56:26,035 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 533 GetRequests, 483 SyntacticMatches, 4 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 899 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=858, Invalid=1398, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 16:56:26,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-01-24 16:56:26,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 143. [2018-01-24 16:56:26,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-01-24 16:56:26,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 144 transitions. [2018-01-24 16:56:26,047 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 144 transitions. Word has length 129 [2018-01-24 16:56:26,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:26,047 INFO L432 AbstractCegarLoop]: Abstraction has 143 states and 144 transitions. [2018-01-24 16:56:26,048 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-01-24 16:56:26,048 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 144 transitions. [2018-01-24 16:56:26,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-01-24 16:56:26,048 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:26,049 INFO L322 BasicCegarLoop]: trace histogram [15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:26,049 INFO L371 AbstractCegarLoop]: === Iteration 19 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:26,049 INFO L82 PathProgramCache]: Analyzing trace with hash 523649564, now seen corresponding path program 9 times [2018-01-24 16:56:26,049 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:26,049 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:26,050 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:56:26,050 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:26,050 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:26,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:26,066 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:26,242 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 16:56:26,243 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:26,243 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:26,243 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:26,243 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:26,243 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:26,243 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:26,248 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:56:26,248 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:56:26,276 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,283 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,287 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,293 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,303 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,323 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,345 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,359 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,384 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,402 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,491 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,553 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,627 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,714 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,921 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:26,923 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:26,927 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:26,949 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 16:56:26,949 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:27,185 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 16:56:27,206 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:27,206 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:27,209 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 16:56:27,209 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 16:56:27,233 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:27,284 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:27,339 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:27,399 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:27,467 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:27,559 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:27,679 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:27,825 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:27,981 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:28,183 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:28,426 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:28,764 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:29,115 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:29,559 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:30,064 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 16:56:30,106 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:30,113 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:30,514 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 16:56:30,515 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:30,992 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 392 trivial. 0 not checked. [2018-01-24 16:56:30,994 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:30,994 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 17, 17, 18, 19] total 66 [2018-01-24 16:56:30,994 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:30,994 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 16:56:30,995 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 16:56:30,995 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1555, Invalid=2735, Unknown=0, NotChecked=0, Total=4290 [2018-01-24 16:56:30,995 INFO L87 Difference]: Start difference. First operand 143 states and 144 transitions. Second operand 20 states. [2018-01-24 16:56:31,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:31,139 INFO L93 Difference]: Finished difference Result 226 states and 229 transitions. [2018-01-24 16:56:31,139 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 16:56:31,139 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 137 [2018-01-24 16:56:31,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:31,140 INFO L225 Difference]: With dead ends: 226 [2018-01-24 16:56:31,140 INFO L226 Difference]: Without dead ends: 155 [2018-01-24 16:56:31,141 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 595 GetRequests, 528 SyntacticMatches, 2 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2061 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1620, Invalid=2802, Unknown=0, NotChecked=0, Total=4422 [2018-01-24 16:56:31,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-01-24 16:56:31,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 151. [2018-01-24 16:56:31,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-01-24 16:56:31,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 152 transitions. [2018-01-24 16:56:31,156 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 152 transitions. Word has length 137 [2018-01-24 16:56:31,156 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:31,156 INFO L432 AbstractCegarLoop]: Abstraction has 151 states and 152 transitions. [2018-01-24 16:56:31,156 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 16:56:31,156 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 152 transitions. [2018-01-24 16:56:31,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2018-01-24 16:56:31,157 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:31,157 INFO L322 BasicCegarLoop]: trace histogram [16, 16, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:31,158 INFO L371 AbstractCegarLoop]: === Iteration 20 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:31,158 INFO L82 PathProgramCache]: Analyzing trace with hash 2142034940, now seen corresponding path program 10 times [2018-01-24 16:56:31,158 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:31,159 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:31,159 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:56:31,159 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:31,159 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:31,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:31,183 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:31,464 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 450 trivial. 0 not checked. [2018-01-24 16:56:31,464 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:31,464 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:31,465 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:31,465 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:31,465 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:31,465 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:31,470 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 16:56:31,471 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 16:56:31,512 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:31,516 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:31,519 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:56:31,519 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:31,520 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:31,521 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:8, output treesize:7 [2018-01-24 16:56:32,057 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 10 [2018-01-24 16:56:32,058 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:32,065 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 16:56:32,065 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:24, output treesize:17 [2018-01-24 16:56:32,136 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 406 proven. 494 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:32,136 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:32,667 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:32,719 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:32,721 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:32,722 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:32,725 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:32,784 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:32,785 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:32,787 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:32,789 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:32,839 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:32,843 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:32,846 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:32,850 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:33,247 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:33,298 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:33,345 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:33,559 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:33,768 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:33,826 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:33,828 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:33,829 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:33,832 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:33,892 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:33,894 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:33,896 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:33,898 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:33,980 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:33,983 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:33,985 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:33,989 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:34,068 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:34,069 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:34,071 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:34,075 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:34,175 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:34,177 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:34,178 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:34,181 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:35,038 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 406 proven. 494 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:35,057 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:35,057 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:35,060 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 16:56:35,061 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 16:56:35,132 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:35,139 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:35,141 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-01-24 16:56:35,141 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:35,142 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-24 16:56:35,142 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:8, output treesize:7 [2018-01-24 16:56:35,156 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 10 [2018-01-24 16:56:35,156 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-24 16:56:35,160 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-01-24 16:56:35,160 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:24, output treesize:17 [2018-01-24 16:56:35,197 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 406 proven. 494 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:35,197 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:35,735 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:35,737 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:35,738 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:35,740 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:35,742 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:35,744 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:35,745 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:35,930 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:35,979 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:36,026 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:36,072 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:36,117 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:36,310 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:36,481 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:36,484 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:36,486 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:36,488 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:36,490 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 16 [2018-01-24 16:56:36,492 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:36,493 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:36,495 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:36,816 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:36,818 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:36,821 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 9 [2018-01-24 16:56:37,269 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 406 proven. 494 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 16:56:37,270 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 16:56:37,271 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 38, 39, 38, 38] total 96 [2018-01-24 16:56:37,271 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 16:56:37,271 INFO L409 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-01-24 16:56:37,271 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-01-24 16:56:37,273 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1826, Invalid=7294, Unknown=0, NotChecked=0, Total=9120 [2018-01-24 16:56:37,273 INFO L87 Difference]: Start difference. First operand 151 states and 152 transitions. Second operand 56 states. [2018-01-24 16:56:38,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 16:56:38,157 INFO L93 Difference]: Finished difference Result 238 states and 241 transitions. [2018-01-24 16:56:38,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 16:56:38,158 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 145 [2018-01-24 16:56:38,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 16:56:38,159 INFO L225 Difference]: With dead ends: 238 [2018-01-24 16:56:38,159 INFO L226 Difference]: Without dead ends: 163 [2018-01-24 16:56:38,161 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 620 GetRequests, 460 SyntacticMatches, 45 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 4 DeprecatedPredicates, 10077 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=2642, Invalid=10930, Unknown=0, NotChecked=0, Total=13572 [2018-01-24 16:56:38,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-01-24 16:56:38,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 159. [2018-01-24 16:56:38,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-01-24 16:56:38,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 160 transitions. [2018-01-24 16:56:38,174 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 160 transitions. Word has length 145 [2018-01-24 16:56:38,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 16:56:38,174 INFO L432 AbstractCegarLoop]: Abstraction has 159 states and 160 transitions. [2018-01-24 16:56:38,174 INFO L433 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-01-24 16:56:38,174 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 160 transitions. [2018-01-24 16:56:38,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 154 [2018-01-24 16:56:38,175 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 16:56:38,175 INFO L322 BasicCegarLoop]: trace histogram [17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 16:56:38,175 INFO L371 AbstractCegarLoop]: === Iteration 21 === [fooErr1RequiresViolation, fooErr0RequiresViolation, fooErr2RequiresViolation, fooErr3RequiresViolation, mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr9RequiresViolation, mainErr0RequiresViolation, mainErr3RequiresViolation, mainErr7RequiresViolation, mainErr11RequiresViolation, mainErr8RequiresViolation, mainErr10RequiresViolation, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr6RequiresViolation, mainErr12EnsuresViolation]=== [2018-01-24 16:56:38,175 INFO L82 PathProgramCache]: Analyzing trace with hash 1883094748, now seen corresponding path program 11 times [2018-01-24 16:56:38,175 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 16:56:38,176 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:38,176 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 16:56:38,176 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 16:56:38,176 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 16:56:38,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 16:56:38,192 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 16:56:38,433 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 16:56:38,433 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:38,433 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 16:56:38,433 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 16:56:38,433 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 16:56:38,433 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:38,434 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 16:56:38,439 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 16:56:38,439 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:56:38,449 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,463 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,478 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,491 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,496 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,511 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,576 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,607 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,643 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,658 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,762 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,795 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,816 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,855 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,890 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:38,923 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:44,054 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:44,070 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:44,078 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:44,103 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 16:56:44,104 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 16:56:44,416 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 16:56:44,440 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 16:56:44,440 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 16:56:44,443 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 16:56:44,443 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 16:56:44,455 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:44,461 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:44,472 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:44,486 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:44,508 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:44,538 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:44,609 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:44,700 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:44,824 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:44,981 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:45,534 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:46,269 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:47,199 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:48,327 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:51,370 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:55,106 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command Received shutdown request... [2018-01-24 16:56:57,724 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 16:56:57,811 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 16:56:57,819 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 16:56:57,821 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-01-24 16:56:57,822 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 16:56:57,825 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 16:56:57,825 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 04:56:57 BoogieIcfgContainer [2018-01-24 16:56:57,825 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 16:56:57,826 INFO L168 Benchmark]: Toolchain (without parser) took 57648.31 ms. Allocated memory was 303.0 MB in the beginning and 683.7 MB in the end (delta: 380.6 MB). Free memory was 262.9 MB in the beginning and 594.7 MB in the end (delta: -331.7 MB). Peak memory consumption was 48.9 MB. Max. memory is 5.3 GB. [2018-01-24 16:56:57,826 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 303.0 MB. Free memory is still 268.9 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 16:56:57,827 INFO L168 Benchmark]: CACSL2BoogieTranslator took 208.29 ms. Allocated memory is still 303.0 MB. Free memory was 261.9 MB in the beginning and 251.7 MB in the end (delta: 10.2 MB). Peak memory consumption was 10.2 MB. Max. memory is 5.3 GB. [2018-01-24 16:56:57,827 INFO L168 Benchmark]: Boogie Preprocessor took 43.10 ms. Allocated memory is still 303.0 MB. Free memory was 251.7 MB in the beginning and 249.7 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 16:56:57,827 INFO L168 Benchmark]: RCFGBuilder took 318.06 ms. Allocated memory is still 303.0 MB. Free memory was 249.7 MB in the beginning and 231.8 MB in the end (delta: 18.0 MB). Peak memory consumption was 18.0 MB. Max. memory is 5.3 GB. [2018-01-24 16:56:57,827 INFO L168 Benchmark]: TraceAbstraction took 57071.92 ms. Allocated memory was 303.0 MB in the beginning and 683.7 MB in the end (delta: 380.6 MB). Free memory was 231.8 MB in the beginning and 594.7 MB in the end (delta: -362.9 MB). Peak memory consumption was 17.7 MB. Max. memory is 5.3 GB. [2018-01-24 16:56:57,828 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 303.0 MB. Free memory is still 268.9 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 208.29 ms. Allocated memory is still 303.0 MB. Free memory was 261.9 MB in the beginning and 251.7 MB in the end (delta: 10.2 MB). Peak memory consumption was 10.2 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 43.10 ms. Allocated memory is still 303.0 MB. Free memory was 251.7 MB in the beginning and 249.7 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 318.06 ms. Allocated memory is still 303.0 MB. Free memory was 249.7 MB in the beginning and 231.8 MB in the end (delta: 18.0 MB). Peak memory consumption was 18.0 MB. Max. memory is 5.3 GB. * TraceAbstraction took 57071.92 ms. Allocated memory was 303.0 MB in the beginning and 683.7 MB in the end (delta: 380.6 MB). Free memory was 231.8 MB in the beginning and 594.7 MB in the end (delta: -362.9 MB). Peak memory consumption was 17.7 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 18 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 226 LocStat_NO_SUPPORTING_DISEQUALITIES : 34 LocStat_NO_DISJUNCTIONS : -36 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 25 TransStat_MAX_WEQGRAPH_SIZE : 0 TransStat_MAX_SIZEOF_WEQEDGELABEL : 0 TransStat_NO_SUPPORTING_EQUALITIES : 65 TransStat_NO_SUPPORTING_DISEQUALITIES : 4 TransStat_NO_DISJUNCTIONS : 26 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.889174 RENAME_VARIABLES(MILLISECONDS) : 0.625415 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.828698 PROJECTAWAY(MILLISECONDS) : 0.345886 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.001184 DISJOIN(MILLISECONDS) : 0.539188 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.677231 ADD_EQUALITY(MILLISECONDS) : 0.082390 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.019234 #CONJOIN_DISJUNCTIVE : 39 #RENAME_VARIABLES : 68 #UNFREEZE : 0 #CONJOIN : 96 #PROJECTAWAY : 61 #ADD_WEAK_EQUALITY : 9 #DISJOIN : 6 #RENAME_VARIABLES_DISJUNCTIVE : 65 #ADD_EQUALITY : 67 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 2 - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 22 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 259 LocStat_NO_SUPPORTING_DISEQUALITIES : 46 LocStat_NO_DISJUNCTIONS : -44 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 29 TransStat_MAX_WEQGRAPH_SIZE : 0 TransStat_MAX_SIZEOF_WEQEDGELABEL : 0 TransStat_NO_SUPPORTING_EQUALITIES : 67 TransStat_NO_SUPPORTING_DISEQUALITIES : 4 TransStat_NO_DISJUNCTIONS : 30 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.829185 RENAME_VARIABLES(MILLISECONDS) : 0.328813 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.347306 PROJECTAWAY(MILLISECONDS) : 0.060365 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.001114 DISJOIN(MILLISECONDS) : 0.580741 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.367112 ADD_EQUALITY(MILLISECONDS) : 0.027182 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.014826 #CONJOIN_DISJUNCTIVE : 51 #RENAME_VARIABLES : 92 #UNFREEZE : 0 #CONJOIN : 108 #PROJECTAWAY : 77 #ADD_WEAK_EQUALITY : 9 #DISJOIN : 10 #RENAME_VARIABLES_DISJUNCTIVE : 89 #ADD_EQUALITY : 69 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 2 - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 29 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 334 LocStat_NO_SUPPORTING_DISEQUALITIES : 68 LocStat_NO_DISJUNCTIONS : -58 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 37 TransStat_MAX_WEQGRAPH_SIZE : 0 TransStat_MAX_SIZEOF_WEQEDGELABEL : 0 TransStat_NO_SUPPORTING_EQUALITIES : 86 TransStat_NO_SUPPORTING_DISEQUALITIES : 7 TransStat_NO_DISJUNCTIONS : 40 TransStat_MAX_NO_DISJUNCTIONS : 4 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.439451 RENAME_VARIABLES(MILLISECONDS) : 0.223387 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.384680 PROJECTAWAY(MILLISECONDS) : 0.103246 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.001725 DISJOIN(MILLISECONDS) : 0.457669 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.262276 ADD_EQUALITY(MILLISECONDS) : 0.033231 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.021527 #CONJOIN_DISJUNCTIVE : 67 #RENAME_VARIABLES : 127 #UNFREEZE : 0 #CONJOIN : 163 #PROJECTAWAY : 105 #ADD_WEAK_EQUALITY : 12 #DISJOIN : 4 #RENAME_VARIABLES_DISJUNCTIVE : 121 #ADD_EQUALITY : 81 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 4 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 625). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 625). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 627). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 627). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 637). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 634). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 639). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 634). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 636). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 637). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 639). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 639). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 639). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 636). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 637). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 637). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 629]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 629). Cancelled while BasicCegarLoop was analyzing trace of length 154 with TraceHistMax 17, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 53 locations, 17 error locations. TIMEOUT Result, 57.0s OverallTime, 21 OverallIterations, 17 TraceHistogramMax, 5.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 570 SDtfs, 3209 SDslu, 3989 SDs, 0 SdLazy, 3410 SolverSat, 726 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 5259 GetRequests, 4495 SyntacticMatches, 98 SemanticMatches, 666 ConstructedPredicates, 0 IntricatePredicates, 6 DeprecatedPredicates, 19607 ImplicationChecksByTransitivity, 16.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=159occurred in iteration=20, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.5s AbstIntTime, 3 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 20 MinimizatonAttempts, 97 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 10.3s SatisfiabilityAnalysisTime, 19.6s InterpolantComputationTime, 3803 NumberOfCodeBlocks, 3707 NumberOfCodeBlocksAsserted, 143 NumberOfCheckSat, 6179 ConstructedInterpolants, 660 QuantifiedInterpolants, 4379007 SizeOfPredicates, 112 NumberOfNonLiveVariables, 7725 ConjunctsInSsa, 470 ConjunctsInUnsatCore, 78 InterpolantComputations, 7 PerfectInterpolantSequences, 11842/24408 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_16-56-57-840.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_16-56-57-840.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_16-56-57-840.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-1-2018-01-24_16-56-57-840.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-1-2018-01-24_16-56-57-840.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-2-2018-01-24_16-56-57-840.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-2-2018-01-24_16-56-57-840.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_16-56-57-840.csv Completed graceful shutdown