java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf -i ../../../trunk/examples/svcomp/loop-acceleration/array3_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 17:41:10,959 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 17:41:10,961 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 17:41:10,976 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 17:41:10,976 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 17:41:10,977 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 17:41:10,978 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 17:41:10,980 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 17:41:10,982 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 17:41:10,983 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 17:41:10,984 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 17:41:10,984 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 17:41:10,985 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 17:41:10,986 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 17:41:10,987 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 17:41:10,990 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 17:41:10,992 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 17:41:10,994 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 17:41:10,995 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 17:41:10,997 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 17:41:10,999 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 17:41:10,999 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 17:41:11,000 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 17:41:11,001 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 17:41:11,002 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 17:41:11,003 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 17:41:11,003 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 17:41:11,004 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 17:41:11,004 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 17:41:11,004 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 17:41:11,005 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 17:41:11,005 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf [2018-01-24 17:41:11,014 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 17:41:11,014 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 17:41:11,015 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 17:41:11,015 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 17:41:11,015 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 17:41:11,015 INFO L133 SettingsManager]: * Deactivate Weak Equivalences=true [2018-01-24 17:41:11,015 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 17:41:11,015 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 17:41:11,016 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 17:41:11,016 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 17:41:11,016 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 17:41:11,016 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 17:41:11,016 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 17:41:11,017 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 17:41:11,017 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 17:41:11,017 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 17:41:11,017 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 17:41:11,017 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 17:41:11,017 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 17:41:11,017 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 17:41:11,018 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 17:41:11,018 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 17:41:11,018 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 17:41:11,018 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 17:41:11,018 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 17:41:11,019 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 17:41:11,019 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 17:41:11,019 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 17:41:11,019 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 17:41:11,019 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 17:41:11,019 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 17:41:11,019 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 17:41:11,019 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 17:41:11,020 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 17:41:11,020 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 17:41:11,020 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 17:41:11,053 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 17:41:11,064 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 17:41:11,067 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 17:41:11,068 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 17:41:11,068 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 17:41:11,069 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/array3_false-valid-deref.i [2018-01-24 17:41:11,167 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 17:41:11,172 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 17:41:11,173 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 17:41:11,173 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 17:41:11,178 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 17:41:11,179 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 05:41:11" (1/1) ... [2018-01-24 17:41:11,182 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1aa3187e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 05:41:11, skipping insertion in model container [2018-01-24 17:41:11,182 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 05:41:11" (1/1) ... [2018-01-24 17:41:11,196 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 17:41:11,210 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 17:41:11,324 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 17:41:11,336 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 17:41:11,340 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 05:41:11 WrapperNode [2018-01-24 17:41:11,341 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 17:41:11,342 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 17:41:11,342 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 17:41:11,342 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 17:41:11,353 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 05:41:11" (1/1) ... [2018-01-24 17:41:11,354 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 05:41:11" (1/1) ... [2018-01-24 17:41:11,360 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 05:41:11" (1/1) ... [2018-01-24 17:41:11,361 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 05:41:11" (1/1) ... [2018-01-24 17:41:11,362 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 05:41:11" (1/1) ... [2018-01-24 17:41:11,366 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 05:41:11" (1/1) ... [2018-01-24 17:41:11,366 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 05:41:11" (1/1) ... [2018-01-24 17:41:11,368 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 17:41:11,368 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 17:41:11,368 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 17:41:11,368 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 17:41:11,369 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 05:41:11" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 17:41:11,427 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 17:41:11,428 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 17:41:11,428 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 17:41:11,428 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 17:41:11,428 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 17:41:11,428 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 17:41:11,428 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 17:41:11,429 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 17:41:11,429 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 17:41:11,429 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 17:41:11,567 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 17:41:11,567 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 05:41:11 BoogieIcfgContainer [2018-01-24 17:41:11,568 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 17:41:11,568 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 17:41:11,569 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 17:41:11,571 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 17:41:11,572 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 05:41:11" (1/3) ... [2018-01-24 17:41:11,573 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@55f0bf5b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 05:41:11, skipping insertion in model container [2018-01-24 17:41:11,573 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 05:41:11" (2/3) ... [2018-01-24 17:41:11,574 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@55f0bf5b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 05:41:11, skipping insertion in model container [2018-01-24 17:41:11,574 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 05:41:11" (3/3) ... [2018-01-24 17:41:11,575 INFO L105 eAbstractionObserver]: Analyzing ICFG array3_false-valid-deref.i [2018-01-24 17:41:11,584 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 17:41:11,589 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2018-01-24 17:41:11,630 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 17:41:11,630 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 17:41:11,630 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 17:41:11,630 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 17:41:11,631 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 17:41:11,631 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 17:41:11,631 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 17:41:11,631 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 17:41:11,632 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 17:41:11,647 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states. [2018-01-24 17:41:11,652 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 17:41:11,652 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:11,653 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:11,653 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:11,657 INFO L82 PathProgramCache]: Analyzing trace with hash 1213833872, now seen corresponding path program 1 times [2018-01-24 17:41:11,659 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:11,700 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:11,701 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:11,701 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:11,701 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:11,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:11,742 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:11,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 17:41:11,855 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 17:41:11,855 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 17:41:11,855 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 17:41:11,857 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 17:41:11,867 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 17:41:11,868 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 17:41:11,870 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 4 states. [2018-01-24 17:41:11,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:11,996 INFO L93 Difference]: Finished difference Result 69 states and 95 transitions. [2018-01-24 17:41:11,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 17:41:11,997 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 8 [2018-01-24 17:41:11,997 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:12,004 INFO L225 Difference]: With dead ends: 69 [2018-01-24 17:41:12,004 INFO L226 Difference]: Without dead ends: 35 [2018-01-24 17:41:12,007 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 17:41:12,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-01-24 17:41:12,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 31. [2018-01-24 17:41:12,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-01-24 17:41:12,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 32 transitions. [2018-01-24 17:41:12,097 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 32 transitions. Word has length 8 [2018-01-24 17:41:12,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:12,098 INFO L432 AbstractCegarLoop]: Abstraction has 31 states and 32 transitions. [2018-01-24 17:41:12,098 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 17:41:12,098 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 32 transitions. [2018-01-24 17:41:12,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-01-24 17:41:12,099 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:12,099 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:12,099 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:12,099 INFO L82 PathProgramCache]: Analyzing trace with hash -863334142, now seen corresponding path program 1 times [2018-01-24 17:41:12,100 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:12,101 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:12,101 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:12,101 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:12,101 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:12,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:12,115 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:12,180 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 17:41:12,180 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 17:41:12,180 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 17:41:12,181 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 17:41:12,182 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 17:41:12,183 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 17:41:12,183 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-24 17:41:12,183 INFO L87 Difference]: Start difference. First operand 31 states and 32 transitions. Second operand 6 states. [2018-01-24 17:41:12,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:12,252 INFO L93 Difference]: Finished difference Result 35 states and 36 transitions. [2018-01-24 17:41:12,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 17:41:12,252 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 16 [2018-01-24 17:41:12,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:12,253 INFO L225 Difference]: With dead ends: 35 [2018-01-24 17:41:12,253 INFO L226 Difference]: Without dead ends: 34 [2018-01-24 17:41:12,254 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-24 17:41:12,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-01-24 17:41:12,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 29. [2018-01-24 17:41:12,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2018-01-24 17:41:12,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 30 transitions. [2018-01-24 17:41:12,259 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 30 transitions. Word has length 16 [2018-01-24 17:41:12,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:12,260 INFO L432 AbstractCegarLoop]: Abstraction has 29 states and 30 transitions. [2018-01-24 17:41:12,260 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 17:41:12,260 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 30 transitions. [2018-01-24 17:41:12,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-24 17:41:12,261 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:12,261 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:12,262 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:12,262 INFO L82 PathProgramCache]: Analyzing trace with hash -1135364244, now seen corresponding path program 1 times [2018-01-24 17:41:12,262 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:12,263 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:12,264 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:12,264 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:12,264 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:12,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:12,278 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:12,319 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 17:41:12,319 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:12,319 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:12,320 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 29 with the following transitions: [2018-01-24 17:41:12,322 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [11], [13], [15], [17], [21], [25], [26], [27], [32], [37], [39], [55], [56], [57] [2018-01-24 17:41:12,372 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 17:41:12,372 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 17:41:12,489 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 17:41:12,490 INFO L268 AbstractInterpreter]: Visited 17 different actions 29 times. Merged at 11 different actions 11 times. Never widened. Found 3 fixpoints after 3 different actions. Largest state had 5 variables. [2018-01-24 17:41:12,507 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 17:41:12,507 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:12,507 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:12,514 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:12,514 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 17:41:12,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:12,539 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:12,556 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 17:41:12,556 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:12,605 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 17:41:12,627 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:12,627 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:12,631 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:12,631 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 17:41:12,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:12,649 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:12,655 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 17:41:12,655 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:12,670 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 17:41:12,671 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:12,671 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-01-24 17:41:12,672 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:12,672 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 17:41:12,672 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 17:41:12,673 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-24 17:41:12,673 INFO L87 Difference]: Start difference. First operand 29 states and 30 transitions. Second operand 5 states. [2018-01-24 17:41:12,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:12,742 INFO L93 Difference]: Finished difference Result 58 states and 60 transitions. [2018-01-24 17:41:12,742 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 17:41:12,742 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2018-01-24 17:41:12,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:12,743 INFO L225 Difference]: With dead ends: 58 [2018-01-24 17:41:12,743 INFO L226 Difference]: Without dead ends: 44 [2018-01-24 17:41:12,744 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-24 17:41:12,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-01-24 17:41:12,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 33. [2018-01-24 17:41:12,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-01-24 17:41:12,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 34 transitions. [2018-01-24 17:41:12,748 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 34 transitions. Word has length 28 [2018-01-24 17:41:12,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:12,748 INFO L432 AbstractCegarLoop]: Abstraction has 33 states and 34 transitions. [2018-01-24 17:41:12,748 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 17:41:12,748 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 34 transitions. [2018-01-24 17:41:12,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 17:41:12,749 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:12,749 INFO L322 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:12,749 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:12,749 INFO L82 PathProgramCache]: Analyzing trace with hash 1230203493, now seen corresponding path program 2 times [2018-01-24 17:41:12,750 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:12,750 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:12,750 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:12,750 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:12,751 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:12,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:12,759 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:12,811 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 17:41:12,812 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:12,812 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:12,812 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:12,812 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:12,812 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:12,813 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:12,825 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 17:41:12,825 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:12,830 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:12,834 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:12,834 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:12,836 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:12,842 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 17:41:12,842 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:12,941 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 17:41:12,975 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:12,975 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:12,981 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 17:41:12,981 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:12,989 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:12,997 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:13,004 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:13,009 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:13,016 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 17:41:13,016 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:13,028 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 17:41:13,030 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:13,030 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-01-24 17:41:13,030 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:13,031 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 17:41:13,031 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 17:41:13,032 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-24 17:41:13,032 INFO L87 Difference]: Start difference. First operand 33 states and 34 transitions. Second operand 6 states. [2018-01-24 17:41:13,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:13,118 INFO L93 Difference]: Finished difference Result 67 states and 70 transitions. [2018-01-24 17:41:13,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 17:41:13,118 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 32 [2018-01-24 17:41:13,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:13,119 INFO L225 Difference]: With dead ends: 67 [2018-01-24 17:41:13,119 INFO L226 Difference]: Without dead ends: 53 [2018-01-24 17:41:13,120 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-24 17:41:13,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-01-24 17:41:13,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 37. [2018-01-24 17:41:13,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-01-24 17:41:13,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 38 transitions. [2018-01-24 17:41:13,127 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 38 transitions. Word has length 32 [2018-01-24 17:41:13,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:13,128 INFO L432 AbstractCegarLoop]: Abstraction has 37 states and 38 transitions. [2018-01-24 17:41:13,128 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 17:41:13,128 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 38 transitions. [2018-01-24 17:41:13,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-24 17:41:13,129 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:13,129 INFO L322 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:13,130 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:13,130 INFO L82 PathProgramCache]: Analyzing trace with hash 417265886, now seen corresponding path program 3 times [2018-01-24 17:41:13,130 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:13,131 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:13,131 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:13,131 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:13,132 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:13,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:13,142 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:13,208 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 17:41:13,208 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:13,208 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:13,209 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:13,209 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:13,209 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:13,209 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:13,214 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 17:41:13,214 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 17:41:13,223 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:13,225 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:13,227 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:13,227 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:13,229 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:13,242 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-24 17:41:13,242 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:13,293 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-24 17:41:13,313 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:13,314 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:13,317 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 17:41:13,318 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 17:41:13,323 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:13,326 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:13,332 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:13,338 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:13,341 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:13,346 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-24 17:41:13,346 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:13,362 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-24 17:41:13,363 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:13,363 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 4, 4] total 13 [2018-01-24 17:41:13,363 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:13,364 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 17:41:13,364 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 17:41:13,364 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2018-01-24 17:41:13,364 INFO L87 Difference]: Start difference. First operand 37 states and 38 transitions. Second operand 10 states. [2018-01-24 17:41:13,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:13,486 INFO L93 Difference]: Finished difference Result 76 states and 80 transitions. [2018-01-24 17:41:13,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 17:41:13,488 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 36 [2018-01-24 17:41:13,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:13,489 INFO L225 Difference]: With dead ends: 76 [2018-01-24 17:41:13,490 INFO L226 Difference]: Without dead ends: 62 [2018-01-24 17:41:13,490 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 138 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2018-01-24 17:41:13,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-01-24 17:41:13,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 46. [2018-01-24 17:41:13,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-01-24 17:41:13,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 47 transitions. [2018-01-24 17:41:13,497 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 47 transitions. Word has length 36 [2018-01-24 17:41:13,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:13,497 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 47 transitions. [2018-01-24 17:41:13,497 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 17:41:13,497 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 47 transitions. [2018-01-24 17:41:13,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-01-24 17:41:13,498 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:13,499 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:13,499 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:13,499 INFO L82 PathProgramCache]: Analyzing trace with hash 576961419, now seen corresponding path program 4 times [2018-01-24 17:41:13,499 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:13,500 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:13,500 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:13,500 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:13,500 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:13,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:13,512 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:13,601 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 17:41:13,601 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:13,602 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:13,602 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:13,602 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:13,602 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:13,602 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:13,607 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 17:41:13,607 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 17:41:13,631 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:13,634 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:13,642 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 17:41:13,643 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:13,724 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 17:41:13,744 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:13,744 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:13,747 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 17:41:13,748 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 17:41:13,766 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:13,769 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:13,779 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 17:41:13,779 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:13,791 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 17:41:13,793 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:13,794 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-01-24 17:41:13,794 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:13,794 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 17:41:13,795 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 17:41:13,795 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-24 17:41:13,795 INFO L87 Difference]: Start difference. First operand 46 states and 47 transitions. Second operand 8 states. [2018-01-24 17:41:13,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:13,884 INFO L93 Difference]: Finished difference Result 90 states and 94 transitions. [2018-01-24 17:41:13,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 17:41:13,885 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 45 [2018-01-24 17:41:13,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:13,886 INFO L225 Difference]: With dead ends: 90 [2018-01-24 17:41:13,886 INFO L226 Difference]: Without dead ends: 71 [2018-01-24 17:41:13,887 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 174 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-24 17:41:13,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-01-24 17:41:13,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 50. [2018-01-24 17:41:13,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 17:41:13,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 51 transitions. [2018-01-24 17:41:13,895 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 51 transitions. Word has length 45 [2018-01-24 17:41:13,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:13,896 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 51 transitions. [2018-01-24 17:41:13,896 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 17:41:13,896 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 51 transitions. [2018-01-24 17:41:13,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-01-24 17:41:13,897 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:13,897 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:13,897 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:13,897 INFO L82 PathProgramCache]: Analyzing trace with hash -194823758, now seen corresponding path program 5 times [2018-01-24 17:41:13,897 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:13,898 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:13,899 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:13,899 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:13,899 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:13,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:13,912 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:14,001 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 17:41:14,001 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:14,001 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:14,001 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:14,001 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:14,001 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:14,001 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:14,010 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 17:41:14,010 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:14,016 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,029 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,031 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,044 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,058 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,069 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,074 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,074 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:14,077 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:14,086 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 17:41:14,086 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:14,211 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 17:41:14,232 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:14,232 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:14,235 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 17:41:14,235 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:14,239 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,241 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,245 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,250 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,257 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,266 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,284 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:14,290 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:14,293 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:14,300 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 17:41:14,300 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:14,309 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 17:41:14,311 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:14,311 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-01-24 17:41:14,311 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:14,311 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 17:41:14,312 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 17:41:14,312 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-24 17:41:14,312 INFO L87 Difference]: Start difference. First operand 50 states and 51 transitions. Second operand 9 states. [2018-01-24 17:41:14,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:14,391 INFO L93 Difference]: Finished difference Result 99 states and 104 transitions. [2018-01-24 17:41:14,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 17:41:14,392 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 49 [2018-01-24 17:41:14,392 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:14,394 INFO L225 Difference]: With dead ends: 99 [2018-01-24 17:41:14,394 INFO L226 Difference]: Without dead ends: 80 [2018-01-24 17:41:14,394 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-24 17:41:14,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-24 17:41:14,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 54. [2018-01-24 17:41:14,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-01-24 17:41:14,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 55 transitions. [2018-01-24 17:41:14,400 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 55 transitions. Word has length 49 [2018-01-24 17:41:14,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:14,401 INFO L432 AbstractCegarLoop]: Abstraction has 54 states and 55 transitions. [2018-01-24 17:41:14,401 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 17:41:14,401 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 55 transitions. [2018-01-24 17:41:14,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-01-24 17:41:14,401 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:14,402 INFO L322 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:14,402 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:14,402 INFO L82 PathProgramCache]: Analyzing trace with hash -1600566183, now seen corresponding path program 6 times [2018-01-24 17:41:14,402 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:14,403 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:14,403 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:14,403 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:14,403 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:14,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:14,413 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:14,502 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 17:41:14,502 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:14,503 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:14,503 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:14,503 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:14,503 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:14,503 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:14,513 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 17:41:14,513 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 17:41:14,518 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,531 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,532 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,533 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,535 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,536 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,538 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,539 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:14,541 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:14,577 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 17:41:14,577 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:14,615 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 17:41:14,635 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:14,635 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:14,638 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 17:41:14,638 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 17:41:14,643 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,645 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,649 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,655 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,662 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,671 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,682 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:14,688 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:14,691 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:14,694 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 17:41:14,694 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:14,713 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 17:41:14,715 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:14,715 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 5, 5, 5, 5] total 18 [2018-01-24 17:41:14,716 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:14,716 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 17:41:14,716 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 17:41:14,717 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=203, Unknown=0, NotChecked=0, Total=306 [2018-01-24 17:41:14,717 INFO L87 Difference]: Start difference. First operand 54 states and 55 transitions. Second operand 14 states. [2018-01-24 17:41:14,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:14,880 INFO L93 Difference]: Finished difference Result 108 states and 114 transitions. [2018-01-24 17:41:14,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 17:41:14,881 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 53 [2018-01-24 17:41:14,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:14,881 INFO L225 Difference]: With dead ends: 108 [2018-01-24 17:41:14,882 INFO L226 Difference]: Without dead ends: 89 [2018-01-24 17:41:14,882 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 204 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 100 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=103, Invalid=203, Unknown=0, NotChecked=0, Total=306 [2018-01-24 17:41:14,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-01-24 17:41:14,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 63. [2018-01-24 17:41:14,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-01-24 17:41:14,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 64 transitions. [2018-01-24 17:41:14,889 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 64 transitions. Word has length 53 [2018-01-24 17:41:14,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:14,889 INFO L432 AbstractCegarLoop]: Abstraction has 63 states and 64 transitions. [2018-01-24 17:41:14,889 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 17:41:14,889 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 64 transitions. [2018-01-24 17:41:14,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 17:41:14,890 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:14,890 INFO L322 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:14,890 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:14,890 INFO L82 PathProgramCache]: Analyzing trace with hash 1495641218, now seen corresponding path program 7 times [2018-01-24 17:41:14,891 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:14,891 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:14,891 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:14,891 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:14,891 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:14,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:14,904 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:15,046 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 17:41:15,046 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:15,047 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:15,047 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:15,047 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:15,047 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:15,047 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:15,058 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:15,059 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 17:41:15,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:15,075 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:15,085 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 17:41:15,085 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:15,177 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 17:41:15,197 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:15,197 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:15,200 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:15,200 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 17:41:15,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:15,225 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:15,243 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 17:41:15,243 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:15,257 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 17:41:15,258 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:15,259 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-01-24 17:41:15,259 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:15,259 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 17:41:15,259 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 17:41:15,259 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-24 17:41:15,260 INFO L87 Difference]: Start difference. First operand 63 states and 64 transitions. Second operand 11 states. [2018-01-24 17:41:15,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:15,372 INFO L93 Difference]: Finished difference Result 122 states and 128 transitions. [2018-01-24 17:41:15,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 17:41:15,372 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 62 [2018-01-24 17:41:15,373 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:15,373 INFO L225 Difference]: With dead ends: 122 [2018-01-24 17:41:15,373 INFO L226 Difference]: Without dead ends: 98 [2018-01-24 17:41:15,374 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 239 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-24 17:41:15,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-01-24 17:41:15,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 67. [2018-01-24 17:41:15,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-01-24 17:41:15,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 68 transitions. [2018-01-24 17:41:15,382 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 68 transitions. Word has length 62 [2018-01-24 17:41:15,383 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:15,383 INFO L432 AbstractCegarLoop]: Abstraction has 67 states and 68 transitions. [2018-01-24 17:41:15,383 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 17:41:15,383 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 68 transitions. [2018-01-24 17:41:15,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-01-24 17:41:15,384 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:15,384 INFO L322 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:15,384 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:15,385 INFO L82 PathProgramCache]: Analyzing trace with hash -1534369477, now seen corresponding path program 8 times [2018-01-24 17:41:15,385 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:15,385 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:15,386 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:15,386 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:15,386 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:15,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:15,399 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:15,523 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 17:41:15,524 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:15,524 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:15,524 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:15,524 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:15,524 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:15,524 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:15,533 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 17:41:15,534 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:15,539 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:15,549 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:15,562 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:15,564 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:15,575 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 17:41:15,575 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:15,729 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 17:41:15,761 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:15,762 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:15,764 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 17:41:15,765 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:15,769 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:15,778 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:15,785 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:15,788 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:15,796 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 17:41:15,796 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:15,806 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 17:41:15,808 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:15,808 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-01-24 17:41:15,808 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:15,808 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 17:41:15,809 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 17:41:15,809 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-24 17:41:15,809 INFO L87 Difference]: Start difference. First operand 67 states and 68 transitions. Second operand 12 states. [2018-01-24 17:41:15,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:15,881 INFO L93 Difference]: Finished difference Result 131 states and 138 transitions. [2018-01-24 17:41:15,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 17:41:15,881 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 66 [2018-01-24 17:41:15,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:15,882 INFO L225 Difference]: With dead ends: 131 [2018-01-24 17:41:15,882 INFO L226 Difference]: Without dead ends: 107 [2018-01-24 17:41:15,883 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 274 GetRequests, 254 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-24 17:41:15,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-01-24 17:41:15,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 71. [2018-01-24 17:41:15,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-01-24 17:41:15,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 72 transitions. [2018-01-24 17:41:15,891 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 72 transitions. Word has length 66 [2018-01-24 17:41:15,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:15,892 INFO L432 AbstractCegarLoop]: Abstraction has 71 states and 72 transitions. [2018-01-24 17:41:15,892 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 17:41:15,892 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 72 transitions. [2018-01-24 17:41:15,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-01-24 17:41:15,893 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:15,893 INFO L322 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:15,893 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:15,894 INFO L82 PathProgramCache]: Analyzing trace with hash -1473900172, now seen corresponding path program 9 times [2018-01-24 17:41:15,894 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:15,895 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:15,895 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:15,895 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:15,895 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:15,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:15,907 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:16,002 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 17:41:16,002 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:16,002 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:16,002 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:16,002 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:16,002 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:16,002 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:16,010 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 17:41:16,010 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 17:41:16,014 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:16,016 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:16,017 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:16,019 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:16,020 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:16,021 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:16,022 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:16,040 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 17:41:16,040 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:16,092 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 17:41:16,111 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:16,111 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:16,114 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 17:41:16,114 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 17:41:16,119 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:16,122 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:16,130 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:16,141 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:16,155 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:16,163 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:16,166 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:16,172 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 17:41:16,172 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:16,180 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 17:41:16,181 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:16,182 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 6, 6, 6, 6] total 23 [2018-01-24 17:41:16,182 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:16,182 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 17:41:16,182 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 17:41:16,182 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=168, Invalid=338, Unknown=0, NotChecked=0, Total=506 [2018-01-24 17:41:16,183 INFO L87 Difference]: Start difference. First operand 71 states and 72 transitions. Second operand 18 states. [2018-01-24 17:41:16,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:16,398 INFO L93 Difference]: Finished difference Result 140 states and 148 transitions. [2018-01-24 17:41:16,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 17:41:16,399 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 70 [2018-01-24 17:41:16,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:16,399 INFO L225 Difference]: With dead ends: 140 [2018-01-24 17:41:16,400 INFO L226 Difference]: Without dead ends: 116 [2018-01-24 17:41:16,400 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 291 GetRequests, 270 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 175 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=168, Invalid=338, Unknown=0, NotChecked=0, Total=506 [2018-01-24 17:41:16,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-01-24 17:41:16,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 80. [2018-01-24 17:41:16,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-01-24 17:41:16,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 81 transitions. [2018-01-24 17:41:16,407 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 81 transitions. Word has length 70 [2018-01-24 17:41:16,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:16,408 INFO L432 AbstractCegarLoop]: Abstraction has 80 states and 81 transitions. [2018-01-24 17:41:16,408 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 17:41:16,408 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 81 transitions. [2018-01-24 17:41:16,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-01-24 17:41:16,409 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:16,409 INFO L322 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:16,409 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:16,409 INFO L82 PathProgramCache]: Analyzing trace with hash -1757583627, now seen corresponding path program 10 times [2018-01-24 17:41:16,409 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:16,410 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:16,410 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:16,410 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:16,410 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:16,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:16,422 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:16,526 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 17:41:16,526 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:16,526 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:16,526 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:16,526 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:16,527 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:16,527 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:16,534 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 17:41:16,534 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 17:41:16,548 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:16,550 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:16,558 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 17:41:16,558 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:16,702 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 17:41:16,721 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:16,722 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:16,725 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 17:41:16,725 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 17:41:16,756 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:16,759 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:16,767 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 17:41:16,767 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:16,778 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 17:41:16,780 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:16,780 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-01-24 17:41:16,780 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:16,780 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 17:41:16,780 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 17:41:16,781 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-24 17:41:16,781 INFO L87 Difference]: Start difference. First operand 80 states and 81 transitions. Second operand 14 states. [2018-01-24 17:41:16,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:16,876 INFO L93 Difference]: Finished difference Result 154 states and 162 transitions. [2018-01-24 17:41:16,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 17:41:16,877 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 79 [2018-01-24 17:41:16,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:16,877 INFO L225 Difference]: With dead ends: 154 [2018-01-24 17:41:16,877 INFO L226 Difference]: Without dead ends: 125 [2018-01-24 17:41:16,878 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 328 GetRequests, 304 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-24 17:41:16,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2018-01-24 17:41:16,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 84. [2018-01-24 17:41:16,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-01-24 17:41:16,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 85 transitions. [2018-01-24 17:41:16,887 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 85 transitions. Word has length 79 [2018-01-24 17:41:16,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:16,887 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 85 transitions. [2018-01-24 17:41:16,887 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 17:41:16,888 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 85 transitions. [2018-01-24 17:41:16,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-01-24 17:41:16,889 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:16,889 INFO L322 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:16,889 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:16,889 INFO L82 PathProgramCache]: Analyzing trace with hash -2099078308, now seen corresponding path program 11 times [2018-01-24 17:41:16,890 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:16,890 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:16,891 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:16,891 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:16,891 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:16,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:16,904 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:17,040 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 17:41:17,040 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:17,073 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:17,074 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:17,074 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:17,074 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:17,074 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:17,079 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 17:41:17,079 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:17,083 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,084 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,084 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,085 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,087 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,088 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,089 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,091 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,093 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,096 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,098 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,101 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,105 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,106 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:17,108 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:17,120 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 17:41:17,120 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:17,333 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 17:41:17,353 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:17,353 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:17,356 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 17:41:17,356 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:17,361 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,363 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,367 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,372 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,377 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,383 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,391 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,400 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,413 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,427 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,446 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,470 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,561 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:17,571 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:17,575 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:17,583 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 17:41:17,584 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:17,594 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 17:41:17,595 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:17,595 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-01-24 17:41:17,596 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:17,596 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 17:41:17,596 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 17:41:17,596 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-24 17:41:17,596 INFO L87 Difference]: Start difference. First operand 84 states and 85 transitions. Second operand 15 states. [2018-01-24 17:41:17,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:17,693 INFO L93 Difference]: Finished difference Result 163 states and 172 transitions. [2018-01-24 17:41:17,694 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 17:41:17,694 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 83 [2018-01-24 17:41:17,694 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:17,695 INFO L225 Difference]: With dead ends: 163 [2018-01-24 17:41:17,695 INFO L226 Difference]: Without dead ends: 134 [2018-01-24 17:41:17,696 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 345 GetRequests, 319 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-24 17:41:17,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-01-24 17:41:17,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 88. [2018-01-24 17:41:17,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-01-24 17:41:17,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 89 transitions. [2018-01-24 17:41:17,702 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 89 transitions. Word has length 83 [2018-01-24 17:41:17,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:17,702 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 89 transitions. [2018-01-24 17:41:17,702 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 17:41:17,702 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 89 transitions. [2018-01-24 17:41:17,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 17:41:17,703 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:17,703 INFO L322 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:17,703 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:17,703 INFO L82 PathProgramCache]: Analyzing trace with hash -159824829, now seen corresponding path program 12 times [2018-01-24 17:41:17,703 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:17,704 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:17,704 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:17,704 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:17,705 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:17,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:17,717 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:17,917 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 17:41:17,917 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:17,917 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:17,917 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:17,918 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:17,918 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:17,918 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:17,924 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 17:41:17,924 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 17:41:17,929 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:17,931 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:17,932 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:17,934 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:17,935 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:17,937 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:17,944 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:17,946 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:17,948 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:17,951 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:17,953 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:17,955 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:17,956 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:17,996 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 17:41:17,996 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:18,087 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 17:41:18,118 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:18,119 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:18,122 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 17:41:18,122 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 17:41:18,129 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:18,132 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:18,138 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:18,145 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:18,156 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:18,170 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:18,188 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:18,202 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:18,218 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:18,255 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:18,282 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:18,291 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:18,295 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:18,300 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 17:41:18,300 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:18,317 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 17:41:18,318 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:18,318 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 7, 7, 7, 7] total 28 [2018-01-24 17:41:18,319 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:18,319 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 17:41:18,319 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 17:41:18,319 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=249, Invalid=507, Unknown=0, NotChecked=0, Total=756 [2018-01-24 17:41:18,319 INFO L87 Difference]: Start difference. First operand 88 states and 89 transitions. Second operand 22 states. [2018-01-24 17:41:18,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:18,487 INFO L93 Difference]: Finished difference Result 172 states and 182 transitions. [2018-01-24 17:41:18,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 17:41:18,488 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 87 [2018-01-24 17:41:18,488 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:18,488 INFO L225 Difference]: With dead ends: 172 [2018-01-24 17:41:18,488 INFO L226 Difference]: Without dead ends: 143 [2018-01-24 17:41:18,489 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 362 GetRequests, 336 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 270 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=249, Invalid=507, Unknown=0, NotChecked=0, Total=756 [2018-01-24 17:41:18,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-01-24 17:41:18,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 97. [2018-01-24 17:41:18,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-01-24 17:41:18,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 98 transitions. [2018-01-24 17:41:18,495 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 98 transitions. Word has length 87 [2018-01-24 17:41:18,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:18,496 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 98 transitions. [2018-01-24 17:41:18,496 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 17:41:18,496 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 98 transitions. [2018-01-24 17:41:18,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-01-24 17:41:18,497 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:18,497 INFO L322 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:18,497 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:18,498 INFO L82 PathProgramCache]: Analyzing trace with hash -2110093160, now seen corresponding path program 13 times [2018-01-24 17:41:18,498 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:18,498 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:18,498 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:18,498 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:18,498 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:18,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:18,511 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:18,694 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 17:41:18,694 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:18,694 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:18,694 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:18,694 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:18,695 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:18,695 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:18,699 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:18,700 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 17:41:18,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:18,715 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:18,726 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 17:41:18,726 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:18,939 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 17:41:18,959 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:18,959 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:18,962 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:18,962 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 17:41:18,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:18,991 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:19,004 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 17:41:19,005 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:19,019 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 17:41:19,021 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:19,021 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-01-24 17:41:19,021 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:19,021 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 17:41:19,021 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 17:41:19,022 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-24 17:41:19,022 INFO L87 Difference]: Start difference. First operand 97 states and 98 transitions. Second operand 17 states. [2018-01-24 17:41:19,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:19,141 INFO L93 Difference]: Finished difference Result 186 states and 196 transitions. [2018-01-24 17:41:19,141 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 17:41:19,141 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 96 [2018-01-24 17:41:19,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:19,142 INFO L225 Difference]: With dead ends: 186 [2018-01-24 17:41:19,142 INFO L226 Difference]: Without dead ends: 152 [2018-01-24 17:41:19,142 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 399 GetRequests, 369 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-24 17:41:19,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-24 17:41:19,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 101. [2018-01-24 17:41:19,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-01-24 17:41:19,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 102 transitions. [2018-01-24 17:41:19,150 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 102 transitions. Word has length 96 [2018-01-24 17:41:19,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:19,150 INFO L432 AbstractCegarLoop]: Abstraction has 101 states and 102 transitions. [2018-01-24 17:41:19,150 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 17:41:19,150 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 102 transitions. [2018-01-24 17:41:19,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-01-24 17:41:19,151 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:19,151 INFO L322 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:19,151 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:19,152 INFO L82 PathProgramCache]: Analyzing trace with hash 1842728721, now seen corresponding path program 14 times [2018-01-24 17:41:19,152 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:19,153 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:19,153 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:19,153 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:19,153 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:19,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:19,167 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:19,395 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 17:41:19,395 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:19,396 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:19,396 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:19,396 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:19,396 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:19,396 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:19,401 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 17:41:19,401 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:19,406 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:19,413 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:19,415 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:19,417 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:19,427 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 17:41:19,427 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:19,654 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 17:41:19,675 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:19,675 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:19,678 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 17:41:19,678 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:19,684 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:19,697 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:19,707 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:19,711 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:19,721 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 17:41:19,722 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:19,745 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 17:41:19,746 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:19,747 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-01-24 17:41:19,747 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:19,755 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 17:41:19,755 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 17:41:19,756 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 17:41:19,756 INFO L87 Difference]: Start difference. First operand 101 states and 102 transitions. Second operand 18 states. [2018-01-24 17:41:19,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:19,964 INFO L93 Difference]: Finished difference Result 195 states and 206 transitions. [2018-01-24 17:41:19,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 17:41:19,965 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 100 [2018-01-24 17:41:19,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:19,965 INFO L225 Difference]: With dead ends: 195 [2018-01-24 17:41:19,965 INFO L226 Difference]: Without dead ends: 161 [2018-01-24 17:41:19,966 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 416 GetRequests, 384 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 17:41:19,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-01-24 17:41:19,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 105. [2018-01-24 17:41:19,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-01-24 17:41:19,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 106 transitions. [2018-01-24 17:41:19,975 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 106 transitions. Word has length 100 [2018-01-24 17:41:19,975 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:19,975 INFO L432 AbstractCegarLoop]: Abstraction has 105 states and 106 transitions. [2018-01-24 17:41:19,975 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 17:41:19,975 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 106 transitions. [2018-01-24 17:41:19,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-01-24 17:41:19,975 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:19,976 INFO L322 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:19,976 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:19,976 INFO L82 PathProgramCache]: Analyzing trace with hash -184078070, now seen corresponding path program 15 times [2018-01-24 17:41:19,976 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:19,976 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:19,977 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:19,977 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:19,977 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:19,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:19,986 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:20,114 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 17:41:20,115 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:20,115 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:20,115 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:20,115 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:20,115 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:20,115 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:20,120 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 17:41:20,120 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 17:41:20,125 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,127 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,129 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,132 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,134 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,135 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:20,137 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:20,170 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 17:41:20,170 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:20,266 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 17:41:20,286 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:20,287 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:20,290 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 17:41:20,290 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 17:41:20,298 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,300 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,306 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,313 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,322 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,336 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,355 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:20,362 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:20,366 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:20,372 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 17:41:20,372 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:20,398 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 17:41:20,399 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:20,399 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 8, 8, 8, 8] total 33 [2018-01-24 17:41:20,399 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:20,399 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 17:41:20,400 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 17:41:20,400 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=346, Invalid=710, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 17:41:20,400 INFO L87 Difference]: Start difference. First operand 105 states and 106 transitions. Second operand 26 states. [2018-01-24 17:41:20,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:20,687 INFO L93 Difference]: Finished difference Result 204 states and 216 transitions. [2018-01-24 17:41:20,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 17:41:20,687 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 104 [2018-01-24 17:41:20,688 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:20,688 INFO L225 Difference]: With dead ends: 204 [2018-01-24 17:41:20,688 INFO L226 Difference]: Without dead ends: 170 [2018-01-24 17:41:20,689 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 433 GetRequests, 402 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 385 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=346, Invalid=710, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 17:41:20,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2018-01-24 17:41:20,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 114. [2018-01-24 17:41:20,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-01-24 17:41:20,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 115 transitions. [2018-01-24 17:41:20,699 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 115 transitions. Word has length 104 [2018-01-24 17:41:20,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:20,699 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 115 transitions. [2018-01-24 17:41:20,699 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 17:41:20,699 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 115 transitions. [2018-01-24 17:41:20,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-01-24 17:41:20,700 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:20,700 INFO L322 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:20,700 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:20,700 INFO L82 PathProgramCache]: Analyzing trace with hash 950262623, now seen corresponding path program 16 times [2018-01-24 17:41:20,700 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:20,700 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:20,701 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:20,701 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:20,701 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:20,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:20,712 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:20,878 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 17:41:20,878 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:20,878 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:20,878 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:20,879 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:20,879 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:20,879 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:20,883 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 17:41:20,884 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 17:41:20,900 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:20,902 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:20,915 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 17:41:20,916 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:21,279 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 17:41:21,299 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:21,299 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:21,303 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 17:41:21,304 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 17:41:21,353 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:21,357 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:21,374 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 17:41:21,374 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:21,406 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 17:41:21,407 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:21,408 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-01-24 17:41:21,408 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:21,408 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 17:41:21,408 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 17:41:21,409 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 17:41:21,409 INFO L87 Difference]: Start difference. First operand 114 states and 115 transitions. Second operand 20 states. [2018-01-24 17:41:21,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:21,597 INFO L93 Difference]: Finished difference Result 218 states and 230 transitions. [2018-01-24 17:41:21,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 17:41:21,598 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 113 [2018-01-24 17:41:21,598 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:21,599 INFO L225 Difference]: With dead ends: 218 [2018-01-24 17:41:21,599 INFO L226 Difference]: Without dead ends: 179 [2018-01-24 17:41:21,600 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 470 GetRequests, 434 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 17:41:21,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-01-24 17:41:21,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 118. [2018-01-24 17:41:21,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-24 17:41:21,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 119 transitions. [2018-01-24 17:41:21,614 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 119 transitions. Word has length 113 [2018-01-24 17:41:21,614 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:21,615 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 119 transitions. [2018-01-24 17:41:21,615 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 17:41:21,615 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 119 transitions. [2018-01-24 17:41:21,615 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-01-24 17:41:21,616 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:21,616 INFO L322 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:21,616 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:21,616 INFO L82 PathProgramCache]: Analyzing trace with hash 1664169478, now seen corresponding path program 17 times [2018-01-24 17:41:21,616 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:21,617 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:21,617 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:21,617 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:21,617 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:21,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:21,630 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:21,883 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 17:41:21,883 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:21,883 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:21,884 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:21,884 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:21,884 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:21,884 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:21,890 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 17:41:21,890 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:21,897 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,898 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,899 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,900 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,902 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,904 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,905 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,907 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,908 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,913 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,915 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,918 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,921 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,924 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,927 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,932 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,936 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,944 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,962 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:21,964 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:21,966 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:21,979 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 17:41:21,979 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:22,325 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 17:41:22,349 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:22,349 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:22,352 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 17:41:22,352 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:22,357 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,363 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,367 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,372 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,379 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,386 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,395 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,406 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,418 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,433 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,451 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,474 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,500 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,532 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,570 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,616 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,671 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:22,987 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:23,005 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:23,010 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:23,027 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 17:41:23,027 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:23,059 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 17:41:23,061 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:23,061 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-01-24 17:41:23,061 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:23,061 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 17:41:23,062 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 17:41:23,062 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 17:41:23,062 INFO L87 Difference]: Start difference. First operand 118 states and 119 transitions. Second operand 21 states. [2018-01-24 17:41:23,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:23,202 INFO L93 Difference]: Finished difference Result 227 states and 240 transitions. [2018-01-24 17:41:23,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 17:41:23,203 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 117 [2018-01-24 17:41:23,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:23,204 INFO L225 Difference]: With dead ends: 227 [2018-01-24 17:41:23,204 INFO L226 Difference]: Without dead ends: 188 [2018-01-24 17:41:23,204 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 487 GetRequests, 449 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 17:41:23,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-01-24 17:41:23,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 122. [2018-01-24 17:41:23,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-01-24 17:41:23,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 123 transitions. [2018-01-24 17:41:23,213 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 123 transitions. Word has length 117 [2018-01-24 17:41:23,213 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:23,213 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 123 transitions. [2018-01-24 17:41:23,213 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 17:41:23,213 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 123 transitions. [2018-01-24 17:41:23,214 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-01-24 17:41:23,214 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:23,214 INFO L322 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:23,214 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:23,214 INFO L82 PathProgramCache]: Analyzing trace with hash 2092098861, now seen corresponding path program 18 times [2018-01-24 17:41:23,214 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:23,215 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:23,215 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:23,215 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:23,215 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:23,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:23,224 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:23,469 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 722 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 17:41:23,469 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:23,469 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:23,469 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:23,469 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:23,469 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:23,469 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:23,474 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 17:41:23,474 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 17:41:23,480 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,483 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,485 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,486 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,487 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,488 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,489 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,490 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,492 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,493 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,495 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,497 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,499 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,501 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,504 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,504 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:23,506 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:23,563 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-24 17:41:23,563 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:23,676 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-24 17:41:23,696 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:23,696 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:23,699 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 17:41:23,699 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 17:41:23,706 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,708 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,712 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,717 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,724 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,733 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,744 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,761 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,776 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,797 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,824 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,859 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,898 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:23,969 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:24,027 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:24,039 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:24,043 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:24,056 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-24 17:41:24,056 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:24,089 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-24 17:41:24,091 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:24,091 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 9, 9, 9, 9] total 38 [2018-01-24 17:41:24,091 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:24,092 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 17:41:24,092 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 17:41:24,092 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=459, Invalid=947, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 17:41:24,093 INFO L87 Difference]: Start difference. First operand 122 states and 123 transitions. Second operand 30 states. [2018-01-24 17:41:24,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:24,480 INFO L93 Difference]: Finished difference Result 236 states and 250 transitions. [2018-01-24 17:41:24,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 17:41:24,481 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 121 [2018-01-24 17:41:24,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:24,482 INFO L225 Difference]: With dead ends: 236 [2018-01-24 17:41:24,482 INFO L226 Difference]: Without dead ends: 197 [2018-01-24 17:41:24,482 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 504 GetRequests, 468 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 520 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=459, Invalid=947, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 17:41:24,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2018-01-24 17:41:24,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 131. [2018-01-24 17:41:24,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-01-24 17:41:24,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 132 transitions. [2018-01-24 17:41:24,494 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 132 transitions. Word has length 121 [2018-01-24 17:41:24,494 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:24,494 INFO L432 AbstractCegarLoop]: Abstraction has 131 states and 132 transitions. [2018-01-24 17:41:24,494 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 17:41:24,494 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 132 transitions. [2018-01-24 17:41:24,494 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-01-24 17:41:24,495 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:24,495 INFO L322 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:24,495 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:24,495 INFO L82 PathProgramCache]: Analyzing trace with hash 734718894, now seen corresponding path program 19 times [2018-01-24 17:41:24,495 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:24,496 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:24,496 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:24,496 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:24,496 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:24,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:24,509 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:24,753 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 17:41:24,753 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:24,753 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:24,753 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:24,753 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:24,753 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:24,753 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:24,759 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:24,759 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 17:41:24,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:24,778 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:24,792 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 17:41:24,792 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:25,157 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 17:41:25,176 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:25,177 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:25,179 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:25,180 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 17:41:25,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:25,217 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:25,239 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 17:41:25,239 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:25,259 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 17:41:25,260 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:25,260 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-01-24 17:41:25,260 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:25,261 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 17:41:25,261 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 17:41:25,261 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 17:41:25,261 INFO L87 Difference]: Start difference. First operand 131 states and 132 transitions. Second operand 23 states. [2018-01-24 17:41:25,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:25,536 INFO L93 Difference]: Finished difference Result 250 states and 264 transitions. [2018-01-24 17:41:25,537 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 17:41:25,537 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 130 [2018-01-24 17:41:25,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:25,538 INFO L225 Difference]: With dead ends: 250 [2018-01-24 17:41:25,538 INFO L226 Difference]: Without dead ends: 206 [2018-01-24 17:41:25,539 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 541 GetRequests, 499 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 17:41:25,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-01-24 17:41:25,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 135. [2018-01-24 17:41:25,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-24 17:41:25,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 136 transitions. [2018-01-24 17:41:25,557 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 136 transitions. Word has length 130 [2018-01-24 17:41:25,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:25,558 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 136 transitions. [2018-01-24 17:41:25,558 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 17:41:25,558 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 136 transitions. [2018-01-24 17:41:25,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-01-24 17:41:25,559 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:25,559 INFO L322 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:25,559 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:25,559 INFO L82 PathProgramCache]: Analyzing trace with hash 1367823335, now seen corresponding path program 20 times [2018-01-24 17:41:25,559 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:25,560 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:25,560 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:25,560 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:25,560 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:25,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:25,575 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:25,792 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 17:41:25,792 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:25,792 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:25,792 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:25,792 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:25,792 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:25,793 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:25,797 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 17:41:25,797 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:25,804 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:25,815 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:25,817 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:25,819 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:25,833 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 17:41:25,833 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:26,379 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 17:41:26,399 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:26,399 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:26,402 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 17:41:26,402 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:26,411 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:26,433 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:26,447 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:26,452 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:26,474 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 17:41:26,474 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:26,524 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 17:41:26,525 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:26,525 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 46 [2018-01-24 17:41:26,525 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:26,526 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 17:41:26,526 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 17:41:26,527 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 17:41:26,527 INFO L87 Difference]: Start difference. First operand 135 states and 136 transitions. Second operand 24 states. [2018-01-24 17:41:26,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:26,782 INFO L93 Difference]: Finished difference Result 259 states and 274 transitions. [2018-01-24 17:41:26,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 17:41:26,783 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 134 [2018-01-24 17:41:26,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:26,784 INFO L225 Difference]: With dead ends: 259 [2018-01-24 17:41:26,784 INFO L226 Difference]: Without dead ends: 215 [2018-01-24 17:41:26,785 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 558 GetRequests, 514 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 17:41:26,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states. [2018-01-24 17:41:26,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 139. [2018-01-24 17:41:26,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-01-24 17:41:26,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 140 transitions. [2018-01-24 17:41:26,805 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 140 transitions. Word has length 134 [2018-01-24 17:41:26,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:26,806 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 140 transitions. [2018-01-24 17:41:26,806 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 17:41:26,806 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 140 transitions. [2018-01-24 17:41:26,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-24 17:41:26,807 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:26,807 INFO L322 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:26,807 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:26,807 INFO L82 PathProgramCache]: Analyzing trace with hash -168626272, now seen corresponding path program 21 times [2018-01-24 17:41:26,807 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:26,808 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:26,808 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:26,808 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:26,808 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:26,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:26,822 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:27,223 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 968 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 17:41:27,223 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:27,259 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:27,260 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:27,260 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:27,260 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:27,260 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:27,265 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 17:41:27,265 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 17:41:27,273 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,275 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,277 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,279 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,281 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,283 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,285 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,289 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,292 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,292 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:27,295 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:27,373 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-24 17:41:27,374 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:27,569 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-24 17:41:27,589 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:27,589 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:27,592 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 17:41:27,592 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 17:41:27,602 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,605 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,613 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,624 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,637 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,658 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,687 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,714 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,750 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:27,759 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:27,764 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:27,779 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-24 17:41:27,779 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:27,818 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-24 17:41:27,820 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:27,820 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 10, 10, 10, 10] total 43 [2018-01-24 17:41:27,820 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:27,821 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-01-24 17:41:27,821 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-01-24 17:41:27,822 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=588, Invalid=1218, Unknown=0, NotChecked=0, Total=1806 [2018-01-24 17:41:27,822 INFO L87 Difference]: Start difference. First operand 139 states and 140 transitions. Second operand 34 states. [2018-01-24 17:41:28,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:28,580 INFO L93 Difference]: Finished difference Result 268 states and 284 transitions. [2018-01-24 17:41:28,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 17:41:28,580 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 138 [2018-01-24 17:41:28,581 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:28,582 INFO L225 Difference]: With dead ends: 268 [2018-01-24 17:41:28,582 INFO L226 Difference]: Without dead ends: 224 [2018-01-24 17:41:28,583 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 575 GetRequests, 534 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 675 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=588, Invalid=1218, Unknown=0, NotChecked=0, Total=1806 [2018-01-24 17:41:28,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-01-24 17:41:28,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 148. [2018-01-24 17:41:28,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-01-24 17:41:28,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 149 transitions. [2018-01-24 17:41:28,608 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 149 transitions. Word has length 138 [2018-01-24 17:41:28,609 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:28,609 INFO L432 AbstractCegarLoop]: Abstraction has 148 states and 149 transitions. [2018-01-24 17:41:28,609 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-01-24 17:41:28,609 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 149 transitions. [2018-01-24 17:41:28,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2018-01-24 17:41:28,610 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:28,610 INFO L322 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:28,610 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:28,611 INFO L82 PathProgramCache]: Analyzing trace with hash -219252535, now seen corresponding path program 22 times [2018-01-24 17:41:28,611 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:28,611 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:28,611 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:28,612 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:28,612 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:28,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:28,626 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:29,172 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 17:41:29,173 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:29,173 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:29,173 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:29,173 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:29,173 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:29,173 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:29,178 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 17:41:29,178 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 17:41:29,197 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:29,199 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:29,214 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 17:41:29,215 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:29,689 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 17:41:29,710 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:29,710 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:29,713 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 17:41:29,713 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 17:41:29,761 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:29,765 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:29,780 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 17:41:29,781 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:29,798 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 17:41:29,799 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:29,799 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-01-24 17:41:29,799 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:29,799 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 17:41:29,800 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 17:41:29,800 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 17:41:29,800 INFO L87 Difference]: Start difference. First operand 148 states and 149 transitions. Second operand 26 states. [2018-01-24 17:41:30,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:30,604 INFO L93 Difference]: Finished difference Result 282 states and 298 transitions. [2018-01-24 17:41:30,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 17:41:30,605 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 147 [2018-01-24 17:41:30,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:30,606 INFO L225 Difference]: With dead ends: 282 [2018-01-24 17:41:30,606 INFO L226 Difference]: Without dead ends: 233 [2018-01-24 17:41:30,607 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 612 GetRequests, 564 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 17:41:30,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2018-01-24 17:41:30,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 152. [2018-01-24 17:41:30,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-01-24 17:41:30,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 153 transitions. [2018-01-24 17:41:30,622 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 153 transitions. Word has length 147 [2018-01-24 17:41:30,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:30,622 INFO L432 AbstractCegarLoop]: Abstraction has 152 states and 153 transitions. [2018-01-24 17:41:30,622 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 17:41:30,622 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 153 transitions. [2018-01-24 17:41:30,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2018-01-24 17:41:30,623 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:30,623 INFO L322 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:30,623 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:30,623 INFO L82 PathProgramCache]: Analyzing trace with hash -2062915152, now seen corresponding path program 23 times [2018-01-24 17:41:30,623 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:30,624 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:30,624 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:30,624 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:30,624 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:30,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:30,634 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:31,297 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 17:41:31,297 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:31,297 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:31,297 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:31,297 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:31,297 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:31,297 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:31,302 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 17:41:31,302 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:31,308 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,309 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,310 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,310 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,312 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,313 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,315 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,317 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,319 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,321 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,323 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,325 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,328 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,330 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,333 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,337 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,341 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,345 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,350 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,355 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,361 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,368 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,376 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,383 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,402 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,403 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:31,405 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:31,421 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 17:41:31,421 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:31,905 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 17:41:31,924 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:31,924 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:31,927 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 17:41:31,927 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:31,935 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,937 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,940 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,945 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,950 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,956 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,964 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,973 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,984 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:31,996 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,011 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,029 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,049 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,071 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,098 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,129 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,164 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,205 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,255 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,313 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,382 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,462 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,557 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:32,664 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:33,590 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:33,628 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:33,633 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:33,653 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 17:41:33,654 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:33,681 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 17:41:33,683 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:33,683 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 52 [2018-01-24 17:41:33,683 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:33,683 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 17:41:33,684 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 17:41:33,684 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 17:41:33,684 INFO L87 Difference]: Start difference. First operand 152 states and 153 transitions. Second operand 27 states. [2018-01-24 17:41:33,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:33,905 INFO L93 Difference]: Finished difference Result 291 states and 308 transitions. [2018-01-24 17:41:33,905 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 17:41:33,905 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 151 [2018-01-24 17:41:33,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:33,906 INFO L225 Difference]: With dead ends: 291 [2018-01-24 17:41:33,906 INFO L226 Difference]: Without dead ends: 242 [2018-01-24 17:41:33,907 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 629 GetRequests, 579 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 17:41:33,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states. [2018-01-24 17:41:33,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 156. [2018-01-24 17:41:33,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-01-24 17:41:33,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 157 transitions. [2018-01-24 17:41:33,934 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 157 transitions. Word has length 151 [2018-01-24 17:41:33,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:33,934 INFO L432 AbstractCegarLoop]: Abstraction has 156 states and 157 transitions. [2018-01-24 17:41:33,934 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 17:41:33,934 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 157 transitions. [2018-01-24 17:41:33,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-01-24 17:41:33,935 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:33,935 INFO L322 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:33,935 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:33,935 INFO L82 PathProgramCache]: Analyzing trace with hash -731541737, now seen corresponding path program 24 times [2018-01-24 17:41:33,935 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:33,936 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:33,936 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:33,936 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:33,936 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:33,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:33,951 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:34,489 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 1250 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 17:41:34,489 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:34,489 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:34,489 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:34,489 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:34,489 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:34,489 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:34,495 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 17:41:34,495 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 17:41:34,501 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,504 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,505 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,506 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,508 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,509 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,511 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,512 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,514 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,516 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,518 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,520 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,522 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,524 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,526 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,529 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,532 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,534 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,538 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,539 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:34,541 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:34,591 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-24 17:41:34,591 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:34,766 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-24 17:41:34,786 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:34,786 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:34,789 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 17:41:34,789 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 17:41:34,797 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,799 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,803 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,808 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,815 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,824 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,836 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,850 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,866 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,900 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,926 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:34,970 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:35,010 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:35,081 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:35,141 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:35,402 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:35,739 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:36,156 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:36,803 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:36,832 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:36,838 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:36,856 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-24 17:41:36,857 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:36,890 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-24 17:41:36,891 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:36,892 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 11, 11, 11, 11] total 48 [2018-01-24 17:41:36,892 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:36,892 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-01-24 17:41:36,893 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-01-24 17:41:36,893 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=733, Invalid=1523, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 17:41:36,893 INFO L87 Difference]: Start difference. First operand 156 states and 157 transitions. Second operand 38 states. [2018-01-24 17:41:37,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:37,534 INFO L93 Difference]: Finished difference Result 300 states and 318 transitions. [2018-01-24 17:41:37,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 17:41:37,563 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 155 [2018-01-24 17:41:37,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:37,565 INFO L225 Difference]: With dead ends: 300 [2018-01-24 17:41:37,565 INFO L226 Difference]: Without dead ends: 251 [2018-01-24 17:41:37,565 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 646 GetRequests, 600 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 850 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=733, Invalid=1523, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 17:41:37,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states. [2018-01-24 17:41:37,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 165. [2018-01-24 17:41:37,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-01-24 17:41:37,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 166 transitions. [2018-01-24 17:41:37,599 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 166 transitions. Word has length 155 [2018-01-24 17:41:37,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:37,599 INFO L432 AbstractCegarLoop]: Abstraction has 165 states and 166 transitions. [2018-01-24 17:41:37,599 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-01-24 17:41:37,600 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 166 transitions. [2018-01-24 17:41:37,600 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-01-24 17:41:37,600 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:37,601 INFO L322 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:37,601 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:37,601 INFO L82 PathProgramCache]: Analyzing trace with hash 7304644, now seen corresponding path program 25 times [2018-01-24 17:41:37,601 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:37,602 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:37,602 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:37,602 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:37,602 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:37,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:37,617 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:38,037 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 17:41:38,037 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:38,038 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:38,038 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:38,038 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:38,038 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:38,038 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:38,044 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:38,044 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 17:41:38,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:38,071 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:38,089 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 17:41:38,089 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:38,779 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 17:41:38,808 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:38,808 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:38,811 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:38,811 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 17:41:38,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:38,864 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:38,897 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 17:41:38,898 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:38,932 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 17:41:38,933 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:38,933 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 56 [2018-01-24 17:41:38,933 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:38,933 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 17:41:38,934 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 17:41:38,934 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 17:41:38,934 INFO L87 Difference]: Start difference. First operand 165 states and 166 transitions. Second operand 29 states. [2018-01-24 17:41:39,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:39,354 INFO L93 Difference]: Finished difference Result 314 states and 332 transitions. [2018-01-24 17:41:39,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 17:41:39,354 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 164 [2018-01-24 17:41:39,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:39,355 INFO L225 Difference]: With dead ends: 314 [2018-01-24 17:41:39,355 INFO L226 Difference]: Without dead ends: 260 [2018-01-24 17:41:39,356 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 683 GetRequests, 629 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 17:41:39,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 260 states. [2018-01-24 17:41:39,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 260 to 169. [2018-01-24 17:41:39,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-01-24 17:41:39,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 170 transitions. [2018-01-24 17:41:39,377 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 170 transitions. Word has length 164 [2018-01-24 17:41:39,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:39,377 INFO L432 AbstractCegarLoop]: Abstraction has 169 states and 170 transitions. [2018-01-24 17:41:39,377 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-24 17:41:39,377 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 170 transitions. [2018-01-24 17:41:39,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2018-01-24 17:41:39,378 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:39,378 INFO L322 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:39,378 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:39,378 INFO L82 PathProgramCache]: Analyzing trace with hash -1420521539, now seen corresponding path program 26 times [2018-01-24 17:41:39,378 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:39,378 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:39,379 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:39,379 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:39,379 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:39,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:39,390 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:40,319 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 17:41:40,319 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:40,319 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:40,320 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:40,320 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:40,320 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:40,320 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:40,330 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 17:41:40,330 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:40,337 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:40,349 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:40,352 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:40,354 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:40,372 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 17:41:40,372 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:40,985 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 17:41:41,005 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:41,005 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:41,008 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 17:41:41,008 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:41,015 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:41,037 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:41,054 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:41,058 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:41,077 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 17:41:41,077 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:41,114 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 17:41:41,115 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:41,115 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 58 [2018-01-24 17:41:41,115 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:41,116 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 17:41:41,116 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 17:41:41,117 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 17:41:41,117 INFO L87 Difference]: Start difference. First operand 169 states and 170 transitions. Second operand 30 states. [2018-01-24 17:41:41,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:41,395 INFO L93 Difference]: Finished difference Result 323 states and 342 transitions. [2018-01-24 17:41:41,396 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-24 17:41:41,396 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 168 [2018-01-24 17:41:41,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:41,397 INFO L225 Difference]: With dead ends: 323 [2018-01-24 17:41:41,397 INFO L226 Difference]: Without dead ends: 269 [2018-01-24 17:41:41,398 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 700 GetRequests, 644 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 17:41:41,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states. [2018-01-24 17:41:41,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 173. [2018-01-24 17:41:41,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-01-24 17:41:41,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 174 transitions. [2018-01-24 17:41:41,418 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 174 transitions. Word has length 168 [2018-01-24 17:41:41,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:41,419 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 174 transitions. [2018-01-24 17:41:41,419 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 17:41:41,419 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 174 transitions. [2018-01-24 17:41:41,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-01-24 17:41:41,419 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:41,419 INFO L322 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:41,419 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:41,420 INFO L82 PathProgramCache]: Analyzing trace with hash -910555850, now seen corresponding path program 27 times [2018-01-24 17:41:41,420 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:41,420 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:41,420 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:41,420 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:41,420 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:41,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:41,435 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:41,930 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 1568 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 17:41:41,930 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:41,930 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:41,930 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:41,931 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:41,931 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:41,931 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:41,937 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 17:41:41,937 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 17:41:41,944 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:41,946 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:41,947 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:41,949 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:41,951 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:41,954 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:41,956 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:41,961 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:41,964 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:41,969 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:41,977 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:41,979 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:41,981 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:42,130 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-24 17:41:42,130 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:42,333 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-24 17:41:42,354 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:42,354 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:42,357 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 17:41:42,357 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 17:41:42,367 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:42,369 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:42,374 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:42,382 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:42,392 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:42,405 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:42,425 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:42,451 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:42,487 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:42,532 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:42,592 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 17:41:42,603 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:42,634 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:42,647 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-24 17:41:42,648 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:42,675 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-24 17:41:42,676 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:42,676 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 12, 12, 12, 12] total 53 [2018-01-24 17:41:42,676 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:42,677 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-01-24 17:41:42,677 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-01-24 17:41:42,677 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=894, Invalid=1862, Unknown=0, NotChecked=0, Total=2756 [2018-01-24 17:41:42,678 INFO L87 Difference]: Start difference. First operand 173 states and 174 transitions. Second operand 42 states. [2018-01-24 17:41:43,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:43,123 INFO L93 Difference]: Finished difference Result 332 states and 352 transitions. [2018-01-24 17:41:43,123 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-24 17:41:43,123 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 172 [2018-01-24 17:41:43,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:43,124 INFO L225 Difference]: With dead ends: 332 [2018-01-24 17:41:43,124 INFO L226 Difference]: Without dead ends: 278 [2018-01-24 17:41:43,125 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 717 GetRequests, 666 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1045 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=894, Invalid=1862, Unknown=0, NotChecked=0, Total=2756 [2018-01-24 17:41:43,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2018-01-24 17:41:43,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 182. [2018-01-24 17:41:43,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-24 17:41:43,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 183 transitions. [2018-01-24 17:41:43,151 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 183 transitions. Word has length 172 [2018-01-24 17:41:43,151 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:43,151 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 183 transitions. [2018-01-24 17:41:43,151 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-01-24 17:41:43,151 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 183 transitions. [2018-01-24 17:41:43,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2018-01-24 17:41:43,152 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:43,152 INFO L322 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:43,152 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:43,152 INFO L82 PathProgramCache]: Analyzing trace with hash 1830068019, now seen corresponding path program 28 times [2018-01-24 17:41:43,152 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:43,153 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:43,153 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:43,153 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:43,153 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:43,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:43,168 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:43,680 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 17:41:43,681 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:43,681 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:43,681 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:43,681 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:43,681 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:43,681 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:43,686 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 17:41:43,686 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 17:41:43,714 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:43,717 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:43,738 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 17:41:43,738 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:44,605 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 17:41:44,625 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:44,625 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:44,628 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 17:41:44,628 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 17:41:44,698 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:44,704 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:44,739 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 17:41:44,739 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:44,787 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 17:41:44,789 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:44,789 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32] total 62 [2018-01-24 17:41:44,789 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:44,790 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-01-24 17:41:44,790 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-01-24 17:41:44,791 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-24 17:41:44,791 INFO L87 Difference]: Start difference. First operand 182 states and 183 transitions. Second operand 32 states. [2018-01-24 17:41:45,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:45,282 INFO L93 Difference]: Finished difference Result 346 states and 366 transitions. [2018-01-24 17:41:45,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-24 17:41:45,282 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 181 [2018-01-24 17:41:45,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:45,283 INFO L225 Difference]: With dead ends: 346 [2018-01-24 17:41:45,283 INFO L226 Difference]: Without dead ends: 287 [2018-01-24 17:41:45,284 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 754 GetRequests, 694 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-24 17:41:45,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states. [2018-01-24 17:41:45,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 186. [2018-01-24 17:41:45,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-01-24 17:41:45,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 187 transitions. [2018-01-24 17:41:45,320 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 187 transitions. Word has length 181 [2018-01-24 17:41:45,320 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:45,320 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 187 transitions. [2018-01-24 17:41:45,320 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-01-24 17:41:45,320 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 187 transitions. [2018-01-24 17:41:45,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2018-01-24 17:41:45,321 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:45,321 INFO L322 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:45,321 INFO L371 AbstractCegarLoop]: === Iteration 31 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:45,321 INFO L82 PathProgramCache]: Analyzing trace with hash -1177971110, now seen corresponding path program 29 times [2018-01-24 17:41:45,321 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:45,322 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:45,322 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:45,322 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:45,322 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:45,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:45,336 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:45,856 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 17:41:45,856 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:45,856 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:45,856 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:45,856 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:45,857 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:45,857 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:45,861 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 17:41:45,861 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:45,869 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,870 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,871 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,872 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,874 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,875 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,876 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,878 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,880 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,881 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,884 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,886 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,889 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,892 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,895 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,898 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,902 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,907 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,912 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,917 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,924 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,931 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,938 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,947 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,957 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,967 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,978 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:45,990 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,003 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,018 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,045 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,046 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:46,048 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:46,069 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 17:41:46,070 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:46,823 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 17:41:46,843 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:46,843 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 59 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:46,846 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 17:41:46,846 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 17:41:46,855 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,857 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,860 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,865 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,870 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,877 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,884 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,893 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,904 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,917 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,932 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,950 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,970 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:46,994 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,021 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,052 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,087 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,128 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,173 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,223 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,281 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,349 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,425 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,511 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,619 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,743 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:47,881 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:48,041 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:48,222 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:48,422 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:50,728 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 17:41:50,794 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:50,799 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:50,821 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 17:41:50,821 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:50,845 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 17:41:50,847 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:50,847 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 64 [2018-01-24 17:41:50,847 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:50,847 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-24 17:41:50,848 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-24 17:41:50,848 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-24 17:41:50,848 INFO L87 Difference]: Start difference. First operand 186 states and 187 transitions. Second operand 33 states. [2018-01-24 17:41:51,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:51,186 INFO L93 Difference]: Finished difference Result 355 states and 376 transitions. [2018-01-24 17:41:51,186 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-01-24 17:41:51,186 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 185 [2018-01-24 17:41:51,186 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:51,187 INFO L225 Difference]: With dead ends: 355 [2018-01-24 17:41:51,187 INFO L226 Difference]: Without dead ends: 296 [2018-01-24 17:41:51,188 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 771 GetRequests, 709 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-24 17:41:51,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 296 states. [2018-01-24 17:41:51,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 296 to 190. [2018-01-24 17:41:51,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-01-24 17:41:51,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 191 transitions. [2018-01-24 17:41:51,227 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 191 transitions. Word has length 185 [2018-01-24 17:41:51,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:51,228 INFO L432 AbstractCegarLoop]: Abstraction has 190 states and 191 transitions. [2018-01-24 17:41:51,228 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-24 17:41:51,228 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 191 transitions. [2018-01-24 17:41:51,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 190 [2018-01-24 17:41:51,229 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:51,229 INFO L322 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:51,229 INFO L371 AbstractCegarLoop]: === Iteration 32 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:51,229 INFO L82 PathProgramCache]: Analyzing trace with hash 659595777, now seen corresponding path program 30 times [2018-01-24 17:41:51,229 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:51,230 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:51,230 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:51,230 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:51,230 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:51,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:51,245 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:51,711 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 1922 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 17:41:51,712 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:51,712 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:51,712 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:51,712 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:51,712 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:51,712 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:51,717 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 17:41:51,717 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 17:41:51,724 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,725 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,726 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,727 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,728 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,729 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,731 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,732 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,734 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,735 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,737 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,739 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,741 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,744 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,747 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,749 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,752 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,755 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,759 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,763 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,767 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,773 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,777 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:51,779 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:51,781 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:51,849 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-24 17:41:51,850 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:52,097 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-24 17:41:52,117 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:52,117 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 61 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 17:41:52,120 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 17:41:52,120 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 17:41:52,129 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,131 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,136 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,141 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,148 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,157 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,169 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,185 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,200 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,221 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,248 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,282 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,322 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,395 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,452 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:52,713 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:53,011 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:53,564 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:54,167 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:55,074 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:56,180 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:57,669 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:58,113 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 17:41:58,138 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 17:41:58,144 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:58,164 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-24 17:41:58,164 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 17:41:58,191 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-24 17:41:58,193 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 17:41:58,193 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 13, 13, 13, 13] total 58 [2018-01-24 17:41:58,193 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 17:41:58,194 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-01-24 17:41:58,194 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-01-24 17:41:58,194 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1071, Invalid=2235, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 17:41:58,194 INFO L87 Difference]: Start difference. First operand 190 states and 191 transitions. Second operand 46 states. [2018-01-24 17:41:58,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 17:41:58,764 INFO L93 Difference]: Finished difference Result 364 states and 386 transitions. [2018-01-24 17:41:58,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-24 17:41:58,764 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 189 [2018-01-24 17:41:58,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 17:41:58,766 INFO L225 Difference]: With dead ends: 364 [2018-01-24 17:41:58,766 INFO L226 Difference]: Without dead ends: 305 [2018-01-24 17:41:58,766 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 788 GetRequests, 732 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1260 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1071, Invalid=2235, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 17:41:58,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 305 states. [2018-01-24 17:41:58,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 305 to 199. [2018-01-24 17:41:58,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199 states. [2018-01-24 17:41:58,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 200 transitions. [2018-01-24 17:41:58,802 INFO L78 Accepts]: Start accepts. Automaton has 199 states and 200 transitions. Word has length 189 [2018-01-24 17:41:58,802 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 17:41:58,803 INFO L432 AbstractCegarLoop]: Abstraction has 199 states and 200 transitions. [2018-01-24 17:41:58,803 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-01-24 17:41:58,803 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 200 transitions. [2018-01-24 17:41:58,803 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-01-24 17:41:58,803 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 17:41:58,803 INFO L322 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 17:41:58,804 INFO L371 AbstractCegarLoop]: === Iteration 33 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 17:41:58,804 INFO L82 PathProgramCache]: Analyzing trace with hash -1088370982, now seen corresponding path program 31 times [2018-01-24 17:41:58,804 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 17:41:58,804 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:58,804 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 17:41:58,805 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 17:41:58,805 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 17:41:58,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:58,820 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 17:41:59,357 INFO L134 CoverageAnalysis]: Checked inductivity of 2402 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 354 trivial. 0 not checked. [2018-01-24 17:41:59,358 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:59,358 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 17:41:59,358 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 17:41:59,358 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 17:41:59,358 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 17:41:59,358 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 17:41:59,364 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 17:41:59,364 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 17:41:59,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 17:41:59,392 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 17:41:59,417 INFO L134 CoverageAnalysis]: Checked inductivity of 2402 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 354 trivial. 0 not checked. [2018-01-24 17:41:59,417 INFO L314 TraceCheckSpWp]: Computing backward predicates... Received shutdown request... [2018-01-24 17:41:59,448 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-01-24 17:41:59,449 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 17:41:59,452 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 17:41:59,453 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 05:41:59 BoogieIcfgContainer [2018-01-24 17:41:59,453 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 17:41:59,454 INFO L168 Benchmark]: Toolchain (without parser) took 48286.54 ms. Allocated memory was 303.6 MB in the beginning and 768.6 MB in the end (delta: 465.0 MB). Free memory was 262.5 MB in the beginning and 391.1 MB in the end (delta: -128.6 MB). Peak memory consumption was 336.4 MB. Max. memory is 5.3 GB. [2018-01-24 17:41:59,455 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 303.6 MB. Free memory is still 266.5 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 17:41:59,455 INFO L168 Benchmark]: CACSL2BoogieTranslator took 168.52 ms. Allocated memory is still 303.6 MB. Free memory was 262.5 MB in the beginning and 254.5 MB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 5.3 GB. [2018-01-24 17:41:59,455 INFO L168 Benchmark]: Boogie Preprocessor took 26.17 ms. Allocated memory is still 303.6 MB. Free memory was 254.5 MB in the beginning and 252.5 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 17:41:59,455 INFO L168 Benchmark]: RCFGBuilder took 199.65 ms. Allocated memory is still 303.6 MB. Free memory was 252.5 MB in the beginning and 239.5 MB in the end (delta: 13.0 MB). Peak memory consumption was 13.0 MB. Max. memory is 5.3 GB. [2018-01-24 17:41:59,456 INFO L168 Benchmark]: TraceAbstraction took 47884.43 ms. Allocated memory was 303.6 MB in the beginning and 768.6 MB in the end (delta: 465.0 MB). Free memory was 239.5 MB in the beginning and 391.1 MB in the end (delta: -151.5 MB). Peak memory consumption was 313.5 MB. Max. memory is 5.3 GB. [2018-01-24 17:41:59,457 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 303.6 MB. Free memory is still 266.5 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 168.52 ms. Allocated memory is still 303.6 MB. Free memory was 262.5 MB in the beginning and 254.5 MB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 26.17 ms. Allocated memory is still 303.6 MB. Free memory was 254.5 MB in the beginning and 252.5 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 199.65 ms. Allocated memory is still 303.6 MB. Free memory was 252.5 MB in the beginning and 239.5 MB in the end (delta: 13.0 MB). Peak memory consumption was 13.0 MB. Max. memory is 5.3 GB. * TraceAbstraction took 47884.43 ms. Allocated memory was 303.6 MB in the beginning and 768.6 MB in the end (delta: 465.0 MB). Free memory was 239.5 MB in the beginning and 391.1 MB in the end (delta: -151.5 MB). Peak memory consumption was 313.5 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 15 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 2 LocStat_NO_SUPPORTING_DISEQUALITIES : 4 LocStat_NO_DISJUNCTIONS : -30 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 21 TransStat_MAX_WEQGRAPH_SIZE : 0 TransStat_MAX_SIZEOF_WEQEDGELABEL : 0 TransStat_NO_SUPPORTING_EQUALITIES : 9 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 22 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.272632 RENAME_VARIABLES(MILLISECONDS) : 0.452995 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.218717 PROJECTAWAY(MILLISECONDS) : 0.325988 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.008973 DISJOIN(MILLISECONDS) : 0.251611 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.504196 ADD_EQUALITY(MILLISECONDS) : 0.081501 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.126230 #CONJOIN_DISJUNCTIVE : 34 #RENAME_VARIABLES : 76 #UNFREEZE : 0 #CONJOIN : 45 #PROJECTAWAY : 59 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 6 #RENAME_VARIABLES_DISJUNCTIVE : 73 #ADD_EQUALITY : 9 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was analyzing trace of length 199 with TraceHistMax 33, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 35 known predicates. - TimeoutResultAtElement [Line: 15]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 15). Cancelled while BasicCegarLoop was analyzing trace of length 199 with TraceHistMax 33, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 35 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 27 locations, 2 error locations. TIMEOUT Result, 47.8s OverallTime, 33 OverallIterations, 33 TraceHistogramMax, 8.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 534 SDtfs, 3943 SDslu, 4942 SDs, 0 SdLazy, 8216 SolverSat, 1248 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 13553 GetRequests, 12532 SyntacticMatches, 0 SemanticMatches, 1021 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5325 ImplicationChecksByTransitivity, 14.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=199occurred in iteration=32, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.1s AbstIntTime, 1 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.5s AutomataMinimizationTime, 32 MinimizatonAttempts, 1789 StatesRemovedByMinimization, 32 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.3s SsaConstructionTime, 17.3s SatisfiabilityAnalysisTime, 18.6s InterpolantComputationTime, 9789 NumberOfCodeBlocks, 9189 NumberOfCodeBlocksAsserted, 492 NumberOfCheckSat, 16147 ConstructedInterpolants, 0 QuantifiedInterpolants, 4918365 SizeOfPredicates, 40 NumberOfNonLiveVariables, 9300 ConjunctsInSsa, 1040 ConjunctsInUnsatCore, 152 InterpolantComputations, 2 PerfectInterpolantSequences, 43980/122610 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_17-41-59-467.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_17-41-59-467.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_17-41-59-467.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_imprecise.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_17-41-59-467.csv Completed graceful shutdown