java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf -i ../../../trunk/examples/svcomp/loop-acceleration/array3_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 21:05:47,276 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 21:05:47,278 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 21:05:47,292 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 21:05:47,292 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 21:05:47,293 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 21:05:47,294 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 21:05:47,296 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 21:05:47,298 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 21:05:47,299 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 21:05:47,300 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 21:05:47,300 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 21:05:47,301 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 21:05:47,303 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 21:05:47,304 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 21:05:47,306 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 21:05:47,308 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 21:05:47,310 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 21:05:47,312 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 21:05:47,313 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 21:05:47,315 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 21:05:47,315 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 21:05:47,315 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 21:05:47,316 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 21:05:47,317 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 21:05:47,318 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 21:05:47,318 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 21:05:47,319 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 21:05:47,319 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 21:05:47,319 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 21:05:47,320 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 21:05:47,320 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf [2018-01-24 21:05:47,330 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 21:05:47,330 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 21:05:47,331 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 21:05:47,331 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 21:05:47,331 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 21:05:47,331 INFO L133 SettingsManager]: * Weq Fattening=true [2018-01-24 21:05:47,331 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 21:05:47,331 INFO L133 SettingsManager]: * Precise comparison operator=true [2018-01-24 21:05:47,332 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 21:05:47,332 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 21:05:47,332 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 21:05:47,333 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 21:05:47,333 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 21:05:47,333 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 21:05:47,333 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 21:05:47,333 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 21:05:47,333 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 21:05:47,334 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 21:05:47,334 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 21:05:47,334 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 21:05:47,334 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 21:05:47,334 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 21:05:47,334 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 21:05:47,335 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 21:05:47,335 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 21:05:47,335 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 21:05:47,335 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 21:05:47,335 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 21:05:47,335 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 21:05:47,336 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 21:05:47,336 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 21:05:47,336 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 21:05:47,336 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 21:05:47,336 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 21:05:47,336 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 21:05:47,337 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 21:05:47,338 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 21:05:47,373 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 21:05:47,385 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 21:05:47,390 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 21:05:47,391 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 21:05:47,392 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 21:05:47,392 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/array3_false-valid-deref.i [2018-01-24 21:05:47,506 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 21:05:47,513 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 21:05:47,514 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 21:05:47,514 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 21:05:47,521 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 21:05:47,523 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 09:05:47" (1/1) ... [2018-01-24 21:05:47,526 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7d2930b9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 09:05:47, skipping insertion in model container [2018-01-24 21:05:47,527 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 09:05:47" (1/1) ... [2018-01-24 21:05:47,544 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 21:05:47,563 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 21:05:47,678 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 21:05:47,690 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 21:05:47,695 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 09:05:47 WrapperNode [2018-01-24 21:05:47,695 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 21:05:47,696 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 21:05:47,696 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 21:05:47,696 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 21:05:47,707 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 09:05:47" (1/1) ... [2018-01-24 21:05:47,707 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 09:05:47" (1/1) ... [2018-01-24 21:05:47,713 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 09:05:47" (1/1) ... [2018-01-24 21:05:47,713 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 09:05:47" (1/1) ... [2018-01-24 21:05:47,715 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 09:05:47" (1/1) ... [2018-01-24 21:05:47,718 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 09:05:47" (1/1) ... [2018-01-24 21:05:47,719 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 09:05:47" (1/1) ... [2018-01-24 21:05:47,720 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 21:05:47,720 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 21:05:47,720 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 21:05:47,720 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 21:05:47,721 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 09:05:47" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 21:05:47,766 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 21:05:47,766 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 21:05:47,766 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 21:05:47,767 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 21:05:47,767 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 21:05:47,767 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 21:05:47,767 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 21:05:47,767 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 21:05:47,767 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 21:05:47,767 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 21:05:47,891 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 21:05:47,892 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 09:05:47 BoogieIcfgContainer [2018-01-24 21:05:47,892 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 21:05:47,893 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 21:05:47,893 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 21:05:47,895 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 21:05:47,896 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 09:05:47" (1/3) ... [2018-01-24 21:05:47,897 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a1872c8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 09:05:47, skipping insertion in model container [2018-01-24 21:05:47,897 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 09:05:47" (2/3) ... [2018-01-24 21:05:47,897 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a1872c8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 09:05:47, skipping insertion in model container [2018-01-24 21:05:47,898 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 09:05:47" (3/3) ... [2018-01-24 21:05:47,899 INFO L105 eAbstractionObserver]: Analyzing ICFG array3_false-valid-deref.i [2018-01-24 21:05:47,906 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 21:05:47,912 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2018-01-24 21:05:47,948 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 21:05:47,948 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 21:05:47,949 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 21:05:47,949 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 21:05:47,949 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 21:05:47,949 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 21:05:47,949 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 21:05:47,949 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 21:05:47,950 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 21:05:47,970 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states. [2018-01-24 21:05:47,976 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 21:05:47,976 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:47,978 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:47,978 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:47,983 INFO L82 PathProgramCache]: Analyzing trace with hash 1213833872, now seen corresponding path program 1 times [2018-01-24 21:05:47,985 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:48,040 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:48,040 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:05:48,041 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:48,041 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:48,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:48,082 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:48,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 21:05:48,195 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 21:05:48,195 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-24 21:05:48,196 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 21:05:48,198 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 21:05:48,214 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 21:05:48,215 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 21:05:48,218 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 4 states. [2018-01-24 21:05:48,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:48,366 INFO L93 Difference]: Finished difference Result 69 states and 95 transitions. [2018-01-24 21:05:48,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 21:05:48,368 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 8 [2018-01-24 21:05:48,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:48,375 INFO L225 Difference]: With dead ends: 69 [2018-01-24 21:05:48,375 INFO L226 Difference]: Without dead ends: 35 [2018-01-24 21:05:48,378 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 21:05:48,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-01-24 21:05:48,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 31. [2018-01-24 21:05:48,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-01-24 21:05:48,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 32 transitions. [2018-01-24 21:05:48,467 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 32 transitions. Word has length 8 [2018-01-24 21:05:48,468 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:48,468 INFO L432 AbstractCegarLoop]: Abstraction has 31 states and 32 transitions. [2018-01-24 21:05:48,468 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 21:05:48,468 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 32 transitions. [2018-01-24 21:05:48,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-01-24 21:05:48,469 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:48,469 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:48,469 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:48,470 INFO L82 PathProgramCache]: Analyzing trace with hash -863334142, now seen corresponding path program 1 times [2018-01-24 21:05:48,470 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:48,471 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:48,471 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:05:48,471 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:48,471 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:48,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:48,488 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:48,544 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 21:05:48,544 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 21:05:48,544 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-24 21:05:48,545 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 21:05:48,546 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 21:05:48,547 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 21:05:48,547 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-24 21:05:48,547 INFO L87 Difference]: Start difference. First operand 31 states and 32 transitions. Second operand 6 states. [2018-01-24 21:05:48,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:48,630 INFO L93 Difference]: Finished difference Result 35 states and 36 transitions. [2018-01-24 21:05:48,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 21:05:48,631 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 16 [2018-01-24 21:05:48,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:48,632 INFO L225 Difference]: With dead ends: 35 [2018-01-24 21:05:48,632 INFO L226 Difference]: Without dead ends: 34 [2018-01-24 21:05:48,633 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-24 21:05:48,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-01-24 21:05:48,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 29. [2018-01-24 21:05:48,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2018-01-24 21:05:48,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 30 transitions. [2018-01-24 21:05:48,638 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 30 transitions. Word has length 16 [2018-01-24 21:05:48,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:48,639 INFO L432 AbstractCegarLoop]: Abstraction has 29 states and 30 transitions. [2018-01-24 21:05:48,639 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 21:05:48,639 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 30 transitions. [2018-01-24 21:05:48,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-24 21:05:48,640 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:48,640 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:48,640 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:48,640 INFO L82 PathProgramCache]: Analyzing trace with hash -1135364244, now seen corresponding path program 1 times [2018-01-24 21:05:48,640 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:48,641 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:48,642 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:05:48,642 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:48,642 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:48,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:48,653 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:48,696 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 21:05:48,696 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:48,696 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:48,697 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 29 with the following transitions: [2018-01-24 21:05:48,698 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [11], [13], [15], [17], [21], [25], [26], [27], [32], [37], [39], [55], [56], [57] [2018-01-24 21:05:48,738 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 21:05:48,738 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 21:05:48,847 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 21:05:48,848 INFO L268 AbstractInterpreter]: Visited 17 different actions 29 times. Merged at 11 different actions 11 times. Never widened. Found 3 fixpoints after 3 different actions. Largest state had 5 variables. [2018-01-24 21:05:48,861 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 21:05:48,861 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:48,861 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:48,870 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:05:48,871 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 21:05:48,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:48,896 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:48,910 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 21:05:48,910 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:48,955 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 21:05:48,987 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:48,987 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:48,991 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:05:48,991 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 21:05:49,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:49,007 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:49,014 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 21:05:49,014 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:49,032 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 21:05:49,033 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:49,033 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-01-24 21:05:49,034 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:49,034 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 21:05:49,034 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 21:05:49,035 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-24 21:05:49,035 INFO L87 Difference]: Start difference. First operand 29 states and 30 transitions. Second operand 5 states. [2018-01-24 21:05:49,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:49,106 INFO L93 Difference]: Finished difference Result 58 states and 60 transitions. [2018-01-24 21:05:49,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 21:05:49,107 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2018-01-24 21:05:49,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:49,108 INFO L225 Difference]: With dead ends: 58 [2018-01-24 21:05:49,108 INFO L226 Difference]: Without dead ends: 44 [2018-01-24 21:05:49,108 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-24 21:05:49,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-01-24 21:05:49,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 33. [2018-01-24 21:05:49,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-01-24 21:05:49,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 34 transitions. [2018-01-24 21:05:49,119 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 34 transitions. Word has length 28 [2018-01-24 21:05:49,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:49,120 INFO L432 AbstractCegarLoop]: Abstraction has 33 states and 34 transitions. [2018-01-24 21:05:49,120 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 21:05:49,120 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 34 transitions. [2018-01-24 21:05:49,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 21:05:49,121 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:49,121 INFO L322 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:49,121 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:49,122 INFO L82 PathProgramCache]: Analyzing trace with hash 1230203493, now seen corresponding path program 2 times [2018-01-24 21:05:49,122 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:49,123 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:49,123 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:05:49,125 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:49,125 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:49,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:49,137 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:49,184 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 21:05:49,184 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:49,185 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:49,185 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:49,185 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:49,185 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:49,185 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:49,192 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 21:05:49,192 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:05:49,197 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:49,200 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:49,201 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:49,203 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:49,209 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 21:05:49,209 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:49,338 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 21:05:49,357 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:49,357 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:49,360 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 21:05:49,360 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:05:49,366 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:49,372 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:49,377 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:49,380 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:49,385 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 21:05:49,385 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:49,391 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 21:05:49,392 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:49,392 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-01-24 21:05:49,392 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:49,393 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 21:05:49,393 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 21:05:49,393 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-24 21:05:49,393 INFO L87 Difference]: Start difference. First operand 33 states and 34 transitions. Second operand 6 states. [2018-01-24 21:05:49,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:49,445 INFO L93 Difference]: Finished difference Result 67 states and 70 transitions. [2018-01-24 21:05:49,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 21:05:49,445 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 32 [2018-01-24 21:05:49,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:49,446 INFO L225 Difference]: With dead ends: 67 [2018-01-24 21:05:49,446 INFO L226 Difference]: Without dead ends: 53 [2018-01-24 21:05:49,447 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-24 21:05:49,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-01-24 21:05:49,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 37. [2018-01-24 21:05:49,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-01-24 21:05:49,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 38 transitions. [2018-01-24 21:05:49,451 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 38 transitions. Word has length 32 [2018-01-24 21:05:49,451 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:49,451 INFO L432 AbstractCegarLoop]: Abstraction has 37 states and 38 transitions. [2018-01-24 21:05:49,451 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 21:05:49,451 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 38 transitions. [2018-01-24 21:05:49,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-24 21:05:49,452 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:49,452 INFO L322 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:49,452 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:49,452 INFO L82 PathProgramCache]: Analyzing trace with hash 417265886, now seen corresponding path program 3 times [2018-01-24 21:05:49,452 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:49,453 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:49,453 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:49,453 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:49,453 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:49,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:49,465 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:49,512 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-24 21:05:49,512 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:49,512 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:49,512 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:49,512 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:49,513 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:49,513 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:49,517 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 21:05:49,518 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 21:05:49,523 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:49,524 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:49,526 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:49,527 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:49,529 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:49,546 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-24 21:05:49,547 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:49,602 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-24 21:05:49,631 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:49,631 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:49,634 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 21:05:49,634 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 21:05:49,639 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:49,642 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:49,648 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:49,654 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:49,657 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:49,661 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-24 21:05:49,661 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:49,675 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-24 21:05:49,676 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:49,676 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 4, 4] total 13 [2018-01-24 21:05:49,676 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:49,677 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 21:05:49,677 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 21:05:49,677 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2018-01-24 21:05:49,677 INFO L87 Difference]: Start difference. First operand 37 states and 38 transitions. Second operand 10 states. [2018-01-24 21:05:49,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:49,786 INFO L93 Difference]: Finished difference Result 76 states and 80 transitions. [2018-01-24 21:05:49,786 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 21:05:49,786 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 36 [2018-01-24 21:05:49,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:49,787 INFO L225 Difference]: With dead ends: 76 [2018-01-24 21:05:49,787 INFO L226 Difference]: Without dead ends: 62 [2018-01-24 21:05:49,788 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 138 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2018-01-24 21:05:49,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-01-24 21:05:49,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 46. [2018-01-24 21:05:49,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-01-24 21:05:49,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 47 transitions. [2018-01-24 21:05:49,792 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 47 transitions. Word has length 36 [2018-01-24 21:05:49,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:49,793 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 47 transitions. [2018-01-24 21:05:49,793 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 21:05:49,793 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 47 transitions. [2018-01-24 21:05:49,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-01-24 21:05:49,793 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:49,794 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:49,794 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:49,794 INFO L82 PathProgramCache]: Analyzing trace with hash 576961419, now seen corresponding path program 4 times [2018-01-24 21:05:49,794 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:49,795 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:49,795 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:49,795 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:49,795 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:49,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:49,808 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:49,877 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 21:05:49,877 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:49,878 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:49,878 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:49,878 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:49,878 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:49,878 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:49,883 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 21:05:49,883 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 21:05:49,895 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:49,898 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:49,905 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 21:05:49,906 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:49,967 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 21:05:49,987 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:49,987 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:49,990 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 21:05:49,991 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 21:05:50,012 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:50,017 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:50,026 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 21:05:50,026 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:50,038 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 21:05:50,039 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:50,039 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-01-24 21:05:50,039 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:50,040 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 21:05:50,040 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 21:05:50,040 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-24 21:05:50,040 INFO L87 Difference]: Start difference. First operand 46 states and 47 transitions. Second operand 8 states. [2018-01-24 21:05:50,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:50,133 INFO L93 Difference]: Finished difference Result 90 states and 94 transitions. [2018-01-24 21:05:50,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 21:05:50,134 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 45 [2018-01-24 21:05:50,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:50,135 INFO L225 Difference]: With dead ends: 90 [2018-01-24 21:05:50,135 INFO L226 Difference]: Without dead ends: 71 [2018-01-24 21:05:50,136 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 174 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-24 21:05:50,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-01-24 21:05:50,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 50. [2018-01-24 21:05:50,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 21:05:50,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 51 transitions. [2018-01-24 21:05:50,143 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 51 transitions. Word has length 45 [2018-01-24 21:05:50,143 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:50,144 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 51 transitions. [2018-01-24 21:05:50,144 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 21:05:50,144 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 51 transitions. [2018-01-24 21:05:50,145 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-01-24 21:05:50,145 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:50,145 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:50,145 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:50,145 INFO L82 PathProgramCache]: Analyzing trace with hash -194823758, now seen corresponding path program 5 times [2018-01-24 21:05:50,146 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:50,147 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:50,147 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:50,147 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:50,147 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:50,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:50,160 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:50,252 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 21:05:50,253 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:50,253 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:50,253 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:50,253 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:50,253 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:50,253 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:50,266 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 21:05:50,266 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:05:50,271 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,274 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,276 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,278 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,281 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,284 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,288 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,289 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:50,292 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:50,301 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 21:05:50,301 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:50,384 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 21:05:50,404 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:50,404 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:50,407 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 21:05:50,407 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:05:50,412 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,415 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,421 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,429 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,436 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,445 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,465 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:50,470 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:50,475 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:50,486 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 21:05:50,487 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:50,501 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 21:05:50,502 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:50,503 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-01-24 21:05:50,503 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:50,503 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 21:05:50,504 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 21:05:50,504 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-24 21:05:50,504 INFO L87 Difference]: Start difference. First operand 50 states and 51 transitions. Second operand 9 states. [2018-01-24 21:05:50,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:50,586 INFO L93 Difference]: Finished difference Result 99 states and 104 transitions. [2018-01-24 21:05:50,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 21:05:50,586 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 49 [2018-01-24 21:05:50,586 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:50,588 INFO L225 Difference]: With dead ends: 99 [2018-01-24 21:05:50,588 INFO L226 Difference]: Without dead ends: 80 [2018-01-24 21:05:50,589 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-24 21:05:50,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-24 21:05:50,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 54. [2018-01-24 21:05:50,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-01-24 21:05:50,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 55 transitions. [2018-01-24 21:05:50,595 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 55 transitions. Word has length 49 [2018-01-24 21:05:50,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:50,596 INFO L432 AbstractCegarLoop]: Abstraction has 54 states and 55 transitions. [2018-01-24 21:05:50,596 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 21:05:50,596 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 55 transitions. [2018-01-24 21:05:50,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-01-24 21:05:50,596 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:50,596 INFO L322 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:50,597 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:50,597 INFO L82 PathProgramCache]: Analyzing trace with hash -1600566183, now seen corresponding path program 6 times [2018-01-24 21:05:50,597 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:50,597 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:50,598 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:50,598 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:50,598 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:50,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:50,608 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:50,713 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-24 21:05:50,714 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:50,714 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:50,714 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:50,714 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:50,715 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:50,715 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:50,723 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 21:05:50,723 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 21:05:50,728 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,730 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,732 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,734 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,737 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,739 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,742 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,743 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:50,746 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:50,789 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 21:05:50,789 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:50,831 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 21:05:50,851 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:50,852 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:50,854 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 21:05:50,855 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 21:05:50,860 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,862 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,866 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,873 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,880 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,890 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,902 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:50,908 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:50,911 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:50,915 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 21:05:50,915 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:50,929 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-24 21:05:50,931 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:50,931 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 5, 5, 5, 5] total 18 [2018-01-24 21:05:50,931 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:50,932 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 21:05:50,932 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 21:05:50,932 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=203, Unknown=0, NotChecked=0, Total=306 [2018-01-24 21:05:50,932 INFO L87 Difference]: Start difference. First operand 54 states and 55 transitions. Second operand 14 states. [2018-01-24 21:05:51,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:51,137 INFO L93 Difference]: Finished difference Result 108 states and 114 transitions. [2018-01-24 21:05:51,137 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 21:05:51,138 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 53 [2018-01-24 21:05:51,138 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:51,138 INFO L225 Difference]: With dead ends: 108 [2018-01-24 21:05:51,138 INFO L226 Difference]: Without dead ends: 89 [2018-01-24 21:05:51,139 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 204 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 100 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=103, Invalid=203, Unknown=0, NotChecked=0, Total=306 [2018-01-24 21:05:51,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-01-24 21:05:51,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 63. [2018-01-24 21:05:51,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-01-24 21:05:51,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 64 transitions. [2018-01-24 21:05:51,147 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 64 transitions. Word has length 53 [2018-01-24 21:05:51,147 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:51,147 INFO L432 AbstractCegarLoop]: Abstraction has 63 states and 64 transitions. [2018-01-24 21:05:51,148 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 21:05:51,148 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 64 transitions. [2018-01-24 21:05:51,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 21:05:51,149 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:51,149 INFO L322 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:51,149 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:51,149 INFO L82 PathProgramCache]: Analyzing trace with hash 1495641218, now seen corresponding path program 7 times [2018-01-24 21:05:51,149 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:51,150 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:51,150 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:51,150 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:51,150 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:51,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:51,162 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:51,234 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 21:05:51,235 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:51,235 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:51,235 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:51,235 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:51,235 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:51,235 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:51,241 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:05:51,241 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 21:05:51,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:51,262 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:51,271 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 21:05:51,272 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:51,479 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 21:05:51,500 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:51,500 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:51,512 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:05:51,512 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 21:05:51,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:51,535 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:51,545 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 21:05:51,546 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:51,559 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 21:05:51,561 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:51,561 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-01-24 21:05:51,561 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:51,562 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 21:05:51,562 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 21:05:51,562 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-24 21:05:51,563 INFO L87 Difference]: Start difference. First operand 63 states and 64 transitions. Second operand 11 states. [2018-01-24 21:05:51,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:51,686 INFO L93 Difference]: Finished difference Result 122 states and 128 transitions. [2018-01-24 21:05:51,687 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 21:05:51,687 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 62 [2018-01-24 21:05:51,687 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:51,688 INFO L225 Difference]: With dead ends: 122 [2018-01-24 21:05:51,688 INFO L226 Difference]: Without dead ends: 98 [2018-01-24 21:05:51,689 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 239 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-24 21:05:51,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-01-24 21:05:51,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 67. [2018-01-24 21:05:51,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-01-24 21:05:51,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 68 transitions. [2018-01-24 21:05:51,697 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 68 transitions. Word has length 62 [2018-01-24 21:05:51,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:51,698 INFO L432 AbstractCegarLoop]: Abstraction has 67 states and 68 transitions. [2018-01-24 21:05:51,698 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 21:05:51,698 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 68 transitions. [2018-01-24 21:05:51,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-01-24 21:05:51,699 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:51,699 INFO L322 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:51,700 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:51,700 INFO L82 PathProgramCache]: Analyzing trace with hash -1534369477, now seen corresponding path program 8 times [2018-01-24 21:05:51,700 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:51,701 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:51,701 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:05:51,701 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:51,701 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:51,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:51,713 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:51,802 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 21:05:51,802 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:51,802 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:51,802 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:51,802 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:51,802 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:51,802 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:51,809 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 21:05:51,810 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:05:51,816 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:51,824 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:51,826 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:51,828 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:51,839 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 21:05:51,839 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:52,004 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 21:05:52,025 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:52,025 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:52,028 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 21:05:52,028 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:05:52,033 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:52,043 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:52,050 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:52,053 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:52,061 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 21:05:52,061 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:52,072 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 21:05:52,074 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:52,074 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-01-24 21:05:52,074 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:52,074 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 21:05:52,074 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 21:05:52,075 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-24 21:05:52,075 INFO L87 Difference]: Start difference. First operand 67 states and 68 transitions. Second operand 12 states. [2018-01-24 21:05:52,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:52,148 INFO L93 Difference]: Finished difference Result 131 states and 138 transitions. [2018-01-24 21:05:52,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 21:05:52,149 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 66 [2018-01-24 21:05:52,149 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:52,149 INFO L225 Difference]: With dead ends: 131 [2018-01-24 21:05:52,150 INFO L226 Difference]: Without dead ends: 107 [2018-01-24 21:05:52,150 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 274 GetRequests, 254 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-24 21:05:52,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-01-24 21:05:52,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 71. [2018-01-24 21:05:52,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-01-24 21:05:52,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 72 transitions. [2018-01-24 21:05:52,156 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 72 transitions. Word has length 66 [2018-01-24 21:05:52,156 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:52,156 INFO L432 AbstractCegarLoop]: Abstraction has 71 states and 72 transitions. [2018-01-24 21:05:52,156 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 21:05:52,157 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 72 transitions. [2018-01-24 21:05:52,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-01-24 21:05:52,158 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:52,158 INFO L322 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:52,158 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:52,158 INFO L82 PathProgramCache]: Analyzing trace with hash -1473900172, now seen corresponding path program 9 times [2018-01-24 21:05:52,158 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:52,159 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:52,159 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:52,159 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:52,160 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:52,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:52,171 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:52,255 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-24 21:05:52,255 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:52,255 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:52,255 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:52,255 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:52,255 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:52,255 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:52,261 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 21:05:52,261 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 21:05:52,266 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:52,268 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:52,269 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:52,271 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:52,272 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:52,273 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:52,274 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:52,295 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 21:05:52,295 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:52,354 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 21:05:52,374 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:52,374 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:52,377 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 21:05:52,377 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 21:05:52,382 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:52,385 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:52,390 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:52,398 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:52,408 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:52,414 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:52,418 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:52,424 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-24 21:05:52,424 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:52,436 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [MP cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (19)] Exception during sending of exit command (exit): Broken pipe [2018-01-24 21:05:52,439 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:52,439 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 6, 6, 6, 6] total 23 [2018-01-24 21:05:52,439 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:52,440 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 21:05:52,440 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 21:05:52,440 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=168, Invalid=338, Unknown=0, NotChecked=0, Total=506 [2018-01-24 21:05:52,441 INFO L87 Difference]: Start difference. First operand 71 states and 72 transitions. Second operand 18 states. [2018-01-24 21:05:52,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:52,675 INFO L93 Difference]: Finished difference Result 140 states and 148 transitions. [2018-01-24 21:05:52,675 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 21:05:52,675 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 70 [2018-01-24 21:05:52,676 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:52,676 INFO L225 Difference]: With dead ends: 140 [2018-01-24 21:05:52,676 INFO L226 Difference]: Without dead ends: 116 [2018-01-24 21:05:52,677 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 291 GetRequests, 270 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 175 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=168, Invalid=338, Unknown=0, NotChecked=0, Total=506 [2018-01-24 21:05:52,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-01-24 21:05:52,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 80. [2018-01-24 21:05:52,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-01-24 21:05:52,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 81 transitions. [2018-01-24 21:05:52,683 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 81 transitions. Word has length 70 [2018-01-24 21:05:52,683 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:52,683 INFO L432 AbstractCegarLoop]: Abstraction has 80 states and 81 transitions. [2018-01-24 21:05:52,683 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 21:05:52,683 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 81 transitions. [2018-01-24 21:05:52,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-01-24 21:05:52,684 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:52,684 INFO L322 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:52,684 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:52,684 INFO L82 PathProgramCache]: Analyzing trace with hash -1757583627, now seen corresponding path program 10 times [2018-01-24 21:05:52,684 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:52,685 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:52,685 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:52,685 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:52,685 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:52,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:52,698 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:52,827 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 21:05:52,828 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:52,828 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:52,828 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:52,828 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:52,828 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:52,828 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:52,845 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 21:05:52,845 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 21:05:52,858 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:52,860 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:52,868 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 21:05:52,868 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:53,012 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 21:05:53,032 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:53,032 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:53,035 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 21:05:53,035 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 21:05:53,062 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:53,066 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:53,075 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 21:05:53,075 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:53,085 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 21:05:53,086 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:53,086 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-01-24 21:05:53,086 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:53,086 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 21:05:53,087 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 21:05:53,087 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-24 21:05:53,087 INFO L87 Difference]: Start difference. First operand 80 states and 81 transitions. Second operand 14 states. [2018-01-24 21:05:53,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:53,196 INFO L93 Difference]: Finished difference Result 154 states and 162 transitions. [2018-01-24 21:05:53,196 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 21:05:53,196 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 79 [2018-01-24 21:05:53,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:53,197 INFO L225 Difference]: With dead ends: 154 [2018-01-24 21:05:53,197 INFO L226 Difference]: Without dead ends: 125 [2018-01-24 21:05:53,197 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 328 GetRequests, 304 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-24 21:05:53,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2018-01-24 21:05:53,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 84. [2018-01-24 21:05:53,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-01-24 21:05:53,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 85 transitions. [2018-01-24 21:05:53,207 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 85 transitions. Word has length 79 [2018-01-24 21:05:53,207 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:53,207 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 85 transitions. [2018-01-24 21:05:53,207 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 21:05:53,207 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 85 transitions. [2018-01-24 21:05:53,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-01-24 21:05:53,209 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:53,209 INFO L322 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:53,209 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:53,209 INFO L82 PathProgramCache]: Analyzing trace with hash -2099078308, now seen corresponding path program 11 times [2018-01-24 21:05:53,210 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:53,210 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:53,210 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:53,211 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:53,211 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:53,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:53,224 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:53,352 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 21:05:53,352 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:53,352 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:53,352 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:53,352 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:53,352 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:53,352 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:53,358 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 21:05:53,359 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:05:53,363 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,364 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,365 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,366 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,367 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,368 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,370 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,372 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,374 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,377 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,379 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,382 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,387 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,387 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:53,389 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:53,399 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 21:05:53,399 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:53,648 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 21:05:53,669 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:53,669 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:53,672 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 21:05:53,672 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:05:53,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,680 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,685 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,690 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,695 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,702 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,710 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,721 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,734 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,749 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,767 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,792 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,882 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:53,893 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:53,897 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:53,905 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 21:05:53,905 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:53,921 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 21:05:53,922 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:53,923 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-01-24 21:05:53,923 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:53,923 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 21:05:53,923 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 21:05:53,923 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-24 21:05:53,923 INFO L87 Difference]: Start difference. First operand 84 states and 85 transitions. Second operand 15 states. [2018-01-24 21:05:54,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:54,051 INFO L93 Difference]: Finished difference Result 163 states and 172 transitions. [2018-01-24 21:05:54,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 21:05:54,051 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 83 [2018-01-24 21:05:54,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:54,052 INFO L225 Difference]: With dead ends: 163 [2018-01-24 21:05:54,052 INFO L226 Difference]: Without dead ends: 134 [2018-01-24 21:05:54,053 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 345 GetRequests, 319 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-24 21:05:54,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-01-24 21:05:54,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 88. [2018-01-24 21:05:54,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-01-24 21:05:54,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 89 transitions. [2018-01-24 21:05:54,059 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 89 transitions. Word has length 83 [2018-01-24 21:05:54,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:54,059 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 89 transitions. [2018-01-24 21:05:54,059 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 21:05:54,059 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 89 transitions. [2018-01-24 21:05:54,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 21:05:54,060 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:54,061 INFO L322 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:54,061 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:54,061 INFO L82 PathProgramCache]: Analyzing trace with hash -159824829, now seen corresponding path program 12 times [2018-01-24 21:05:54,061 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:54,062 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:54,062 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:54,062 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:54,062 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:54,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:54,075 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:54,219 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 21:05:54,219 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:54,219 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:54,220 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:54,220 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:54,220 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:54,220 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:54,228 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 21:05:54,228 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 21:05:54,234 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,237 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,238 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,240 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,241 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,243 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,247 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,249 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,251 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,254 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,256 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,257 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:54,259 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:54,291 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 21:05:54,291 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:54,400 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 21:05:54,432 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:54,432 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:54,435 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 21:05:54,435 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 21:05:54,442 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,445 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,452 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,460 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,471 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,487 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,506 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,519 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,535 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,568 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,593 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:54,600 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:54,603 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:54,612 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 21:05:54,612 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:54,623 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-24 21:05:54,624 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:54,625 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 7, 7, 7, 7] total 28 [2018-01-24 21:05:54,625 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:54,625 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 21:05:54,625 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 21:05:54,626 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=249, Invalid=507, Unknown=0, NotChecked=0, Total=756 [2018-01-24 21:05:54,626 INFO L87 Difference]: Start difference. First operand 88 states and 89 transitions. Second operand 22 states. [2018-01-24 21:05:54,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:54,786 INFO L93 Difference]: Finished difference Result 172 states and 182 transitions. [2018-01-24 21:05:54,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 21:05:54,787 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 87 [2018-01-24 21:05:54,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:54,788 INFO L225 Difference]: With dead ends: 172 [2018-01-24 21:05:54,788 INFO L226 Difference]: Without dead ends: 143 [2018-01-24 21:05:54,789 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 362 GetRequests, 336 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 270 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=249, Invalid=507, Unknown=0, NotChecked=0, Total=756 [2018-01-24 21:05:54,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-01-24 21:05:54,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 97. [2018-01-24 21:05:54,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-01-24 21:05:54,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 98 transitions. [2018-01-24 21:05:54,797 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 98 transitions. Word has length 87 [2018-01-24 21:05:54,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:54,797 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 98 transitions. [2018-01-24 21:05:54,797 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 21:05:54,797 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 98 transitions. [2018-01-24 21:05:54,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-01-24 21:05:54,799 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:54,799 INFO L322 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:54,799 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:54,799 INFO L82 PathProgramCache]: Analyzing trace with hash -2110093160, now seen corresponding path program 13 times [2018-01-24 21:05:54,799 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:54,800 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:54,800 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:54,800 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:54,800 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:54,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:54,815 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:54,977 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 21:05:54,978 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:54,978 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:54,978 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:54,978 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:54,978 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:54,978 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:54,984 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:05:54,984 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 21:05:54,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:55,000 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:55,010 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 21:05:55,010 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:55,218 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 21:05:55,238 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:55,238 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:55,241 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:05:55,241 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 21:05:55,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:55,271 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:55,284 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 21:05:55,284 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:55,297 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 21:05:55,298 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:55,299 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-01-24 21:05:55,299 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:55,299 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 21:05:55,299 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 21:05:55,299 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-24 21:05:55,300 INFO L87 Difference]: Start difference. First operand 97 states and 98 transitions. Second operand 17 states. [2018-01-24 21:05:55,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:55,430 INFO L93 Difference]: Finished difference Result 186 states and 196 transitions. [2018-01-24 21:05:55,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 21:05:55,431 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 96 [2018-01-24 21:05:55,431 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:55,432 INFO L225 Difference]: With dead ends: 186 [2018-01-24 21:05:55,432 INFO L226 Difference]: Without dead ends: 152 [2018-01-24 21:05:55,432 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 399 GetRequests, 369 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-24 21:05:55,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-24 21:05:55,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 101. [2018-01-24 21:05:55,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-01-24 21:05:55,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 102 transitions. [2018-01-24 21:05:55,440 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 102 transitions. Word has length 96 [2018-01-24 21:05:55,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:55,440 INFO L432 AbstractCegarLoop]: Abstraction has 101 states and 102 transitions. [2018-01-24 21:05:55,440 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 21:05:55,440 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 102 transitions. [2018-01-24 21:05:55,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-01-24 21:05:55,441 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:55,441 INFO L322 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:55,441 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:55,441 INFO L82 PathProgramCache]: Analyzing trace with hash 1842728721, now seen corresponding path program 14 times [2018-01-24 21:05:55,441 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:55,442 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:55,442 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:05:55,442 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:55,442 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:55,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:55,452 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:55,630 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 21:05:55,630 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:55,630 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:55,630 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:55,630 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:55,630 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:55,631 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:55,636 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 21:05:55,636 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:05:55,642 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:55,650 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:55,652 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:55,654 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:55,664 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 21:05:55,664 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:55,890 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 21:05:55,910 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:55,910 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:55,913 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 21:05:55,913 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:05:55,921 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:55,934 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:55,945 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:55,948 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:55,960 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 21:05:55,960 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:56,000 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 21:05:56,002 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:56,002 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-01-24 21:05:56,002 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:56,002 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 21:05:56,002 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 21:05:56,003 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 21:05:56,003 INFO L87 Difference]: Start difference. First operand 101 states and 102 transitions. Second operand 18 states. [2018-01-24 21:05:56,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:56,170 INFO L93 Difference]: Finished difference Result 195 states and 206 transitions. [2018-01-24 21:05:56,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 21:05:56,170 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 100 [2018-01-24 21:05:56,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:56,171 INFO L225 Difference]: With dead ends: 195 [2018-01-24 21:05:56,172 INFO L226 Difference]: Without dead ends: 161 [2018-01-24 21:05:56,172 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 416 GetRequests, 384 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 21:05:56,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-01-24 21:05:56,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 105. [2018-01-24 21:05:56,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-01-24 21:05:56,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 106 transitions. [2018-01-24 21:05:56,187 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 106 transitions. Word has length 100 [2018-01-24 21:05:56,187 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:56,187 INFO L432 AbstractCegarLoop]: Abstraction has 105 states and 106 transitions. [2018-01-24 21:05:56,187 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 21:05:56,188 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 106 transitions. [2018-01-24 21:05:56,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-01-24 21:05:56,188 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:56,189 INFO L322 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:56,189 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:56,189 INFO L82 PathProgramCache]: Analyzing trace with hash -184078070, now seen corresponding path program 15 times [2018-01-24 21:05:56,189 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:56,190 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:56,190 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:56,190 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:56,190 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:56,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:56,203 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:56,372 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-24 21:05:56,372 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:56,372 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:56,373 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:56,373 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:56,373 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:56,373 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:56,378 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 21:05:56,378 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 21:05:56,384 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,385 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,387 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,389 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,391 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,393 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,395 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,396 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:56,398 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:56,431 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 21:05:56,431 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:56,607 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 21:05:56,628 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:56,629 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:56,632 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 21:05:56,632 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 21:05:56,641 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,643 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,649 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,656 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,666 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,680 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,700 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:05:56,707 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:56,711 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:56,722 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 21:05:56,722 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:56,747 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-24 21:05:56,748 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:56,749 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 8, 8, 8, 8] total 33 [2018-01-24 21:05:56,749 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:56,749 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 21:05:56,749 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 21:05:56,750 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=346, Invalid=710, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 21:05:56,750 INFO L87 Difference]: Start difference. First operand 105 states and 106 transitions. Second operand 26 states. [2018-01-24 21:05:57,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:57,008 INFO L93 Difference]: Finished difference Result 204 states and 216 transitions. [2018-01-24 21:05:57,008 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 21:05:57,008 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 104 [2018-01-24 21:05:57,009 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:57,009 INFO L225 Difference]: With dead ends: 204 [2018-01-24 21:05:57,009 INFO L226 Difference]: Without dead ends: 170 [2018-01-24 21:05:57,010 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 433 GetRequests, 402 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 385 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=346, Invalid=710, Unknown=0, NotChecked=0, Total=1056 [2018-01-24 21:05:57,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2018-01-24 21:05:57,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 114. [2018-01-24 21:05:57,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-01-24 21:05:57,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 115 transitions. [2018-01-24 21:05:57,019 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 115 transitions. Word has length 104 [2018-01-24 21:05:57,019 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:57,019 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 115 transitions. [2018-01-24 21:05:57,019 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 21:05:57,019 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 115 transitions. [2018-01-24 21:05:57,020 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-01-24 21:05:57,020 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:57,020 INFO L322 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:57,020 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:57,020 INFO L82 PathProgramCache]: Analyzing trace with hash 950262623, now seen corresponding path program 16 times [2018-01-24 21:05:57,020 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:57,021 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:57,021 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:57,021 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:57,022 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:57,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:57,035 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:57,217 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 21:05:57,218 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:57,218 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:57,218 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:57,218 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:57,218 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:57,218 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:57,223 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 21:05:57,223 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 21:05:57,242 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:57,244 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:57,263 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 21:05:57,263 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:57,610 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 21:05:57,631 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:57,631 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:57,635 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 21:05:57,635 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 21:05:57,676 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:57,680 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:57,692 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 21:05:57,692 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:57,710 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 21:05:57,711 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:57,711 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-01-24 21:05:57,711 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:57,712 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 21:05:57,712 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 21:05:57,712 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 21:05:57,713 INFO L87 Difference]: Start difference. First operand 114 states and 115 transitions. Second operand 20 states. [2018-01-24 21:05:58,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:58,002 INFO L93 Difference]: Finished difference Result 218 states and 230 transitions. [2018-01-24 21:05:58,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 21:05:58,002 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 113 [2018-01-24 21:05:58,002 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:58,003 INFO L225 Difference]: With dead ends: 218 [2018-01-24 21:05:58,003 INFO L226 Difference]: Without dead ends: 179 [2018-01-24 21:05:58,004 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 470 GetRequests, 434 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 21:05:58,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-01-24 21:05:58,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 118. [2018-01-24 21:05:58,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-24 21:05:58,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 119 transitions. [2018-01-24 21:05:58,013 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 119 transitions. Word has length 113 [2018-01-24 21:05:58,013 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:58,013 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 119 transitions. [2018-01-24 21:05:58,013 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 21:05:58,013 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 119 transitions. [2018-01-24 21:05:58,014 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-01-24 21:05:58,014 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:58,014 INFO L322 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:58,014 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:58,014 INFO L82 PathProgramCache]: Analyzing trace with hash 1664169478, now seen corresponding path program 17 times [2018-01-24 21:05:58,014 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:58,015 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:58,015 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:58,015 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:58,016 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:58,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:58,025 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:58,271 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 21:05:58,271 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:58,271 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:58,271 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:58,271 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:58,271 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:58,271 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:58,276 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 21:05:58,276 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:05:58,283 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,284 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,285 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,286 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,287 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,288 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,289 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,291 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,292 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,294 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,296 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,299 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,301 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,305 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,308 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,312 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,316 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,321 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,333 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,333 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:58,336 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:58,348 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 21:05:58,348 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:58,651 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 21:05:58,671 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:58,671 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:05:58,673 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 21:05:58,674 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:05:58,680 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,682 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,686 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,691 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,696 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,703 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,711 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,721 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,732 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,746 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,762 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,781 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,805 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,833 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,869 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,909 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:58,957 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:59,014 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:59,323 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:05:59,338 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:59,343 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:59,362 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 21:05:59,362 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:05:59,397 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 21:05:59,398 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:05:59,399 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-01-24 21:05:59,399 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:05:59,399 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 21:05:59,399 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 21:05:59,400 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 21:05:59,400 INFO L87 Difference]: Start difference. First operand 118 states and 119 transitions. Second operand 21 states. [2018-01-24 21:05:59,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:05:59,558 INFO L93 Difference]: Finished difference Result 227 states and 240 transitions. [2018-01-24 21:05:59,558 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 21:05:59,558 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 117 [2018-01-24 21:05:59,558 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:05:59,559 INFO L225 Difference]: With dead ends: 227 [2018-01-24 21:05:59,559 INFO L226 Difference]: Without dead ends: 188 [2018-01-24 21:05:59,559 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 487 GetRequests, 449 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 21:05:59,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-01-24 21:05:59,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 122. [2018-01-24 21:05:59,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-01-24 21:05:59,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 123 transitions. [2018-01-24 21:05:59,568 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 123 transitions. Word has length 117 [2018-01-24 21:05:59,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:05:59,569 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 123 transitions. [2018-01-24 21:05:59,569 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 21:05:59,569 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 123 transitions. [2018-01-24 21:05:59,569 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-01-24 21:05:59,569 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:05:59,569 INFO L322 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:05:59,569 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:05:59,569 INFO L82 PathProgramCache]: Analyzing trace with hash 2092098861, now seen corresponding path program 18 times [2018-01-24 21:05:59,570 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:05:59,570 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:59,570 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:05:59,570 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:05:59,570 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:05:59,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:05:59,580 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:05:59,772 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 722 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-24 21:05:59,773 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:59,773 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:05:59,773 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:05:59,773 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:05:59,773 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:05:59,773 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:05:59,778 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 21:05:59,778 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 21:05:59,784 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,785 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,786 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,787 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,817 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,818 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,820 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,821 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,823 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,824 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,826 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,828 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,830 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,833 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,836 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:05:59,837 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:05:59,839 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:05:59,886 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-24 21:05:59,886 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:00,002 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-24 21:06:00,023 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:00,023 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:00,026 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 21:06:00,026 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 21:06:00,033 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,035 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,039 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,045 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,052 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,061 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,073 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,089 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,105 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,127 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,154 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,189 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,231 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,307 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,369 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:00,382 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:00,387 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:00,395 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-24 21:06:00,395 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:00,417 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-24 21:06:00,418 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:00,419 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 9, 9, 9, 9] total 38 [2018-01-24 21:06:00,419 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:00,419 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 21:06:00,419 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 21:06:00,420 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=459, Invalid=947, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 21:06:00,420 INFO L87 Difference]: Start difference. First operand 122 states and 123 transitions. Second operand 30 states. [2018-01-24 21:06:00,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:00,870 INFO L93 Difference]: Finished difference Result 236 states and 250 transitions. [2018-01-24 21:06:00,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 21:06:00,870 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 121 [2018-01-24 21:06:00,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:00,871 INFO L225 Difference]: With dead ends: 236 [2018-01-24 21:06:00,871 INFO L226 Difference]: Without dead ends: 197 [2018-01-24 21:06:00,872 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 504 GetRequests, 468 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 520 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=459, Invalid=947, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 21:06:00,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2018-01-24 21:06:00,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 131. [2018-01-24 21:06:00,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-01-24 21:06:00,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 132 transitions. [2018-01-24 21:06:00,888 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 132 transitions. Word has length 121 [2018-01-24 21:06:00,888 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:00,888 INFO L432 AbstractCegarLoop]: Abstraction has 131 states and 132 transitions. [2018-01-24 21:06:00,888 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 21:06:00,888 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 132 transitions. [2018-01-24 21:06:00,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-01-24 21:06:00,888 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:00,889 INFO L322 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:00,889 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:00,889 INFO L82 PathProgramCache]: Analyzing trace with hash 734718894, now seen corresponding path program 19 times [2018-01-24 21:06:00,889 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:00,890 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:00,890 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:06:00,890 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:00,890 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:00,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:00,902 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:01,221 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 21:06:01,221 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:01,221 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:01,221 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:01,221 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:01,221 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:01,222 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:01,227 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:06:01,227 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 21:06:01,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:01,247 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:01,269 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 21:06:01,269 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:01,812 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 21:06:01,833 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:01,833 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:01,836 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:06:01,836 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 21:06:01,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:01,879 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:01,902 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 21:06:01,902 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:01,938 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 21:06:01,939 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:01,939 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-01-24 21:06:01,939 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:01,940 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 21:06:01,940 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 21:06:01,941 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 21:06:01,941 INFO L87 Difference]: Start difference. First operand 131 states and 132 transitions. Second operand 23 states. [2018-01-24 21:06:02,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:02,347 INFO L93 Difference]: Finished difference Result 250 states and 264 transitions. [2018-01-24 21:06:02,347 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 21:06:02,347 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 130 [2018-01-24 21:06:02,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:02,348 INFO L225 Difference]: With dead ends: 250 [2018-01-24 21:06:02,348 INFO L226 Difference]: Without dead ends: 206 [2018-01-24 21:06:02,349 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 541 GetRequests, 499 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 21:06:02,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-01-24 21:06:02,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 135. [2018-01-24 21:06:02,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-24 21:06:02,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 136 transitions. [2018-01-24 21:06:02,362 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 136 transitions. Word has length 130 [2018-01-24 21:06:02,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:02,362 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 136 transitions. [2018-01-24 21:06:02,362 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 21:06:02,363 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 136 transitions. [2018-01-24 21:06:02,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-01-24 21:06:02,363 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:02,363 INFO L322 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:02,363 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:02,363 INFO L82 PathProgramCache]: Analyzing trace with hash 1367823335, now seen corresponding path program 20 times [2018-01-24 21:06:02,363 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:02,364 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:02,364 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:06:02,364 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:02,364 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:02,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:02,375 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:02,647 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 21:06:02,647 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:02,648 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:02,648 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:02,648 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:02,648 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:02,648 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:02,653 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 21:06:02,653 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:06:02,659 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:02,669 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:02,671 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:02,673 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:02,687 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 21:06:02,687 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:03,284 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 21:06:03,303 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:03,303 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:03,306 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 21:06:03,307 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:06:03,316 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:03,336 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:03,350 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:03,354 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:03,369 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 21:06:03,369 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:03,395 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 21:06:03,396 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:03,396 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 46 [2018-01-24 21:06:03,396 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:03,397 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 21:06:03,397 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 21:06:03,397 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 21:06:03,398 INFO L87 Difference]: Start difference. First operand 135 states and 136 transitions. Second operand 24 states. [2018-01-24 21:06:03,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:03,664 INFO L93 Difference]: Finished difference Result 259 states and 274 transitions. [2018-01-24 21:06:03,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 21:06:03,664 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 134 [2018-01-24 21:06:03,664 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:03,666 INFO L225 Difference]: With dead ends: 259 [2018-01-24 21:06:03,666 INFO L226 Difference]: Without dead ends: 215 [2018-01-24 21:06:03,666 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 558 GetRequests, 514 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 21:06:03,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states. [2018-01-24 21:06:03,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 139. [2018-01-24 21:06:03,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-01-24 21:06:03,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 140 transitions. [2018-01-24 21:06:03,679 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 140 transitions. Word has length 134 [2018-01-24 21:06:03,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:03,679 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 140 transitions. [2018-01-24 21:06:03,679 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 21:06:03,679 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 140 transitions. [2018-01-24 21:06:03,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-24 21:06:03,680 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:03,680 INFO L322 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:03,680 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:03,680 INFO L82 PathProgramCache]: Analyzing trace with hash -168626272, now seen corresponding path program 21 times [2018-01-24 21:06:03,680 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:03,681 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:03,681 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:06:03,681 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:03,681 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:03,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:03,691 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:04,027 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 968 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-24 21:06:04,028 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:04,028 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:04,028 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:04,028 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:04,028 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:04,028 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:04,033 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 21:06:04,033 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 21:06:04,040 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,042 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,043 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,045 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,046 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,048 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,050 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,053 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,056 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,057 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:04,059 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:04,127 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-24 21:06:04,127 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:04,270 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-24 21:06:04,290 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:04,290 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:04,293 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 21:06:04,293 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 21:06:04,301 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,304 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,311 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,322 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,336 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,356 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,384 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,411 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,448 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:04,457 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:04,461 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:04,470 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-24 21:06:04,470 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:04,498 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-24 21:06:04,499 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:04,500 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 10, 10, 10, 10] total 43 [2018-01-24 21:06:04,500 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:04,500 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-01-24 21:06:04,500 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-01-24 21:06:04,501 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=588, Invalid=1218, Unknown=0, NotChecked=0, Total=1806 [2018-01-24 21:06:04,501 INFO L87 Difference]: Start difference. First operand 139 states and 140 transitions. Second operand 34 states. [2018-01-24 21:06:04,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:04,911 INFO L93 Difference]: Finished difference Result 268 states and 284 transitions. [2018-01-24 21:06:04,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 21:06:04,933 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 138 [2018-01-24 21:06:04,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:04,934 INFO L225 Difference]: With dead ends: 268 [2018-01-24 21:06:04,935 INFO L226 Difference]: Without dead ends: 224 [2018-01-24 21:06:04,935 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 575 GetRequests, 534 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 675 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=588, Invalid=1218, Unknown=0, NotChecked=0, Total=1806 [2018-01-24 21:06:04,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-01-24 21:06:04,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 148. [2018-01-24 21:06:04,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-01-24 21:06:04,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 149 transitions. [2018-01-24 21:06:04,951 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 149 transitions. Word has length 138 [2018-01-24 21:06:04,951 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:04,951 INFO L432 AbstractCegarLoop]: Abstraction has 148 states and 149 transitions. [2018-01-24 21:06:04,951 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-01-24 21:06:04,951 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 149 transitions. [2018-01-24 21:06:04,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2018-01-24 21:06:04,952 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:04,952 INFO L322 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:04,952 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:04,952 INFO L82 PathProgramCache]: Analyzing trace with hash -219252535, now seen corresponding path program 22 times [2018-01-24 21:06:04,952 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:04,953 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:04,953 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:06:04,953 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:04,953 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:04,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:04,963 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:05,659 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 21:06:05,659 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:05,659 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:05,659 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:05,659 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:05,659 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:05,659 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:05,664 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 21:06:05,665 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 21:06:05,688 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:05,690 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:05,706 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 21:06:05,706 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:06,184 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 21:06:06,204 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:06,204 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:06,210 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 21:06:06,210 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 21:06:06,260 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:06,264 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:06,280 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 21:06:06,280 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:06,298 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 21:06:06,300 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:06,300 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-01-24 21:06:06,300 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:06,300 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 21:06:06,300 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 21:06:06,301 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 21:06:06,301 INFO L87 Difference]: Start difference. First operand 148 states and 149 transitions. Second operand 26 states. [2018-01-24 21:06:06,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:06,623 INFO L93 Difference]: Finished difference Result 282 states and 298 transitions. [2018-01-24 21:06:06,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 21:06:06,624 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 147 [2018-01-24 21:06:06,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:06,625 INFO L225 Difference]: With dead ends: 282 [2018-01-24 21:06:06,625 INFO L226 Difference]: Without dead ends: 233 [2018-01-24 21:06:06,625 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 612 GetRequests, 564 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 21:06:06,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2018-01-24 21:06:06,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 152. [2018-01-24 21:06:06,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-01-24 21:06:06,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 153 transitions. [2018-01-24 21:06:06,641 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 153 transitions. Word has length 147 [2018-01-24 21:06:06,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:06,641 INFO L432 AbstractCegarLoop]: Abstraction has 152 states and 153 transitions. [2018-01-24 21:06:06,641 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 21:06:06,641 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 153 transitions. [2018-01-24 21:06:06,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2018-01-24 21:06:06,642 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:06,642 INFO L322 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:06,642 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:06,642 INFO L82 PathProgramCache]: Analyzing trace with hash -2062915152, now seen corresponding path program 23 times [2018-01-24 21:06:06,642 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:06,643 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:06,643 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:06:06,643 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:06,643 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:06,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:06,653 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:06,929 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 21:06:06,929 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:06,929 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:06,929 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:06,929 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:06,930 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:06,930 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:06,934 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 21:06:06,934 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:06:06,941 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,942 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,943 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,944 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,945 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,946 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,948 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,949 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,951 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,952 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,954 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,956 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,959 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,962 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,965 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,969 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,973 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,978 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,983 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,989 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:06,996 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,004 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,012 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,021 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,041 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,042 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:07,045 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:07,069 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 21:06:07,069 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:07,579 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 21:06:07,600 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:07,600 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:07,603 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 21:06:07,603 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:06:07,610 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,612 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,616 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,621 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,626 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,632 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,640 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,649 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,661 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,673 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,687 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,704 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,724 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,748 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,773 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,803 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,837 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,878 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,934 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:07,994 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:08,065 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:08,149 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:08,254 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:08,369 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:09,390 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:09,435 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:09,441 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:09,457 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 21:06:09,457 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:09,478 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 21:06:09,480 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:09,480 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 52 [2018-01-24 21:06:09,480 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:09,480 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 21:06:09,481 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 21:06:09,481 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 21:06:09,481 INFO L87 Difference]: Start difference. First operand 152 states and 153 transitions. Second operand 27 states. [2018-01-24 21:06:09,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:09,758 INFO L93 Difference]: Finished difference Result 291 states and 308 transitions. [2018-01-24 21:06:09,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 21:06:09,758 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 151 [2018-01-24 21:06:09,758 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:09,759 INFO L225 Difference]: With dead ends: 291 [2018-01-24 21:06:09,759 INFO L226 Difference]: Without dead ends: 242 [2018-01-24 21:06:09,761 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 629 GetRequests, 579 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 21:06:09,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states. [2018-01-24 21:06:09,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 156. [2018-01-24 21:06:09,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-01-24 21:06:09,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 157 transitions. [2018-01-24 21:06:09,785 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 157 transitions. Word has length 151 [2018-01-24 21:06:09,785 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:09,785 INFO L432 AbstractCegarLoop]: Abstraction has 156 states and 157 transitions. [2018-01-24 21:06:09,785 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 21:06:09,785 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 157 transitions. [2018-01-24 21:06:09,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-01-24 21:06:09,786 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:09,786 INFO L322 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:09,786 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:09,787 INFO L82 PathProgramCache]: Analyzing trace with hash -731541737, now seen corresponding path program 24 times [2018-01-24 21:06:09,787 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:09,787 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:09,788 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:06:09,788 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:09,788 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:09,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:09,804 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:10,259 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 1250 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-24 21:06:10,259 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:10,259 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:10,259 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:10,259 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:10,259 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:10,259 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:10,268 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 21:06:10,268 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 21:06:10,276 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,285 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,291 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,301 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,302 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,304 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,305 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,307 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,310 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,312 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,314 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,317 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,319 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,322 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,324 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,327 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,331 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,334 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,338 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,339 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:10,342 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:10,490 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-24 21:06:10,490 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:10,662 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-24 21:06:10,683 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:10,683 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:10,686 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 21:06:10,686 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 21:06:10,695 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,696 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,701 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,706 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,713 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,723 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,735 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,749 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,765 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,801 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,829 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,877 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,918 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:10,993 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:11,059 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:11,335 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:11,668 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:12,100 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:12,797 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:12,828 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:12,833 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:12,851 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-24 21:06:12,851 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:12,876 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-24 21:06:12,878 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:12,878 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 11, 11, 11, 11] total 48 [2018-01-24 21:06:12,878 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:12,879 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-01-24 21:06:12,879 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-01-24 21:06:12,879 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=733, Invalid=1523, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 21:06:12,879 INFO L87 Difference]: Start difference. First operand 156 states and 157 transitions. Second operand 38 states. [2018-01-24 21:06:13,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:13,527 INFO L93 Difference]: Finished difference Result 300 states and 318 transitions. [2018-01-24 21:06:13,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 21:06:13,528 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 155 [2018-01-24 21:06:13,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:13,529 INFO L225 Difference]: With dead ends: 300 [2018-01-24 21:06:13,529 INFO L226 Difference]: Without dead ends: 251 [2018-01-24 21:06:13,530 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 646 GetRequests, 600 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 850 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=733, Invalid=1523, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 21:06:13,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states. [2018-01-24 21:06:13,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 165. [2018-01-24 21:06:13,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-01-24 21:06:13,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 166 transitions. [2018-01-24 21:06:13,549 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 166 transitions. Word has length 155 [2018-01-24 21:06:13,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:13,549 INFO L432 AbstractCegarLoop]: Abstraction has 165 states and 166 transitions. [2018-01-24 21:06:13,549 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-01-24 21:06:13,550 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 166 transitions. [2018-01-24 21:06:13,550 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-01-24 21:06:13,550 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:13,550 INFO L322 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:13,550 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:13,550 INFO L82 PathProgramCache]: Analyzing trace with hash 7304644, now seen corresponding path program 25 times [2018-01-24 21:06:13,551 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:13,551 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:13,551 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:06:13,551 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:13,552 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:13,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:13,562 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:14,231 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 21:06:14,231 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:14,231 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:14,232 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:14,232 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:14,232 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:14,232 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:14,244 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:06:14,244 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 21:06:14,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:14,270 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:14,288 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 21:06:14,288 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:14,949 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 21:06:14,970 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:14,970 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:15,014 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:06:15,015 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 21:06:15,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:15,069 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:15,087 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 21:06:15,088 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:15,108 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 21:06:15,109 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:15,109 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 56 [2018-01-24 21:06:15,109 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:15,110 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 21:06:15,110 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 21:06:15,111 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 21:06:15,111 INFO L87 Difference]: Start difference. First operand 165 states and 166 transitions. Second operand 29 states. [2018-01-24 21:06:15,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:15,489 INFO L93 Difference]: Finished difference Result 314 states and 332 transitions. [2018-01-24 21:06:15,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 21:06:15,489 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 164 [2018-01-24 21:06:15,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:15,490 INFO L225 Difference]: With dead ends: 314 [2018-01-24 21:06:15,491 INFO L226 Difference]: Without dead ends: 260 [2018-01-24 21:06:15,491 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 683 GetRequests, 629 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 21:06:15,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 260 states. [2018-01-24 21:06:15,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 260 to 169. [2018-01-24 21:06:15,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-01-24 21:06:15,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 170 transitions. [2018-01-24 21:06:15,511 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 170 transitions. Word has length 164 [2018-01-24 21:06:15,512 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:15,512 INFO L432 AbstractCegarLoop]: Abstraction has 169 states and 170 transitions. [2018-01-24 21:06:15,512 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-24 21:06:15,512 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 170 transitions. [2018-01-24 21:06:15,512 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2018-01-24 21:06:15,512 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:15,513 INFO L322 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:15,513 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:15,513 INFO L82 PathProgramCache]: Analyzing trace with hash -1420521539, now seen corresponding path program 26 times [2018-01-24 21:06:15,513 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:15,513 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:15,513 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:06:15,514 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:15,514 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:15,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:15,524 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:15,979 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 21:06:15,980 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:15,980 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:15,980 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:15,980 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:15,980 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:15,980 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:15,987 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 21:06:15,987 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:06:15,995 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:16,012 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:16,015 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:16,017 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:16,037 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 21:06:16,037 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:16,686 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 21:06:16,706 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:16,706 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:16,709 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 21:06:16,709 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:06:16,717 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:16,739 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:16,757 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:16,761 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:16,780 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 21:06:16,780 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:16,803 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 21:06:16,805 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:16,805 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 58 [2018-01-24 21:06:16,805 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:16,805 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 21:06:16,805 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 21:06:16,806 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 21:06:16,806 INFO L87 Difference]: Start difference. First operand 169 states and 170 transitions. Second operand 30 states. [2018-01-24 21:06:17,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:17,113 INFO L93 Difference]: Finished difference Result 323 states and 342 transitions. [2018-01-24 21:06:17,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-24 21:06:17,113 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 168 [2018-01-24 21:06:17,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:17,115 INFO L225 Difference]: With dead ends: 323 [2018-01-24 21:06:17,115 INFO L226 Difference]: Without dead ends: 269 [2018-01-24 21:06:17,116 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 700 GetRequests, 644 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 21:06:17,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states. [2018-01-24 21:06:17,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 173. [2018-01-24 21:06:17,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-01-24 21:06:17,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 174 transitions. [2018-01-24 21:06:17,148 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 174 transitions. Word has length 168 [2018-01-24 21:06:17,148 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:17,148 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 174 transitions. [2018-01-24 21:06:17,149 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 21:06:17,149 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 174 transitions. [2018-01-24 21:06:17,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-01-24 21:06:17,149 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:17,149 INFO L322 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:17,149 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:17,150 INFO L82 PathProgramCache]: Analyzing trace with hash -910555850, now seen corresponding path program 27 times [2018-01-24 21:06:17,150 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:17,150 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:17,150 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:06:17,150 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:17,150 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:17,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:17,164 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:17,838 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 1568 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-24 21:06:17,838 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:17,838 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:17,838 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:17,838 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:17,838 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:17,839 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:17,844 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 21:06:17,844 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 21:06:17,851 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:17,855 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:17,857 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:17,859 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:17,861 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:17,863 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:17,866 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:17,869 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:17,872 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:17,875 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:17,881 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:17,882 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:17,884 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:17,949 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-24 21:06:17,949 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:18,156 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-24 21:06:18,190 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:18,191 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:18,194 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 21:06:18,194 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 21:06:18,204 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:18,207 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:18,212 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:18,220 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:18,230 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:18,244 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:18,265 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:18,292 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:18,332 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:18,379 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:18,442 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 21:06:18,454 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:18,459 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:18,487 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-24 21:06:18,487 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:18,514 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-24 21:06:18,515 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:18,516 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 12, 12, 12, 12] total 53 [2018-01-24 21:06:18,516 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:18,516 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-01-24 21:06:18,517 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-01-24 21:06:18,517 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=894, Invalid=1862, Unknown=0, NotChecked=0, Total=2756 [2018-01-24 21:06:18,517 INFO L87 Difference]: Start difference. First operand 173 states and 174 transitions. Second operand 42 states. [2018-01-24 21:06:18,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:18,987 INFO L93 Difference]: Finished difference Result 332 states and 352 transitions. [2018-01-24 21:06:18,988 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-24 21:06:18,988 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 172 [2018-01-24 21:06:18,988 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:18,989 INFO L225 Difference]: With dead ends: 332 [2018-01-24 21:06:18,989 INFO L226 Difference]: Without dead ends: 278 [2018-01-24 21:06:18,990 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 717 GetRequests, 666 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1045 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=894, Invalid=1862, Unknown=0, NotChecked=0, Total=2756 [2018-01-24 21:06:18,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2018-01-24 21:06:19,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 182. [2018-01-24 21:06:19,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-24 21:06:19,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 183 transitions. [2018-01-24 21:06:19,016 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 183 transitions. Word has length 172 [2018-01-24 21:06:19,016 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:19,016 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 183 transitions. [2018-01-24 21:06:19,016 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-01-24 21:06:19,016 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 183 transitions. [2018-01-24 21:06:19,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2018-01-24 21:06:19,017 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:19,017 INFO L322 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:19,017 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:19,017 INFO L82 PathProgramCache]: Analyzing trace with hash 1830068019, now seen corresponding path program 28 times [2018-01-24 21:06:19,017 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:19,018 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:19,018 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:06:19,018 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:19,018 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:19,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:19,032 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:19,578 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 21:06:19,578 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:19,578 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:19,578 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:19,578 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:19,578 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:19,579 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:19,585 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 21:06:19,585 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 21:06:19,612 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:19,614 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:19,650 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 21:06:19,650 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:20,522 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 21:06:20,555 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:20,555 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:20,558 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 21:06:20,559 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 21:06:20,625 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:20,630 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:20,668 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 21:06:20,668 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:20,707 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 21:06:20,708 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:20,708 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32] total 62 [2018-01-24 21:06:20,708 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:20,709 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-01-24 21:06:20,709 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-01-24 21:06:20,709 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-24 21:06:20,709 INFO L87 Difference]: Start difference. First operand 182 states and 183 transitions. Second operand 32 states. [2018-01-24 21:06:21,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:21,504 INFO L93 Difference]: Finished difference Result 346 states and 366 transitions. [2018-01-24 21:06:21,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-24 21:06:21,505 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 181 [2018-01-24 21:06:21,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:21,506 INFO L225 Difference]: With dead ends: 346 [2018-01-24 21:06:21,506 INFO L226 Difference]: Without dead ends: 287 [2018-01-24 21:06:21,507 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 754 GetRequests, 694 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-24 21:06:21,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states. [2018-01-24 21:06:21,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 186. [2018-01-24 21:06:21,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-01-24 21:06:21,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 187 transitions. [2018-01-24 21:06:21,534 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 187 transitions. Word has length 181 [2018-01-24 21:06:21,534 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:21,534 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 187 transitions. [2018-01-24 21:06:21,534 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-01-24 21:06:21,534 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 187 transitions. [2018-01-24 21:06:21,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2018-01-24 21:06:21,535 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:21,535 INFO L322 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:21,535 INFO L371 AbstractCegarLoop]: === Iteration 31 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:21,535 INFO L82 PathProgramCache]: Analyzing trace with hash -1177971110, now seen corresponding path program 29 times [2018-01-24 21:06:21,535 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:21,536 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:21,536 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:06:21,536 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:21,536 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:21,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:21,547 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:21,940 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 21:06:21,940 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:21,940 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:21,941 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:21,941 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:21,941 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:21,941 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:21,948 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 21:06:21,948 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:06:21,957 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,958 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,959 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,961 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,963 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,964 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,966 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,968 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,970 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,972 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,975 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,979 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,982 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,986 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,989 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:21,993 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,000 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,007 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,015 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,021 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,028 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,035 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,043 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,052 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,062 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,072 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,085 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,097 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,112 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,128 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,156 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,157 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:22,160 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:22,182 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 21:06:22,182 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:22,951 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 21:06:22,972 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:22,973 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 59 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:22,976 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 21:06:22,976 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 21:06:22,984 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,986 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,990 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:22,994 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,000 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,007 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,015 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,025 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,036 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,050 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,066 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,084 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,105 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,130 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,158 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,191 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,228 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,270 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,318 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,371 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,430 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,500 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,580 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,659 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,765 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:23,889 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:24,034 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:24,199 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:24,389 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:24,592 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:27,037 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 21:06:27,111 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:27,117 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:27,142 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 21:06:27,142 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:27,177 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 21:06:27,180 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:27,181 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 64 [2018-01-24 21:06:27,181 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:27,181 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-24 21:06:27,181 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-24 21:06:27,182 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-24 21:06:27,182 INFO L87 Difference]: Start difference. First operand 186 states and 187 transitions. Second operand 33 states. [2018-01-24 21:06:27,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:27,542 INFO L93 Difference]: Finished difference Result 355 states and 376 transitions. [2018-01-24 21:06:27,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-01-24 21:06:27,542 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 185 [2018-01-24 21:06:27,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:27,543 INFO L225 Difference]: With dead ends: 355 [2018-01-24 21:06:27,543 INFO L226 Difference]: Without dead ends: 296 [2018-01-24 21:06:27,544 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 771 GetRequests, 709 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-24 21:06:27,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 296 states. [2018-01-24 21:06:27,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 296 to 190. [2018-01-24 21:06:27,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-01-24 21:06:27,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 191 transitions. [2018-01-24 21:06:27,571 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 191 transitions. Word has length 185 [2018-01-24 21:06:27,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:27,571 INFO L432 AbstractCegarLoop]: Abstraction has 190 states and 191 transitions. [2018-01-24 21:06:27,571 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-24 21:06:27,572 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 191 transitions. [2018-01-24 21:06:27,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 190 [2018-01-24 21:06:27,572 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:27,572 INFO L322 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:27,572 INFO L371 AbstractCegarLoop]: === Iteration 32 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:27,573 INFO L82 PathProgramCache]: Analyzing trace with hash 659595777, now seen corresponding path program 30 times [2018-01-24 21:06:27,573 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:27,573 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:27,573 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:06:27,573 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:27,573 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:27,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:27,583 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:28,152 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 1922 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-24 21:06:28,152 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:28,152 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:28,152 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:28,152 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:28,152 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:28,152 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:28,158 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 21:06:28,158 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 21:06:28,167 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,172 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,173 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,174 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,176 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,178 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,179 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,181 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,182 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,184 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,187 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,190 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,192 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,196 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,200 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,203 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,207 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,211 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,215 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,219 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,224 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,230 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,236 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,238 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:28,241 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:28,324 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-24 21:06:28,324 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:28,571 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-24 21:06:28,592 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:28,592 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 61 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 21:06:28,595 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 21:06:28,595 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 21:06:28,604 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,606 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,611 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,617 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,624 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,634 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,646 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,663 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,679 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,700 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,726 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,762 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,802 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,877 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:28,936 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:29,208 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:29,522 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:30,117 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:30,711 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:31,788 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:33,033 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:34,431 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:34,897 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 21:06:34,924 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 21:06:34,930 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:34,945 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-24 21:06:34,945 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 21:06:34,972 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-24 21:06:34,974 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 21:06:34,974 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 13, 13, 13, 13] total 58 [2018-01-24 21:06:34,974 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 21:06:34,974 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-01-24 21:06:34,975 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-01-24 21:06:34,975 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1071, Invalid=2235, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 21:06:34,975 INFO L87 Difference]: Start difference. First operand 190 states and 191 transitions. Second operand 46 states. [2018-01-24 21:06:35,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 21:06:35,532 INFO L93 Difference]: Finished difference Result 364 states and 386 transitions. [2018-01-24 21:06:35,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-24 21:06:35,532 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 189 [2018-01-24 21:06:35,532 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 21:06:35,533 INFO L225 Difference]: With dead ends: 364 [2018-01-24 21:06:35,533 INFO L226 Difference]: Without dead ends: 305 [2018-01-24 21:06:35,534 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 788 GetRequests, 732 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1260 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1071, Invalid=2235, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 21:06:35,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 305 states. [2018-01-24 21:06:35,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 305 to 199. [2018-01-24 21:06:35,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199 states. [2018-01-24 21:06:35,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 200 transitions. [2018-01-24 21:06:35,568 INFO L78 Accepts]: Start accepts. Automaton has 199 states and 200 transitions. Word has length 189 [2018-01-24 21:06:35,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 21:06:35,569 INFO L432 AbstractCegarLoop]: Abstraction has 199 states and 200 transitions. [2018-01-24 21:06:35,569 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-01-24 21:06:35,569 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 200 transitions. [2018-01-24 21:06:35,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-01-24 21:06:35,570 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 21:06:35,570 INFO L322 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 21:06:35,571 INFO L371 AbstractCegarLoop]: === Iteration 33 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-24 21:06:35,571 INFO L82 PathProgramCache]: Analyzing trace with hash -1088370982, now seen corresponding path program 31 times [2018-01-24 21:06:35,571 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 21:06:35,572 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:35,572 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 21:06:35,572 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 21:06:35,572 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 21:06:35,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:35,587 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 21:06:36,177 INFO L134 CoverageAnalysis]: Checked inductivity of 2402 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 354 trivial. 0 not checked. [2018-01-24 21:06:36,178 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:36,178 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 21:06:36,178 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 21:06:36,178 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 21:06:36,178 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 21:06:36,178 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 21:06:36,183 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 21:06:36,183 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 21:06:36,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 21:06:36,209 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 21:06:36,252 INFO L134 CoverageAnalysis]: Checked inductivity of 2402 backedges. 0 proven. 2048 refuted. 0 times theorem prover too weak. 354 trivial. 0 not checked. [2018-01-24 21:06:36,252 INFO L314 TraceCheckSpWp]: Computing backward predicates... Received shutdown request... [2018-01-24 21:06:36,814 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-01-24 21:06:36,814 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 21:06:36,817 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 21:06:36,817 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 09:06:36 BoogieIcfgContainer [2018-01-24 21:06:36,818 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 21:06:36,818 INFO L168 Benchmark]: Toolchain (without parser) took 49311.92 ms. Allocated memory was 307.8 MB in the beginning and 826.8 MB in the end (delta: 519.0 MB). Free memory was 266.7 MB in the beginning and 741.8 MB in the end (delta: -475.2 MB). Peak memory consumption was 43.9 MB. Max. memory is 5.3 GB. [2018-01-24 21:06:36,819 INFO L168 Benchmark]: CDTParser took 0.23 ms. Allocated memory is still 307.8 MB. Free memory is still 271.6 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 21:06:36,819 INFO L168 Benchmark]: CACSL2BoogieTranslator took 181.67 ms. Allocated memory is still 307.8 MB. Free memory was 266.7 MB in the beginning and 258.4 MB in the end (delta: 8.2 MB). Peak memory consumption was 8.2 MB. Max. memory is 5.3 GB. [2018-01-24 21:06:36,819 INFO L168 Benchmark]: Boogie Preprocessor took 24.39 ms. Allocated memory is still 307.8 MB. Free memory was 258.4 MB in the beginning and 256.5 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 21:06:36,820 INFO L168 Benchmark]: RCFGBuilder took 171.89 ms. Allocated memory is still 307.8 MB. Free memory was 256.5 MB in the beginning and 244.3 MB in the end (delta: 12.1 MB). Peak memory consumption was 12.1 MB. Max. memory is 5.3 GB. [2018-01-24 21:06:36,820 INFO L168 Benchmark]: TraceAbstraction took 48924.75 ms. Allocated memory was 307.8 MB in the beginning and 826.8 MB in the end (delta: 519.0 MB). Free memory was 244.3 MB in the beginning and 741.8 MB in the end (delta: -497.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 5.3 GB. [2018-01-24 21:06:36,822 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23 ms. Allocated memory is still 307.8 MB. Free memory is still 271.6 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 181.67 ms. Allocated memory is still 307.8 MB. Free memory was 266.7 MB in the beginning and 258.4 MB in the end (delta: 8.2 MB). Peak memory consumption was 8.2 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 24.39 ms. Allocated memory is still 307.8 MB. Free memory was 258.4 MB in the beginning and 256.5 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 171.89 ms. Allocated memory is still 307.8 MB. Free memory was 256.5 MB in the beginning and 244.3 MB in the end (delta: 12.1 MB). Peak memory consumption was 12.1 MB. Max. memory is 5.3 GB. * TraceAbstraction took 48924.75 ms. Allocated memory was 307.8 MB in the beginning and 826.8 MB in the end (delta: 519.0 MB). Free memory was 244.3 MB in the beginning and 741.8 MB in the end (delta: -497.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 15 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 2 LocStat_NO_SUPPORTING_DISEQUALITIES : 4 LocStat_NO_DISJUNCTIONS : -30 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 21 TransStat_MAX_WEQGRAPH_SIZE : 1 TransStat_MAX_SIZEOF_WEQEDGELABEL : 1 TransStat_NO_SUPPORTING_EQUALITIES : 9 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 22 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.194461 RENAME_VARIABLES(MILLISECONDS) : 0.208262 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.162621 PROJECTAWAY(MILLISECONDS) : 0.361444 ADD_WEAK_EQUALITY(MILLISECONDS) : 2.870025 DISJOIN(MILLISECONDS) : 0.260755 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.232575 ADD_EQUALITY(MILLISECONDS) : 0.045932 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.087386 #CONJOIN_DISJUNCTIVE : 34 #RENAME_VARIABLES : 76 #UNFREEZE : 0 #CONJOIN : 45 #PROJECTAWAY : 59 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 6 #RENAME_VARIABLES_DISJUNCTIVE : 73 #ADD_EQUALITY : 9 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was analyzing trace of length 199 with TraceHistMax 33, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 15]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 15). Cancelled while BasicCegarLoop was analyzing trace of length 199 with TraceHistMax 33, while TraceCheckSpWp was constructing backward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 27 locations, 2 error locations. TIMEOUT Result, 48.8s OverallTime, 33 OverallIterations, 33 TraceHistogramMax, 8.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 534 SDtfs, 3943 SDslu, 4942 SDs, 0 SdLazy, 8216 SolverSat, 1248 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 13553 GetRequests, 12532 SyntacticMatches, 0 SemanticMatches, 1021 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5325 ImplicationChecksByTransitivity, 14.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=199occurred in iteration=32, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.1s AbstIntTime, 1 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.4s AutomataMinimizationTime, 32 MinimizatonAttempts, 1789 StatesRemovedByMinimization, 32 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.3s SsaConstructionTime, 18.1s SatisfiabilityAnalysisTime, 18.4s InterpolantComputationTime, 9789 NumberOfCodeBlocks, 9189 NumberOfCodeBlocksAsserted, 492 NumberOfCheckSat, 16147 ConstructedInterpolants, 0 QuantifiedInterpolants, 4918365 SizeOfPredicates, 40 NumberOfNonLiveVariables, 9300 ConjunctsInSsa, 1040 ConjunctsInUnsatCore, 152 InterpolantComputations, 2 PerfectInterpolantSequences, 43980/122610 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_21-06-36-831.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_21-06-36-831.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_21-06-36-831.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_21-06-36-831.csv Completed graceful shutdown